CLC5957PCASM

October 1999 CLC5957 12-bit, 70MSPS Broadband Monolithic A/D Converter N CLC5957 12-bit, 70MSPS Broadband Monolithic A/D Converter General Description The CLC5957 is a monolithic 12-bit, 70MSPS analog-to-digital converter. The device has been optimized for use in IF-sampled digital receivers and other applications where high resolution, high sampling rate, wide dynamic range, low power dissipation, and compact size are required. The CLC5957 features differential analog inputs, low jitter differential universal clock inputs, a low distortion track-and-hold with 0-300MHz input bandwidth, a bandgap voltage reference, data valid clock output, TTL compatible CMOS (3.3V or 2.5V) programmable output logic, and a proprietary 12-bit multi-stage quantizer. The CLC5957 is fabricated on the ABIC-V 0.8 micron BiCMOS process. The CLC5957 features a 74dBc spurious free dynamic range (SFDR) and a 67dB signal to noise ratio (SNR). The wideband track-and-hold allows sampling of IF signals to greater than 250MHz. The part produces two-tone, dithered, SFDR of 83dBFS at 75MHz input frequency. The differential analog input provides excellent common mode rejection, while the differential universal clock inputs minimize jitter. The 48-pin TSSOP package provides an extremely small footprint for applications where space is a critical consideration. The CLC5957 operates from a single +5V power supply. Operation over the industrial temperature range of -40°C to +85°C is guaranteed. National Semiconductor tests each part to verify compliance with the guaranteed specifications. Features • 70MSPS • Wide dynamic range SFDR: 74dBc SFDR w/dither: 85dBFS SNR: 67dB • IF sampling capability • Input bandwidth = 0-300MHz • Low power dissipation: 640mW • Very small package: 48-pin TSSOP • Single +5V supply • Data valid clock output • Programmable output levels: 3.3V or 2.5V Applications • • • • • • • • Cellular base-stations Digital communications Infrared/CCD imaging IF sampling Electro-optics Instrumentation Medical imaging High definition video MTD N IMTD ME79TG CLC5957 CL5956 Actual Size ADC Block Diagram DAV Clock In IF Input IF Saw First IF Receiver DVGA (∆G = 42dB) CLC5902 CLC5957 12-bit 70MSPS ADC 12 DAV Dig. Tuner/ Filter AGC 20 ~ ~ BPF (150MHz typ.) Noise BPF 3-bit (Gain Control) AIn T/H 3-bit Q 3-bit Q 3-bit Q 3-bit Q 3 3 3 3 12 ADC Out Bit Align/Error Correct Decimation/filter = 190/0.8 Output BW = 50M/190 X 0.8 = 210KHz Receiver SINAD vs. Input Amplitude 90 Single Tone Output Spectrum w/Dither 0 SINAD dBc (BW = 216KHz) 16 20 24 28 32 -10 Fin = 25.3MHZ Fsample = 66MHz 80 70 60 50 40 30 20 10 0 -125 -100 -75 -50 -25 0 Output Level (dBFS) -20 -30 -40 -50 -60 -70 -80 -90 -100 0 4 8 12 Frequency (MHz) Input (dBFS) © 1999 National Semiconductor Corporation Printed in the U.S.A. http://www.national.com CLC5957 Electrical Characteristics (Vcc= +5V, 66MSPS; unless specified) (Tmin = -40°C, Tmax = +85°C) PARAMETERS CONDITIONS TEMP MIN RESOLUTION DIFF. INPUT VOLTAGE RANGE MAXIMUM CONVERSION RATE SNR SFDR NO MISSING CODES DYNAMIC PERFORMANCE large-signal bandwidth overvoltage recovery time effective aperture delay (Ta) aperture jitter Full Full Full +25°C +25°C +25°C +25°C +25°C +25°C +25°C RATINGS TYP 12 2.048 75 66 74 Guaranteed 300 12 -0.41 0.3 MAX Bits V MSPS dBFS dBc UNITS NOTES 2 1 1 1 1 1 fin = 25MHz, Ain = -1dBFS fin = 25MHz, Ain = -1dBFS fin = 5MHz, Ain = -1dBFS Ain = -3dBFS Ain = 1.5FS (0.01%) 70 63 66 MHz ns ns ps(rms) NOISE AND DISTORTION signal-to-noise ratio (w/o 50 harmonics) fin = 5.0MHz Ain = -1dBFS Ain = -1dBFS fin = 25MHz fin = 75MHz Ain = -3dBFS fin = 150MHz Ain = -15dBFS fin = 250MHz Ain = -15dBFS spurious-free dynamic range Ain = -1dBFS fin = 5.0MHz fin = 25MHz Ain = -1dBFS Ain = -3dBFS fin = 75MHz fin = 150MHz Ain = -15dBFS Ain = -15dBFS fin = 250MHz intermodulation distortion fin1 = 149.84MHz, fin2 = 149.7MHz Ain = -10dBFS fin1 = 249.86MHz, fin2 = 249.69MHz Ain = -10dBFS dithered performance spurious-free dynamic range Ain = -6dBFS fin = 19MHz intermodulation distortion fin1 = 74MHz, fin2 = 75MHz Ain = -12dBFS DC ACCURACY AND PERFORMANCE differential non-linearity integral non-linearity no missing codes offset error gain error Vref ANALOG INPUTS analog differential input voltage range analog input resistance (single ended) analog input resistance (differential) analog input capacitance (single-ended) ENCODE INPUTS (Universal) VIH VIL differential input swing DIGITAL OUTPUTS output voltage OUTLEV = 1 (open) OUTLEV = 0 (GND) logic LOW logic HIGH logic HIGH fin = 5MHz, Ain = -1dBFS fin = 5MHz, Ain = -1dBFS fin = 5MHz, Ain = -1dBFS Full Full Full Full Full Full Full Full Full Full +25°C +25°C +25°C +25°C Full Full Full Full Full Full Full Full Full Full +25°C +25°C +25°C +25°C +25°C +25°C Full +25°C Full Full Full +25°C +25°C 60 67 66 65 66 66 74 74 72 69 65 68 58 85 83 ±0.65 ±1.5 Guaranteed 0 1.2 2.37 2.048 500 1000 2 5 dBFS dBFS dBFS dBFS dBFS dBc dBc dBc dBc dBc dBFS dBFS dBFS dBFS LSB LSB 30 2.6 mV %FS V Vpp Ω Ω pF V V V V V V MSPS MSPS ns ns clk cycle ns ns 1 60 1 -30 2.2 1 1 1 0 0.2 0.01 3.5 2.7 75 10 7.2 7.2 3.0 10 9.6 0.4 3.8 3.0 3 3 3 1 1 1 1 3.2 2.4 70 TIMING (C load < 7pF) maximum conversion rate minimum conversion rate pulse width high pulse width low pipeline latency falling ENCODE to output change (50%) (Tod) rising ENCODE to DAV change (50%) (Tdv) http://www.national.com 2 CLC5957 Electrical Characteristics (Vcc= +5V, 66MSPS; unless specified) (Tmin = -40°C, Tmax = +85°C) PARAMETERS POWER REQUIREMENTS +5V supply current Power dissipation VCC power supply rejection ratio CONDITIONS TEMP MIN Full Full +25°C RATINGS TYP 128 640 64 MAX 150 750 mA mW dB UNITS NOTES 2 1 1 Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. Notes 1) These parameters are 100% tested at 25°C. Sample tested at full temperature range. 2) Typical specifications are based on the mean test values of deliverable converters from the first three diffusion lots. 3) See page 7, Figure 3 for ENCODE Inputs circuit. Absolute Maximum Ratings positive supply voltage (Vcc) differential voltage between any two grounds analog input voltage range digital input voltage range output short circuit duration (one-pin to ground) junction temperature storage temperature range lead solder duration (+300°C) -0.5V to +6V 200mV). The clock input is internally biased to VCC/2 with a termination impedance of 2.5kΩ. (Pins 30-34, 39-45) Digital data outputs are CMOS and TTL compatible. D0 is the LSB and D11 is the MSB. MSB is inverted. Output coding is two’s complement. (Pin 27) Data Valid Clock. Data is valid on rising edge. (Pin 28) Output Logic 3.3V or 2.5V option. Open = 3.3V, GND = 2.5V. (Pin 21) Internal common mode voltage reference. Nominally +2.4V. Can be used for the input common mode voltage. This voltage is derived from an internal bandgap reference. (Pins 1-4, 8, 11, 12, 15, 19, 20, 23-26, 29, 35, 36, 47, 48) circuit ground. (Pins 5-7, 16-18, 22,) +5V power supply for the analog section. Bypass to ground with a 0.1µF capacitor. (Pin 37, 38, 46) +5V power supply for the digital section. Bypass to ground with a 0.1µF capacitor. ENCODE, ENCODE CLC5957 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 D0-D11 DAV OUTLEV VCM GND +AVCC +DVCC http://www.national.com 6 CLC5957 Applications Analog Inputs and Bias Figure 1 depicts the analog input and bias scheme. Each of the differential analog inputs are internally biased to a nominal voltage of 2.40 volts DC through a 500Ω resistor to a low impedance buffer. This enables a simple interface to a broadband RF transformer with a centertapped output winding that is decoupled to the analog ground. If the application requires the inputs to be DC coupled, the Vcm output can be used to establish the proper common -mode input voltage for the ADC. The Vcm voltage reference is generated from an internal bandgap source that is very accurate and stable. ADC Bias Mirror Ain Ain To T/H and ADC ENCODE Clock Inputs The CLC5957’s differential input clock scheme is compatible with all commonly used clock sources. Although small differential and single-ended signals are adequate, for best aperture jitter performance a low noise differential clock with a high slew rate is preferred. As depicted in Figure 3, both ENCODE clock inputs are internally biased to VCC/2 though a pair of 5KΩ resistors. The clock input buffer operates with any common-mode voltage between the supply and ground. VCCA 5kΩ 5kΩ 500µΑ 500Ω 500Ω ENC ENC + 1.23V Bandgap Reference – 2.4V 2KΩ Vcm 5kΩ 5kΩ BJT Current Mirror GNDA Figure 1: CLC5957 Bias Scheme The Vcm output may also be used to power down the ADC. When the Vcm pin is pulled above 3.5V, the internal bias mirror is disabled and the total current is reduced to less than 10mA. Figure 2 depicts how this function can be used. The diode is necessary to prevent the logic gate from altering the ADC bias value. Figure 3: CLC5957 ENCODE Clock Inputs The internal bias resistors simplify the clock interface to another center-tapped transformer as depicted in Figure 4. A low phase noise, RF synthesizer of moderate amplitude (1 - 4Vpp) can drive the ADC through this interface. ENC ~ ENC CLC5957 CLC5957 5V CMOS "1" = on "0" = off Vref Figure 2: Power Shutdown Scheme Figure 4: Transfer Coupled Clock Scheme 7 http://www.national.com Figures 5 and 6 show the clock interface schemes to several other types of clock sources. 2.4Vref + - VCCD Controlled Current Output Buffer ENC ENC CML to CMOS Digital Signal + 50Ω Digital Output 0.01µF CLC5957 10kΩ Output Level GNDD Open = 3.3Vhi GND = 2.5Vhi Figure 7: CLC5957 Digital Outputs The logic high level is slaved to the internal 2.4 voltage reference. The OUTLEV control pin selects either a 3.3V or 2.5V logic high level. An internal pullup resistor selects the 3.3 volt level as the default when the OUTLEV pin is left open. Grounding the OUTLEV pin selects the 2.5V logic high level. To ease user interface to subsequent digital circuitry, the CLC5957 has a data valid clock output (DAV). In order to match delays over IC processing variables, this digital output also uses the same output buffer as the data bits. The DAV clock output is simply a delayed version of the ENCODE input clock. Since the ADC output data change is slaved to the falling edge of the ENCODE clock, the rising DAV clock edge occurs near the center of the data valid window (or eye) regardless of the sampling frequency. Figure 5: 5V CMOS Level Clock Scheme ENC ENC CLC5957 0.01µF Figure 6: TTL or 3V CMOS Level Clock Scheme Digital Outputs and Level Select Figure 7 depicts the digital output buffer and bias used in the CLC5957. Although each of the twelve output bits uses a controlled current buffer to limit supply transients, it is recommended that parasitic loading of the outputs is minimized. Because these output transients are harmonically related to the analog input signal, excessive loading will degrade ADC performance at some frequencies. http://www.national.com 8 CLC5957 Evaluation Board Description The Evaluation board for the CLC5957 allows for easy test and evaluation of the product. The part may be ordered with all components loaded and tested. The order number is the CLC5957PCASM. The user supplies an analog input signal, encode signal and power to the board and is able to take latched 12-bit digital data out of the board. ENCODE Input (ENC) The ENCODE input is an SMA connector with a termination of 50Ω. The encode signal is converted to an AC coupled, differential clock signal centered between VCC and ground. The user should supply a sinusoidal or square wave signal of >200mVpp and