COP87L88

COP87L88EB/RB Family, 8-Bit CMOS OTP Microcontrollers with 16k or 32k Memory, CAN Interface, 8-Bit A/D, and USART September 1999 COP87L88EB/RB Family 8-Bit CMOS OTP Microcontrollers with 16k or 32k Memory, CAN Interface, 8-Bit A/D, and USART General Description The COP87L88EB/RB Family OTP (One Time programmable) microcontrollers are highly integrated COP8™ Feature core devices with 16k or 32k memory and advanced features including a CAN 2.0B (passive) interface, A/D and USART. These multi-chip CMOS devices are suited for applications requiring a full featured controller with a CAN interface, low EMI, and versatile communications interfaces, and as pre-production devices for ROM designs. Pin and software compatible 8k ROM versions (COP888EB) are available as well as a range of COP8 software and hardware development tools. Device COP87L88EB COP87L89EB COP87L88RB COP87L89RB Memory (bytes) 16k OTP EPROM 16k OTP EPROM 32k OTP EPROM 32k OTP EPROM Features include an 8-bit memory mapped architecture, 10 MHz CKI (-XE = crystal oscillator) with 1µs instruction cycle, two multi-function 16-bit timer/counters, WATCHDOG and clock monitor, idle timer, CAN 2.0B (passive) interface, MICROWIRE/PLUS™ serial I/O, SPI master/slave interface, fully buffered USART, 8 bit A/D with 8 channels, two power saving HALT/IDLE modes, MIWU, software selectable I/O options, low EMI 4.5V to 5.5V operation, program code security, and 44/68 pin packages. Note: A companion device with CAN interface, less I/O and memory, A/D, and PWM timer is the COP87L84BC. Devices included in this datasheet are: I/O Pins 35 58 35 58 Packages 44 PLCC 68 PLCC 44 PLCC 68 PLCC Temperature -40 to +85˚C -40 to +85˚C -40 to +85˚C -40 to +85˚C RAM (bytes) 192 192 192 192 Key Features n CAN 2.0B (passive) bus interface, with Software Power save mode n 8-bit A/D Converter with 8 channels n Fully buffered USART n Multi-input wake up (MIWU) on both Port L and M n SPI Compatible Master/Slave Interface n 16 or 32 kbytes of on-board OTP EPROM with security feature Note: Mask ROMed device with equivalent on-chip features and program memory size of 8k is available. CPU/Instruction Set Features n 1 µs instruction cycle time n Fourteen multi-sourced vectored interrupts servicing — External interrupt — Idle Timer T0 — Timers (T1 and T2) (4 Interrupts) — MICROWIRE/PLUS and SPI — Multi-input Wake up — Software Trap — CAN interface (3 interrupts) — USART (2 Inputs) n Versatile easy to use instruction set n 8-bit stacker pointer (SP) (Stack in RAM) n Two 8-bit RegisterR Indirect Memory Pointers (B, X) n 192 bytes of on-board RAM Additional Peripheral Features n Idle timer (programmable) n Two 16-bit timer, with two 16-bit registers supporting — Processor independent PWM mode — External Event counter mode — Input capture mode n WATCHDOG™ and Clock Monitor n MICROWIRE/PLUS serial I/O Fully Static CMOS n Two power saving modes: HALT, IDLE n Single supply operation: 4.5V to 5.5V n Temperature range: −40˚C to +85˚C Development Support n Emulation device for COP888EB n Real time emulation and full program debug offered by MetaLink Development System I/O Features n Software selectable I/O options (TRI-STATE ® outputs, Push pull outputs, Weak pull up input, High impedance input) n Schmitt trigger inputs on Port G, L and M n Packages: 44 PLCC with 35 I/O pins; 68 PLCC with 58 I/O pins TRI-STATE ® is a registered trademark of National Semiconductor Corporation. COP8™, MICROWIRE/PLUS™, WATCHDOG™ and MICROWIRE™ are trademarks of National Semiconductor Corporation. iceMASTER ® is a registered trademark of MetaLink Corporation. © 2000 National Semiconductor Corporation DS100044 www.national.com COP87L88RB/COP87L89RB Basic Functional Description n CAN I/F — CAN serial bus interface block as described in the CAN specification part 2.0B (Passive) — Interface rates up to 250k bit/s are supported utilizing standard message identifiers n Programmable double buffered USART n A/D — 8-bit, 8 channel, 1-LSB Resolution, with improved Source Impedance and improved channel to channel cross talk immunity n Multi-Input-Wake-Up (MIWU) — edge selectable wake-up and interrupt capability via input port and CAN interface (Port L, Port M and CAN I/F); supports Wake-Up capability on SPI, USART, and T2 n Port C — 8-bit bi-directional I/O port n Port D — 8-bit Output port with high current drive capability (10 mA) n Port F — 8-bit bidirectional I/O n Port G — 8-bit bidirectional I/O port, including alternate functions for: — MICROWIRE™ Input and Output — Timer 1 Input or Output (Depending on mode selected) — External Interrupt input — WATCHDOG Output n Port I — 8-bit input port combining either digital input, or up to eight A/D input channels n Port L — 8-bit bidirectional I/O port, including alternate functions for: — USART Transmit/Receive I/O — Multi-input-wake up (MIWU on all pins) n Port M — 8-bit I/O port, with the following alternate function — SPI Interface — MIWU n n n n n n n n — CAN Interface Wake-up (MSB) — Timer 2 Input or Output (Depending on mode selected) Port N — 8-bit bidirectional I/O — SPI Slave Select Expander Two 16-bit multi-function Timer counters (T1 and T2) plus supporting registers — (I/P Capture, PWM and Event Counting) Idle timer — Provides a basic time-base counter, (with interrupt) and automatic wake up from IDLE mode programmable MICROWIRE/PLUS — MICROWIRE serial peripheral interface, supporting both Master and Slave operation HALT and IDLE — Software programmable low current modes — HALT — Processor stopped, Minimum current — IDLE — Processor semi-active more than 60% power saving 16 or 32 kbytes OTP EPROM and 192 bytes of on board static RAM SPI Master/Slave interface includes 12 bytes Transmit and 12 bytes Receive FIFO Buffers. Operates up to 1M Bit/S On board programmable WATCHDOG and CLOCK Monitor Applications n n n n n Automobile Body Control and Comfort System Integrated Driver Informaiton Systems Steering Wheel Control Car Radio Control Panel Sensor/Actuator Applications in Automotive and Industrial Control Block Diagram DS100044-1 FIGURE 1. Block Diagram www.national.com 2 COP87L88RB/COP87L89RB Connection Diagrams Plastic Chip Carrier DS100044-2 Top View Order Number COP87L88EBV-XE or COP87L88RBV-XE See NS Plastic Chip Package Number V44A Plastic Leaded Chip Carrier DS100044-3 Note: -X Crystal Oscillator -E Halt Mode Enabled Top View Order Number COP87L89EBV-XE or COP87L89RBV-XE See NS Plastic Chip Package Number V68A FIGURE 2. Connection Diagrams 3 www.national.com COP87L88RB/COP87L89RB Connection Diagrams Port Pin G0 G1 G2 G3 G4 G5 G6 G7 D0 D1 D2 D3 D4 D5 D6 D7 I0 I1 I2 I3 I4 I5 I6 I7 L0 L1 L2 L3 L4 L5 L6 L7 M0 M1 M2 M3 M4 M5 M6 N0 N1 N2 N3 N4 N5 N6 N7 I/O I/O I/O I/O I/O I/O I I O O O O O O O O I I I I I I I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ADCH0 ADCH1 ADCH2 ADCH3 ADCH4 ADCH5 ADCH6 ADCH7 MIWU MIWU;CKX MIWU;TDX MIWU;RDX MIWU MIWU MIWU MIWU MIWU;MISO MIWU;MOSI MIWU;SCK MIWU;SS MIWU;T2A MIWU;T2B MIWU ESS0 ESS1 ESS2 ESS3 ESS4 ESS5 ESS6 ESS7 Type INT WDOUT T1B T1A SO SK SI CKO ALT Function (Continued) Port Pin 68-Pin PLCC 1 2 3 4 5 6 7 8 27 28 29 30 31 32 33 34 F0 F1 F2 F3 F4 C0 C1 C2 RX0 RX1 TX0 TX1 CANVREF CKI RESET DVCC GND A/D VREF Type I/O I/O I/O I/O I/O I/O I/O I/O I I O O ALT Function 44-Pin PLCC 68-Pin PLCC 10 11 12 13 14 35 36 37 Pinouts for 44-Pin and 68-Pin Packages 44-Pin PLCC 44 1 2 3 4 5 6 7 17 18 19 20 31 30 29 28 32 8 16 10, 33 9, 11, 34 35 48 47 46 45 49 9 26 16, 50 15, 17, 51 52 36 37 38 39 53 54 55 56 57 58 59 60 40 41 42 43 61 62 63 64 65 66 67 68 21 22 23 24 25 26 27 12 13 14 15 38 39 40 41 42 43 44 18 19 20 21 22 23 24 25 www.national.com 4 COP87L88RB/COP87L89RB Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) Voltage at Any Pin 6V −0.3V to VCC +0.3V Total Current into VCC Pins (Source) Total Current out of GND Pins (Sink) Storage Temperature Range 90 mA 100 mA −65˚C to +150˚C Note 1: Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings. DC Electrical Characteristics −40˚C ≤ TA ≤ +85˚C Parameter Operating Voltage Power Supply Ripple (Note 2) Supply Current CKI = 10 MHz (Note 3) HALT Current (Notes 4, 5) IDLE Current (Note 5) CKI = 10 MHz Input Levels (VIH, VIL) Reset, CKI Logic High Logic Low All Other Inputs Logic High Logic Low Hi-Z Input Leakage Input Pull-Up Current Port G, L and M Input Hysteresis Output Current Levels D Outputs Source Sink CAN Transmitter Outputs Source (Tx1) Sink (Tx0) All Others Source (Weak Pull-Up) Source (Push-Pull) Sink (Push-Pull) TRI-STATE Leakage Allowable Sink/Source Current per Pin D Outputs (sink) Tx0 (Sink) (Note 8) Tx1 (Source) (Note 8) All Other Maximum Input Current without Latchup (Notes 6, 8) RAM Retention Voltage, Vr (Note 7) Input Capacitance Load Capacitance on D2 Note 2: Maxiumum rate of voltage change must be Conditions Peak-to-Peak VCC = 5.5V, tc = 1 µs VCC = 5.5V, CKI = 0 MHz VCC = 5.5V, tc = 1 µs Min 4.5 Typ Max 5.5 0.1 VCC 16 Units V V mA µA 10 kHz — No clock rejection. 1/tc < 10 Hz — Guaranteed clock rejection. 59 www.national.com WATCHDOG The device contains a WATCHDOG and clock monitor. The WATCHDOG is designed to detect the user program getting stuck in infinite loops resulting in loss of program control or “runaway” programs. The Clock Monitor is used to detect the absence of a clock or a very slow clock below a specified rate on the CKI pin. The WATCHDOG consists of two independent logic blocks: WD UPPER and WD LOWER. WD UPPER establishes the upper limit on the service window and WD LOWER defines the lower limit of the service window. Servicing the WATCHDOG consists of writing a specific value to a WATCHDOG Service Register named WDSVR which is memory mapped in the RAM. This value is composed of three fields, consisting of a 2-bit Window Select, a 5-bit Key Data field, and the 1-bit Clock Monitor Select field. Table 18 shows the WDSVR register. TABLE 17. WATCHDOG Service Register (WDSVR) Window Select X Bit 7 X 0 1 1 0 0 Key Data Clock Monitor Y Bit 0 The lower limit of the service window is fixed at 2048 instruction cycles. Bits 7 and 6 of the WDSVR register allow the user to pick an upper limit of the service window. Table 18 shows the four possible combinations of lower and upper limits for the WATCHDOG service window. This flexibility in choosing the WATCHDOG service window prevents any undue burden on the user software. TABLE 18. WATCHDOG Service Window Select WDSVR WDSVR Bit 7 0 0 1 1 x x Bit 6 0 1 0 1 x x Clock Monitor x x x x 0 1 Service Window (Lower-Upper Limits) 2048–8k tC Cycles 2048–16k tC Cycles 2048–32k tC Cycles 2048–64k tC Cycles Clock Monitor Disabled Clock Monitor Enabled Bits 5, 4, 3, 2 and 1 of the WDSVR register represent the 5-bit Key Data field. The key data is fixed at 01100. Bit 0 of the WDSVR Register is the Clock Monitor Select bit. COP87L88RB/COP87L89RB WATCHDOG Operation (Continued) • WATCHDOG AND CLOCK MONITOR SUMMARY The following salient points regarding the COP888 WATCHDOG and CLOCK MONITOR should be noted: • • Both the WATCHDOG and Clock Monitor detector circuits are inhibited during RESET. Following RESET, the WATCHDOG and CLOCK MONITOR are both enabled, with the WATCHDOG having the maximum service window selected. The WATCHDOG service window and Clock Monitor enable/disable option can only be changed once, during the initial WATCHDOG service following RESET. The initial WATCHDOG service must match the key data value in the WATCHDOG Service register WDSVR in order to avoid a WATCHDOG error. Subsequent WATCHDOG services must match all three data fields in WDSVR in order to avoid WATCHDOG errors. The correct key data value cannot be read from the WATCHDOG Service register WDSVR. Any attempt to read this key data value of 01100 from WDSVR will read as key data value of all 0’s. The WATCHDOG detector circuit is inhibited during both the HALT and IDLE modes. The Clock Monitor detector circuit is active during both the HALT and IDLE modes. Consequently, the device inadvertently entering the HALT mode will be detected as a Clock Monitor error (provided that the Clock Monitor enable option has been selected by the program). With the single-pin R/C oscillator mask option selected and the CLKDLY bit reset, the WATCHDOG service window will resume following HALT mode from where it left off before entering the HALT mode. With the crystal oscillator mask option selected, or with the single-pin R/C oscillator mask option selected and the CLKDLY bit set, the WATCHDOG service window will be set to its selected value from WDSVR following HALT. Consequently, the WATCHDOG should not be serviced for at least 2048 instruction cycles following HALT, but must be serviced within the selected window to avoid a WATCHDOG error. The IDLE timer T0 is not initialized with RESET. The user can sync in to the IDLE counter cycle with an IDLE counter (T0) interrupt or by monitoring the T0PND flag. The T0PND flag is set whenever the thirteenth bit of the IDLE counter toggles (every 4096 instruction cycles). The user is responsible for resetting the T0PND flag. A hardware WATCHDOG service occurs just as the device exits the IDLE mode. Consequently, the WATCHDOG should not be serviced for at least 2048 instruction cycles following IDLE, but must be serviced within the selected window to avoid a WATCHDOG error. Following RESET, the initial WATCHDOG service (where the service window and the CLOCK MONITOR enable/ disable must be selected) may be programmed anywhere within the maximum service window (65,536 instruction cycles) initialized by RESET. Note that this initial WATCHDOG service may be programmed within the intitial 2048 instruction cycles without causing a WATCHDOG error. • • • • • • • • • • • TABLE 19. WATCHDOG Service Actions Key Data Match Don’t Care Mismatch Don’t Care Window Data Match Mismatch Don’t Care Don’t Care Clock Monitor Match Don’t Care Don’t Care Mismatch Valid Service: Restart Service Window Error: Generate WATCHDOG Output Error: Generate WATCHDOG Output Error: Generate WATCHDOG Output Action www.national.com 60 COP87L88RB/COP87L89RB Memory Map All RAM, ports and registers (except A and PC) are mapped into data memory address space. Address 0000 to 006F 0070 to 007F 0080 0081 0082 0083 0084 0085 0086 0087 0088 0089 008A 008B 008C to 008F 0090 0091 0092 0093 0094 0095 0096 0097 0098 0099 009A 009B 009C to 009F 00A0 00A1 Contents On-Chip RAM bytes (112 bytes) Unused RAM Address Space (Reads as All Ones) PORTMD, Port M Data Register PORTMC, Port M Configuration Register PORTMP, Port M Input Pins (Read Only) Reserved for Port M MMIWU Edge Select Register (MWKEDG) MMIWU Enable Register (MWKEN) MMIWU Pending Register (MWKPND) Reserved for MMIWU PORTND, Port N Data Register PORTNC, Port N Configuration Register PORTNP, Port N Input Pins (Read Only) PORTNX, Port N Alternate Function Enable Unused RAM Address Space (Reads Undefined Data) PORTED, Port E Data Register PORTEC, Port E Configuration Register PORTEP, Port E Input Pins (Read Only) Reserved for Port E PORTFD, Port F Data Register PORTFC, Port F Configuration Register PORTFP, Port F Input Pins (Read Only) Reserved for Port F SPICNTL, SPI Control Register SPISTAT, SPI Status Register SPIRXD, SPI Current Receive Data (Read Only) SPITXD, SPI Transmit Data Reserved TXD1, Transmit 1 Data TXD2, Transmit 2 Data 61 Address 00A2 00A3 00A4 00A5 00A6 00A7 00A8 00A9 00AA 00AB 00AC 00AD 00AE 00AF 00B8 00B9 00BA 00BB 00BC 00BD 00BE 00BF 00C0 00C1 00C2 00C3 00C4 00C5 00C6 00C7 00C8 00C9 00CA Contents TDLC, Transmit Data Length Code and Identifier Low TID, Transmit Identifier High RXD1, Receive Data 1 RXD2, Receive Data 2 RIDL, Receive Data Length Code RID, Receive Identify HIgh CSCAL, CAN Prescaler CTIM, Bus Timing Register CBUS, Bus Control Register TCNTL, Transmit/Receive Control Register RTSTAT Receive/Transmit Status Register TEC, Transmit Error Count Register REC, Receive Error Count Register PLATST, CAN Bit Stream Processor Test Register UART Transmit Buffer (TBUF) UART Receive Buffer (RBUF) UART Control Status (ENU) UART Receive Control Status (ENUR) UART Interrupt and Clock (ENUI) UART Baud Register (BAUD) UART Prescaler Register (PSR) Reserved for UART Timer T2 Lower Byte (TMR2LO) Timer T2 Upper Byte (TMR2HI) Timer T2 Autoload Register T2RA Lower Byte (T2RALO) Timer T2 Autoload Register T2RA Upper Byte (T2RAHI) Timer T2 Autoload Register T2RB Lower Byte (T2RBLO) Timer T2 Autoload Register T2RB Upper Byte (T2RBHI) Timer T2 Control Register (T2CNTRL) WATCHDOG Service Register (Reg:WDSVR) LMIWU Edge Select Register (LWKEDG) LMIWU Enable Register (LWKEN) LLMIWU Pending Register (LWKPND) www.national.com COP87L88RB/COP87L89RB Memory Map Address 00CB 00CC 00CD to 00CE 00CF 00D0 00D1 00D2 00D3 00D4 00D5 00D6 00D7 00D8 00D9 00DA 00DB 00DC 00DD to 00DF 00E0 to 00E5 00E6 00E7 00E8 00E9 00EA 00EB 00EC 00ED 00EE 00EF (Continued) Contents A/D Converter Control Register (Reg:ENAD) A/D Converter Result Register (Reg:ADRSLT) Reserved IDLE Timer Control Register (Reg:ITMR) PORTLD, Port L Data Register PORTLC, Port L Configuration Register PORTLP, Port L Input Pins (Read Only) Reserved for Port L PORTGD, Port G Data Register PORTGC, Port G Configuration Register PORTGP, Port G Input Pins (Read Only) Port I Input Pins (Read Only) Port CD, Port C Data Register Port CC, Port C Configuration Register Port CP, Port C Input Pins (Read Only) Reserved for Port C Port D Reserved for Port D Reserved for EE Control Registers Timer T1 Autoload Register T1RB Lower Byte (T1BRLO) Timer T1 Autoload Register T1RB Upper Byte (T1BRHI) ICNTRL Register MICROWIRE/PLUS Shift Register (SOIR) Timer T1 Lower Byte (TMR1LO) Timer T1 Upper Byte (TMR1HI) Timer T1 Autoload Register T1RA Lower Byte (T1RALO) Timer T1 Autoload Register T1RA Upper Byte (T1RAHI) CNTRL, Control Register PSW, Processor Status Word Register Address 00F0 to 00FB 00FC 00FD 00FE 00FF 0100 to 013F Contents On-Chip RAM Mapped as Registers X Register SP Register B Register S Register On-Chip RAM Bytes (64 Bytes) Reading memory locations 0070H–007FH will return all ones. Reading unused memory locations 00xxH–00xxH will return undefined data. Reading memory locations from other Segments (i.e. segment 2, segment 3, ...etc.) will return undefined data. Addressing Modes There are ten addressing modes, six for operand addressing and four for transfer of control. OPERAND ADDRESSING MODES Register Indirect This is the “normal” addressing mode. The operand is the data memory addressed by the B pointer or X pointer. Register Indirect (with auto post increment or decrement of pointer) This addressing mode is used with the LD and X instructions. The operand is the data memory addressed by the B pointer or X pointer. This is a register indirect mode that automatically post increments or decrements the B or X register after executing the instruction. Direct The instruction contains an 8-bit address field that directly points to the data memory for the operand. Immediate The instruction contains an 8-bit immediate field as the operand. Short Immediate This addressing mode is used with the Load B Immediate instruction. The instruction contains a 4-bit immediate field as the operand. Indirect This addressing mode is used with the LAID instruction. The contents of the accumulator are used as a partial address (lower 8 bits of PC) for accessing a data operand from the program memory. TRANSFER OF CONTROL ADDRESSING MODES Relative This mode is used for the JP instruction, with the instruction field being added to the program counter to get the new program location. JP has a range from −31 to +32 to allow a 1-byte relatie jump (JP + 1 is implemented by a NOP instruction). There are no “pages” when using JP, since all 15 bits of PC are used. 62 www.national.com COP87L88RB/COP87L89RB Addressing Modes Absolute (Continued) Instruction Set Register and Symbol Definition Registers A B X SP PC PU PL C HC GIE VU VL 8-Bit Accumulator Register 8-Bit Address Register 8-Bit Address Register 8-Bit Stack Pointer Register 15-Bit Program Counter Register Upper 7 Bits of PC Lower 8 Bits of PC 1 Bit of PSW Register for Carry 1 Bit of PSW Register for Half Carry 1 Bit of PSW Register for Global Interrupt Enable Interrupt Vector Upper Byte Interrupt Vector Lower Byte Symbols [B] [X] MD Mem Meml Imm Reg Bit ← Memory Indirectly Addressed by B Register Memory Indirectly Addressed by X Register Direct Addressed Memory Direct Addressed Memory or [B] Direct Addressed Memory or [B] or Immediate Data 8-Bit Immediate Data Register Memory: Addresses F0 to FF (Includes B, X and SP) Bit Number (0 to 7) Loaded with Exchanged with The mode is used with the JMP and JSR instructions, with the instruction field of 12 bits replacing the lower 12 bits of the program counter (PC). This allows jumping to any location in the current 4k program memory segment. Absolute Long This mode is used with the JMPL and JSRL instructions, with the instruction field of 15 bits replacing the entire 15 bits of the program counter (PC). This allows jumping to any location up to 32k in the program memory space. Indirect This mode is used with the JID instruction. The contents of the accumulator are used as a partial address (lower 8 bits of PC) for accessing a location in the program memory. The contents of this program memory location serve as a partial address (lower 8 bits of PC) for the jump to the next instruction. Note: The VIS is a special case of the Indirect Transfer of Control addressing mode, where the double byte vector associated with the interrupt is transferred from adjacent addresses in the program memory into the program counter (PC) in order to jump to the associated interrupt service routine. ↔ 63 www.national.com COP87L88RB/COP87L89RB Instruction Set INSTRUCTION SET ADD ADC SUBC AND ANDSZ OR XOR IFEQ IFEQ IFNE IFGT IFBNE DRSZ SBIT RBIT IFBIT RPND X X LD LD LD LD LD X X LD LD LD CLR INC DEC LAID DCOR RRC RLC SWAP SC RC IFC IFNC POP PUSH VIS JMPL JMP JP Addr. Addr. Disp. A A A A A A A,Mem A,[X] A,Meml A,[X] B,Imm Mem,Imm Reg,Imm A, [B] A, [X] A, [B] A,[X] [B],Imm A A A A,Meml A,Meml A,Meml A,Meml A,Imm A,Meml A,Meml MD,Imm A,Meml A,Meml A,Meml # Reg #,Mem #,Mem #,Mem (Continued) ADD ADD with Carry Subtract with Carry Logical AND Logical AND Immed., Skip if Zero Logical OR Logical EXclusive OR IF EQual IF EQual IF Not Equal IF Greater Than IF B Not Equal Decrement Reg., Skip if Zero Set BIT Reset BIT IF BIT Reset PeNDing Flag EXchange A with Memory EXchange A with Memory [X] LoaD A with Memory LoaD A with Memory [X] LoaD B with Immed. LoaD Memory Immed. LoaD Register Memory Immed. EXchange A with Memory [B] EXchange A with Memory [X] LoaD A with Memory [B] LoaD A with Memory [X] LoaD Memory [B] Immed. CLeaR A INCrement A DECrement A Load A InDirect from ROM Decimal CORrect A Rotate A Right thru C Rotate A Left thru C SWAP nibbles of A Set C Reset C IF C IF Not C POP the stack into A PUSH A onto the stack Vector to Interrupt Service Routine Jump absolute Long Jump absolute Jump relative short A← A + Meml A← A + Meml + C, C← Carry, HC← Half Carry, A← A − MemI + C, C← Carry, HC← Half Carry A← A and Meml Skip next if (A and Imm) = 0 A← A or Meml A← A xor Meml Compare MD and Imm, Do next if MD = Imm Compare A and Meml, Do next if A = Meml Compare A and Meml, Do next if A ≠ Meml Compare A and Meml, Do next if A > Meml Do next if lower 4 bits of B ≠ Imm Reg← Reg − 1, Skip if Reg = 0 1 to bit, Mem (bit = 0 to 7 immediate) 0 to bit, Mem If bit in A or Mem is true do next instruction Reset Software Interrupt Pending Flag A↔Mem A↔[X] A←Meml A←[X] B← Imm Mem← Imm Reg← Imm A↔[B], (B← B 1) A↔[X], (X← X 1) A←[B], (B←B 1) A← [X], (X← X 1) [B]← Imm, (B← B 1) A←0 A←A + 1 A←A − 1 A← ROM (PU,A) A← BCD correction of A (follows ADC, SUBC) C→A7 → …→ A0 →C C← A7 ← … ←A0 ← C A7…A4↔A3…A0 C←1, HC← 1 C←0, HC←0 IF C is true, do next instruction If C is not true, do next instruction SP← SP + 1, A←[SP] [SP]← A, SP← SP − 1 PU←[VU], PL← [VL] PC←ii (ii = 15 bits, 0 to 32k) PC9…0← i (i = 12 bits) PC←PC + r (r is −31 to +32, except 1) www.national.com 64 COP87L88RB/COP87L89RB Instruction Set JSRL JSR JID RET RETSK RETI INTR NOP Addr. Addr. (Continued) INSTRUCTION SET (Continued) Jump SubRoutine Long Jump SubRoutine Jump InDirect RETurn from subroutine RETurn and SKip RETurn from Interrupt Generate an Interrupt No OPeration [SP]← PL, [SP−1]← PU,SP−2, PC← ii [SP]← PL, [SP−1]← PU,SP−2, PC9…0← i PL← ROM (PU,A) SP + 2, PL← [SP], PU← [SP−1] SP + 2, PL← [SP],PU← [SP−1] SP + 2, PL ← [SP],PU← [SP−1],GIE← 1 [SP]← PL, [SP−1]← PU, SP−2, PC← 0FF PC← PC + 1 65 www.national.com COP87L88RB/COP87L89RB Instruction Set (Continued) Instructions Using A and C CLRA INCA DECA LAID DCORA RRCA RLCA SWAPA SC RC IFC IFNC PUSHA POPA ANDSZ 1/1 1/1 1/1 1/3 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/3 1/3 2/2 INSTRUCTION EXECUTION TIME Most instructions are single byte (with immediate addressing mode instructions taking two bytes). Most single byte instructions take one cycle time to execute. Skipped instructions require x number of cycles to be skipped, where x equals the number of bytes in the skipped instruction opcode. See the BYTES and CYCLES per INSTRUCTION table for details. Bytes and Cycles per Instruction The following table shows the number of bytes and cycles for each instruction in the format of byte/cycle. Arithmetic and Logic Instructions [B] ADD ADC SUBC AND OR XOR IFEQ IFGT IFBNE DRSZ SBIT RBIT IFBIT RPND 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/3 3/4 3/4 3/4 Direct 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Immed. 2/2 2/2 2/2 2/2 2/2 2/2 2/2 2/2 Transfer of Control Instructions JMPL JMP JP JSRL JSR JID VIS RET RETSK RETI INTR NOP 3/4 2/3 1/3 3/5 2/5 1/3 1/5 1/5 1/5 1/5 1/7 1/1 Memory Transfer Instructions Register Indirect [B] X A, (Note *NO TARGET FOR FNXref NS13180*) LD A, (Note 24) LD B, Imm LD B, Imm LD Mem, Imm LD Reg, Imm IFEQ MD, Imm Note 24: = Register Indirect Direct 2/3 Immed. Auto Incr. and Decr. [B+, B−] 1/2 [X+, X−] 1/3 [X] 1/3 1/1 1/1 1/3 2/3 2/2 1/1 2/3 1/2 1/3 (IF B < 16) (IF B > 15) 2/2 3/3 2/3 3/3 2/2 > Memory location addressed by B or X or directly. www.national.com 66 Opcode Table Upper Nibble D DRSZ 0F0 DRSZ 0F1 DRSZ 0F2 DRSZ 0F3 DRSZ 0F4 DRSZ 0F5 DRSZ 0F6 DRSZ 0F7 * NOP IFNE A,[B] LD A,[X+] LD A,[X−] LD Md,#i DIR LD A,[X] * * LD B,#i LD A,[B] LD [B],#i JSRL LD A,Md RETSK RET RETI JMPL X A,Md POPA SBIT 4,[B] SBIT 5,[B] SBIT 6,[B] SBIT 7,[B] LD A,[B−] LD [B−],#i DECA SBIT 3,[B] RBIT 3,[B] RBIT 4,[B] RBIT 5,[B] RBIT 6,[B] RBIT 7,[B] LD A,[B+] LD [B+],#i INCA SBIT 2,[B] RBIT 2,[B] IFEQ Md,#i IFNE A,#i IFNC SBIT 1,[B] RBIT 1,[B] LD B,#06 LD B,#05 LD B,#04 LD B,#03 LD B,#02 LD B,#01 LD B,#00 RLCA LD A,#i IFC SBIT 0,[B] RBIT 0,[B] LD B,#07 * OR A,#i OR A,[B] IFBIT PUSHA 7,[B] LD B,#08 DRSZ 0F8 DRSZ 0F9 DRSZ 0FA DRSZ 0FB DRSZ 0FC DRSZ 0FD DRSZ 0FE DRSZ 0FF IFBNE 7 IFBNE 8 IFBNE 9 IFBNE 0A IFBNE 0B IFBNE 0C IFBNE 0D IFBNE 0E IFBNE 0F X A,[X] X A,[B] XOR A,#i XOR A,[B] IFBIT DCORA 6,[B] LD B,#09 IFBNE 6 RPND JID AND A,#i AND A,[B] IFBIT SWAPA LD 5,[B] B,#0A IFBNE 5 JSR x500–x5FF JSR x600–x6FF JSR x700–x7FF JSR x800–x8FF JSR x900–x9FF VIS LAID ADD A,#i ADD A,[B] IFBIT 4,[B] CLRA LD B,#0B IFBNE 4 JSR x400–x4FF X A,[X−] X A,[B−] IFGT A,#i IFGT A,[B] IFBIT 3,[B] * LD B,#0C IFBNE 3 JSR x300–x3FF X A,[X+] X A,[B+] IFEQ A,#i IFEQ A,[B] IFBIT 2,[B] * LD B,#0D IFBNE 2 JSR x200–x2FF * SC SUBC A, #i SUBC A,[B] IFBIT 1,[B] * LD B,#0E IFBNE 1 JSR x100–x1FF JMP JP+18 JP+2 x100–x1FF JMP JP+19 JP+3 x200–x2FF JMP JP+20 JP+4 x300–x3FF JMP JP+21 JP+5 x400–x4FF JMP JP+22 JP+6 x500–x5FF JMP JP+23 JP+7 x600–x6FF JMP JP+24 JP+8 x700–x7FF JMP JP+25 JP+9 x800–x8FF RRCA RC ADC A,#i ADC A,[B] IFBIT ANDSZ 0,[B] A, #i LD B,#0F IFBNE 0 JSR x000–x0FF JMP JP+17 INTR x000–x0FF 0 1 2 3 4 5 6 7 8 JMP JP+26 JP+10 9 x900–x9FF JSR JMP JP+27 JP+11 A xA00–xAFF xA00–xAFF JSR JMP JP+28 JP+12 B xB00–xBFF xB00–xBFF JSR JMP JP+29 JP+13 C xC00–xCFF xC00–xCFF JSR JMP JP+30 JP+14 D xD00–xDFF xD00–xDFF JSR JMP JP+31 JP+15 E xE00–xEFF xE00–xEFF JSR JMP JP+32 JP+16 F xF00–xFFF xF00–xFFF C B A 9 8 7 6 5 4 3 2 1 0 F E JP−15 JP−31 LD 0F0, #i JP−14 JP−30 LD 0F1, #i JP−13 JP−29 LD 0F2, #i JP−12 JP−28 LD 0F3, #i JP−11 JP−27 LD 0F4, #i JP−10 JP−26 LD 0F5, #i JP−9 JP−25 LD 0F6, #i JP−8 JP−24 LD 0F7, #i JP−5 JP−21 LD 0FA, #i JP−4 JP−20 LD 0FB, #i JP−3 JP−19 LD 0FC, #i JP−2 JP−18 LD 0FD, #i JP−1 JP−17 LD 0FE, #i JP−0 JP−16 LD 0FF, #i COP87L88RB/COP87L89RB www.national.com Where, i is the immediate data Md is a directly addressed memory location * is an unused opcode The opcode 60 Hex is also the opcode for IFBIT #i,A Lower Nibble 67 JP−7 JP−23 LD 0F8, #i JP−6 JP−22 LD 0F9, #i COP87L88RB/COP87L89RB Development Tools Support OVERVIEW National is engaged with an international community of independent 3rd party vendors who provide hardware and software development tool support. Through National’s interaction and guidance, these tools cooperate to form a choice of solutions that fits each developer’s needs. This section provides a summary of the tool and development kits currently available. Up-to-date information, selection guides, free tools, demos, updates, and purchase information can be obtained at our web site at: www.national.com/cop8. SUMMARY OF TOOLS COP8 Evaluation Tools • cludes BCLIDE (Byte Craft Limited Integrated Development Environment) for Win32, editor, optimizing C CrossCompiler, macro cross assembler, BC-Linker, and MetaLink tools support. (DOS/SUN versions available; Compiler is installable under WCOP8 IDE; Compatible with DriveWay COP8). EWCOP8-KS: Very Low cost ANSI C-Compiler and Embedded Workbench from IAR (Kickstart version: COP8Sx/Fx only with 2k code limit; No FP). A fully integrated Win32 IDE, ANSI C-Compiler, macro assembler, editor, linker, Liberian, C-Spy simulator/debugger, PLUS MetaLink EPU/DM emulator support. EWCOP8-AS: Moderately priced COP8 Assembler and Embedded Workbench from IAR (no code limit). A fully integrated Win32 IDE, macro assembler, editor, linker, librarian, and C-Spy high-level simulator/debugger with I/O and interrupts support. (Upgradeable with optional C-Compiler and/or MetaLink Debugger/Emulator support). EWCOP8-BL: Moderately priced ANSI C-Compiler and Embedded Workbench from IAR (Baseline version: All COP8 devices; 4k code limit; no FP). A fully integrated Win32 IDE, ANSI C-Compiler, macro assembler, editor, linker, librarian, and C-Spy high-level simulator/debugger. (Upgradeable; CWCOP8-M MetaLink tools interface support optional). EWCOP8: Full featured ANSI C-Compiler and Embedded Workbench for Windows from IAR (no code limit). A fully integrated Win32 IDE, ANSI C-Compiler, macro assembler, editor, linker, librarian, and C-Spy high-level simulator/debugger. (CWCOP8-M MetaLink tools interface support optional). • • COP8–NSEVAL: Free Software Evaluation package for Windows. A fully integrated evaluation environment for COP8, including versions of WCOP8 IDE (Integrated Development Environment), COP8-NSASM, COP8-MLSIM, COP8C, DriveWay™ COP8, Manuals, and other COP8 information. COP8–MLSIM: Free Instruction Level Simulator tool for Windows. For testing and debugging software instructions only (No I/O or interrupt support). COP8–EPU: Very Low cost COP8 Evaluation & Programming Unit. Windows based evaluation and hardware-simulation tool, with COP8 device programmer and erasable samples. Includes COP8-NSDEV, Driveway COP8 Demo, MetaLink Debugger, I/O cables and power supply. COP8–EVAL-ICUxx: Very Low cost evaluation and design test board for COP8ACC and COP8SGx Families, from ICU. Real-time environment with add-on A/D, D/A, and EEPROM. Includes software routines and reference designs. • • • • • Manuals, Applications Notes, Literature: Available free from our web site at: www.national.com/cop8. COP8 Integrated Software/Hardware Design Development Kits • EWCOP8-M: Full featured ANSI C-Compiler and Embedded Workbench for Windows from IAR (no code limit). A fully integrated Win32 IDE, ANSI C-Compiler, macro assembler, editor, linker, librarian, C-Spy high-level simulator/debugger, PLUS MetaLink debugger/hardware interface (CWCOP8-M). COP8 Productivity Enhancement Tools • • • COP8-EPU: Very Low cost Evaluation & Programming Unit. Windows based development and hardwaresimulation tool for COPSx/xG families, with COP8 device programmer and samples. Includes COP8-NSDEV, Driveway COP8 Demo, MetaLink Debugger, cables and power supply. WCOP8 IDE: Very Low cost IDE (Integrated Development Environment) from KKD. Supports COP8C, COP8NSASM, COP8-MLSIM, DriveWay COP8, and MetaLink debugger under a common Windows Project Management environment. Code development, debug, and emulation tools can be launched from the project window framework. DriveWay-COP8: Low cost COP8 Peripherals Code Generation tool from Aisys Corporation. Automatically generates tested and documented C or Assembly source code modules containing I/O drivers and interrupt handlers for each on-chip peripheral. Application specific code can be inserted for customization using the integrated editor. (Compatible with COP8-NSASM, COP8C, and WCOP8 IDE.) COP8-UTILS: Free set of COP8 assembly code examples, device drivers, and utilities to speed up code development. COP8-MLSIM: Free Instruction Level Simulator tool for Windows. For testing and debugging software instructions only (No I/O or interrupt support). • COP8-DM: Moderate cost Debug Module from MetaLink. A Windows based, real-time in-circuit emulation tool with COP8 device programmer. Includes COP8-NSDEV, DriveWay COP8 Demo, MetaLink Debugger, power supply, emulation cables and adapters. COP8 Development Languages and Environments • • COP8-NSASM: Free COP8 Assembler v5 for Win32. Macro assembler, linker, and librarian for COP8 software development. Supports all COP8 devices. (DOS/Win16 v4.10.2 available with limited support). (Compatible with WCOP8 IDE, COP8C, and DriveWay COP8). COP8-NSDEV: Very low cost Software Development Package for Windows. An integrated development environment for COP8, including WCOP8 IDE, COP8NSASM, COP8-MLSIM. COP8C: Moderately priced C Cross-Compiler and Code Development System from Byte Craft (no code limit). In68 • • • • www.national.com COP87L88RB/COP87L89RB Development Tools Support (Continued) COP8 Real-Time Emulation Tools COP8 Device Programmer Support • • MetaLink’s EPU and Debug Module include development device programming capability for COP8 devices. Third-party programmers and automatic handling equipment cover needs from engineering prototype and pilot production, to full production environments. Factory programming available for high-volume requirements. • COP8-DM: MetaLink Debug Module. A moderately priced real-time in-circuit emulation tool, with COP8 device programmer. Includes COP8-NSDEV, DriveWay COP8 Demo, MetaLink Debugger, power supply, emulation cables and adapters. IM-COP8: MetaLink iceMASTER ® . A full featured, realtime in-circuit emulator for COP8 devices. Includes MetaLink Windows Debugger, and power supply. Packagespecific probes and surface mount adaptors are ordered separately. • • TOOLS ORDERING NUMBERS FOR THE COP87L88EB/RB FAMILY DEVICES Vendor National Tools COP8-NSEVAL COP8-NSASM COP8-MLSIM COP8-NSDEV COP8-EPU COP8-DM Development Devices OTP Programming Adapters IM-COP8 MetaLink COP8-EPU COP8-DM Order Number COP8-NSEVAL COP8-NSASM COP8-MLSIM COP8-NSDEV Not available for this device Contact MetaLink COP87L88EB/RB EDI -44+68PL/40DZAL-W-COP888EB Contact MetaLink Not available for this device DM4-COP8-888EB (10 MHz), plus PS-10, plus DM-COP8/xxx (ie. 44P) EDI -44/68PL/40DZAL-W-COP888EB IM-COP8-AD-464 (-220) (10 MHz maximum) PC-888EB44P5-AD-10 PC-888EB68P5-AD-10 ICU KKD IAR Byte Craft Aisys COP8-EVAL WCOP8-IDE EWCOP8-xx COP8C DriveWay COP8 Not available for this device WCOP8-IDE See summary above COP8C DriveWay COP8 Contact vendors VL L-H M L L-H Included in EPU and DM Included all software and manuals Included all software and manuals Included all software and manuals For approved programmer listings and vendor information, go to our OTP support page at: www.national.com/cop8 M Included p/s (PS-10), target cable of choice (PLCC; i.e. DM-COP8/40P), EDI 44/68 PLCC OTP adapter For programming 44/68 PLCC VL L 16k or 32k OTP devices For programming 44/68 PLCC on any programmer. Contact EDI Cost Free Free Free VL Web site download Included in EPU and DM. Web site download Included in EPU and DM. Web site download Included in EPU and DM. Order CD from website Notes OTP Programming Adapters IM-COP8 L H Base unit 10 MHz; -220 = 220V; add probe card (required) and target adapter (if needed); included software and manuals 10 MHz 44 PLCC probe card; 2.5V to 6.0V 10 MHz 68 PLCC probe card; 2.5V to 6.0V IM Probe Card M M OTP Programmers Cost: Free; VL = < $100; L = $100 - $300; M = $300 - $1k; H = $1k - $3k; VH = $3k - $5k 69 www.national.com COP87L88RB/COP87L89RB Development Tools Support WHERE TO GET TOOLS (Continued) Tools are ordered directly from the following vendors. Please go to the vendor’s web site for current listings of distributors. Vendor Aisys Home Office U.S.A.: Santa Clara, CA 1-408-327-8820 fax: 1-408-327-8830 Byte Craft U.S.A. 1-519-888-6911 fax: 1-519-746-6751 IAR Sweden: Uppsala +46 18 16 78 00 fax: +46 18 16 78 38 www.iar.se info@iar.se info@iar.com info@iarsys.co.uk info@iar.de U.S.A.: San Francisco 1-415-765-5500 fax: 1-415-765-5503 U.K.: London +44 171 924 33 34 fax: +44 171 924 53 41 Germany: Munich +49 89 470 6022 fax: +49 89 470 956 ICU Sweden: Polygonvaegen +46 8 630 11 20 fax: +46 8 630 11 70 KKD MetaLink Denmark: U.S.A.: Chandler, AZ 1-800-638-2423 fax: 1-602-926-1198 www.icu.se support@icu.se support@icu.ch www.kkd.dk www.metaice.com sales@metaice.com support@metaice.com bbs: 1-602-962-0013 www.metalink.de National U.S.A.: Santa Clara, CA 1-800-272-9959 fax: 1-800-737-7018 www.national.com/cop8 support@nsc.com europe.support@nsc.com Germany: Kirchseeon 80-91-5696-0 fax: 80-91-2386 islanger@metalink.de Distributors Worldwide Europe: +49 (0) 180 530 8585 fax: +49 (0) 180 530 8586 Distributors Worldwide Switzeland: Hoehe +41 34 497 28 20 fax: +41 34 497 28 21 www.bytecraft.com info@bytecraft.com Distributors Electronic Sites www.aisysinc.com info @aisysinc.com Other Main Offices Distributors The following companies have approved COP8 programmers in a variety of configurations. Contact your local office or distributor. You can link to their web sites and get the latest listing of approved programmers from National’s COP8 OTP Support page at: www.national.com/cop8. Advantech; Advin; BP Microsystems; Data I/O; Hi-Lo Systems; ICE Technology; Lloyd Research; Logical Devices; MQP; Needhams; Phyton; SMS; Stag Programmers; System General; Tribal Microsystems; Xeltek. Customer Support Complete product information and technical support is available from National’s customer response centers, and from our on-line COP8 customer support sites. www.national.com 70 COP87L88RB/COP87L89RB Physical Dimensions inches (millimeters) unless otherwise noted 44-Lead Molded Plastic Leaded Chip Carrier Order Number COP87L88EBV-XE or COP87L88RBV-XE NS Plastic Chip Package Number V44A 68-Lead Molded Plastic Leaded Chip Carrier Order Number COP87L89EBV-XE or COP87L89RBV-XE NS Plastic Chip Package Number V68A 71 www.national.com COP87L88EB/RB Family, 8-Bit CMOS OTP Microcontrollers with 16k or 32k Memory, CAN Interface, 8-Bit A/D, and USART Notes LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com www.national.com National Semiconductor Europe Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 87 90 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: ap.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Email: nsj.crc@jksmtp.nsc.com Fax: 81-3-5639-7507 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.