COP8ACC7XXX9

COP8ACC7 8-Bit CMOS OTP Microcontroller with 16k Memory and High Resolution A/D May 1999 COP8ACC7 8-Bit CMOS OTP Microcontroller with 16k Memory and High Resolution A/D General Description The COP8ACC7 OTP (One Time Programmable) microcontrollers are highly integrated COP8™ Feature core devices with 16k memory and advanced features including a HighResolution A/D. This multi-chip CMOS device is suited for applications requiring a full featured controller with a high resolution A/D (only one external capacitor required), and for pre-production devices for a ROM design. Pin and software compatible (different VCC range) 4k ROM versions are available (COPACC5). Erasable windowed versions are available for use with a range of COP8 software and hardware development tools. Device COP8ACC7xxx9 COP8ACC7xxx8 Memory (bytes) 16k OTP EPROM 16k OTP EPROM RAM (bytes) 128 128 Family features include an 8-bit memory mapped architecture, 4 MHz CKI with 2.5 µs instruction cycle, two external clock options (–XE = Crystal; –RE = RC), 6 channel A/D with 12-bit resolution, analog capture timer, analog current source and VCC/2 reference, one multi-function 16-bit timer/ counter, MICROWIRE/PLUS™ serial I/O, two power saving HALT/IDLE modes, MIWU, high current outputs, software selectable I/O options, WATCHDOG™ timer and Clock Monitor, 2.7V to 5.5V operation, program code security, and 20/28 pin packages. Device included in this datasheet is: I/O Pins 15/23 15/23 Packages 20 SOIC, 28 DIP/SOIC 20 SOIC, 28 DIP/SOIC Temperature 0 to +70˚C -40 to +85˚C Key Features n Analog Function Block with 12-bit A/D including: — Analog comparator with seven input muxes — Constant Current Source and VCC/2 Reference — 16-bit capture timer (upcounter) clocked from CKI with auto reset on timer startup n Quiet design (reduced radiated emissions) n 4096 bytes on-board OTP EPROM with security feature n 128 bytes on-board RAM CPU/Instruction Set Features n 2.5 µs instruction cycle time n Eight multi-source vectored interrupt servicing: — External Interrupt — Idle Timer T0 — Timer T1 associated Interrupts — MICROWIRE/PLUS — Multi-Input Wake Up — Software Trap — Default VIS — A/D (Capture Timer) n 8-bit Stack Pointer (SP) — stack in RAM n Two 8-bit Registers Indirect Data Memory Pointers (B and X) Additional Peripheral Features n Idle Timer n One 16-bit timer with two 16-bit registers supporting: — Processor Independent PWM mode — External Event counter mode — Input Capture mode n Multi-Input Wake-Up (MIWU) with optional interrupts n WATCHDOG and clock monitor logic n MICROWIRE/PLUS serial I/O with programmable shift clock-polarity Fully Static CMOS n Two power saving modes: HALT and IDLE n Temperature ranges: 0˚C to +70˚C, −40˚C to +85˚C n Available with Crystal (-XE) or R/C (-RE) oscillator Development System n Emulation device for COP8ACC5 n Real time emulation and full program debug offered by MetaLink ® development system I/O Features n Software selectable I/O options (Push-Pull Output, Weak Pull-Up Input, High Impedance Input) n High current outputs n Schmitt Trigger inputs on ports G and L n Packages: — 28 DIP/SO with 23 I/O pins — 20 SO with 15 I/O pins Applications n Battery Chargers n Appliances n Data Acquisition systems Driveway™ is a trademark of Aisys Intelligent Systems. COP8™, MICROWIRE™, MICROWIRE/PLUS™, and WATCHDOG™ are trademarks of National Semiconductor Corporation. TRI-STATE ® is a registered trademark of National Semiconductor Corporation. iceMASTER ® is a registered trademark of MetaLink Corporation. © 1999 National Semiconductor Corporation DS012869 www.national.com Block Diagram DS012869-1 FIGURE 1. Block Diagram Connection Diagrams DS012869-3 Top View Order Number COP8ACC720M9–XE/RE or COP8ACC720N8–XE/RE See NS Molded Package Number M20B DS012869-2 Note: -X Crystal Oscillator -R R/C Oscillator -E Halt Enable Top View Order Number COP8ACC728N9–XE/RE or COP8ACC728N8–XE/RE See NS Molded Package Number N28A Order Number COP8ACC728M9–XE/RE or COP8ACC728M8–XE/RE See NS Molded Package Number M28B FIGURE 2. Connection Diagrams www.national.com 2 Connection Diagrams Port L4 L5 L6 L7 G0 G1 G2 G3 G4 G5 G6 G7 D0 D1 D2 D3 I0 I1 I2 I3 I4 I5 I6 I7 VCC GND CKI RESET I/O I/O I/O I/O I/O WDOUT I/O I/O I/O I/O I I/CKO O O O O I I I I I I I I Type (Continued) Pinouts for 28-Pin, 20-Pin Packages Alt. Fun MIWU MIWU MIWU MIWU INT T1B T1A SO SK SI HALT Restart Alt. Fun Ext. Int. Ext. Int. Ext. Int. Ext. Int. 28-Pin DIP/SO 4 5 6 7 23 24 25 26 27 28 1 2 11 12 13 14 Analog CH1 ISRC Analog CH2 Analog CH3 Analog CH4 Analog CH5 Analog CH6 COUT 15 16 17 18 19 20 21 22 9 8 3 10 5 4 3 6 10 11 12 13 14 15 16 17 18 19 20 1 2 7 8 9 20-Pin SO Ordering Information DS012869-39 FIGURE 3. Part Numbering Scheme 3 www.national.com Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) Voltage at Any Pin 7V −0.3V to VCC +0.3V Total Current into VCC Pin (Source) Total Current out of GND Pin (Sink) Storage Temperature Range 100 mA 110 mA −65˚C to +140˚C Note 1: Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings. DC Electrical Characteristics 0˚C ≤ TA ≤ +70˚C unless otherwise specified Parameter Operating Voltage Power Supply Ripple (Note 2) Supply Current (Note 3) CKI = 4 MHz CKI = 4 MHz CKI = 1 MHz HALT Current (Note 4) IDLE Current CKI = 4 MHz CKI = 1 MHz Input Levels (VIH, VIL) RESET Logic High Logic Low CKI, All Other Inputs Logic High Logic Low Hi-Z Input Leakage Input Pullup Current G and L Port Input Hysteresis Output Current Levels D Outputs Source Sink All Others Source (Weak Pull-Up Mode) Source (Push-Pull Mode) Sink (Push-Pull Mode) TRI-STATE ® Leakage Allowable Sink/Source Current per Pin D Outputs (Sink) All others Maximum Input Current without Latchup (Note 5) RAM Retention Voltage, Vr www.national.com Conditions Peak-to-Peak Min 2.7 Typ Max 5.5 0.1 VCC Units V V mA mA mA µA µA mA mA VCC = 5.5V, tC = 2.5 µs VCC = 4V, tC = 2.5 µs VCC = 4V, tC = 10 µs VCC = 5.5V, CKI = 0 MHz VCC = 4V, CKI = 0 MHz VCC = 5.5V, tC = 2.5 µs VCC = 4V, tC = 10 µs 9.5 6.5 5.4 VCC (the pins do not have source current when biased at a voltage below VCC). The effective resistance to VCC is 750Ω (typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14V. WARNING: Voltages in excess of 14V will cause damage to the pins. This warning excludes ESD transients. Note 6: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs. Note 7: Parameter characterized but not tested. Note 8: tC = Instruction Cycle Time. Conditions 2.7V ≤ VCC ≤ 4V 4V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 4V 4V ≤ VCC ≤ 5.5V 4V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 4V 4V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 4V RL = 2.2k, CL = 100 pF 4V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 4V 4V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 4V VCC ≥ 4V VCC ≥ 4V VCC ≥ 4V Min 2.5 1.0 7.5 3.0 200 500 60 150 Typ Max DC DC DC DC Units µs µs µs µs ns ns ns ns 0.7 1.75 1 2.5 20 56 220 1 1 1 1 1 µs µs µs µs ns ns ns tC tC tC tC µs 5 www.national.com Absolute Maximum Ratings (Note 9) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) Voltage at Any Pin 7V −0.3V to VCC +0.3V Total Current into VCC Pin (Source) Total Current out of GND Pin (Sink) Storage Temperature Range 100 mA 110 mA −65˚C to +140˚C Note 9: Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings. DC Electrical Characteristics −40˚C ≤ TA ≤ +85˚C unless otherwise specified Parameter Operating Voltage Power Supply Ripple (Note 10) Supply Current (Note 11) CKI = 4 MHz CKI = 4 MHz CKI = 1 MHz HALT Current (Note 12) IDLE Current CKI = 4 MHz CKI = 1 MHz Input Levels (VIH, VIL) RESET Logic High Logic Low CKI, All Other Inputs Logic High Logic Low Hi-Z Input Leakage Input Pullup Current G and L Port Input Hysteresis Output Current Levels D Outputs Source Sink All Others Source (Weak Pull-Up Mode) Source (Push-Pull Mode) Sink (Push-Pull Mode) TRI-STATE Leakage Allowable Sink/Source Current per Pin D Outputs (Sink) All others Maximum Input Current without Latchup (Note 13) RAM Retention Voltage, Vr www.national.com Conditions Peak-to-Peak VCC = 5.5V, tC = 2.5 µs VCC = 4V, tC = 2.5 µs VCC = 4V, tC = 10 µs VCC = 5.5V, CKI = 0 MHz VCC = 4V, CKI = 0 MHz VCC = 5.5V, tC = 2.5 µs VCC = 4V, tC = 10 µs Min 2.7 Typ Max 5.5 0.1 VCC 9.5 6.5 5.4 Units V V mA mA mA µA µA mA mA 5 x POWER SUPPLY RISE TIME FIGURE 6. Recommended Reset Circuit Figure 7 shows the Crystal and R/C Oscillator diagrams. CRYSTAL OSCILLATOR CKI and CKO can be connected to make a closed loop crystal (or resonator) controlled oscillator. Table 1 shows the component values required for various standard crystal values. TABLE 1. Crystal Oscillator Configuration, TA = 25˚C R1 (kΩ) 0 0 0 R2 (MΩ) 1 1 1 C1 (pF) 30 30 200 C2 (pF) 30–36 30–36 100–150 CKI Freq (MHz) 10 4 0.455 Conditions VCC = 5V VCC = 5V VCC = 5V Reset The RESET input when pulled low initializes the microcontroller. Initialization will occur whenever the RESET input is pulled low. Upon initialization, the data and configuration registers for ports L and G are cleared, resulting in these Ports being initialized to the TRI-STATE mode. Pin G1 of the G Port is an exception (as noted below) since pin G1 is dedicated as the WATCHDOG and/or Clock Monitor error output pin. Port D is set high. The PC, PSW, ICNTRL and CNTRL-control registers are cleared. The Comparator Select Register is cleared. The S register is initialized to zero. The Multi-Input Wakeup registers WKEN and WKEDG are cleared. Wakeup register WKPND is unknown. The stack pointer, SP, is initialized to 6F Hex. The device comes out of reset with both the WATCHDOG logic and the Clock Monitor detector armed, with the WATCHDOG service window bits set and the Clock Monitor bit set. The WATCHDOG and Clock Monitor circuits are inhibited during reset. The WATCHDOG service window bits being initialized high default to the maximum WATCHDOG service window of 64k tC clock cycles. The Clock Monitor bit being initialized high will cause a Clock Monitor error following reset if the clock has not reached the minimum specified frequency at the termination of reset. A Clock Monitor error will cause an active low error output on pin G1. This error output will continue until 16 tC-32 tC clock cycles following the clock frequency reaching the minimum specified value, at which time the G1 output will enter the TRI-STATE mode. The external RC network shown in Figure 6 should be used to ensure that the RESET pin is held low until the power supply to the chip stabilizes. WARNING: When the device is held in reset for a long time it will consume high current (typically about 7 mA). This is not true for the equivalent ROM device (COP8ACC5). www.national.com 12 R/C OSCILLATOR By selecting CKI as a single pin oscillator input, a single pin R/C oscillator circuit can be connected to it. CKO is available as a general purpose input, and/or HALT restart input. Note: Use of the R/C oscillator option will result in higher electromagnetic emissions. Table 2 shows the variation in the oscillator frequencies as functions of the component (R and C) values. TABLE 2. RC Oscillator Configuration, TA = 25˚C R (kΩ) 3.3 5.6 6.8 C (pF) 82 100 100 CKI Freq (MHz) 2.2 to 2.7 1.1 to 1.3 0.9 to 1.1 Instr. Cycle (µs) 3.7 to 4.6 7.4 to 9.0 8.8 to 10.8 Conditions VCC = 5V VCC = 5V VCC = 5V Note 18: 3k ≤ R ≤ 200k Note 19: 50 pF ≤ C ≤ 200 pF Oscillator Circuits (Continued) GIE Global interrupt enable (enables interrupts) The Half-Carry flag is also affected by all the instructions that affect the Carry flag. The SC (Set Carry) and R/C (Reset Carry) instructions will respectively set or clear both the carry flags. In addition to the SC and R/C instructions, ADC, SUBC, RRC and RLC instructions affect the Carry and Half Carry flags. ICNTRL Register (Address X'00E8) Reserved Bit 7 LPEN T0PND T0EN µWPND µWEN T1PNDB T1ENB Bit 0 The ICNTRL register contains the following bits: Reserved This bit is reserved and should be zero. DS012869-7 LPEN T0PND T0EN µWPND µWEN T1PNDB L Port Interrupt Enable (Multi-Input Wakeup/ Interrupt) Timer T0 Interrupt pending Timer T0 Interrupt Enable (Bit 12 toggle) MICROWIRE/PLUS interrupt pending Enable MICROWIRE/PLUS interrupt Timer T1 Interrupt Pending Flag for T1B capture edge Timer T1 Interrupt Enable for T1B Input capture edge DS012869-8 T1ENB FIGURE 7. Crystal and R/C Oscillator Diagrams Control Registers CNTRL Register (Address X'00EE) T1C3 Bit 7 T1C2 T1C1 T1C0 MSEL IEDG SL1 SL0 Bit 0 Timers The device contains a very versatile set of timers (T0 and T1). All timers and associated autoreload/capture registers power up containing random data. TIMER T0 (IDLE TIMER) The device supports applications that require maintaining real time and low power with the IDLE mode. This IDLE mode support is furnished by the IDLE timer T0, which is a 16-bit timer. The Timer T0 runs continuously at the fixed rate of the instruction cycle clock, tC. The user cannot read or write to the IDLE Timer T0, which is a count down timer. The Timer T0 supports the following functions: The Timer1 (T1) and MICROWIRE/PLUS control register contains the following bits: T1C3 Timer T1 mode control bit T1C2 Timer T1 mode control bit T1C1 Timer T1 mode control bit T1C0 Timer T1 Start/Stop control in timer modes 1 and 2, T1 Underflow Interrupt Pending Flag in timer mode 3 MSEL Selects G5 and G4 as MICROWIRE/PLUS signals SK and SO respectively IEDG External interrupt edge polarity select (0 = Rising edge, 1 = Falling edge) SL1 & SL0 Select the MICROWIRE/PLUS clock divide by (00 = 2, 01 = 4, 1x = 8) PSW Register (Address X'00EF) HC Bit 7 C T1PNDA T1ENA EXPND BUSY EXEN GIE Bit 0 The PSW register contains the following select bits: HC Half Carry Flag C Carry Flag T1PNDA Timer T1 Interrupt Pending Flag (Autoreload RA in mode 1, T1 Underflow in Mode 2, T1A capture edge in mode 3) T1ENA Timer T1 Interrupt Enable for Timer Underflow or T1A Input capture edge EXPND BUSY EXEN External interrupt pending MICROWIRE/PLUS busy shifting flag Enable external interrupt • Exit out of the Idle Mode (See Idle Mode description) • WATCHDOG logic (See WATCHDOG description) • Start up delay out of the HALT mode is a functional block diagram showing the structure of the IDLE Timer and its associated interrupt logic. Bits 11 through 15 of the ITMR register can be selected for triggering the IDLE Timer interrupt. Each time the selected bit underflows (every 4k, 8k, 16k, 32k or 64k instruction cycles), the IDLE Timer interrupt pending bit T0PND is set, thus generating an interrupt (if enabled), and bit 6 of the Port G data register is reset, thus causing an exit from the IDLE mode if the device is in that mode. In order for an interrupt to be generated, the IDLE Timer interrupt enable bit T0EN must be set, and the GIE (Global Interrupt Enable) bit must also be set. The T0PND flag and T0EN bit are bits 5 and 4 of the ICNTRL register, respectively. The interrupt can be used for any purpose. Typically, it is used to perform a task upon exit from the IDLE mode. For more information on the IDLE mode, refer to the Power Save Modes section. The Idle Timer period is selected by bits 0–2 of the ITMR register Bits 3–7 of the ITMR Register are reserved and should not be used as software flags. 13 www.national.com Timers (Continued) ITSEL2 ITSEL2 Bit 3 ITSEL1 ITSEL0 Bit 0 ITSEL1 1 X ITSEL0 1 X Idle Timer Period (Instruction Cycles) 32,768 65,536 ITMR Register (Address X’0xCF) Reserved Bit 7 0 1 TABLE 3. Idle Timer Window Length ITSEL2 0 0 0 ITSEL1 0 0 1 ITSEL0 0 1 0 Idle Timer Period (Instruction Cycles) 4,096 8,192 16,384 The ITMR register is cleared on Reset and the Idle Timer period is reset to 4,096 instruction cycles. Any time the IDLE Timer period is changed there is the possibility of generating a spurious IDLE Timer interrupt by setting the T0PND bit. The user is advised to disable IDLE Timer interrupts prior to changing the value of the ITSEL bits of the ITMR Register and then clear the T0PND bit before attempting to synchronize operation to the IDLE Timer. DS012869-9 FIGURE 8. Functional Block Diagram for Idle Timer T0 TIMER T1 The device has a powerful timer/counter block. The timer consists of a 16-bit timer, T1, and two supporting 16-bit autoreload/capture registers, R1A and R1B. The timer block has two pins associated with it, T1A and T1B. The pin T1A supports I/O required by the timer block, while the pin T1B is an input to the timer block. The powerful and flexible timer block allows the device to easily perform all timer functions with minimal software overhead. The timer block has three operating modes: Processor Independent PWM mode, External Event Counter mode, and Input Capture mode. The control bits T1C3, T1C2, and T1C1 allow selection of the different modes of operation. Mode 1. Processor Independent PWM Mode As the name suggests, this mode allows the device to generate a PWM signal with very minimal user intervention. The user only has to define the parameters of the PWM signal (ON time and OFF time). Once begun, the timer block will continuously generate the PWM signal completely independent of the microcontroller. The user software services the timer block only when the PWM parameters require updating. In this mode the timer T1 counts down at a fixed rate of tC. Upon every underflow the timer is alternately reloaded with the contents of supporting registers, R1A and R1B. The very first underflow of the timer causes the timer to reload from the register R1A. Subsequent underflows cause the timer to be reloaded from the registers alternately beginning with the register R1B. The T1 Timer control bits, T1C3, T1C2 and T1C1 set up the timer for PWM mode operation. shows a block diagram of the timer in PWM mode. The underflows can be programmed to toggle the T1A output pin. The underflows can also be programmed to generate interrupts. Underflows from the timer are alternately latched into two pending flags, T1PNDA and T1PNDB. The user must reset these pending flags under software control. Two control enable flags, T1ENA and T1ENB, allow the interrupts from the timer underflow to be enabled or disabled. Setting the timer enable flag T1ENA will cause an interrupt when a timer underflow causes the R1A register to be reloaded into the timer. Setting the timer enable flag T1ENB will cause an interrupt when a timer underflow causes the R1B register to be reloaded into the timer. Resetting the timer enable flags will disable the associated interrupts. Either or both of the timer underflow interrupts may be enabled. This gives the user the flexibility of interrupting once www.national.com 14 Timers (Continued) per PWM period on either the rising or falling edge of the PWM output. Alternatively, the user may choose to interrupt on both edges of the PWM output. Mode 2. External Event Counter Mode This mode is quite similar to the processor independent PWM mode previously described. The main difference is that the timer, T1, is clocked by the input signal from the T1A pin. The T1 timer control bits, T1C3, T1C2 and T1C1 allow the timer to be clocked either on a positive or negative edge from the T1A pin. Underflows from the timer are latched into the T1PNDA pending flag. Setting the T1ENA control flag will cause an interrupt when the timer underflows. In this mode the input pin T1B can be used as an independent positive edge sensitive interrupt input if the T1ENB control flag is set. The occurrence of a positive edge on the T1B input pin is latched into the T1PNDB flag. Figure 10 shows a block diagram of the timer in External Event Counter mode. Note: The PWM output is not available in this mode since the T1A pin is being used as the counter input clock. The trigger conditions can also be programmed to generate interrupts. The occurrence of the specified trigger condition on the T1A and T1B pins will be respectively latched into the pending flags, T1PNDA and T1PNDB. The control flag T1ENA allows the interrupt on T1A to be either enabled or disabled. Setting the T1ENA flag enables interrupts to be generated when the selected trigger condition occurs on the T1A pin. Similarly, the flag T1ENB controls the interrupts from the T1B pin. Underflows from the timer can also be programmed to generate interrupts. Underflows are latched into the timer T1C0 pending flag (the T1C0 control bit serves as the timer underflow interrupt pending flag in the Input Capture mode). Consequently, the T1C0 control bit should be reset when entering the Input Capture mode. The timer underflow interrupt is enabled with the T1ENA control flag. When a T1A interrupt occurs in the Input Capture mode, the user must check both the T1PNDA and T1C0 pending flags in order to determine whether a T1A input capture or a timer underflow (or both) caused the interrupt. Figure 11 shows a block diagram of the timer in Input Capture mode. Mode 3. Input Capture Mode The device can precisely measure external frequencies or time external events by placing the timer block, T1, in the input capture mode. In this mode, the timer T1 is constantly running at the fixed tC rate. The two registers, R1A and R1B, act as capture registers. Each register acts in conjunction with a pin. The register R1A acts in conjunction with the T1A pin and the register R1B acts in conjunction with the T1B pin. The timer value gets copied over into the register when a trigger event occurs on its corresponding pin. Control bits, T1C3, T1C2 and T1C1, allow the trigger events to be specified either as a positive or a negative edge. The trigger condition for each input pin can be specified independently. DS012869-11 FIGURE 10. Timer in External Event Counter Mode DS012869-10 FIGURE 9. Timer in PWM Mode DS012869-12 FIGURE 11. Timer in Input Capture Mode 15 www.national.com Timers (Continued) TIMER CONTROL FLAGS The control bits and their functions are summarized below. T1C3 Timer mode control T1C2 Timer mode control T1C1 T1C0 Timer mode control Timer Start/Stop control in Modes 1 and 2 (Processor Independent PWM and External Event Counter), where 1 = Start, 0 = Stop Timer Underflow Interrupt Pending Flag in Mode 3 (Input Capture) T1PNDA Timer Interrupt Pending Flag T1ENA Timer Interrupt Enable Flag 1 = Timer Interrupt Enabled 0 = Timer Interrupt Disabled T1PNDB Timer Interrupt Pending Flag T1ENB Timer Interrupt Enable Flag 1 = Timer Interrupt Enabled 0 = Timer Interrupt Disabled The timer mode control bits (T1C3, T1C2 and T1C1) are detailed below: Mode T1C3 1 1 1 0 2 0 0 T1C2 0 0 0 0 1 T1C1 1 0 0 1 0 Description PWM: T1A Toggle PWM: No T1A Toggle External Event Counter External Event Counter Captures: T1A Pos. Edge T1B Pos. Edge 1 1 0 Captures: T1A Pos. Edge 3 T1B Neg. Edge 0 1 1 Captures: T1A Neg. Edge T1B Neg. Edge 1 1 1 Captures: T1A Neg. Edge T1B Neg. Edge HIGH SPEED CAPTURE TIMER The device provides a 16-bit high-speed capture timer. The timer consists of a 16-bit up-counter that is clocked with the device clock input frequency (CKI) and an 8-bit control register. The 16-bit counter is mapped as two read/write 8-bit registers. This timer is specifically designed to be used in conjunction with the Analog Function Block (comparator, analog multiplexer, constant current source) to implement a low-cost, high-resolution, single-slope A/D. The timer is automatically stopped in the event of a capture to allow the software to read the timer value. Coming out of reset the counter is disabled (stopped) and reads all “0”. Setting the Capture Timer Run bit CAPRUN bit in the Capture Control Register (CAPCNTL) will start the counter. The counter will count up until a capture event (negative edge) is received. Upon a capture the counter will be stopped, the Capture Pending bit (CAPPND) is set, and the CAPRUN bit is automatically reset. If capture interrupts are enabled (CAPIEN = 1), the capture event will generate an interrupt. Setting the CAPRUN bit again by software will start a new counting cycle. If the Capture Mode bit is reset (CAPMOD = 0) the capture timer will be automatically initialized to all “0” with each setting of the CAPRUN bit. If CAPMOD = 1 www.national.com 16 Interrupt A Source Autoreload RA Autoreload RA Timer Underflow Timer Underflow Pos. T1A Edge or Timer Underflow Pos. T1A Edge or Timer Underflow Neg. T1A Edge or Timer Underflow Neg. T1A Edge or Timer Underflow Interrupt B Source Autoreload RB Autoreload RB Pos. T1B Edge Pos. T1B Edge Pos. T1B Edge Timer Counts On tC tC Pos. T1A Edge Pos. T1A Edge tC Neg. T1B Edge Neg. T1B Edge Neg. T1B Edge tC tC tC the timer will not be cleared when setting the CAPRUN bit, thus allowing the user’s software to pre-load the timer registers with any desired value. This mode can be used in conjunction with the timer’s overflow to implement for example a programmable delay counter. “CAPTURE MODE” is only active when the CAPRUN bit is set, i.e. any capture events received while the timer is stopped (CAPRUN = 0) will be ignored and will not cause the CAPPND bit to be set. The capture counter can also be stopped (frozen) by the user’s software resetting the CAPRUN bit. If the user program tries to set the CAPRUN bit at the same time that the hardware gets a capture event and tries to reset the CAPRUN bit, the hardware will have precedence. Should the counter overflow before a capture condition occurs, the Capture Overflow bit (CAPOVL) bit in the CAPCNTL register will be set. If Capture interrupts are enabled (CAPIEN = 1) an overflow will generate an interrupt. The user software should reset this bit before the next overflow occurs, otherwise subsequent overflow conditions cannot be detected. Timers (Continued) Capture Overflow interrupt and Capture Pending interrupt share the same interrupt vector. CAPCNTL Register (Address (X’CE) Reserved Bit 7-5 CAPMOD Bit 4 CAPRUN CAPOVL CAPPND CAPIEN Bit 0 The CAPCNTL register contains the following bits: Reserved These bits are reserved and must be zero. CAPMOD Reset Time. 0: reset timer to “0” when CAPRUN bit gets set 1: DO NOT reset timer to “0” when CAPRUN bit gets set. CAPRUN Capture Timer Run. Setting this bit to one will start the capture timer. This bit gets automatically reset to “0” when a capture events occurs. Writing a “0” by software will also reset the bit and stop the timer. CAPOVL Capture Timer Overflow. Gets set to “1” upon timer overflow. Has to be reset by user’s software. If CAPIEN = 1 an interrupt is generated. CAPPND Capture pending. Gets automatically set when a capture event occurs. If CAPIEN = 1 an interrupt is generated. Has to be reset by the user’s software. CAPIEN Capture Interrupt enable, 1 = enable interrupts, 0 = disable interrupts Since a crystal or ceramic resonator may be selected as the oscillator, the Wakeup signal is not allowed to start the chip running immediately since crystal oscillators and ceramic resonators have a delayed start up time to reach full amplitude and frequency stability. The IDLE timer is used to generate a fixed delay to ensure that the oscillator has indeed stabilized before allowing instruction execution. In this case, upon detecting a valid Wakeup signal, only the oscillator circuitry is enabled. The IDLE timer is loaded with a value of 256 and is clocked with the tC instruction cycle clock. The tC clock is derived by dividing the oscillator clock down by a factor of 10. The Schmitt trigger following the CKI inverter on the chip ensures that the IDLE timer is clocked only when the oscillator has a sufficiently large amplitude to meet the Schmitt trigger specifications. This Schmitt trigger is not part of the oscillator closed loop. The startup timeout from the IDLE timer enables the clock signals to be routed to the rest of the chip. If an RC clock option is being used, the fixed delay is introduced optionally. A control bit, CLKDLY, mapped as configuration bit G7, controls whether the delay is to be introduced or not. The delay is included if CLKDLY is set, and excluded if CLKDLY is reset. The CLKDLY bit is cleared on reset. The device has two mask options associated with the HALT mode. The first mask option enables the HALT mode feature, while the second mask option disables the HALT mode. With the HALT mode enable mask option, the device will enter and exit the HALT mode as described above. With the HALT disable mask option, the device cannot be placed in the HALT mode (writing a “1” to the HALT flag will have no effect, the HALT flag will remain “0”). IDLE MODE In the IDLE mode, program execution stops and power consumption is reduced to a very low level as with the HALT mode. However, the on-board oscillator, IDLE Timer (Timer T0), and Clock Monitor continue to operate, allowing real time to be maintained. The device remains idle for a selected amount of time up to 65,536 instruction cycles, or 65.536 milliseconds with a 1 MHz instruction clock frequency, and then automatically exits the IDLE mode and returns to normal program execution. The device is placed in the IDLE mode under software control by setting the IDLE bit (bit 6 of the Port G data register). The IDLE timer window is selectable from one of five values, 4k, 8k, 16k, 32k or 64k instruction cycles. Selection of this value is made through the ITMR register. The IDLE mode uses the on-chip IDLE Timer (Timer T0) to keep track of elapsed time in the IDLE state. The IDLE timer runs continuously at the instruction clock rate, whether or not the device is in the IDLE mode. Each time the bit of the timer associated with the selected window toggles, the T0PND bit is set, an interrupt is generated (if enabled), and the device exits the IDLE mode if in that mode. If the IDLE timer interrupt is enabled, the interrupt is serviced before execution of the main program resumes. (However, the instruction which was started as the part entered the IDLE mode is completed before the interrupt is serviced. This instruction should be a NOP which should follow the enter IDLE instruction.) The user must reset the IDLE timer pending flag (T0PND) before entering the IDLE mode. As with the HALT mode, this device can also be returned to normal operation with a reset, or with a Multi-Input Wakeup input. Upon reset the ITMR register is cleared and the ITMR register selects the 4,096 instruction cycle tap of the Idle Timer. 17 www.national.com Power Save Modes The device offers the user two power save modes of operation: HALT and IDLE. In the HALT mode, all microcontroller activities are stopped. In the IDLE mode, the on-board oscillator circuitry and timer T0 are active but all other microcontroller activities are stopped. In either mode, all on-board RAM, registers, I/O states, and timers (with the exception of T0) are unaltered. HALT MODE The device can be placed in the HALT mode by writing a “1” to the HALT flag (G7 data bit). All microcontroller activities, including the clock and timers, are stopped. The WATCHDOG logic on the device is disabled during the HALT mode. However, the clock monitor circuitry, if enabled, remains active and will cause the WATCHDOG output pin (WDOUT) to go low. If the HALT mode is used and the user does not want to activate the WDOUT pin, the Clock Monitor should be disabled after the device comes out of reset (resetting the Clock Monitor control bit with the first write to the WDSVR register). In the HALT mode, the power requirements of the device are minimal and the applied voltage (VCC) may be decreased to Vr (Vr = 2.0V) without altering the state of the machine. The device supports three different ways of exiting the HALT mode. The first method of exiting the HALT mode is with the Multi-Input Wakeup feature on the Port L. The second method is with a low to high transition on the CKO (G7) pin. This method precludes the use of the crystal clock configuration (since CKO becomes a dedicated output), and so may only be used with an RC clock configuration. The third method of exiting the HALT mode is by pulling the RESET pin low. Power Save Modes (Continued) Multi-Input Wakeup The Multi-Input Wakeup feature is used to return (wakeup) the device from either the HALT or IDLE modes. Alternately Multi-Input Wakeup/Interrupt feature may also be used to generate up to 4 edge selectable external interrupts. The IDLE timer cannot be started or stopped under software control, and it is not memory mapped, so it cannot be read or written by the software. Its state upon Reset is unknown. Therefore, if the device is put into the IDLE mode at an arbitrary time, it will stay in the IDLE mode for somewhere between 1 and the selected number of instruction cycles. In order to precisely time the duration of the IDLE state, entry into the IDLE mode must be synchronized to the state of the IDLE Timer. The best way to do this is to use the IDLE Timer interrupt, which occurs on every underflow of the bit of the IDLE Timer which is associated with the selected window. Another method is to poll the state of the IDLE Timer pending bit T0PND, which is set on the same occurrence. The Idle Timer interrupt is enabled by setting bit T0EN in the ICNTRL register. Any time the IDLE Timer window length is changed there is the possibility of generating a spurious IDLE Timer interrupt by setting the T0PND bit. The user is advised to disable IDLE Timer interrupts prior to changing the value of the ITSEL bits of the ITMR Register and then clear the TOPND bit before attempting to synchronize operation to the IDLE Timer. Note: As with the HALT mode, it is necessary to program two NOP’s to allow clock resynchronization upon return from the IDLE mode. The NOP’s are placed either at the beginning of the IDLE timer interrupt routine or immediately following the “enter IDLE mode” instruction. Figure 12 shows the Multi-Input Wakeup logic. The Multi-Input Wakeup feature utilizes the L Port. The user selects which particular L port bit (or combination of L Port bits) will cause the device to exit the HALT or IDLE modes. The selection is done through the register WKEN. The register WKEN is an 8-bit read/write register, which contains a control bit for every L port bit. Setting a particular WKEN bit enables a Wakeup from the associated L port pin. The user can select whether the trigger condition on the selected L Port pin is going to be either a positive edge (low to high transition) or a negative edge (high to low transition). This selection is made via the register WKEDG, which is an 8-bit control register with a bit assigned to each L Port pin. Setting the control bit will select the trigger condition to be a negative edge on that particular L Port pin. Resetting the bit selects the trigger condition to be a positive edge. Changing an edge select entails several steps in order to avoid a Wakeup condition as a result of the edge change. First, the associated WKEN bit should be reset, followed by the edge select change in WKEDG. Next, the associated WKPND bit should be cleared, followed by the associated WKEN bit being re-enabled. For more information on the IDLE Timer and its associated interrupt, see the description in the Timers section. DS012869-13 FIGURE 12. Multi-Input Wake Up Logic www.national.com 18 Multi-Input Wakeup (Continued) An example may serve to clarify this procedure. Suppose we wish to change the edge select from positive (low going high) to negative (high going low) for L Port bit 5, where bit 5 has previously been enabled for an input interrupt. The program would be as follows: RBIT SBIT RBIT SBIT 5, 5, 5, 5, WKEN WKEDG WKPND WKEN ; ; ; ; Disable MIWU Change edge polarity Reset pending flag Enable MIWU modes. In the other case, the device will first execute the interrupt service routine and then revert to normal operation. (See HALT MODE for clock option wakeup information.) Analog Function Block This device contains an analog function block with the intent to provide a function which allows for single slope, low cost, A/D conversion of up to 6 channels. CMPSL REGISTER (ADDRESS X’00B7) CMPT2B Bit 7 CMPISEL2 CMPISEL1 CMPISEL0 CMPOE CSEN CMPEN CMPNEG Bit 0 If the L port bits have been used as outputs and then changed to inputs with Multi-Input Wakeup/Interrupt, a safety procedure should also be followed to avoid wakeup conditions. After the selected L port bits have been changed from output to input but before the associated WKEN bits are enabled, the associated edge select bits in WKEDG should be set or reset for the desired edge selects, followed by the associated WKPND bits being cleared. This same procedure should be used following reset, since the L port inputs are left floating as a result of reset. The occurrence of the selected trigger condition for Multi-Input Wakeup is latched into a pending register called WKPND. The respective bits of the WKPND register will be set on the occurrence of the selected trigger edge on the corresponding Port L pin. The user has the responsibility of clearing these pending flags. Since WKPND is a pending register for the occurrence of selected wakeup conditions, the device will not enter the HALT mode if any Wakeup bit is both enabled and pending. Consequently, the user must clear the pending flags before attempting to enter the HALT mode. WKEN, WKPND and WKEDG are all read/write registers, and are cleared at reset. PORT L INTERRUPTS Port L provides the user with an additional eight fully selectable, edge sensitive interrupts which are all vectored into the same service subroutine. The interrupt from Port L shares logic with the wake up circuitry. The register WKEN allows interrupts from Port L to be individually enabled or disabled. The register WKEDG specifies the trigger condition to be either a positive or a negative edge. Finally, the register WKPND latches in the pending trigger conditions. The GIE (Global Interrupt Enable) bit enables the interrupt function. A control flag, LPEN, functions as a global interrupt enable for Port L interrupts. Setting the LPEN flag will enable interrupts and vice versa. A separate global pending flag is not needed since the register WKPND is adequate. Since Port L is also used for waking the device out of the HALT or IDLE modes, the user can elect to exit the HALT or IDLE modes either with or without the interrupt enabled. If he elects to disable the interrupt, then the device will restart execution from the instruction immediately following the instruction that placed the microcontroller in the HALT or IDLE The CMPSL register contains the following bits: CMPT2B Selects the “High Speed 16-bit Capture Timer” input to be driven directly by the comparator output. If the comparator is disabled (CMPEN = 0), this function is disabled, i.e. the Capture Timer input is connected to GND. CMPISEL0/1/2 Will select one of seven possible sources (I0/I2/I3/I4/I5/I6/internal reference) as a positive input to the comparator (see Table 4 for more information) CMPOE Enables the comparator output to either pin I3 or pin I7 (“1” = enable) depending on the value of CMPISEL0/1/2. CSEN Enables the internal constant current source. This current source provides a nominal 20 µA constant current at the I1 pin. This current can be used to ensure a linear charging rate on an external capacitor. This bit has no affect and the current source is disabled if the comparator is not enabled (CMPEN = 0). CMPEN Enable the comparator (“1” = enable) CMPNEG Will drive I1 to a low level. This bit can be used to discharge an external capacitor. This bit is disabled if the comparator is not enabled (CMPEN = 0). The Comparator Select Register is cleared on RESET (the comparator is disabled). To save power the program should also disable the comparator before the µC enters the HALT/ IDLE modes. Disabling the comparator will turn off the constant current source and the VCC/2 reference, disconnect the comparator output from the Capture Timer input and pin I3/I7 and remove the low on I1 caused by CMPNEG. It is often useful for the user’s program to read the result of a comparator operation. Since I1 is always selected to be COMPIN — when the comparator is enabled (CMPEN = 1), the comparator output can be read internally by reading bit 1 (CMPRD) of register PORTI (RAM address 0xD7). The following table lists the comparator inputs and outputs versus the value of the CMPISEL0/1/2 bits. The output will only be driven if the CMPOE bit is set to 1. 19 www.national.com Analog Function Block (Continued) DS012869-14 FIGURE 13. Analog Function Block TABLE 4. Comparator Input Selection Control Bit CMPISEL2 0 0 0 0 1 1 1 1 CMPISEL1 0 0 1 1 0 0 1 1 CMPISEL0 0 1 0 1 0 1 0 1 Neg. Input I1 I1 I1 I1 I1 I1 I1 I1 Comparator Input Source Pos. Input I2 CH2 I2 CH2 I3 CH3 I0 CH1 I4 CH4 I5 CH5 I6 CH6 VCC/2 Ref. I3 I7 I7 I7 I7 I7 I7 I7 Comparator Output Reset The state of the Analog Block immediately after RESET is as follows: 1. 2. 3. 4. 5. 6. 7. 8. The CMPSL Register is set to all zeros The Comparator is disabled The Constant Current Source is disabled CMPNEG is turned off The Port I inputs are electrically isolated from the comparator The Capture Timer input is connected to GND CMPISEL0–CMPISEL2 are set to zero All Port I inputs are selected to the default digital input mode The comparator outputs have the same specification as Ports L and G except that the rise and fall times are symmetrical. Interrupts INTRODUCTION Each device supports eight vectored interrupts. Interrupt sources include Timer 0, Timer 1, Timer 2, Timer 3, Port L Wakeup, Software Trap, MICROWIRE/PLUS, and External Input. All interrupts force a branch to location 00FF Hex in program memory. The VIS instruction may be used to vector to the appropriate service routine from location 00FF Hex. The Software trap has the highest priority while the default VIS has the lowest priority. www.national.com 20 Interrupts (Continued) Figure 14 shows the Interrupt Block Diagram. Each of the 8 maskable inputs has a fixed arbitration ranking and vector. DS012869-15 FIGURE 14. Interrupt Block Diagram MASKABLE INTERRUPTS All interrupts other than the Software Trap are maskable. Each maskable interrupt has an associated enable bit and pending flag bit. The pending bit is set to 1 when the interrupt condition occurs. The state of the interrupt enable bit, combined with the GIE bit determines whether an active pending flag actually triggers an interrupt. All of the maskable interrupt pending and enable bits are contained in mapped control registers, and thus can be controlled by the software. A maskable interrupt condition triggers an interrupt under the following conditions: 1. The enable bit associated with that interrupt is set. 2. The GIE bit is set. 3. The device is not processing a non-maskable interrupt. (If a non-maskable interrupt is being serviced, a maskable interrupt must wait until that service routine is completed.) sociated pending bit must be reset to zero prior to enabling the interrupt. Otherwise, the interrupt may be simply enabled; if the pending bit is already set, it will immediately trigger an interrupt. A maskable interrupt is active if its associated enable and pending bits are set. An interrupt is an asychronous event which may occur before, during, or after an instruction cycle. Any interrupt which occurs during the execution of an instruction is not acknowledged until the start of the next normally executed instruction is to be skipped, the skip is performed before the pending interrupt is acknowledged. At the start of interrupt acknowledgment, the following actions occur: 1. The GIE bit is automatically reset to zero, preventing any subsequent maskable interrupt from interrupting the current service routine. This feature prevents one maskable interrupt from interrupting another one being serviced. 2. The address of the instruction about to be executed is pushed onto the stack. 3. The program counter (PC) is loaded with 00FF Hex, causing a jump to that program memory location. An interrupt is triggered only when all of these conditions are met at the beginning of an instruction. If different maskable interrupts meet these conditions simultaneously, the highest priority interrupt will be serviced first, and the other pending interrupts must wait. Upon Reset, all pending bits, individual enable bits, and the GIE bit are reset to zero. Thus, a maskable interrupt condition cannot trigger an interrupt until the program enables it by setting both the GIE bit and the individual enable bit. When enabling an interrupt, the user should consider whether or not a previously activated (set) pending bit should be acknowledged. If, at the time an interrupt is enabled, any previous occurrences of the interrupt should be ignored, the as21 The device requires seven instruction cycles to perform the actions listed above. If the user wishes to allow nested interrupts, the interrupts service routine may set the GIE bit to 1 by writing to the PSW register, and thus allow other maskable interrupts to interrupt the current service routine. If nested interrupts are allowed, caution must be exercised. The user must write the program in such a way as to prevent stack overflow, loss of saved context information, and other unwanted conditions. www.national.com Interrupts (Continued) The interrupt service routine stored at location 00FF Hex should use the VIS instruction to determine the cause of the interrupt, and jump to the interrupt handling routine corresponding to the highest priority enabled and active interrupt. Alternately, the user may choose to poll all interrupt pending and enable bits to determine the source(s) of the interrupt. If more than one interrupt is active, the user’s program must decide which interrupt to service. Within a specific interrupt service routine, the associated pending bit should be cleared. This is typically done as early as possible in the service routine in order to avoid missing the next occurrence of the same type of interrupt event. Thus, if the same event occurs a second time, even while the first occurrence is still being serviced, the second occurrence will be serviced immediately upon return from the current interrupt routine. An interrupt service routine typically ends with an RETI instruction. This instruction sets the GIE bit back to 1, pops the address stored on the stack, and restores that address to the program counter. Program execution then proceeds with the next instruction that would have been executed had there been no interrupt. If there are any valid interrupts pending, the highest-priority interrupt is serviced immediately upon return from the previous interrupt. VIS INSTRUCTION The general interrupt service routine, which starts at address 00FF Hex, must be capable of handling all types of interrupts. The VIS instruction, together with an interrupt vector table, directs the device to the specific interrupt handling routine based on the cause of the interrupt. VIS is a single-byte instruction, typically used at the very beginning of the general interrupt service routine at address 00FF Hex, or shortly after that point, just after the code used for context switching. The VIS instruction determines which enabled and pending interrupt has the highest priority, and causes an indirect jump to the address corresponding to that interrupt source. The jump addresses (vectors) for all possible interrupts sources are stored in a vector table. The vector table may be as long as 32 bytes (maximum of 16 vectors) and resides at the top of the 256-byte block containing the VIS instruction. However, if the VIS instruction is at the very top of a 256-byte block (such as at 00FF Hex), the vector table resides at the top of the next 256-byte block. Thus, if the VIS instruction is located somewhere between 00FF and 01DF Hex (the usual case), the vector table is located between addresses 01E0 and 01FF Hex. If the VIS instruction is located between 01FF and 02DF Hex, then the vector table is located between addresses 02E0 and 02FF Hex, and so on. Each vector is 15 bits long and points to the beginning of a specific interrupt service routine somewhere in the 32 kbyte memory space. Each vector occupies two bytes of the vector table, with the higher-order byte at the lower address. The vectors are arranged in order of interrupt priority. The vector of the maskable interrupt with the lowest rank is located to 0yE0 (higher-order byte) and 0yE1 (lower-order byte). The next priority interrupt is located at 0yE2 and 0yE3, and so forth in increasing rank. The Software Trap has the highest rank and its vector is always located at 0yFE and 0yFF. The number of interrupts which can become active defines the size of the table. Table 5 shows the types of interrupts, the interrupt arbitration ranking, and the locations of the corresponding vectors in the vector table. The vector table should be filled by the user with the memory locations of the specific interrupt service routines. For example, if the Software Trap routine is located at 0310 Hex, then the vector location 0yFE and -0yFF should contain the data 03 and 10 Hex, respectively. When a Software Trap interrupt occurs and the VIS instruction is executed, the program jumps to the address specified in the vector table. The interrupt sources in the vector table are listed in order of rank, from highest to lowest priority. If two or more enabled and pending interrupts are detected at the same time, the one with the highest priority is serviced first. Upon return from the interrupt service routine, the next highest-level pending interrupt is serviced. If the VIS instruction is executed, but no interrupts are enabled and pending, the lowest-priority interrupt vector is used, and a jump is made to the corresponding address in the vector table. This is an unusual occurrence, and may be the result of an error. It can legitimately result from a change in the enable bits or pending flags prior to the execution of the VIS instruction, such as executing a single cycle instruction which clears an enable flag at the same time that the pending flag is set. It can also result, however, from inadvertent execution of the VIS command outside of the context of an interrupt. The default VIS interrupt vector can be useful for applications in which time critical interrupts can occur during the servicing of another interrupt. Rather than restoring the program context (A, B, X, etc.) and executing the RETI instruction, an interrupt service routine can be terminated by returning to the VIS instruction. In this case, interrupts will be serviced in turn until no further interrupts are pending and the default VIS routine is started. After testing the GIE bit to ensure that execution is not erroneous, the routine should restore the program context and execute the RETI to return to the interrupted program. This technique can save up to fifty instruction cycles (tc), or more, (50µs at 10 MHz oscillator) of latency for pending interrupts with a penalty of fewer than ten instruction cycles if no further interrupts are pending. To ensure reliable operation, the user should always use the VIS instruction to determine the source of an interrupt. Although it is possible to poll the pending bits to detect the source of an interrupt, this practice is not recommended. The use of polling allows the standard arbitration ranking to be altered, but the reliability of the interrupt system is compromised. The polling routine must individually test the enable and pending bits of each maskable interrupt. If a Software Trap interrupt should occur, it will be serviced last, even though it should have the highest priority. Under certain conditions, a Software Trap could be triggered but not serviced, resulting in an inadvertent “locking out” of all maskable interrupts by the Software Trap pending flag. Problems such as this can be avoided by using VIS instruction. www.national.com 22 Interrupts (Continued) TABLE 5. Interrupt Vector Table ARBITRATION RANKING (1) Highest (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) Lowest Software Reserved External Timer T0 Timer T1 Timer T1 MICROWIRE/PLUS Reserved Reserved Reserved SOURCE DESCRIPTION INTR Instruction G0 Idle Timer T1A/Underflow T1B Busy Low VECTOR* ADDRESS (Hi-Low Byte) 0yFE–0yFF 0yFC–0yFD 0yFA–0yFB 0yF8–0yF9 0yF6–0yF7 0yF4–0yF5 0yF2–0yF3 0yF0–0yF1 0yEE–0yEF 0yEC–0yED Capture Overflow/ Capture Pending 0yEA–0yEB 0yE8–0yE9 0yE6–0yE7 0yE4–0yE5 Port L Edge Reserved 0yE2–0yE3 0yE0–0yE1 High Speed Capture Timer Reserved Reserved Reserved Port L/Wakeup Default VIS Note 20: *y is a variable which represents the VIS block. VIS and the vector table must be located in the same 256-byte block except if VIS islocated at the last address of a block. In this case, the table must be in the next block. VIS Execution When the VIS instruction is executed it activates the arbitration logic. The arbitration logic generates an even number between E0 and FE (E0, E2, E4, E6 etc...) depending on which active interrupt has the highest arbitration ranking at the time of the 1st cycle of VIS is executed. For example, if the software trap interrupt is active, FE is generated. If the external interrupt is active and the software trap interrupt is not, then FA is generated and so forth. If the only active interrupt is software trap, than E0 is generated. This number replaces the lower byte of the PC. The upper byte of the PC remains unchanged. The new PC is therefore pointing to the vector of the active interrupt with the highest arbitration ranking. This vector is read from program memory and placed into the PC which is now pointed to the 1st instruction of the service routine of the active interrupt with the highest arbitration ranking. Figure 15 illustrates the different steps performed by the VIS instruction. Figure 16 shows a flowchart for the VIS instruction. The non-maskable interrupt pending flag is cleared by the RPND (Reset Non-Maskable Pending Bit) instruction (under certain conditions) and upon RESET. 23 www.national.com Interrupts (Continued) DS012869-29 FIGURE 15. VIS Operation DS012869-30 FIGURE 16. VIS Flowchart www.national.com 24 Interrupts (Continued) Programming Example: External Interrupt PSW CNTRL RBIT RBIT SBIT SBIT SBIT JP . . . .=0FF VIS =00EF =00EE 0,PORTGC 0,PORTGD IEDG, CNTRL EXEN, PSW GIE, PSW WAIT WAIT: ; ; ; ; ; G0 pin configured Hi-Z Ext interrupt polarity; falling edge Enable the external interrupt Set the GIE bit Wait for external interrupt ; The interrupt causes a ; branch to address 0FF ; The VIS causes a branch to ;interrupt vector table . . . .=01FA .ADDRW SERVICE . . INT_EXIT: RETI . . RBIT . . . JP ; Vector table (within 256 byte ; of VIS inst.) containing the ext ; interrupt service routine SERVICE: EXPND, PSW ; Interrupt Service Routine ; Reset ext interrupt pend. bit INT_EXIT ; Return, set the GIE bit 25 www.national.com Interrupts (Continued) NON-MASKABLE INTERRUPT Pending Flag There is a pending flag bit associated with the non-maskable interrupt, called STPND. This pending flag is not memorymapped and cannot be accessed directly by the software. The pending flag is reset to zero when a device Reset occurs. When the non-maskable interrupt occurs, the associated pending bit is set to 1. The interrupt service routine should contain an RPND instruction to reset the pending flag to zero. The RPND instruction always resets the STPND flag. Software Trap The Software Trap is a special kind of non-maskable interrupt which occurs when the INTR instruction (used to acknowledge interrupts) is fetched from program memory and placed in the instruction register. This can happen in a variety of ways, usually because of an error condition. Some examples of causes are listed below. If the program counter incorrectly points to a memory location beyond the available program memory space, the nonexistent or unused memory location returns zeroes which is interpreted as the INTR instruction. If the stack is popped beyond the allowed limit (address 06F Hex), a 7FFF will be loaded into the PC, if this last location in program memory is unprogrammed or unavailable, a Software Trap will be triggered. A Software Trap can be triggered by a temporary hardware condition such as a brownout or power supply glitch. The Software Trap has the highest priority of all interrupts. When a Software Trap occurs, the STPND bit is set. The GIE bit is not affected and the pending bit (not accessible by the user) is used to inhibit other interrupts and to direct the program to the ST service routine with the VIS instruction. Nothing can interrupt a Software Trap service routine except for another Software Trap. The STPND can be reset only by the RPND instruction or a chip Reset. The Software Trap indicates an unusual or unknown error condition. Generally, returning to normal execution at the point where the Software Trap occurred cannot be done reliably. Therefore, the Software Trap service routine should reinitialize the stack pointer and perform a recovery procedure that restarts the software at some known point, similar to a device Reset, but not necessarily performing all the same functions as a device Reset. The routine must also execute the RPND instruction to reset the STPND flag. Otherwise, all other interrupts will be locked out. To the extent possible, the interrupt routine should record or indicate the context of the device so that the cause of the Software Trap can be determined. If the user wishes to return to normal execution from the point at which the Software Trap was triggered, the user must first execute RPND, followed by RETSK rather than RETI or RET. This is because the return address stored on the stack is the address of the INTR instruction that triggered the interrupt. The program must skip that instruction in order to proceed with the next one. Otherwise, an infinite loop of Software Traps and returns will occur. Programming a return to normal execution requires careful consideration. If the Software Trap routine is interrupted by another Software Trap, the RPND instruction in the service routine for the second Software Trap will reset the STPND www.national.com 26 flag; upon return to the first Software Trap routine, the STPND flag will have the wrong state. This will allow maskable interrupts to be acknowledged during the servicing of the first Software Trap. To avoid problems such as this, the user program should contain the Software Trap routine to perform a recovery procedure rather than a return to normal execution. Under normal conditions, the STPND flag is reset by a RPND instruction in the Software Trap service routine. If a programming error or hardware condition (brownout, power supply glitch, etc.) sets the STPND flag without providing a way for it to be cleared, all other interrupts will be locked out. To alleviate this condition, the user can use extra RPND instructions in the main program and in the WATCHDOG service routine (if present). There is no harm in executing extra RPND instructions in these parts of the program. PORT L INTERRUPTS Port L provides the user with an additional eight fully selectable, edge sensitive interrupts which are all vectored into the same service subroutine. The interrupt from Port L shares logic with the wake up circuitry. The register WKEN allows interrupts from Port L to be individually enabled or disabled. The register WKEDG specifies the trigger condition to be either a positive or a negative edge. Finally, the register WKPND latches in the pending trigger conditions. The GIE (Global Interrupt Enable) bit enables the interrupt function. A control flag, LPEN, functions as a global interrupt enable for Port L interrupts. Setting the LPEN flag will enable interrupts and vice versa. A separate global pending flag is not needed since the register WKPND is adequate. Since Port L is also used for waking the device out of the HALT or IDLE modes, the user can elect to exit the HALT or IDLE modes either with or without the interrupt enabled. If he elects to disable the interrupt, then the device will restart execution from the instruction immediately following the instruction that placed the microcontroller in the HALT or IDLE modes. In the other case, the device will first execute the interrupt service routine and then revert to normal operation. (See HALT MODE for clock option wakeup information.) INTERRUPT SUMMARY The device uses the following types of interrupts, listed below in order of priority: 1. The Software Trap non-maskable interrupt, triggered by the INTR (00 opcode) instruction. The Software Trap is acknowledged immediately. This interrupt service routine can be interrupted only by another Software Trap. The Software Trap should end with two RPND instructions followed by a restart procedure. 2. Maskable interrupts, triggered by an on-chip peripheral block or an external device connected to the device. Under ordinary conditions, a maskable interrupt will not interrupt any other interrupt routine in progress. A maskable interrupt routine in progress can be interrupted by the non-maskable interrupt request. A maskable interrupt routine should end with an RETI instruction or, prior to restoring context, should return to execute the VIS instruction. This is particularly useful when exiting long interrupt service routiness if the time between interrupts is short. In this case the RETI instruction would only be executed when the default VIS routine is reached. WATCHDOG The devices contain a WATCHDOG and clock monitor. The WATCHDOG is designed to detect the user program getting stuck in infinite loops resulting in loss of program control or “runaway” programs. The Clock Monitor is used to detect the absence of a clock or a very slow clock below a specified rate on the CKI pin. The WATCHDOG consists of two independent logic blocks: WD UPPER and WD LOWER. WD UPPER establishes the upper limit on the service window and WD LOWER defines the lower limit of the service window. Servicing the WATCHDOG consists of writing a specific value to a WATCHDOG Service Register named WDSVR which is memory mapped in the RAM. This value is composed of three fields, consisting of a 2-bit Window Select, a 5-bit Key Data field, and the 1-bit Clock Monitor Select field. Table 6 shows the WDSVR register. TABLE 6. WATCHDOG Service Register (WDSVR) Window Select X 7 X 6 0 5 1 4 Key Data 1 3 0 2 0 1 Clock Monitor Y 0 The lower limit of the service window is fixed at 2048 instruction cycles. Bits 7 and 6 of the WDSVR register allow the user to pick an upper limit of the service window. Table 7 shows the four possible combinations of lower and upper limits for the WATCHDOG service window. This flexibility in choosing the WATCHDOG service window prevents any undue burden on the user software. Bits 5, 4, 3, 2 and 1 of the WDSVR register represent the 5-bit Key Data field. The key data is fixed at 01100. Bit 0 of the WDSVR Register is the Clock Monitor Select bit. TABLE 7. WATCHDOG Service Window Select WDSVR Bit 7 0 0 1 1 WDSVR Bit 6 0 1 0 1 Service Window (Lower-Upper Limits) 2k–8k tC Cycles 2k–16k tC Cycles 2k–32k tC Cycles 2k–64k tC Cycles The WDSVR register can be written to only once after reset and the key data (bits 5 through 1 of the WDSVR Register) must match to be a valid write. This write to the WDSVR register involves two irrevocable choices: (i) the selection of the WATCHDOG service window (ii) enabling or disabling of the Clock Monitor. Hence, the first write to WDSVR Register involves selecting or deselecting the Clock Monitor, select the WATCHDOG service window and match the WATCHDOG key data. Subsequent writes to the WDSVR register will compare the value being written by the user to the WATCHDOG service window value and the key data (bits 7 through 1) in the WDSVR Register. Table IX shows the sequence of events that can occur. The user must service the WATCHDOG at least once before the upper limit of the service window expires. The WATCHDOG may not be serviced more than once in every lower limit of the service window. The user may service the WATCHDOG as many times as wished in the time period between the lower and upper limits of the service window. The first write to the WDSVR Register is also counted as a WATCHDOG service. The WATCHDOG has an output pin associated with it. This is the WDOUT pin, on pin 1 of the port G. WDOUT is active low. The WDOUT pin is in the high impedance state in the inactive state. Upon triggering the WATCHDOG, the logic will pull the WDOUT (G1) pin low for an additional 16 tC–32 tC cycles after the signal level on WDOUT pin goes below the lower Schmitt trigger threshold. After this delay, the device will stop forcing the WDOUT output low. The WATCHDOG service window will restart when the WDOUT pin goes high. It is recommended that the user tie the WDOUT pin back to VCC through a resistor in order to pull WDOUT high. A WATCHDOG service while the WDOUT signal is active will be ignored. The state of the WDOUT pin is not guaranteed on reset, but if it powers up low then the WATCHDOG will time out and WDOUT will enter high impedance state. The Clock Monitor forces the G1 pin low upon detecting a clock frequency error. The Clock Monitor error will continue until the clock frequency has reached the minimum specified value, after which the G1 output will enter the high impedance TRI-STATE mode following 16 tC–32 tC clock cycles. The Clock Monitor generates a continual Clock Monitor error if the oscillator fails to start, or fails to reach the minimum specified frequency. The specification for the Clock Monitor is as follows: 1/tC > 10 kHz — No clock rejection. 1/tC < 10 Hz — Guaranteed clock rejection. WATCHDOG AND CLOCK MONITOR SUMMARY The following salient points regarding the WATCHDOG and CLOCK MONITOR should be noted: • Both the WATCHDOG and CLOCK MONITOR detector circuits are inhibited during RESET. Clock Monitor The Clock Monitor aboard the device can be selected or deselected under program control. The Clock Monitor is guaranteed not to reject the clock if the instruction cycle clock (1/tC) is greater or equal to 10 kHz. This equates to a clock input rate on CKI of greater or equal to 100 kHz. • WATCHDOG Operation The WATCHDOG and Clock Monitor are disabled during reset. The device comes out of reset with the WATCHDOG armed, the WATCHDOG Window Select bits (bits 6, 7 of the WDSVR Register) set, and the Clock Monitor bit (bit 0 of the WDSVR Register) enabled. Thus, a Clock Monitor error will occur after coming out of reset, if the instruction cycle clock frequency has not reached a minimum specified value, including the case where the oscillator fails to start. Following RESET, the WATCHDOG and CLOCK MONITOR are both enabled, with the WATCHDOG having the maximum service window selected. The WATCHDOG service window and CLOCK MONITOR enable/disable option can only be changed once, during the initial WATCHDOG service following RESET. The initial WATCHDOG service must match the key data value in the WATCHDOG Service register WDSVR in order to avoid a WATCHDOG error. • • 27 www.national.com WATCHDOG Operation • (Continued) Subsequent WATCHDOG services must match all three data fields in WDSVR in order to avoid WATCHDOG errors. The correct key data value cannot be read from the WATCHDOG Service register WDSVR. Any attempt to read this key data value of 01100 from WDSVR will read as key data value of all 0’s. The WATCHDOG detector circuit is inhibited during both the HALT and IDLE modes. The CLOCK MONITOR detector circuit is active during both the HALT and IDLE modes. Consequently, the device inadvertently entering the HALT mode will be detected as a CLOCK MONITOR error (provided that the CLOCK MONITOR enable option has been selected by the program). With the single-pin R/C oscillator mask option selected and the CLKDLY bit reset, the WATCHDOG service window will resume following HALT mode from where it left off before entering the HALT mode. With the crystal oscillator mask option selected, or with the single-pin R/C oscillator mask option selected and the CLKDLY bit set, the WATCHDOG service window will be set to its selected value from WDSVR following HALT. Consequently, the WATCHDOG should not be serviced for at least 2048 instruction cycles following HALT, but must be serviced within the selected window to avoid a WATCHDOG error. • • • • • The IDLE timer T0 is not initialized with RESET. The user can sync in to the IDLE counter cycle with an IDLE counter (T0) interrupt or by monitoring the T0PND flag. The T0PND flag is set whenever the thirteenth bit of the IDLE counter toggles (every 4096 instruction cycles). The user is responsible for resetting the T0PND flag. A hardware WATCHDOG service occurs just as the device exits the IDLE mode. Consequently, the WATCHDOG should not be serviced for at least 2048 instruction cycles following IDLE, but must be serviced within the selected window to avoid a WATCHDOG error. Following RESET, the initial WATCHDOG service (where the service window and the CLOCK MONITOR enable/ disable must be selected) may be programmed anywhere within the maximum service window (65,536 instruction cycles) initialized by RESET. Note that this initial WATCHDOG service may be programmed within the initial 2048 instruction cycles without causing a WATCHDOG error. • • • • TABLE 8. WATCHDOG Service Actions Key Data Match Don’t Care Mismatch Don’t Care Window Data Match Mismatch Don’t Care Don’t Care Clock Monitor Match Don’t Care Don’t Care Mismatch Action Valid Service: Restart Service Window Error: Generate WATCHDOG Output Error: Generate WATCHDOG Output Error: Generate WATCHDOG Output Detection of Illegal Conditions The device can detect various illegal conditions resulting from coding errors, transient noise, power supply voltage drops, runaway programs, etc. Reading of undefined ROM gets zeros. The opcode for software interrupt is 00. If the program fetches instructions from undefined ROM, this will force a software interrupt, thus signaling that an illegal condition has occurred. The subroutine stack grows down for each call (jump to subroutine), interrupt, or PUSH, and grows up for each return or POP. The stack pointer is initialized to RAM location 06F Hex during reset. Consequently, if there are more returns than calls, the stack pointer will point to addresses 070 and 071 Hex (which are undefined RAM). Undefined RAM from addresses 070 to 07F (Segment 0), and all other segments (i.e., Segments 4... etc.) is read as all 1’s, which in turn will cause the program to return to address 7FFF Hex. This is an undefined ROM location and the instruction fetched (all 0’s) from this location will generate a software interrupt signaling an illegal condition. Thus, the chip can detect the following illegal conditions: 1. 2. Executing from undefined ROM Over “POP”ing the stack by having more returns than calls. When the software interrupt occurs, the user can re-initialize the stack pointer and do a recovery procedure before restarting (this recovery program is probably similar to that following reset, but might not contain the same program initialization procedures). The recovery program should reset the software interrupt pending bit using the RPND instruction. MICROWIRE/PLUS MICROWIRE/PLUS is a serial synchronous communications interface. The MICROWIRE/PLUS capability enables the device to interface with any of National Semiconductor’s MICROWIRE peripherals (i.e. A/D converters, display drivers, E2PROMs etc.) and with other microcontrollers which support the MICROWIRE interface. It consists of an 8-bit serial shift register (SIO) with serial data input (SI), serial data output (SO) and serial shift clock (SK). Figure 17 shows a block diagram of the MICROWIRE/PLUS logic. The shift clock can be selected from either an internal source or an external source. Operating the MICROWIRE/PLUS arrangement with the internal clock source is called the Master mode of operation. Similarly, operating the MICROWIRE/ PLUS arrangement with an external shift clock is called the Slave mode of operation. The CNTRL register is used to configure and control the MICROWIRE/PLUS mode. To use the MICROWIRE/PLUS, the MSEL bit in the CNTRL register is set to one. In the master mode, the SK clock rate is selected by the two bits, SL0 and SL1, in the CNTRL register. Table 9 details the different clock rates that may be selected. TABLE 9. MICROWIRE/PLUS Master Mode Clock Select SL1 0 0 1 SL0 0 1 x SK period 2 X tC 4 X tC 8 X tC Where tC is the instruction cycle clock 28 www.national.com MICROWIRE/PLUS (Continued) MICROWIRE/PLUS OPERATION Setting the BUSY bit in the PSW register causes the MICROWIRE/PLUS to start shifting the data. It gets reset when eight data bits have been shifted. The user may reset the BUSY bit by software to allow less than 8 bits to shift. If enabled, an interrupt is generated when eight data bits have been shifted. The device may enter the MICROWIRE/PLUS mode either as a Master or as a Slave. Figure 18 shows how two devices, microcontrollers and several peripherals may be interconnected using the MICROWIRE/PLUS arrangements. DS012869-16 FIGURE 17. MICROWIRE/PLUS Block Diagram WARNING The SIO register should only be loaded when the SK clock is low. Loading the SIO register while the SK clock is high will result in undefined data in the SIO register. SK clock is normally low when not shifting. Setting the BUSY flag when the input SK clock is high in the MICROWIRE/PLUS slave mode may cause the current SK clock for the SIO shift register to be narrow. For safety, the BUSY flag should only be set when the input SK clock is low. MICROWIRE/PLUS Master Mode Operation In the MICROWIRE/PLUS Master mode of operation the shift clock (SK) is generated internally. The MICROWIRE Master always initiates all data exchanges. The MSEL bit in the CNTRL register must be set to enable the SO and SK functions onto the G Port. The SO and SK pins must also be selected as outputs by setting appropriate bits in the Port G configuration register. Table 10 summarizes the bit settings required for Master mode of operation. MICROWIRE/PLUS Slave Mode Operation In the MICROWIRE/PLUS Slave mode of operation the SK clock is generated by an external source. Setting the MSEL bit in the CNTRL register enables the SO and SK functions onto the G Port. The SK pin must be selected as an input and the SO pin is selected as an output pin by setting and resetting the appropriate bits in the Port G configuration register. Table XI summarizes the settings required to enter the Slave mode of operation. The user must set the BUSY flag immediately upon entering the Slave mode. This will ensure that all data bits sent by the Master will be shifted properly. After eight clock pulses the BUSY flag will be cleared and the sequence may be repeated. TABLE 10. MICROWIRE/PLUS Mode Settings This table assumes that the control flag MSEL is set. G4 (SO) Config. Bit 1 0 1 0 G5 (SK) Config. Bit 1 1 0 0 G4 Fun. SO TRISTATE SO TRISTATE G5 Fun. Int. SK Int. SK Ext. SK Ext. SK Operation MICROWIRE/PLUS Master MICROWIRE/PLUS Master MICROWIRE/PLUS Slave MICROWIRE/PLUS Slave Alternate SK Phase Operation The device allows either the normal SK clock or an alternate phase SK clock to shift data in and out of the SIO register. In both the modes the SK is normally low. In the normal mode data is shifted in on the rising edge of the SK clock and the data is shifted out on the falling edge of the SK clock. The SIO register is shifted on each falling edge of the SK clock. In the alternate SK phase operation, data is shifted in on the falling edge of the SK clock and shifted out on the rising edge of the SK clock. A control flag, SKSEL, allows either the normal SK clock or the alternate SK clock to be selected. Resetting SKSEL causes the MICROWIRE/PLUS logic to be clocked from the normal SK signal. Setting the SKSEL flag selects the alternate SK clock. The SKSEL is mapped into the G6 configuration bit. The SKSEL flag will power up in the reset condition, selecting the normal SK signal. 29 www.national.com MICROWIRE/PLUS (Continued) DS012869-17 FIGURE 18. MICROWIRE/PLUS Application www.national.com 30 Memory Map All RAM, ports and registers (except A and PC) are mapped into data memory address space. Address S/ADD REG 0000 to 006F 0070 to 007F xx80 to xxAF xxB0 XXB1 xxB2 xxB3 xxB4 xxB5 xxB6 xxB7 xxB8 to xxBF xxC0 xxC1 xxC2 xxC3 xxC4 xxC5 xxC6 xxC7 xxC8 xxC9 xxCA xxCB xxCC xxCD xxCE xxCF xxD0 xxD1 xxD2 xxD3 xxD4 xxD5 xxD6 xxD7 xxD8 xxD9 xxDA On-Chip RAM bytes (112 bytes) Unused RAM Address Space (Reads As All Ones) Unused RAM Address Space (Reads Undefined Data) Reserved Reserved Reserved Reserved Reserved Reserved Reserved Comparator Select Register (CMPSL) Reserved xxEE Reserved Reserved Reserved Reserved Reserved Reserved Reserved WATCHDOG Service Register (Reg:WDSVR) MIWU Edge Select Register (Reg:WKEDG) MIWU Enable Register (Reg:WKEN) MIWU Pending Register (Reg:WKPND) Reserved CAPTLO (Capture Timer Low-Byte) CAPTHI (Capture Timer High-Byte) CAPCNTL (Capture Timer Control Register) Idle Timer Control Register Port L Data Register Port L Configuration Register Port L Input Pins (Read Only) Reserved Port G Data Register Port G Configuration Register Port G Input Pins (Read Only) Port I Input Pins (Read Only) Reserved Reserved Reserved xxEF xxF0 to FB xxFC xxFD xxFE xxFF 0100-017F xxED xxE8 xxE9 xxEA xxEB xxEC Contents Address S/ADD REG xxDB xxDC xxDD to DF xxE0 to xxE5 xxE6 xxE7 Reserved Port D Reserved Reserved Timer T1 Autoload Register T1RB Lower Byte Timer T1 Autoload Register T1RB Upper Byte ICNTRL Register MICROWIRE/PLUS Shift Register Timer T1 Lower Byte Timer T1 Upper Byte Timer T1 Autoload Register T1RA Lower Byte Timer T1 Autoload Register T1RA Upper Byte CNTRL Control Register PSW Register On-Chip RAM Mapped as Registers X Register SP Register B Register Reserved Reserved Contents Reading memory locations 0070H-007FH (Segment 0) will return all ones. Reading unused memory locations 0080H-00AFH (Segment 0) will return undefined data. Reading memory locations from other Segments (i.e., Segment 2, Segment 3,…etc.) will return undefined data. Addressing Modes There are ten addressing modes, six for operand addressing and four for transfer of control. OPERAND ADDRESSING MODES Register Indirect This is the “normal” addressing mode. The operand is the data memory addressed by the B pointer or X pointer. Register Indirect (with auto post increment or decrement of pointer) This addressing mode is used with the LD and X instructions. The operand is the data memory addressed by the B pointer or X pointer. This is a register indirect mode that automatically post increments or decrements the B or X register after executing the instruction. Direct The instruction contains an 8-bit address field that directly points to the data memory for the operand. 31 www.national.com Addressing Modes Immediate (Continued) The instruction contains an 8-bit immediate field as the operand. Short Immediate This addressing mode is used with the Load B Immediate instruction. The instruction contains a 4-bit immediate field as the operand. Indirect This addressing mode is used with the LAID instruction. The contents of the accumulator are used as a partial address (lower 8 bits of PC) for accessing a data operand from the program memory. TRANSFER OF CONTROL ADDRESSING MODES Relative This mode is used for the JP instruction, with the instruction field being added to the program counter to get the new program location. JP has a range from −31 to +32 to allow a 1-byte relative jump (JP + 1 is implemented by a NOP instruction). There are no “pages” when using JP, since all 15 bits of PC are used. Absolute This mode is used with the JMP and JSR instructions, with the instruction field of 12 bits replacing the lower 12 bits of the program counter (PC). This allows jumping to any location in the current 4k program memory segment. Absolute Long This mode is used with the JMPL and JSRL instructions, with the instruction field of 15 bits replacing the entire 15 bits of the program counter (PC). This allows jumping to any location up to 32k in the program memory space. Indirect This mode is used with the JID instruction. The contents of the accumulator are used as a partial address (lower 8 bits of PC) for accessing a location in the program memory. The contents of this program memory location serve as a partial address (lower 8 bits of PC) for the jump to the next instruction. INSTRUCTION SET ADD ADC SUBC AND ANDSZ OR XOR IFEQ IFEQ IFNE IFGT IFBNE DRSZ A,Meml A,Meml A,Meml A,Meml A,Imm A,Meml A,Meml MD,Imm A,Meml A,Meml A,Meml ADD ADD with Carry Subtract with Carry Logical AND Logical AND Immed., Skip if Zero Logical OR Logical EXclusive OR IF EQual IF EQual IF Not Equal IF Greater Than If B Not Equal Decrement Reg., Skip if Zero Note: The VIS is a special case of the Indirect Transfer of Control addressing mode, where the double byte vector associated with the interrupt is transferred from adjacent addresses in the program memory into the program counter (PC) in order to jump to the associated interrupt service routine. Instruction Set Register and Symbol Definition Registers A B X SP PC PU PL C HC GIE VU VL [B] [X] MD Mem Meml Imm Reg Bit ← 8-Bit Accumulator Register 8-Bit Address Register 8-Bit Address Register 8-Bit Stack Pointer Register 15-Bit Program Counter Register Upper 7 Bits of PC Lower 8 Bits of PC 1-Bit of PSW Register for Carry 1-Bit of PSW Register for Half Carry 1-Bit of PSW Register for Global Interrupt Enable Interrupt Vector Upper Byte Interrupt Vector Lower Byte Symbols Memory Indirectly Addressed by B Register Memory Indirectly Addressed by X Register Direct Addressed Memory Direct Addressed Memory or [B] Direct Addressed Memory or [B] or Immediate Data 8-Bit Immediate Data Register Memory: Addresses F0 to FF (Includes B, X and SP) Bit Number (0 to 7) Loaded with Exchanged with ↔ A ← A + Meml A ← A + Meml + C, C ← Carry, HC ← Half Carry A ← A − MemI + C, C ← Carry, HC ← Half Carry A ← A and Meml Skip next if (A and Imm) = 0 A ← A or Meml A ← A xor Meml Compare MD and Imm, Do next if MD = Imm Compare A and Meml, Do next if A = Meml Compare A and Meml, Do next if A ≠ Meml Compare A and Meml, Do next if A > Meml Do next if lower 4 bits of B ≠ Imm Reg ← Reg − 1, Skip if Reg = 0 # Reg www.national.com 32 Instruction Set SBIT RBIT IFBIT RPND X X LD LD LD LD LD X X LD LD LD CLR INC DEC LAID DCOR RRC RLC SWAP SC RC IFC IFNC POP PUSH VIS JMPL JMP JP JSRL JSR JID RET RETSK RETI INTR NOP Addr. Addr. Disp. Addr. Addr A A A A A A A,Mem A,[X] A,Meml A,[X] B,Imm Mem,Imm Reg,Imm A, [B ± ] A, [X ± ] A, [B ± ] A, [X ± ] [B ± ],Imm A A A (Continued) Set BIT Reset BIT IF BIT Reset PeNDing Flag EXchange A with Memory EXchange A with Memory [X] LoaD A with Memory LoaD A with Memory [X] LoaD B with Immed. LoaD Memory Immed LoaD Register Memory Immed. EXchange A with Memory [B] EXchange A with Memory [X] LoaD A with Memory [B] LoaD A with Memory [X] LoaD Memory [B] Immed. CLeaR A INCrement A DECrement A Load A InDirect from ROM Decimal CORrect A Rotate A Right thru C Rotate A Left thru C SWAP nibbles of A Set C Reset C IF C IF Not C POP the stack into A PUSH A onto the stack Vector to Interrupt Service Routine Jump absolute Long Jump absolute Jump relative short Jump SubRoutine Long Jump SubRoutine Jump InDirect RETurn from subroutine RETurn and SKip RETurn from Interrupt Generate an Interrupt No OPeration 1 to bit, Mem (bit = 0 to 7 immediate) 0 to bit, Mem If bit #,A or Mem is true do next instruction Reset Software Interrupt Pending Flag A ↔ Mem A ↔ [X] A ← Meml A ← [X] B ← Imm Mem ← Imm Reg ← Imm A ↔ [B], (B ← B ± 1) A ↔ [X], (X ←X ± 1) A ← [B], (B ← B ± 1) A ← [X], (X ← X ± 1) [B] ← Imm, (B ← B ± 1) A←0 A←A+1 A←A−1 A ← ROM (PU,A) A ← BCD correction of A (follows ADC, SUBC) C → A7 → ... → A0 → C C ← A7 ←... ← A0 ← C A7...A4 ↔ A3...A0 C ← 1, HC ← 1 C ← 0, HC ← 0 IF C is true, do next instruction If C is not true, do next instruction SP ← SP + 1, A ← [SP] [SP] ← A, SP ← SP − 1 PU ← [VU], PL ←[VL] PC ← ii (ii = 15 bits, 0 to 32k) PC9...0 ← i (i = 12 bits) PC ← PC + r (r is −31 to +32, except 1) [SP] ←PL, [SP-1] ← PU,SP-2, PC ← ii [SP] ←PL, [SP-1] ← PU,SP-2, PC9...0 ← i PL ←ROM (PU,A) SP + 2, PL← [SP], PU ← [SP-1] SP + 2, PL← [SP],PU ← [SP-1], skip next instruction SP + 2, PL ← [SP],PU ← [SP-1],GIE ←1 [SP] ← PL, [SP-1]← PU, SP-2, PC ← 0FF PC ← PC + 1 #,Mem #,Mem #,Mem 33 www.national.com Instruction Set (Continued) Instruction Execution Time Most instructions are single byte (with immediate addressing mode instructions taking two bytes). Most single byte instructions take one cycle time to execute. Skipped instructions require x number of cycles to be skipped, where x equals the number of bytes in the skipped instruction opcode. See the BYTES and CYCLES per INSTRUCTION table for details. Bytes and Cycles per Instruction The following table shows the number of bytes and cycles for each instruction in the format of byte/cycle. Arithmetic and Logic Instructions [B] ADD ADC SUBC AND OR XOR IFEQ IFGT IFBNE DRSZ SBIT RBIT IFBIT RPND 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/3 3/4 3/4 3/4 Direct 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Immed 2/2 2/2 2/2 2/2 2/2 2/2 2/2 2/2 Transfer of Control Instructions JMPL JMP JP JSRL JSR JID VIS RET RETSK RETI INTR NOP Memory Transfer Instructions Register Indirect [B] X A, (Note 21) LD A, (Note 21) LD B,Imm LD B,Imm LD Mem,Imm LD Reg,Imm IFEQ MD,Imm Note 21: Memory location addressed by B or X or directly. Instructions Using A and C CLRA INCA DECA LAID DCORA RRCA RLCA SWAPA SC RC IFC IFNC PUSHA POPA ANDSZ 1/1 1/1 1/1 1/3 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/3 1/3 2/2 3/4 2/3 1/3 3/5 2/5 1/3 1/5 1/5 1/5 1/5 1/7 1/1 Register Indirect Direct 2/3 2/3 2/2 1/1 2/2 Immed. Auto Incr and Decr [B+, B−] 1/2 1/2 [X+, X−] 1/3 1/3 (If B < 16) (If B > 15) 2/2 [X] 1/3 1/3 1/1 1/1 2/2 3/3 2/3 3/3 www.national.com 34 Opcode Table UPPER NIBBLE D DRSZ 0F0 DRSZ 0F1 DRSZ 0F2 DRSZ 0F3 DRSZ 0F4 DRSZ 0F5 DRSZ 0F6 DRSZ 0F7 DRSZ 0F8 DRSZ 0F9 DRSZ 0FA DRSZ 0FB DRSZ 0FC DRSZ 0FD DRSZ 0FE DRSZ 0FF * * * * * F RRCA SC X A,[B+] X A,[B−] LAID JID X A,[B] OR A,#i IFC IFNC INCA DECA POPA RETSK RET RETI SBIT 7,[B] SBIT 6,[B] SBIT 5,[B] RBIT 5,[B] RBIT 6,[B] RBIT 7,[B] SBIT 4,[B] RBIT 4,[B] LD B,#03 LD B,#02 LD B,#01 LD B,#00 SBIT 3,[B] RBIT 3,[B] LD B,#04 SBIT 2,[B] RBIT 2,[B] LD B,#05 IFBNE 0A IFBNE 0B IFBNE 0C IFBNE 0D IFBNE 0E IFBNE 0F SBIT 1,[B] RBIT 1,[B] LD B,#06 IFBNE 9 SBIT 0,[B] RBIT 0,[B] LD B,#07 IFBNE 8 JSR x800–x8FF JSR x900–x9FF OR A,[B] IFBIT PUSHA 7,[B] LD B,#08 IFBNE 7 JSR x700–x7FF XOR A,#i XOR A,[B] IFBIT DCORA 6,[B] LD B,#09 IFBNE 6 JSR x600–x6FF AND A,#i AND A,[B] IFBIT SWAPA LD 5,[B] B,#0A IFBNE 5 JSR x500–x5FF ADD A,#i ADD A,[B] IFBIT 4,[B] CLRA LD B,#0B IFBNE 4 JSR x400–x4FF IFGT A,#i IFGT A,[B] LD B,#0C IFBIT 3,[B] * E RC SUBC A,#i IFEQ A,#i IFBNE 3 JSR x300–x3FF JMP JP+20 JP+4 x300–x3FF JMP JP+21 JP+5 x400–x4FF JMP JP+22 JP+6 x500–x5FF JMP JP+23 JP+7 x600–x6FF JMP JP+24 JP+8 x700–x7FF JMP JP+25 JP+9 x800–x8FF 3 4 5 6 7 8 JMP JP+26 JP+10 9 x900–x9FF JSR JMP JP+27 JP+11 A xA00–xAFF xA00–xAFF JSR JMP JP+28 JP+12 B xB00–xBFF xB00–xBFF JSR JMP JP+29 JP+13 C xC00–xCFF xC00–xCFF JSR JMP JP+30 JP+14 D xD00–xDFF xD00–xDFF JSR JMP JP+31 JP+15 E xE00–xEFF xE00–xEFF JSR JMP JP+32 JP+16 F xF00–xFFF xF00–xFFF IFEQ A,[B] LD B,#0D IFBIT 2,[B] * C ADC A,#i SUBC A,[B] LD B,#0E IFBNE 2 JSR x200–x2FF JMP JP+19 JP+3 x200–x2FF 2 IFBIT 1,[B] * B ADC A,[B] IFBNE 1 JSR x100–x1FF JMP JP+18 JP+2 x100–x1FF 1 IFBIT ANDSZ 0,[B] A,#i LD B,#0F IFBNE 0 JSR x000–x0FF JMP JP+17 INTR x000–x0FF 0 A 9 8 7 6 5 4 3 2 1 0 JP−15 JP−31 LD 0F0,#i Instruction Set JP−14 X A,[X+] X A,[X−] VIS RPND X A,[X] JP−30 LD 0F1,#i JP−13 JP−29 LD 0F2,#i (Continued) JP−12 JP−28 LD 0F3,#i JP−11 JP−27 LD 0F4,#i JP−10 JP−26 LD 0F5,#i JP−9 JP−25 LD 0F6,#i JP−8 NOP IFNE A,[B] LD A,[X+] LD A,[X−] LD Md,#i DIR LD A,[X] LD B,#i LD A,[B] LD [B],#i JSRL LD A,Md JMPL X A,Md LD A,[B−] LD [B−],#i LD A,[B+] LD [B+],#i IFEQ Md,#i IFNE A,#i RLCA LD A,#i JP−24 LD 0F7,#i JP−5 JP−21 LD 0FA,#i JP−4 JP−20 LD 0FB,#i JP−3 JP−19 LD 0FC,#i JP−2 JP−18 LD 0FD,#i JP−1 JP−17 LD 0FE,#i JP−0 JP−16 LD 0FF,#i www.national.com where, i is the immediate data Md is a directly addressed memory location * is an unused opcode The opcode 60 Hex is also the opcode for IFBIT #i,A LOWER NIBBLE 35 JP−7 JP−23 LD 0F8,#i JP−6 JP−22 LD 0F9,#i Development Tools Support OVERVIEW National is engaged with an international community of independent 3rd party vendors who provide hardware and software development tool support. Through National’s interaction and guidance, these tools cooperate to form a choice of solutions that fits each developer’s needs. This section provides a summary of the tool and development kits currently available. Up-to-date information, selection guides, free tools, demos, updates, and purchase information can be obtained at our web site at: www.national.com/cop8. SUMMARY OF TOOLS COP8 Evaluation Tools cludes BCLIDE (Byte Craft Limited Integrated Development Environment) for Win32, editor, optimizing C CrossCompiler, macro cross assembler, BC-Linker, and MetaLink tools support. (DOS/SUN versions available; Compiler is installable under WCOP8 IDE; Compatible with DriveWay COP8). • EWCOP8-KS: Very Low cost ANSI C-Compiler and Embedded Workbench from IAR (Kickstart version: COP8Sx/Fx only with 2k code limit; No FP). A fully integrated Win32 IDE, ANSI C-Compiler, macro assembler, editor, linker, Liberian, C-Spy simulator/debugger, PLUS MetaLink EPU/DM emulator support. EWCOP8-AS: Moderately priced COP8 Assembler and Embedded Workbench from IAR (no code limit). A fully integrated Win32 IDE, macro assembler, editor, linker, librarian, and C-Spy high-level simulator/debugger with I/O and interrupts support. (Upgradeable with optional C-Compiler and/or MetaLink Debugger/Emulator support). EWCOP8-BL: Moderately priced ANSI C-Compiler and Embedded Workbench from IAR (Baseline version: All COP8 devices; 4k code limit; no FP). A fully integrated Win32 IDE, ANSI C-Compiler, macro assembler, editor, linker, librarian, and C-Spy high-level simulator/debugger. (Upgradeable; CWCOP8-M MetaLink tools interface support optional). EWCOP8: Full featured ANSI C-Compiler and Embedded Workbench for Windows from IAR (no code limit). A fully integrated Win32 IDE, ANSI C-Compiler, macro assembler, editor, linker, librarian, and C-Spy high-level simulator/debugger. (CWCOP8-M MetaLink tools interface support optional). • • COP8–NSEVAL: Free Software Evaluation package for Windows. A fully integrated evaluation environment for COP8, including versions of WCOP8 IDE (Integrated Development Environment), COP8-NSASM, COP8-MLSIM, COP8C, DriveWay™ COP8, Manuals, and other COP8 information. COP8–MLSIM: Free Instruction Level Simulator tool for Windows. For testing and debugging software instructions only (No I/O or interrupt support). COP8–EPU: Very Low cost COP8 Evaluation & Programming Unit. Windows based evaluation and hardware-simulation tool, with COP8 device programmer and erasable samples. Includes COP8-NSDEV, Driveway COP8 Demo, MetaLink Debugger, I/O cables and power supply. COP8–EVAL-ICUxx: Very Low cost evaluation and design test board for COP8ACC and COP8SGx Families, from ICU. Real-time environment with add-on A/D, D/A, and EEPROM. Includes software routines and reference designs. • • • • • Manuals, Applications Notes, Literature: Available free from our web site at: www.national.com/cop8. COP8 Integrated Software/Hardware Design Development Kits • EWCOP8-M: Full featured ANSI C-Compiler and Embedded Workbench for Windows from IAR (no code limit). A fully integrated Win32 IDE, ANSI C-Compiler, macro assembler, editor, linker, librarian, C-Spy high-level simulator/debugger, PLUS MetaLink debugger/hardware interface (CWCOP8-M). COP8 Productivity Enhancement Tools • • • COP8-EPU: Very Low cost Evaluation & Programming Unit. Windows based development and hardwaresimulation tool for COPSx/xG families, with COP8 device programmer and samples. Includes COP8-NSDEV, Driveway COP8 Demo, MetaLink Debugger, cables and power supply. WCOP8 IDE: Very Low cost IDE (Integrated Development Environment) from KKD. Supports COP8C, COP8NSASM, COP8-MLSIM, DriveWay COP8, and MetaLink debugger under a common Windows Project Management environment. Code development, debug, and emulation tools can be launched from the project window framework. DriveWay-COP8: Low cost COP8 Peripherals Code Generation tool from Aisys Corporation. Automatically generates tested and documented C or Assembly source code modules containing I/O drivers and interrupt handlers for each on-chip peripheral. Application specific code can be inserted for customization using the integrated editor. (Compatible with COP8-NSASM, COP8C, and WCOP8 IDE.) COP8-UTILS: Free set of COP8 assembly code examples, device drivers, and utilities to speed up code development. COP8-MLSIM: Free Instruction Level Simulator tool for Windows. For testing and debugging software instructions only (No I/O or interrupt support). • COP8-DM: Moderate cost Debug Module from MetaLink. A Windows based, real-time in-circuit emulation tool with COP8 device programmer. Includes COP8-NSDEV, DriveWay COP8 Demo, MetaLink Debugger, power supply, emulation cables and adapters. COP8 Development Languages and Environments • • COP8-NSASM: Free COP8 Assembler v5 for Win32. Macro assembler, linker, and librarian for COP8 software development. Supports all COP8 devices. (DOS/Win16 v4.10.2 available with limited support). (Compatible with WCOP8 IDE, COP8C, and DriveWay COP8). COP8-NSDEV: Very low cost Software Development Package for Windows. An integrated development environment for COP8, including WCOP8 IDE, COP8NSASM, COP8-MLSIM. COP8C: Moderately priced C Cross-Compiler and Code Development System from Byte Craft (no code limit). In36 • • • • www.national.com Development Tools Support (Continued) COP8 Real-Time Emulation Tools COP8 Device Programmer Support • • MetaLink’s EPU and Debug Module include development device programming capability for COP8 devices. Third-party programmers and automatic handling equipment cover needs from engineering prototype and pilot production, to full production environments. Factory programming available for high-volume requirements. • COP8-DM: MetaLink Debug Module. A moderately priced real-time in-circuit emulation tool, with COP8 device programmer. Includes COP8-NSDEV, DriveWay COP8 Demo, MetaLink Debugger, power supply, emulation cables and adapters. • IM-COP8: MetaLink iceMASTER ® . A full featured, realtime in-circuit emulator for COP8 devices. Includes MetaLink Windows Debugger, and power supply. Packagespecific probes and surface mount adaptors are ordered separately. • TOOLS ORDERING NUMBERS FOR THE COP8ACC7 FAMILY DEVICES Vendor National Tools COP8-NSEVAL COP8-NSASM COP8-MLSIM COP8-NSDEV COP8-EPU COP8-DM Development Devices OTP Programming Adapters IM-COP8 MetaLink COP8-EPU COP8-DM Order Number COP8-NSEVAL COP8-NSASM COP8-MLSIM COP8-NSDEV Not available for this device Contact MetaLink COP8ACC7 PN# EDI 28D (SO)/40D-Z-COP8LXC Contact MetaLink Not available for this device DM4-COP8-ACx (10 MHz), plus PS-10, plus DM-COP8/xxx (ie. 28D) MHW-CNV38 or 39 PN# EDI 28D (SO)/40D-Z-COP8LXC IM-COP8-AD-464 (-220) (10 MHz maximum) PC-8AC28DW-AD-10 IM Probe Target Adapter ICU KKD IAR Byte Craft Aisys COP8-EVAL WCOP8-IDE EWCOP8-xx COP8C DriveWay COP8 MHW-SOIC28 COP8-EVAL_ICUAC WCOP8-IDE See summary above COP8C DriveWay COP8 Contact vendors M Included p/s (PS-10), target cable of choice (DIP or PLCC; i.e. DM-COP8/28D), EDI programming sockets. Add target adapter (if needed) DM target converters for 20SO or 28SO; (i.e. MHW-CNV38 for 20 pin DIP to SO package converter) For programming 20/28 SOIC and DIP on any programmer. Base unit 10 MHz; -220 = 220V; add probe card (required) and target adapter (if needed); included software and manuals 10 MHz 20/28 DIP probe card; 2.5V to 5.5V 28 pin SOIC adapter for probe card No poweer supply Included in EPU and DM Included all software and manuals Included all software and manuals Included all software and manuals For approved programmer listings and vendor information, go to our OTP support page at: www.national.com/cop8 VL L 16k OTP devices; 20/28 pin. For programming 20/28 SOIC and DIP on any programmer. Cost Free Free Free VL Web site download Included in EPU and DM. Web site download Included in EPU and DM. Web site download Included in EPU and DM. Order CD from website Notes DM Target Adapters OTP Programming Adapters IM-COP8 L L H M L L VL L-H M L L-H OTP Programmers Cost: Free; VL = < $100; L = $100 - $300; M = $300 - $1k; H = $1k - $3k; VH = $3k - $5k 37 www.national.com Development Tools Support WHERE TO GET TOOLS (Continued) Tools are ordered directly from the following vendors. Please go to the vendor’s web site for current listings of distributors. Vendor Aisys Home Office U.S.A.: Santa Clara, CA 1-408-327-8820 fax: 1-408-327-8830 Byte Craft U.S.A. 1-519-888-6911 fax: 1-519-746-6751 IAR Sweden: Uppsala +46 18 16 78 00 fax: +46 18 16 78 38 www.iar.se info@iar.se info@iar.com info@iarsys.co.uk info@iar.de U.S.A.: San Francisco 1-415-765-5500 fax: 1-415-765-5503 U.K.: London +44 171 924 33 34 fax: +44 171 924 53 41 Germany: Munich +49 89 470 6022 fax: +49 89 470 956 ICU Sweden: Polygonvaegen +46 8 630 11 20 fax: +46 8 630 11 70 KKD MetaLink Denmark: U.S.A.: Chandler, AZ 1-800-638-2423 fax: 1-602-926-1198 www.icu.se support@icu.se support @icu.ch www.kkd.dk www.metaice.com sales @metaice.com support @metaice.com bbs: 1-602-962-0013 www.metalink.de National U.S.A.: Santa Clara, CA 1-800-272-9959 fax: 1-800-737-7018 www.national.com/cop8 support @nsc.com europe.support @nsc.com Germany: Kirchseeon 80-91-5696-0 fax: 80-91-2386 islanger@metalink.de Distributors Worldwide Europe: +49 (0) 180 530 8585 fax: +49 (0) 180 530 8586 Distributors Worldwide Switzeland: Hoehe +41 34 497 28 20 fax: +41 34 497 28 21 www.bytecraft.com info @bytecraft.com Distributors Electronic Sites www.aisysinc.com info@aisysinc.com Other Main Offices Distributors The following companies have approved COP8 programmers in a variety of configurations. Contact your local office or distributor. You can link to their web sites and get the latest listing of approved programmers from National’s COP8 OTP Support page at: www.national.com/cop8. Advantech; Advin; BP Microsystems; Data I/O; Hi-Lo Systems; ICE Technology; Lloyd Research; Logical Devices; MQP; Needhams; Phyton; SMS; Stag Programmers; System General; Tribal Microsystems; Xeltek. Customer Support Complete product information and technical support is available from National’s customer response centers, and from our on-line COP8 customer support sites. www.national.com 38 Physical Dimensions inches (millimeters) unless otherwise noted Order Number COP8ACC728N9–XE/RE or COP8ACC728N8–XE/RE NS Molded Package Number N28B Order Number COP8ACC728M9–XE/RE or COP8ACC728M8–XE/RE NS Molded Package Number M28B 39 www.national.com COP8ACC7 8-Bit CMOS OTP Microcontroller with 16k Memory and High Resolution A/D Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Order Number COP8ACC720M9–XE/RE or COP8ACC720M8–XE/RE NS Molded Package Number M20B LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com www.national.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: sea.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.