COP8SE

COP8SE Family, 8-Bit CMOS ROM Based and OTP Microcontrollers with 4k Memory and 128 Bytes EERAM July 1999 COP8SE Family 8-Bit CMOS ROM Based and OTP Microcontrollers with 4k Memory and 128 Bytes EERAM General Description The COP8SEx5 Family ROM based microcontrollers are highly integrated COP8™ Feature core devices with 4k memory and advanced features including EERAM. COP8SER7 devices are pin and software compatible (different VCC range), 32k OTP (One Time Programmable) versions for engineering development use with a range of COP8 software and hardware development tools. Family features include an 8-bit memory mapped architecture, 10 MHz CKI with 1µs instruction cycle, 128 bytes of EEDevice COP8SEC5 COP8SER7-XE xtal OSC Memory (bytes) 4k ROM 32k OTP EPROM RAM (bytes) 128 128 128 RAM, one multi-function 16-bit timer/counter, idle timer with MIWU, MICROWIRE/PLUS™, serial I/O, crystal or R/C oscillator, two power saving HALT/IDLE modes, Schmitt trigger inputs, software selectable I/O options, WATCHDOG™ timer and Clock Monitor, Low EMI 2.7V to 5.5V operation, and 16/20 pin packages. Devices included in this data sheet are: EERAM 128 bytes 128 bytes 128 bytes I/O Pins 12/16 16 16 Package 20 SOIC 20 SOIC Temperature -40 to +85˚C, Engineering -use only 16/20 SOIC -40 to +85˚C, -40 to +135˚C COP8SER7-RE R/C 32k OTP EPROM Key Features n 256 bytes data memory — 128 bytes RAM — 128 bytes EERAM n OTP with security feature (SER7) n Quiet Design (low radiated emissions) n Multi-Input Wakeup pins with optional interrupts (8 pins) n User selectable clock options: — R/C oscillator — Crystal oscillator n n Other Features Fully static CMOS, with low current drain Available with Crystal (-XE) or RC (-RE) oscillator Two power saving modes: HALT and IDLE 1 µs instruction cycle time 4k bytes on-board masked ROM or 32k bytes OTP Single supply operation: 2.7V — 5.5V MICROWIRE/PLUS Serial Peripheral Interface Compatible n Nine multi-source vectored interrupts servicing — EERAM write complete — External interrupt — Idle Timer T0 — One Timer (with 2 Interrupts) — MICROWIRE/PLUS Serial Interface — Multi-Input Wake Up n n n n n n n n n n n n n n n n n n n — Software Trap — Default VIS Idle Timer with programmable interrupt interval One 16 bit timer with two 16-bit registers supporting: — Processor Independent PWM mode — External Event counter mode — Input Capture mode 8-bit Stack Pointer SP (stack in RAM) Two 8-bit Register Indirect Data Memory Pointers Versatile instruction set True bit manipulation Memory mapped I/O BCD arithmetic instructions WATCHDOG and Clock Monitor logic Software selectable I/O options: — TRI-STATE ® Output: — Push-Pull Output — Weak Pull Up Input — High Impedance Input Schmitt trigger inputs on ports G and L Temperature ranges: — −40˚C to +85˚C — −40˚C to +135˚C (SEC5 only) Packaging: 16, and 20 SO (SEC5); 20 SO (SER7) Real time emulation and full program debug offered by MetaLink Development System TRI-STATE ® is a registered trademark of National Semiconductor Corporation. MICROWIRE/PLUS™, COP8™, MICROWIRE™ and WATCHDOG™ are trademarks of National Semiconductor Corporation. iceMASTER™ is a trademark of MetaLink Corporation. PC ® is a registered trademark of International Business Machines Corporation. © 1999 National Semiconductor Corporation DS100973 www.national.com Block Diagram DS100973-44 FIGURE 1. Block Diagram 1.0 Device Description 1.1 ARCHITECTURE The COP8 family is based on a modified Harvard architecture, which allows data tables to be accessed directly from program memory. This is very important with modern microcontroller-based applications, since program memory is usually ROM or EPROM, while data memory is usually RAM. Consequently data tables need to be contained in non-volatile memory, so they are not lost when the microcontroller is powered down. Non-memory for the storage of data variables is provided by the EERAM in the COP8SEC5 and COP8SER7. In a Harvard architecture, instruction fetch and memory data transfers can be overlapped with a two stage pipeline, which allows the next instruction to be fetched from program memory while the current instruction is being executed using data memory. This is not possible with a Von Neumann single-address bus architecture. The COP8 family supports a software stack scheme that allows the user to incorporate many subroutine calls. This capability is important when using High Level Languages. With a hardware stack, the user is limited to a small fixed number of stack levels. 1.2 INSTRUCTION SET In today’s 8-bit microcontroller application arena cost/ performance, flexibility and time to market are several of the key issues that system designers face in attempting to build well-engineered products that compete in the marketplace. Many of these issues can be addressed through the manner in which a microcontroller’s instruction set handles processing tasks. And that’s why the COP8 family offers a unique and code-efficient instruction set — one that provides the flexibility, functionality, reduced costs and faster time to market that today’s microcontroller based products require. Code efficiency is important because it enables designers to pack more on-chip functionality into less program memory www.national.com 2 space (ROM/OTP). Selecting a microcontroller with less program memory size translates into lower system costs, and the added security of knowing that more code can be packed into the available program memory space. 1.2.1 Key Instruction Set Features The COP8 family incorporates a unique combination of instruction set features, which provide designers with optimum code efficiency and program memory utilization. Single Byte/Single Cycle Code Execution The efficiency is due to the fact that the majority of instructions are of the single byte variety, resulting in minimum program space. Because compact code does not occupy a substantial amount of program memory space, designers can integrate additional features and functionality into the microcontroller program memory space. Also, the majority instructions executed by the device are single cycle, resulting in minimum program execution time. In fact, 77% of the instructions are single byte single cycle, providing greater code and I/O efficiency, and faster code execution. 1.2.2 Many Single-Byte, Multifunction Instructions The COP8 instruction set utilizes many single-byte, multifunction instructions. This enables a single instruction to accomplish multiple functions, such as DRSZ, DCOR, JID, LD (Load) and X (Exchange) instructions with post-incrementing and post-decrementing, to name just a few examples. In many cases, the instruction set can simultaneously execute as many as three functions with the same single-byte instruction. JID: (Jump Indirect); Single byte instruction; decodes external events and jumps to corresponding service routines (analogous to “DO CASE” statements in higher level languages). LAID: (Load Accumulator-Indirect); Single byte look up table instruction provides efficient data path from the program 1.0 Device Description (Continued) memory to the CPU. This instruction can be used for table lookup and to read the entire program memory for checksum calculations. RETSK: (Return Skip); Single byte instruction allows return from subroutine and skips next instruction. Decision to branch can be made in the subroutine itself, saving code. AUTOINC/DEC: (Auto-Increment/Auto-Decrement); These instructions use the two memory pointers B and X to efficiently process a block of data (analogous to “FOR NEXT” in higher level languages). 1.2.3 Bit-Level Control Bit-level control over many of the microcontroller’s I/O ports provides a flexible means to ease layout concerns and save board space. All members of the COP8 family provide the ability to set, reset and test any individual bit in the data memory address space, including memory-mapped I/O ports and associated registers. 1.2.4 Register Set Three memory-mapped pointers handle register indirect addressing and software stack pointer functions. The memory data pointers allow the option of post-incrementing or postdecrementing with the data movement instructions (LOAD/ EXCHANGE). And 15 memory-maped registers allow designers to optimize the precise implementation of certain specific instructions. 1.3 PACKAGING/PIN EFFICIENCY Real estate and board configuration considerations demand maximum space and pin efficiency, particularly given today’s high integration and small product form factors. Microcontroller users try to avoid using large packages to get the I/O needed. Large packages take valuable board space and increase device cost, two trade-offs that microcontroller designs can ill afford. The COP8 family offers a wide range of packages and does not waste pins: up to 90.9% (or 40 pins in the 44-pin package, these packages are not available on all COP8 devices) are devoted to useful I/O. Connection Diagrams DS100973-6 Top View Order Number COP8SEC516M See NS Package Number M16B DS100973-43 Top View Order Number COP8SEC520M or COP8SER720M See NS Package Number M20B FIGURE 2. Connection Diagrams 3 www.national.com Connection Diagrams Port L0 L1 L2 L3 L4 L5 L6 L7 G0 G1 G2 G3 G4 G5 G6 G7 D0 D1 D2 D3 F0 F1 F2 F3 VCC GND CKI RESET I I Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I O O O O I/O I/O I/O I/O (Continued) Pinouts for 16-, and 20-Pin Packages Alt. Fun MIWU MIWU MIWU MIWU MIWU MIWU MIWU MIWU INT WDOUT* T1B T1A SO SK SI CKO 20-Pin SO 7 8 9 10 11 12 13 14 17 18 19 20 1 2 3 4 13 14 15 16 1 2 3 4 16-Pin SO 7 8 9 10 6 15 5 16 6 11 5 12 * G1 operation as WDOUT is controlled by Mask Option. 2.1 Ordering Information DS100973-8 FIGURE 3. Part Numbering Scheme www.national.com 4 3.0 Electrical Characteristics Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) Voltage at Any Pin Total Current into VCC Pin (Source) Total Current out of GND Pin (Sink) 7V −0.3V to VCC +0.3V 80 mA 100 mA Storage Temperature Range ESD Protection Level ESD Protection Level (CKI pin) −65˚C to +150˚C 2 kV(Human Body Model) 150 V(Machine Model) Note 1: Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings. Note 2: The COP8SER7 is for Engineering Development purpose only and is not recommended for production or pre-production use. DC Electrical Characteristics −40˚C ≤ TA ≤ +85˚C unless otherwise specified. Parameter Operating Voltage Power Supply Rise Time Power Supply Ripple (Note 4) Supply Current (Note 5) CKI = 10 MHz HALT Current (Note 6) (SEC5) (SER7)(Note 13) VCC = 5.5V, CKI = 0 MHz (SEC5) (SER7) IDLE Current (Note 5) CKI = 10 MHz Input Levels (VIH, VIL) RESET Logic High Logic Low CKI, All Other Inputs Logic High Logic Low Hi-Z Input Leakage Input Pullup Current G and L Port Input Hysteresis VCC = 5.5V VCC = 5.5V, VIN = 0V VCC = 5.5V VCC = 2.7V −2 −40 0.25 Vcc 0.31 Vcc 0.7 Vcc 0.2 Vcc +2 −250 V V µA µA V V 0.8 Vcc 0.2 Vcc V V (SEC5) (SER7) VCC = 5.5V, tC = 1 µs 1.5 1.5 mA mA 8 20 22 µA µA Peak-to-Peak VCC = 5.5V, tC = 1 µs 6 10 mA mA Conditions Min 2.7 10 Typ Max 5.5 50 x 106 0.1 Vcc Units V ns V 5 www.national.com DC Electrical Characteristics −40˚C ≤ TA ≤ +85˚C unless otherwise specified. Parameter Output Current Levels Source (Weak Pull-Up Mode) Source (Push-Pull Mode) Sink (Push-Pull Mode) TRI-STATE Leakage Allowable Sink Current per Pin Maximum Input Current without Latchup (Note 7) RAM Retention Voltage, Vr VCC Rise Time from a VCC ≥ 2.0V Input Capacitance EERAM Number of Write Cycles EERAM Data Retention (Continued) Conditions VCC = 4.5V, VOH = 2.7V VCC = 2.7V, VOH = 1.8V VCC = 4.5V, VOH = 3.3V VCC = 2.7V, VOH = 1.8V VCC = 4.5V, VOL = 0.4V VCC = 2.7V, VOL = 0.4V VCC = 5.5V (Note 9) Room Temp. (Note 9) (Note 9) (Note 9) (Note 9) Min −10 −2.5 −0.4 −0.2 1.6 0.7 −2 Typ Max −110 −33 Units µA µA mA mA mA mA +2 3 µA mA mA V µs ± 200 2 6 7 105 10 pF cycles years www.national.com 6 AC Electrical Characteristics −40˚C ≤ TA ≤ +85˚C unless otherwise specified. Parameter Instruction Cycle Time (tC) Crystal/Resonator R/C Oscillator Frequency Variation (Note 9), (Note 10) CKI Clock Duty Cycle (Note 9) Rise Time (Note 9) Fall Time (Note 9) EERAM Write Cycle Delay from Power-Up to first EERAM Write Cycle Output Propagation Delay (Note 8) tPD1, tPD0 SO, SK All Others MICROWIRE Setup Time (tUWS) (Note 12) MICROWIRE Hold Time (tUWH) (Note 12) MICROWIRE Output Propagation Delay (tUPD)(Note 12) Input Pulse Width (Note 9) Interrupt Input High Time Interrupt Input Low Time Timer 1 Input High Time Timer 1 Input Low Time Reset Pulse Width Note 3: tC = Instruction cycle time. Note 4: Maximum rate of voltage change must be < 0.5 V/ms. Note 5: Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, CKO driven 180˚ out of phase with CKI, inputs connected to VCC and outputs driven low but not connected to a load. Note 6: The HALT mode will stop CKI from oscillating in the R/C and the Crystal configurations. In the R/C configuration, CKI is forced high internally. In the crystal configuration, CKI is TRI-STATE. Measurement of IDD HALT is done with device neither sourcing nor sinking current; with L, G0, and G2–G5 programmed as low outputs and not driving a load; all outputs programmed low and not driving a load; all inputs tied to VCC; WATCHDOG and clock monitor disabled. Parameter refers to HALT mode entered via setting bit 7 of the G Port data register. Note 7: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages > VCC and the pins will have sink current to VCC when biased at voltages > VCC (the pins do not have source current when biased at a voltage below VCC). The effective resistance to VCC is 750Ω (typical). These two pins will not latch up. The voltage at the pins must be limited to < 14V. WARNING: Voltages in excess of 14V will cause damage to the pins. This warning excludes ESD transients. Note 8: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs. Note 9: Parameter characterized but not tested. Note 10: Rise times faster than the minimum specification may trigger an internal power-on-reset. Note 11: Exclusive of R and C variation. Note 12: MICROWIRE Setup and Hold Times and Propagation Delays are referenced to the appropriate edge of the MICROWIRE clock. See Figure 4 and the MICROWIRE operation description. Note 13: COP7SER7 Supply Current during Reset will be somewhat higher. Conditions 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC < 4.5V 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC < 4.5V 4.5V ≤ VCC ≤ 5.5V fr = Max fr = 10 MHz Ext Clock fr = 10 MHz Ext Clock Min 1 2 3 6 45 Typ Max DC DC DC DC Units µs µs µs µs % % ns ns ms µs ± 15 55 12 8 7 15 65 RL = 2.2k, CL = 100 pF 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC < 4.5V 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC < 4.5V 20 56 220 0.7 1.75 1 2.5 µs µs µs µs ns ns ns 1 1 1 1 1 tC tC tC tC µs 7 www.national.com Absolute Maximum Ratings (Note 14) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) Voltage at Any Pin Total Current into VCC Pin (Source) Total Current out of GND Pin (Sink) 7V −0.3V to VCC +0.3V 80 mA 100 mA Storage Temperature Range ESD Protection Level ESD Protection Level (CKI pin) −65˚C to +150˚C 2kV (Human Body Model) 150 V (Machine Model) Note 14: Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings. Note 15: The COP8SER7 is for Engineering Development purpose only and is not recommended for production or pre-production use. DC Electrical Characteristics (SEC5 only) −40˚C ≤ TA ≤ +135˚C unless otherwise specified. Parameter Operating Voltage Power Supply Rise Time Power Supply Ripple (Note 17) Supply Current (Note 18) CKI = 10 MHz HALT Current (Note 19) IDLE Current (Note 18) CKI = 10 MHz Input Levels (VIH, VIL) RESET Logic High Logic Low CKI, All Other Inputs Logic High Logic Low Hi-Z Input Leakage Input Pullup Current G and L Port Input Hysteresis Output Current Levels Source (Weak Pull-Up Mode) Source (Push-Pull Mode) Sink (Push-Pull Mode) TRI-STATE Leakage Allowable Sink Current per Pin (Note 22) Maximum Input Current without Latchup (Note 20) RAM Retention Voltage, Vr VCC Rise Time from a VCC ≥ 2.0V Input Capacitance EERAM Number of Write Cycles EERAM Data Retention (Note 23) (Note 22) (Note 22) (Note 22) 10 105 Room Temp. 2.0 6 7 VCC = 4.5V, VOH = 2.7V VCC = 4.5V, VOH = 3.3V VCC = 4.5V, VOL = 0.4V VCC = 5.5V −9.0 −0.4 1.6 −5 +5 −140 µA mA mA µA VCC = 5.5V VCC = 5.5V, VIN = 0V VCC = 5.5V −5 −35 0.25 Vcc 0.7 Vcc 0.2 Vcc +5 −400 V V µA µA V 0.8 Vcc 0.2 Vcc V V VCC = 5.5V, tC = 1 µs 2 mA VCC = 5.5V, tC = 1 µs VCC = 5.5V, CKI = 0 MHz 15 8 50 mA µA Peak-to-Peak Conditions Min 4.5 10 Typ Max 5.5 50 x 106 0.1 Vcc Units V ns V ± 200 mA V µs pF cycles years www.national.com 8 AC Electrical Characteristics −40˚C ≤ TA ≤ +135˚C unless otherwise specified. Parameter Instruction Cycle Time (tC) Crystal/Resonator, External R/C Oscillator (Internal) Frequency Variation (Note 22), (Note 21) CKI Clock Duty Cycle (Note 22) Rise Time (Note 22) Fall Time (Note 22) EERAM Write Cycle Delay from Power-up to first EERAM Write Cycle Output Propagation Delay (Note 21) tPD1, tPD0 SO, SK All Others MICROWIRE Setup Time (tUWS) (Note 25) MICROWIRE Hold Time (tUWH) (Note 25) MICROWIRE Output Propagation Delay (tUPD) (Note 25) Input Pulse Width (Note 22) Interrupt Input High Time Interrupt Input Low Time Timer 1 Input High Time Timer 1 Input Low Time Reset Pulse Width Note 16: tC = Instruction cycle time. Note 17: Maximum rate of voltage change must be < 0.5 V/ms. Note 18: Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, CKO driven 180˚ out of phase with CKI, inputs connected to VCC and outputs driven low but not connected to a load. Note 19: The HALT mode will stop CKI from oscillating in the R/C and the Crystal configurations. In the R/C configuration, CKI is forced high internally. In the crystal configuration, CKI is TRI-STATE. Measurement of IDD HALT is done with device neither sourcing nor sinking current; with L, G0, and G2–G5 programmed as low outputs and not driving a load; all outputs programmed low and not driving a load; all inputs tied to VCC; clock monitor disabled. Parameter refers to HALT mode entered via setting bit 7 of the G Port data register. Note 20: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages > VCC and the pins will have sink current to VCC when biased at voltages > VCC (the pins do not have source current when biased at a voltage below VCC). The effective resistance to VCC is 750Ω (typical). These two pins will not latch up. The voltage at the pins must be limited to < 14V. WARNING: Voltages in excess of 14V will cause damage to the pins. This warning excludes ESD transients. Note 21: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs. Note 22: Parameter characterized but not tested. Note 23: Rise times faster than the minimum specification may trigger an internal power-on-reset. Note 24: Exclusive of R and C variation. Note 25: MICROWIRE Setup and Hold Times and Propagation Delays are referenced to the appropriate edge of the MICROWIRE clock. See Figure 4 and the MICROWIRE operation description. Conditions 4.5V ≤ VCC ≤ 5.5V 4.5V ≤ VCC ≤ 5.5V 4.5V ≤ VCC ≤ 5.5V fr = Max fr = 10 MHz Ext Clock fr = 10 MHz Ext Clock Min 1 3 45 Typ Max DC DC Units µs µs % % ns ns ms µs ± 20 55 12 8 7 15 65 RL = 2.2k, CL = 100 pF 4.5V ≤ VCC ≤ 5.5V 4.5V ≤ VCC ≤ 5.5V 20 56 220 0.7 1.0 µs µs ns ns ns 1 1 1 1 1 tC tC tC tC µs DS100973-9 FIGURE 4. MICROWIRE/PLUS Timing 9 www.national.com 4.0 Pin Descriptions The device I/O structure enables designers to reconfigure the microcontroller’s I/O functions with a single instruction. Each individual I/O pin can be independently configured as output pin low, output high, input with high impedance or input with weak pull-up device. A typical example is the use of I/O pins as the keyboard matrix input lines. The input lines can be programmed with internal weak pull-ups so that the input lines read logic high when the keys are all open. With a key closure, the corresponding input line will read a logic zero since the weak pull-up can easily be overdriven. When the key is released, the internal weak pull-up will pull the input line back to logic high. This eliminates the need for external pull-up resistors. The high current options are available for driving LEDs, motors and speakers. This flexibility helps to ensure a cleaner design, with fewer external components and lower costs. Below is the general description of all available pins. VCC and GND are the power supply pins. All VCC and GND pins must be connected. CKI is the clock input. This can come from the Internal R/C oscillator, or a crystal oscillator (in conjunction with CKO). See Oscillator Description section. RESET is the master reset input. See Reset description section. Each device contains two bidirectional 8-bit I/O ports (G and L) and one bidirectional 4-I/O port (F), where each individual bit may be independently configured as an input (Schmitt trigger inputs on ports L and G), output or TRI-STATE under program control. Three data memory address locations are allocated for each of these I/O ports. Each I/O port has two associated 8-bit memory mapped registers, the CONFIGURATION register and the output DATA register. A memory mapped address is also reserved for the input pins of each I/O port. (See the memory map for the various addresses associated with the I/O ports.) Figure 5 shows the I/O port configurations. The DATA and CONFIGURATION registers allow for each port bit to be individually configured under software control as shown below: CONFIGURATION Register 0 0 1 1 DATA Register 0 1 0 1 Port Set-Up Hi-Z Input (TRI-STATE Output) Input with Weak Pull-Up Push-Pull Zero Output Push-Pull One Output Port G is an 8-bit port. Pin G0, G2–G5 are bi-directional I/O ports. Pin G6 is always a general purpose Hi-Z input. All pins have Schmitt Triggers on their inputs. Pin G1 serves as the dedicated WATCHDOG output with weak pullup, if WATCHDOG feature is selected by the mask option. The pin is a general purpose I/O, if WATCHDOG feature is not selected. If WATCHDOG feature is selected, bit 1 of the Port G configuration and data register does not have any effect on Pin G1 setup. Pin G7 is either input or output depending on the oscillator option selected. With the crystal oscillator option selected, G7 serves as the dedicated output pin for the CKO clock output. With the R/C oscillator option selected, G7 serves as a general purpose Hi-Z input pin and is also used to bring the device out of HALT mode with a low to high transition on G7. Since G6 is an input only pin and G7 is the dedicated CKO clock output pin (crystal clock option) or general purpose input (R/C or clock option), the associated bits in the data and configuration registers for G6 and G7 are used for special purpose functions as outlined below. Reading the G6 and G7 data bits will return zeroes. Each device will be placed in the HALT mode by writing a “1” to bit 7 of the Port G Data Register. Similarly the device will be placed in the IDLE mode by writing a “1” to bit 6 of the Port G Data Register. Writing a “1” to bit 6 of the Port G Configuration Register enables the MICROWIRE/PLUS to operate with the alternate phase of the SK clock. The G7 configuration bit, if set high, enables the clock start up delay after HALT when the R/C clock configuration is used. Config. Reg. G7 G6 CLKDLY Alternate SK Data Reg. HALT IDLE Port G has the following alternate features: G7 CKO Oscillator dedicated output or general purpose input G6 SI (MICROWIRE Serial Data Input) G5 SK (MICROWIRE Serial Clock) G4 SO (MICROWIRE Serial Data Output) G3 T1A (Timer T1 I/O) G2 T1B (Timer T1 Capture Input) G1 WDOUT WATCHDOG and/or CLock Monitor if WATCHDOG enabled, otherwise it is a general purpose I/O (General purpose I/O is not available on COP8SER7) G0 INTR (External Interrupt Input) Port L is an 8-bit I/O port. All L-pins have Schmitt triggers on the inputs. Port L supports the Multi-Input Wake Up feature on all eight pins. DS100973-10 FIGURE 5. I/O Port Configurations www.national.com 10 4.0 Pin Descriptions (Continued) SP is the 8-bit stack pointer, which points to the subroutine/ interrupt stack (in RAM). With reset the SP is initialized to RAM address 02F Hex (devices with 64 bytes of RAM), or initialized to RAM address 06F Hex (devices with 128 bytes of RAM). All the CPU registers are memory mapped with the exception of the Accumulator (A) and the Program Counter (PC). 5.2 PROGRAM MEMORY The program memory consists of 4096 Bytes of ROM or 32,768 bytes of OTP EPROM. These bytes may hold program instructions or constant data (data tables for the LAID instruction, jump vectors for the JID instruction, and interrupt vectors for the VIS instruction). The program memory is addressed by the 15-bit program counter (PC). All interrupts in the device vector to program memory location 0FF Hex. The contents of the program memory read 00 Hex in the erased state. Program execution starts at location 0 after RESET. 5.3 DATA MEMORY The data memory address space includes the on-chip RAM and data registers, the I/O registers (Configuration, Data and Pin), the control registers, the MICROWIRE/PLUS SIO shift register, and the various registers, and counters associated with the timers (with the exception of the IDLE timer). Data memory is addressed directly by the instruction or indirectly by the B, X and SP pointers. The data memory consists of 256 bytes of combined EERAM and RAM. Sixteen bytes of RAM are mapped as “registers” at addresses 0F0 to 0FE Hex. These registers can be loaded immediately, and also decremented and tested with the DRSZ (decrement register and skip if zero) instruction. The memory pointer registers X, SP and B are memory mapped into this space at address locations 0FC to 0FE Hex respectively, with the other registers (except 0FF) being available for general usage. The instruction set permits any bit in memory to be set, reset or tested. All I/O and registers (except A and PC) are memory mapped; therefore, I/O bits and register bits can be directly and individually set, reset and tested. The accumulator (A) bits can also be directly and individually tested. Note: RAM contents are undefined upon power-up. DS100973-12 FIGURE 6. I/O Port Configurations — Output Mode DS100973-11 FIGURE 7. I/O Port Configurations — Input Mode 5.0 Functional Description The architecture of the devices is a modified Harvard architecture. With the Harvard architecture, the program memory ROM or EPROM is separated from the data store memory (RAM). Program Memory will be referred to as ROM. Both ROM and RAM have their own separate addressing space with separate address buses. The architecture, though based on the Harvard architecture, permits transfer of data from ROM to RAM. 5.1 CPU REGISTERS The CPU can do an 8-bit addition, subtraction, logical or shift operation in one instruction (tC) cycle time. There are six CPU registers: A is the 8-bit Accumulator Register PC is the 15-bit Program Counter Register PU is the upper 7 bits of the program counter (PC) PL is the lower 8 bits of the program counter (PC) B is an 8-bit RAM address pointer, which can be optionally post auto incremented or decremented. X is an 8-bit alternate RAM address pointer, which can be optionally post auto incremented or decremented. S is the 8-bit Segment Address Register used to extend the lower half of the address range (00 to 7F) into 256 data segments of 128 bytes each. 5.4 EERAM / NON-VOLATILE MEMORY The devices provide 128 bytes of EERAM in segment 1 for nonvolatile data memory. The data EERAM can be read and written in exactly the same way as the RAM. All instructions that perform read and write operations on the RAM work similarly upon the data EERAM. EERAM write cycles take much more time than reads. During this time, processing continues, but all EERAM accesses are inhibited. The data EERAM contains all 00s when shipped by the factory. A data memory EERAM programming cycle is initiated by an instruction that writes to the EERAM such as X, LD, SBIT and RBIT. The EERAM memory support circuitry sets the E2BUSY flag in the E2CFG register immediately upon beginning a data EERAM write cycle. It will be automatically reset by the hardware at the end of the data EERAM write cycle. The application program should test the E2BUSY flag before attempting a read or write operation to the data EERAM. An EERAM read or write operation while an operation is in progress will be ignored and the E2ILRW flag in the E2CFG register will be set to indicate the error status. Once the write operation starts, nothing will stop the write operation, not by resetting the device, and not even turning off the VCC will guarantee the write operation to stop. 11 www.national.com 5.0 Functional Description (Continued) Caution: In order to prevent the unexpected setting of the ILRW of the E2CFG Register and the corresponding interrupt, the use of the X Register and direct addressing are recommanded for EERAM access. It is further recommended that the B Register be set to a value between 80 (hex) and FF (hex) before setting the Segment register to 1 and that this value be retained until S is set back to 0. Due to an artifact of the COP8 architecture, the ILRW bit of the E2CFG Register will be set and an interrupt will be generated under the following conditions: 1. The Segment Register (S) = 01, and 2. The B Register points to the EERAM, i.e. B ≤7F (hex), and 3. One of the following instructions is executed: SC, RC, IFC, IFNC, NOP, RPND, SWAPA, JMPL, VIS or LD B, Imm with Imm ≤7F (hex), or 3a. if any instruction is skipped. Warning: The segment register should not point to the EERAM unless the EERAM is addressed. This will prevent inadvertent writes to EERAM. 5.4.1. E2CFG and EE Support Circuitry The EERAM module contains EERAM support circuits to generate all necessary high voltage programming pulses. The E2CFG register provides control and status functions for the EERAM module. The E2CFG register bit assignments are shown below. The E2CFG register is set to 0 on RESET except the E2BUSY bit, which is unaffected. The EECFG register can be accessed at any time without error. Reserved, must be 0 R/W Bit 7 R/W R/W R/W E2PEND R/W E2ILRW R/W E2BUSY RO E2EI R/W Bit 0 The data store memory is either addressed directly by a single byte address within the instruction, or indirectly relative to the reference of the B, X, or SP pointers (each contains a single-byte address). This single-byte address allows an addressing range of 256 locations from 00 to FF hex. The upper bit of this single-byte address divides the data store memory into two separate sections as outlined previously. With the exception of the RAM register memory from address locations 00F0 to 00FF, all RAM memory is memory mapped with the upper bit of the single-byte address being equal to zero. This allows the upper bit of the single-byte address to determine whether or not the base address range (from 0000 to 00FF) is extended. If this upper bit equals one (representing address range 0080 to 00FF), then address extension does not take place. Alternatively, if this upper bit equals zero, then the data segment extension register S is used to extend the base address range (from 0000 to 007F) from XX00 to XX7F, where XX represents the 8 bits from the S register. Thus the 128-byte data segment extensions are located from addresses 0100 to 017F for data segment 1, 0200 to 027F for data segment 2, etc., up to FF00 to FF7F for data segment 255. The base address range from 0000 to 007F represents data segment 0. RESERVED These bits are reserved and must be 0. E2PEND Interrupt Pending Bit. This bit indicates that a write operation has completed and a Write Complete Interrupt is pending. This bit is logically ANDed with the E2EI bit to cause an interrupt. This bit can be written by either hardware or software. This bit must be reset by software after processing the interrupt. E2ILRW EERAM illegal read/write operation. This bit is set when the EERAM array is accessed while E2BUSY is set. This bit will cause an EERAM interrupt, without setting the E2PEND bit, if the E2EI bit is set. This bit can be written by either hardware or software. This bit must be reset by software after processing the interrupt. E2BUSY This bit is set by the hardware when a write to the EERAM is in process and reset by the hardware when the write completes. The E2PEND bit is set when this bit is reset. This bit is software read-only. E2EI Interrupt Enable Bit. Setting this bit enables EERAM interrupts. The default condition is interrupts disabled after RESET. This bit must be used in conjunction with the GIE bit. This bit can be written by software only. 5.5 DATA MEMORY SEGMENT RAM EXTENSION Data memory address 0FF is used as a memory mapped location for the Data Segment Address Register (S). Figure 8 illustrates how the S register data memory extension is used in extending the lower half of the base address range (00 to 7F hex) into 256 data segments of 128 bytes each, with a total addressing range of 32 kbytes from XX00 to XX7F. This organization allows a total of 256 data segments of 128 bytes each with an additional upper base segment of 128 bytes. Furthermore, all addressing modes are available for all data segments. The S register must be changed under program control to move from one data segment (128 bytes) to another. However, the upper base segment (containing the 16 memory registers, I/O registers, control registers, etc.) is always available regardless of the contents of the S register, since the upper base segment (address range 0080 to 00FF) is independent of data segment extension. DS100973-45 FIGURE 8. RAM Organization The instructions that utilize the stack pointer (SP) always reference the stack as part of the base segment (Segment 0), regardless of the contents of the S register. The S register is 12 www.national.com 5.0 Functional Description (Continued) not changed by these instructions. Consequently, the stack (used with subroutine linkage and interrupts) is always located in the base segment. The stack pointer will be initialized to point at data memory location 006F as a result of reset. The 128 bytes of RAM contained in the base segment are split between the lower and upper base segments. The first 112 bytes of RAM are resident from address 0000 to 006F in the lower base segment, while the remaining 16 bytes of RAM represent the 16 data memory registers located at addresses 00F0 to 00FF of the upper base segment. No RAM is located at the upper sixteen addresses (0070 to 007F) of the lower base segment. Additional RAM beyond these initial 128 bytes, however, will always be memory mapped in groups of 128 bytes (or less) at the data segment address extensions (XX00 to XX7F) of the lower base segment. The 128 bytes of EERAM in this device are memory mapped at address locations 0100 to 017F. 5.6 SECURITY FEATURE (COP8SER7 only) The program memory array has an associated Security Byte that is located outside of the program address range. This byte can be addressed only from programming mode by a programmer tool. Security is an optional feature and can only be asserted after the memory array has been programmed and verified. A secured part will read 00(hex) by a programmer. The part will fail Blank Check and will fail Verify operations. A READ operation will fill the programmer’s memory with 00(hex). The Security Byte itself is always readable with value of 00(hex) if unsecure and FF(hex) if secure. 5.7 RESET The devices are initialized when the RESET pin is pulled low. The following occurs upon initialization: Port L: TRI-STATE (High Impedance Input) Port G: TRI-STATE (High Impedance Input) PC: CLEARED to 0000 PSW, CNTRL and ICNTRL registers: CLEARED SIOR: UNAFFECTED after RESET with power already applied RANDOM after RESET at power-on Accumulator, Timer 1: RANDOM after RESET with crystal clock option (power already applied) UNAFFECTED after RESET with R/C clock option (power already applied) RANDOM after RESET at power-on WKEN, WKEDG: CLEARED WKPND: RANDOM SP (Stack Pointer): Initialized to RAM address 06F Hex B and X Pointers: UNAFFECTED after RESET with power already applied RANDOM after RESET at power-on S Register: CLEARED E2CFG: Cleared except the E2BUSY Bit (Bit 1) EERAM: Unaffected ITMR: Cleared RAM: UNAFFECTED after RESET with power already applied RANDOM after RESET at power-on WATCHDOG (if enabled): The device comes out of reset with both the WATCHDOG logic and the Clock Monitor detector armed, with the WATCHDOG service window bits set and the Clock Monitor bit set. The WATCHDOG and Clock Monitor circuits are inhibited during reset. The WATCHDOG service window bits being initialized high default to the maximum WATCHDOG service window of 64k tC clock cycles. The Clock Monitor bit being initialized high will cause a Clock Monitor error following reset if the clock has not reached the minimum specified frequency at the termination of reset. A Clock Monitor error will cause an active low error output on pin G1. This error output will continue until 16 tC–32 tC clock cycles following the clock frequency reaching the minimum specified value, at which time the G1 output will go high. 5.8.1 External Reset The RESET input when pulled low initializes the device. The RESET pin must be held low for a minimum of one instruction cycle to guarantee a valid reset. During Power-Up initialization, the user must ensure that the RESET pin is held low until the device is within the specified VCC voltage. An R/C circuit on the RESET pin with a delay 5 times (5x) greater than the power supply rise time is recommended. Reset should also be wide enough to ensure crystal start-up upon Power-Up. RESET may also be used to cause an exit from the HALT mode. A recommended reset circuit for this device is shown in Figure 9. DS100973-14 RC > 5x power supply rise time. FIGURE 9. Reset Circuit Using External Reset 5.9 OSCILLATOR CIRCUITS These devices can be driven by a clock input on the CKI input pin which can be between DC and 10 MHz. The CKO output clock is on pin G7 (crystal configuration). The CKI input frequency is divided down by 10 to produce the instruction cycle clock (1/tC ). Figure 10 shows the crystal and R/C oscillator connection diagram. 13 www.national.com 5.0 Functional Description (Continued) DS100973-51 DS100973-50 FIGURE 10. Crystal and R/C Oscillator 5.9.1 Crystal Oscillator CKI and CKO can be connected to make a closed loop crystal (or resonator) controlled oscillator. Table 1 shows the component values required for various standard crystal values. TABLE 1. Crystal Oscillator Configuration, TA = 25˚C, VCC = 5V R1 (kΩ) 0 0 5.6 R2 (MΩ) 1 1 1 C1 (pF) 32 39 100 C2 (pF) 32 39 100–156 CKI Freq. (MHz) 10 4 0.455 R (kΩ) 3.3 5.6 6.8 5.9.2 R/C Oscillator By selecting CKI as a single pin oscillator input, a single pin R/C oscillator circuit can be connected to it. CKO is available as a general purpose input, and /or HALT restart input. Table 2 shows the variation in the oscillator frequency as a function of the component (R and C) value. TABLE 2. R/C Oscillator Configuration, TA = 25˚C, VCC = 5V C (pF) 82 100 100 CKI Freq.(MHz) 2.2 to 2.7 1.1 to 1.3 0.9 to 1.1 Instr. Cycle (µs) 3.7 to 4.6 7.4 to 9.0 8.8 to 10.8 www.national.com 14 5.0 Functional Description 5.10 CONTROL REGISTERS CNTRL Register (Address X'00EE) T1C3 Bit 7 T1C2 T1C1 T1C0 MSEL IEDG (Continued) 6.0 Timers Each device contains a very versatile set of timers (T0 and T1). All timers and associated autoreload/capture registers power up containing random data. SL1 SL0 Bit 0 The Timer1 (T1) and MICROWIRE/PLUS control register contains the following bits: T1C3 Timer T1 mode control bit T1C2 T1C1 T1C0 Timer T1 mode control bit Timer T1 mode control bit Timer T1 Start/Stop control in timer modes 1 and 2, T1 Underflow Interrupt Pending Flag in timer mode 3 Selects G5 and G4 as MICROWIRE/PLUS signals SK and SO respectively External interrupt edge polarity select (0 = Rising edge, 1 = Falling edge) Select the MICROWIRE/PLUS clock divide by (00 = 2, 01 = 4, 1x = 8) 6.1 TIMER T0 (IDLE TIMER) Each device supports applications that require maintaining real time and low power with the IDLE mode. This IDLE mode support is furnished by the IDLE timer T0, which is a 16-bit timer. The Timer T0 runs continuously at the fixed rate of the instruction cycle clock, tC. The user cannot read or write to the IDLE Timer T0, which is a count down timer. The Timer T0 supports the following functions: MSEL IEDG SL1 & SL0 PSW Register (Address X'00EF) HC Bit 7 C T1PNDA T1ENA EXPND BUSY EXEN GIE Bit 0 The PSW register contains the following bits: HC Half Carry Flag C Carry Flag T1PNDA Timer T1 Interrupt Pending Flag (Autoreload RA in mode 1, T1 Underflow in Mode 2, T1A capture edge in mode 3) T1ENA Timer T1 Interrupt Enable for Timer Underflow or T1A Input capture edge EXPND External interrupt pending BUSY MICROWIRE/PLUS busy shifting flag EXEN Enable external interrupt GIE Global interrupt enable (enables interrupts) The Half-Carry flag is also affected by all the instructions that affect the Carry flag. The SC (Set Carry) and R/C (Reset Carry) instructions will respectively set or clear both the carry flags. In addition to the SC and R/C instructions, ADC, SUBC, RRC and RLC instructions affect the Carry and Half Carry flags. ICNTRL Register (Address X'00E8) Reserved Bit 7 LPEN T0PND T0EN µWPND µWEN T1PNDB T1ENB Bit 0 • Exit out of the Idle Mode (See Idle Mode description) • WATCHDOG logic (See WATCHDOG description) • Start up delay out of the HALT mode Figure 11 is a functional block diagram showing the structure of the IDLE Timer and its associated interrupt logic. Bits 11 through 15 of the Idle Timer register can be selected for triggering the IDLE Timer interrupt. Each time the selected bit underflows (every 4k, 8k, 16k, 32k or 64k instruction cycles), the IDLE Timer interrupt pending bit T0PND is set, thus generating an interrupt (if enabled), and bit 6 of the Port G data register is reset, thus causing an exit from the IDLE mode if the device is in that mode. In order for an interrupt to be generated, the IDLE Timer interrupt enable bit T0EN must be set, and the GIE (Global Interrupt Enable) bit must also be set. The T0PND flag and T0EN bit are bits 5 and 4 of the ICNTRL register, respectively. The interrupt can be used for any purpose. Typically, it is used to perform a task upon exit from the IDLE mode. For more information on the IDLE mode, refer to the Power Save Modes section. The Idle Timer period is selected by bits 0–2 of the ITMR register Bits 3–7 of the ITMR Register are reserved and must be “0”. TABLE 3. Idle Timer Window Length ITSEL2 0 0 0 0 1 ITSEL1 0 0 1 1 X ITSEL0 0 1 0 1 X Idle Timer Period (Instruction Cycles) 4,096 8,192 16,384 32,768 65,536 The ITMR register is cleared on Reset and the Idle Timer period is reset to 4,096 instruction cycles. ITMR Register (Address X’0xCF) Reserved (Must be ″0″) Bit 7 Bit 3 ITSEL2 ITSEL1 ITSEL0 Bit 0 The ICNTRL register contains the following bits: Reserved This bit is reserved and must be set to zero LPEN T0PND T0EN µWPND µWEN T1PNDB T1ENB L Port Interrupt Enable (Multi-Input Wakeup/ Interrupt) Timer T0 Interrupt pending Timer T0 Interrupt Enable (Bit 12 toggle) MICROWIRE/PLUS interrupt pending Enable MICROWIRE/PLUS interrupt Timer T1 Interrupt Pending Flag for T1B capture edge Timer T1 Interrupt Enable for T1B Input capture edge 15 Any time the IDLE Timer period is changed there is the possibility of generating a spurious IDLE Timer interrupt by setting the T0PND bit. The user is advised to disable IDLE Timer interrupts prior to changing the value of the ITSEL bits of the ITMR Register and then clear the T0PND bit before attempting to synchronize operation to the IDLE Timer. www.national.com 6.0 Timers (Continued) DS100973-52 FIGURE 11. Functional Block Diagram for Idle Timer T0 6.2 TIMER T1 The device has a powerful timer/counter block. The timer consists of a 16-bit timer, T1, and two supporting 16-bit autoreload/capture registers, R1A and R1B. The timer block has two pins associated with it, T1A and T1B. The pin T1A supports I/O required by the timer block, while the pin T1B is an input to the timer block. The powerful and flexible timer block allows the device to easily perform all timer functions with minimal software overhead. The timer block has three operating modes: Processor Independent PWM mode, External Event Counter mode, and Input Capture mode. The control bits T1C3, T1C2, and T1C1 allow selection of the different modes of operation. 6.2.1 Mode 1. Processor Independent PWM Mode As the name suggests, this mode allows the device to generate a PWM signal with very minimal user intervention. The user only has to define the parameters of the PWM signal (ON time and OFF time). Once begun, the timer block will continuously generate the PWM signal completely independent of the microcontroller. The user software services the timer block only when the PWM parameters require updating. In this mode the timer T1 counts down at a fixed rate of tC. Upon every underflow the timer is alternately reloaded with the contents of supporting registers, R1A and R1B. The very first underflow of the timer causes the timer to reload from the register R1A. Subsequent underflows cause the timer to be reloaded from the registers alternately beginning with the register R1B. The T1 Timer control bits, T1C3, T1C2 and T1C1 set up the timer for PWM mode operation. Figure 12 shows a block diagram of the timer in PWM mode. The underflows can be programmed to toggle the T1A output pin. The underflows can also be programmed to generate interrupts. Underflows from the timer are alternately latched into two pending flags, T1PNDA and T1PNDB. The user must reset these pending flags under software control. Two control enable flags, T1ENA and T1ENB, allow the interrupts from the timer underflow to be enabled or disabled. Setting the timer enable flag T1ENA will cause an interrupt when a timer underflow causes the R1A register to be reloaded into the timer. Setting the timer enable flag T1ENB will cause an interrupt when a timer underflow causes the R1B register to be reloaded into the timer. Resetting the timer enable flags will disable the associated interrupts. Either or both of the timer underflow interrupts may be enabled. This gives the user the flexibility of interrupting once per PWM period on either the rising or falling edge of the PWM output. Alternatively, the user may choose to interrupt on both edges of the PWM output. www.national.com 16 6.0 Timers (Continued) DS100973-46 FIGURE 12. Timer in PWM Mode 6.2.2 Mode 2. External Event Counter Mode This mode is quite similar to the processor independent PWM mode previously described. The main difference is that the timer, T1, is clocked by the input signal from the T1A pin. The T1 timer control bits, T1C3, T1C2 and T1C1 allow the timer to be clocked either on a positive or negative edge from the T1A pin. Underflows from the timer are latched into the T1PNDA pending flag. Setting the T1ENA control flag will cause an interrupt when the timer underflows. In this mode the input pin T1B can be used as an independent positive edge sensitive interrupt input if the T1ENB control flag is set. The occurrence of a positive edge on the T1B input pin is latched into the T1PNDB flag. Figure 13 shows a block diagram of the timer in External Event Counter mode. Note: The PWM output is not available in this mode since the T1A pin is being used as the counter input clock. DS100973-47 FIGURE 13. Timer in External Event Counter Mode 6.2.3 Mode 3. Input Capture Mode The device can precisely measure external frequencies or time external events by placing the timer block, T1, in the input capture mode. In this mode, the timer T1 is constantly running at the fixed tC rate. The two registers, R1A and R1B, act as capture registers. Each register acts in conjunction with a pin. The register R1A acts in conjunction with the T1A pin and the register R1B acts in conjunction with the T1B pin. The timer value gets copied over into the register when a trigger event occurs on its corresponding pin. Control bits, T1C3, T1C2 and T1C1, allow the trigger events to be specified either as a positive or a negative edge. The trigger condition for each input pin can be specified independently. The trigger conditions can also be programmed to generate interrupts. The occurrence of the specified trigger condition on the T1A and T1B pins will be respectively latched into the pending flags, T1PNDA and T1PNDB. The control flag T1ENA allows the interrupt on T1A to be either enabled or disabled. Setting the T1ENA flag enables interrupts to be generated when the selected trigger condition occurs on the T1A pin. Similarly, the flag T1ENB controls the interrupts from the T1B pin. Underflows from the timer can also be programmed to generate interrupts. Underflows are latched into the timer T1C0 pending flag (the T1C0 control bit serves as the timer underflow interrupt pending flag in the Input Capture mode). Consequently, the T1C0 control bit should be reset when entering the Input Capture mode. The timer underflow interrupt is enabled with the T1ENA control flag. When a T1A interrupt occurs in the Input Capture mode, the user must check both the T1PNDA and T1C0 pending flags in order to determine whether a T1A input capture or a timer underflow (or both) caused the interrupt. Figure 14 shows a block diagram of the timer in Input Capture Mode. 17 www.national.com 6.0 Timers (Continued) DS100973-48 FIGURE 14. Timer in Input Capture Mode 6.3 TIMER CONTROL FLAGS The Timer T1 control bits and their functions are summarized below. T1C3 Timer mode control T1C2 Timer mode control T1C1 Timer mode control T1C0 Timer Start/Stop control in Modes 1 and 2 (Processor Independent PWM and External Event Counter), where 1 = Start, 0 = Stop Timer Underflow Interrupt Pending Flag in Mode 3 (Input Capture) T1PNDA Timer Interrupt Pending Flag T1ENA Timer Interrupt Enable Flag 1 = Timer Interrupt Enabled 0 = Timer Interrupt Disabled T1PNDB Timer Interrupt Pending Flag T1ENB Timer Interrupt Enable Flag 1 = Timer Interrupt Enabled 0 = Timer Interrupt Disabled The timer mode control bits (T1C3, T1C2 and T1C1) are detailed below: Mode T1C3 1 1 1 0 2 0 0 T1C2 0 0 0 0 1 T1C1 1 0 0 1 0 Description PWM: T1A Toggle PWM: No T1A Toggle External Event Counter External Event Counter Captures: T1A Pos. Edge T1B Pos. Edge 1 1 0 Captures: T1A Pos. Edge 3 T1B Neg. Edge 0 1 1 Captures: T1A Neg. Edge T1B Neg. Edge 1 1 1 Captures: T1A Neg. Edge T1B Neg. Edge Interrupt A Source Autoreload RA Autoreload RA Timer Underflow Timer Underflow Pos. T1A Edge or Timer Underflow Pos. T1A Edge or Timer Underflow Neg. T1A Edge or Timer Underflow Neg. T1A Edge or Timer Underflow Neg. T1B Edge tC Neg. T1B Edge tC Neg. T1B Edge tC Interrupt B Source Autoreload RB Autoreload RB Pos. T1B Edge Pos. T1B Edge Pos. T1B Edge Timer Counts On tC tC Pos. T1A Edge Pos. T1A Edge tC www.national.com 18 7.0 Power Saving Features Today, the proliferation of battery-operated based applications has placed new demands on designers to drive power consumption down. Battery-operated systems are not the only type of applications demanding low power. The power budget constraints are also imposed on those consumer/ industrial applications where well regulated and expensive power supply costs cannot be tolerated. Such applications rely on low cost and low power supply voltage derived directly from the “mains” by using voltage rectifier and passive components. Low power is demanded even in automotive applications, due to increased vehicle electronics content. This is required to ease the burden from the car battery. Low power 8-bit microcontrollers supply the smarts to control battery-operated, consumer/industrial, and automotive applications. Each device offers system designers a variety of low-power consumption features that enable them to meet the demanding requirements of today’s increasing range of low-power applications. These features include low voltage operation, low current drain, and power saving features such as HALT, IDLE, and Multi-Input wakeup (MIWU). Each device offers the user two power save modes of operation: HALT and IDLE. In the HALT mode, all microcontroller activities are stopped. In the IDLE mode, the on-board oscillator circuitry and timer T0 are active but all other microcontroller activities are stopped. In either mode, all on-board RAM, registers, I/O states, and timers (with the exception of T0) are unaltered. Clock Monitor if enabled can be active in both modes. 7.1 HALT MODE Each device can be placed in the HALT mode by writing a “1” to the HALT flag (G7 data bit). All microcontroller activities, including the clock and timers, are stopped. The WATCHDOG logic on the devices are disabled during the HALT mode. However, the clock monitor circuitry, if enabled, remains active and will cause the WATCHDOG output pin (WDOUT) to go low. If the HALT mode is used and the user does not want to activate the WDOUT pin, the Clock Monitor should be disabled after the devices come out of reset (resetting the Clock Monitor control bit with the first write to the WDSVR register). In the HALT mode, the power requirements of the devices are minimal and the applied voltage (VCC) may be decreased to Vr (Vr = 2.0V) without altering the state of the machine. Each device supports three different ways of exiting the HALT mode. The first method of exiting the HALT mode is with the Multi-Input Wakeup feature on Port L. The second method is with a low to high transition on the CKO (G7) pin. This method precludes the use of the crystal clock configuration (since CKO becomes a dedicated output), and so may only be used with an R/C clock configuration. The third method of exiting the HALT mode is by pulling the RESET pin low. On wakeup from G7 or Port L, the devices resume execution from the HALT point. On wakeup from RESET execution will resume from location PC=0 and all RESET conditions apply. If a crystal or ceramic resonator may be selected as the oscillator, the Wakeup signal is not allowed to start the chip running immediately since crystal oscillators and ceramic resonators have a delayed start up time to reach full amplitude and frequency stability. The IDLE timer is used to generate a fixed delay to ensure that the oscillator has indeed stabilized before allowing instruction execution. In this case, upon detecting a valid Wakeup signal, only the oscillator circuitry is enabled. The IDLE timer is loaded with a value of 256 and is clocked with the tC instruction cycle clock. The tC clock is derived by dividing the oscillator clock down by a factor of 9. The Schmitt trigger following the CKI inverter on the chip ensures that the IDLE timer is clocked only when the oscillator has a sufficiently large amplitude to meet the Schmitt trigger specifications. This Schmitt trigger is not part of the oscillator closed loop. The start-up time-out from the IDLE timer enables the clock signals to be routed to the rest of the chip. If an R/C clock option is being used, the fixed delay is introduced optionally. A control bit, CLKDLY, mapped as configuration bit G7, controls whether the delay is to be introduced or not. The delay is included if CLKDLY is set, and excluded if CLKDLY is reset. The CLKDLY bit is cleared on reset. Each device has two options associated with the HALT mode. The first option enables the HALT mode feature, while the second option disables the HALT mode selected through bit 0 of the mask option. With the HALT mode enable option, the device will enter and exit the HALT mode as described above. With the HALT disable option, the device cannot be placed in the HALT mode (writing a “1” to the HALT flag will have no effect, the HALT flag will remain “0”). The WATCHDOG detector circuit is inhibited during the HALT mode. However, the clock monitor circuit if enabled remains active during HALT mode in order to ensure a clock monitor error if the device inadvertently enters the HALT mode as a result of a runaway program or power glitch. If the device is placed in the HALT mode, with the R/C oscillator selected, the clock input pin (CKI) is forced to a logic high internally. With the crystal oscillator the CKI pin is TRI-STATE. 19 www.national.com 7.0 Power Saving Features (Continued) DS100973-25 FIGURE 15. Wakeup from HALT 7.2 IDLE MODE The device is placed in the IDLE mode by writing a ″1″ to the IDLE flag (G6 data bit). In this mode, all activity, except the associated on-board oscillator circuitry, the WATCHDOG logic, the clock monitor and the IDLE Timer T0, is stopped. The power supply requirements of the microcontroller in this mode of operation are typically around 30% of normal power requirement of the microcontroller. As with the HALT mode, the device can be returned to normal operation with a reset, or with a Multi-Input Wakeup from the L Port. The microcontroller may also be awakened from the IDLE mode after a selectable amount of time up to 65,536 instruction cycles, or 65.536 milliseconds with a 1 MHz instruction clock frequency (10 MHz oscillator). The IDLE timer period is selectable from one of five values, 4k, 8k, 16k, 32k or 64k instruction cycles. Selection of this value is made through the ITMR register. The user has the option of being interrupted with an underflow of the selected bit of the IDLE Timer T0. This condition is latched into the T0PND pending flag. The interrupt can be enabled or disabled via the T0EN control bit. Setting the T0EN flag enables the interrupt and vice versa. The user can enter the IDLE mode with the Timer T0 interrupt enabled. In this case, when the T0PND bit gets set, the device will first execute the Timer T0 interrupt service routine and then return to the instruction following the ″Enter Idle Mode″ instruction. Alternatively, the user can enter the IDLE mode with the IDLE Timer T0 interrupt disabled. In this case, the device will resume normal operation with the instruction immediately following the ″Enter IDLE Mode″ instruction. The IDLE timer cannot be started or stopped under software control, and it is not memory mapped, so it cannot be read or written by the software. Its state upon Reset is unknown. Therefore, if the device is put into the IDLE mode at an arbitrary time, it will stay in the IDLE mode for somewhere between 1 and the selected number of instruction cycles. Upon reset the ITMR register is cleared and selects the 4,096 instruction cycle tap of the Idle Timer. Note: It is necessary to program two NOP instructions following both the set HALT mode and set IDLE mode instructions. These NOP instructions are necessary to allow clock resynchronization following the HALT or IDLE modes. For more information on the IDLE Timer and its associated interrupt, see the description in the Timers Section. www.national.com 20 7.0 Power Saving Features (Continued) DS100973-26 FIGURE 16. Wakeup from IDLE 7.3 MULTI-INPUT WAKEUP The Multi-Input Wakeup feature is used to return (wakeup) the device from either the HALT or IDLE modes. Alternately Multi-Input Wakeup/Interrupt feature may also be used to generate up to 8 edge selectable external interrupts. Figure 17 shows the Multi-Input Wakeup logic. The Multi-Input Wakeup feature utilizes the L Port. The user selects which particular L port bit (or combination of L Port bits) will cause the device to exit the HALT or IDLE modes. The selection is done through the register WKEN. The register WKEN is an 8-bit read/write register, which contains a control bit for every L port bit. Setting a particular WKEN bit enables a Wakeup from the associated L port pin. The user can select whether the trigger condition on the selected L Port pin is going to be either a positive edge (low to high transition) or a negative edge (high to low transition). This selection is made via the register WKEDG, which is an 8-bit control register with a bit assigned to each L Port pin. Setting the control bit will select the trigger condition to be a negative edge on that particular L Port pin. Resetting the bit selects the trigger condition to be a positive edge. Changing an edge select entails several steps in order to avoid a Wakeup condition as a result of the edge change. First, the associated WKEN bit should be reset, followed by the edge select change in WKEDG. Next, the associated WKPND bit should be cleared, followed by the associated WKEN bit being re-enabled. An example may serve to clarify this procedure. Suppose we wish to change the edge select from positive (low going high) to negative (high going low) for L Port bit 5, where bit 5 has previously been enabled for an input interrupt. The program would be as follows: RBIT 5, WKEN ; Disable MIWU SBIT 5, WKEDG ; Change edge polarity RBIT 5, WKPND ; Reset pending flag SBIT 5, WKEN ; Enable MIWU If the L port bits have been used as outputs and then changed to inputs with Multi-Input Wakeup/Interrupt, a safety procedure should also be followed to avoid wakeup conditions. After the selected L port bits have been changed from output to input but before the associated WKEN bits are enabled, the associated edge select bits in WKEDG should be set or reset for the desired edge selects, followed by the associated WKPND bits being cleared. This same procedure should be used following reset, since the L port inputs are left floating as a result of reset. The occurrence of the selected trigger condition for MultiInput Wakeup is latched into a pending register called WKPND. The respective bits of the WKPND register will be set on the occurrence of the selected trigger edge on the corresponding Port L pin. The user has the responsibility of clearing these pending flags. Since WKPND is a pending register for the occurrence of selected wakeup conditions, the device will not enter the HALT mode if any Wakeup bit is both enabled and pending. Consequently, the user must clear the pending flags before attempting to enter the HALT mode. WKEN and WKEDG are all read/write registers, and are cleared at reset. WKPND register contains random value after reset. 21 www.national.com 7.0 Power Saving Features (Continued) DS100973-27 FIGURE 17. Multi-Input Wake Up Logic 8.0 Interrupts 8.1 INTRODUCTION Each device supports eight vectored interrupts. Interrupt sources include Timer 0, Timer 1, EERAM Write Complete, Port L Wakeup, Software Trap, MICROWIRE/PLUS, and External Input. All interrupts force a branch to location 00FF Hex in program memory. The VIS instruction may be used to vector to the appropriate service routine from location 00FF Hex. The Software trap has the highest priority while the default VIS has the lowest priority. Each of the 7 maskable inputs has a fixed arbitration ranking and vector. Figure 18 shows the Interrupt Block Diagram. DS100973-28 FIGURE 18. Interrupt Block Diagram www.national.com 22 8.0 Interrupts (Continued) 8.2 MASKABLE INTERRUPTS All interrupts other than the Software Trap are maskable. Each maskable interrupt has an associated enable bit and pending flag bit. The pending bit is set to 1 when the interrupt condition occurs. The state of the interrupt enable bit, combined with the GIE bit determines whether an active pending flag actually triggers an interrupt. All of the maskable interrupt pending and enable bits are contained in mapped control registers, and thus can be controlled by the software. A maskable interrupt condition triggers an interrupt under the following conditions: 1. The enable bit associated with that interrupt is set. 2. The GIE bit is set. 3. The device is not processing a non-maskable interrupt. (If a non-maskable interrupt is being serviced, a maskable interrupt must wait until that service routine is completed.) An interrupt is triggered only when all of these conditions are met at the beginning of an instruction. If different maskable interrupts meet these conditions simultaneously, the highest priority interrupt will be serviced first, and the other pending interrupts must wait. Upon Reset, all pending bits, individual enable bits, and the GIE bit are reset to zero. Thus, a maskable interrupt condition cannot trigger an interrupt until the program enables it by setting both the GIE bit and the individual enable bit. When enabling an interrupt, the user should consider whether or not a previously activated (set) pending bit should be acknowledged. If, at the time an interrupt is enabled, any previous occurrences of the interrupt should be ignored, the associated pending bit must be reset to zero prior to enabling the interrupt. Otherwise, the interrupt may be simply enabled; if the pending bit is already set, it will immediately trigger an interrupt. A maskable interrupt is active if its associated enable and pending bits are set. An interrupt is an asychronous event which may occur before, during, or after an instruction cycle. Any interrupt which occurs during the execution of an instruction is not acknowledged until the start of the next normally executed instruction is to be skipped, the skip is performed before the pending interrupt is acknowledged. At the start of interrupt acknowledgment, the following actions occur: 1. The GIE bit is automatically reset to zero, preventing any subsequent maskable interrupt from interrupting the current service routine. This feature prevents one maskable interrupt from interrupting another one being serviced. 2. The address of the instruction about to be executed is pushed onto the stack. 3. The program counter (PC) is loaded with 00FF Hex, causing a jump to that program memory location. The device requires seven instruction cycles to perform the actions listed above. If the user wishes to allow nested interrupts, the interrupts service routine may set the GIE bit to 1 by writing to the PSW register, and thus allow other maskable interrupts to interrupt the current service routine. If nested interrupts are allowed, caution must be exercised. The user must write the program in such a way as to prevent stack overflow, loss of saved context information, and other unwanted conditions. The interrupt service routine stored at location 00FF Hex should use the VIS instruction to determine the cause of the 23 interrupt, and jump to the interrupt handling routine corresponding to the highest priority enabled and active interrupt. Alternately, the user may choose to poll all interrupt pending and enable bits to determine the source(s) of the interrupt. If more than one interrupt is active, the user’s program must decide which interrupt to service. Within a specific interrupt service routine, the associated pending bit should be cleared. This is typically done as early as possible in the service routine in order to avoid missing the next occurrence of the same type of interrupt event. Thus, if the same event occurs a second time, even while the first occurrence is still being serviced, the second occurrence will be serviced immediately upon return from the current interrupt routine. An interrupt service routine typically ends with an RETI instruction. This instruction sets the GIE bit back to 1, pops the address stored on the stack, and restores that address to the program counter. Program execution then proceeds with the next instruction that would have been executed had there been no interrupt. If there are any valid interrupts pending, the highest-priority interrupt is serviced immediately upon return from the previous interrupt. 8.3 VIS INSTRUCTION The general interrupt service routine, which starts at address 00FF Hex, must be capable of handling all types of interrupts. The VIS instruction, together with an interrupt vector table, directs the device to the specific interrupt handling routine based on the cause of the interrupt. VIS is a single-byte instruction, typically used at the very beginning of the general interrupt service routine at address 00FF Hex, or shortly after that point, just after the code used for context switching. The VIS instruction determines which enabled and pending interrupt has the highest priority, and causes an indirect jump to the address corresponding to that interrupt source. The jump addresses (vectors) for all possible interrupts sources are stored in a vector table. The vector table may be as long as 32 bytes (maximum of 16 vectors) and resides at the top of the 256-byte block containing the VIS instruction. However, if the VIS instruction is at the very top of a 256-byte block (such as at 00FF Hex), the vector table resides at the top of the next 256-byte block. Thus, if the VIS instruction is located somewhere between 00FF and 01DF Hex (the usual case), the vector table is located between addresses 01E0 and 01FF Hex. If the VIS instruction is located between 01FF and 02DF Hex, then the vector table is located between addresses 02E0 and 02FF Hex, and so on. Each vector is 15 bits long and points to the beginning of a specific interrupt service routine somewhere in the 32 kbyte memory space. Each vector occupies two bytes of the vector table, with the higher-order byte at the lower address. The vectors are arranged in order of interrupt priority. The vector of the maskable interrupt with the lowest rank is located to 0yE0 (higher-order byte) and 0yE1 (lower-order byte). The next priority interrupt is located at 0yE2 and 0yE3, and so forth in increasing rank. The Software Trap has the highest rank and its vector is always located at 0yFE and 0yFF. The number of interrupts which can become active defines the size of the table. Table 4 shows the types of interrupts, the interrupt arbitration ranking, and the locations of the corresponding vectors in the vector table. The vector table should be filled by the user with the memory locations of the specific interrupt service routines. For exwww.national.com 8.0 Interrupts (Continued) ample, if the Software Trap routine is located at 0310 Hex, then the vector location 0yFE and -0yFF should contain the data 03 and 10 Hex, respectively. When a Software Trap interrupt occurs and the VIS instruction is executed, the program jumps to the address specified in the vector table. The interrupt sources in the vector table are listed in order of rank, from highest to lowest priority. If two or more enabled and pending interrupts are detected at the same time, the one with the highest priority is serviced first. Upon return from the interrupt service routine, the next highest-level pending interrupt is serviced. If the VIS instruction is executed, but no interrupts are enabled and pending, the lowest-priority interrupt vector is used, and a jump is made to the corresponding address in the vector table. This is an unusual occurrence, and may be the result of an error. It can legitimately result from a change in the enable bits or pending flags prior to the execution of the VIS instruction, such as executing a single cycle instruction which clears an enable flag at the same time that the pending flag is set. It can also result, however, from inadvertent execution of the VIS command outside of the context of an interrupt. The default VIS interrupt vector can be useful for applications in which time critical interrupts can occur during the servicing of another interrupt. Rather than restoring the pro- gram context (A, B, X, etc.) and executing the RETI instruction, an interrupt service routine can be terminated by returning to the VIS instruction. In this case, interrupts will be serviced in turn until no further interrupts are pending and the default VIS routine is started. After testing the GIE bit to ensure that execution is not erroneous, the routine should restore the program context and execute the RETI to return to the interrupted program. This technique can save up to fifty instruction cycles (tc), or more, (50µs at 10 MHz oscillator) of latency for pending interrupts with a penalty of fewer than ten instruction cycles if no further interrupts are pending. To ensure reliable operation, the user should always use the VIS instruction to determine the source of an interrupt. Although it is possible to poll the pending bits to detect the source of an interrupt, this practice is not recommended. The use of polling allows the standard arbitration ranking to be altered, but the reliability of the interrupt system is compromised. The polling routine must individually test the enable and pending bits of each maskable interrupt. If a Software Trap interrupt should occur, it will be serviced last, even though it should have the highest priority. Under certain conditions, a Software Trap could be triggered but not serviced, resulting in an inadvertent “locking out” of all maskable interrupts by the Software Trap pending flag. Problems such as this can be avoided by using VIS instruction. TABLE 4. Interrupt Vector Table Arbitration Ranking (1) Highest (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) Lowest Software Reserved External Timer T0 Timer T1 Timer T1 MICROWIRE/PLUS EERAM Reserved Reserved Reserved Reserved Reserved Reserved Port L/Wakeup Default VIS Port L Edge Reserved G0 Underflow T1A/Underflow T1B BUSY Low EERAM Write Complete Source Description INTR Instruction Vector Address (Note 26) (Hi-Low Byte) 0yFE–0yFF 0yFC–0yFD 0yFA–0yFB 0yF8–0yF9 0yF6–0yF7 0yF4–0yF5 0yF2–0yF3 0yF0–0yF1 0yEE–0yEF 0yEC–0yED 0yEA–0yEB 0yE8–0yE9 0yE6–0yE7 0yE4–0yE5 0yE2–0yE3 0yE0–0yE1 Note 26: y is a variable which represents the VIS block. VIS and the vector table must be located in the same 256-byte block except if VIS is located at the last address of a block. In this case, the table must be in the next block. www.national.com 24 8.0 Interrupts 8.3.1 VIS Execution (Continued) When the VIS instruction is executed it activates the arbitration logic. The arbitration logic generates an even number between E0 and FE (E0, E2, E4, E6 etc...) depending on which active interrupt has the highest arbitration ranking at the time of the 1st cycle of VIS is executed. For example, if the software trap interrupt is active, FE is generated. If the external interrupt is active and the software trap interrupt is not, then FA is generated and so forth. If the only active interrupt is software trap, than E0 is generated. This number replaces the lower byte of the PC. The upper byte of the PC re- mains unchanged. The new PC is therefore pointing to the vector of the active interrupt with the highest arbitration ranking. This vector is read from program memory and placed into the PC which is now pointed to the 1st instruction of the service routine of the active interrupt with the highest arbitration ranking. Figure 19 illustrates the different steps performed by the VIS instruction. Figure 20 shows a flowchart for the VIS instruction. The non-maskable interrupt pending flag is cleared by the RPND (Reset Non-Maskable Pending Bit) instruction (under certain conditions) and upon RESET. DS100973-29 FIGURE 19. VIS Operation 25 www.national.com 8.0 Interrupts (Continued) DS100973-30 FIGURE 20. VIS Flowchart www.national.com 26 8.0 Interrupts PSW CNTRL RBIT RBIT SBIT SBIT SBIT JP . . . .=0FF VIS (Continued) Programming Example: External Interrupt =00EF =00EE 0,PORTGC 0,PORTGD IEDG, CNTRL EXEN, PSW GIE, PSW WAIT WAIT: ; ; ; ; ; G0 pin configured Hi-Z Ext interrupt polarity; falling edge Enable the external interrupt Set the GIE bit Wait for external interrupt ; The interrupt causes a ; branch to address 0FF ; The VIS causes a branch to ;interrupt vector table . . . .=01FA .ADDRW SERVICE . . INT_EXIT: RETI . . RBIT . . . JP ; Vector table (within 256 byte ; of VIS inst.) containing the ext ; interrupt service routine SERVICE: EXPND, PSW ; Interrupt Service Routine ; Reset ext interrupt pend. bit INT_EXIT ; Return, set the GIE bit 27 www.national.com 8.0 Interrupts (Continued) 8.4 NON-MASKABLE INTERRUPT 8.4.1 Pending Flag There is a pending flag bit associated with the non-maskable interrupt, called STPND. This pending flag is not memorymapped and cannot be accessed directly by the software. The pending flag is reset to zero when a device Reset occurs. When the non-maskable interrupt occurs, the associated pending bit is set to 1. The interrupt service routine should contain an RPND instruction to reset the pending flag to zero. The RPND instruction always resets the STPND flag. 8.4.2 Software Trap The Software Trap is a special kind of non-maskable interrupt which occurs when the INTR instruction (used to acknowledge interrupts) is fetched from program memory and placed in the instruction register. This can happen in a variety of ways, usually because of an error condition. Some examples of causes are listed below. If the program counter incorrectly points to a memory location beyond the available program memory space, the nonexistent or unused memory location returns zeroes which is interpreted as the INTR instruction. If the stack is popped beyond the allowed limit (address 06F Hex), a 7FFF will be loaded into the PC, if this last location in program memory is unprogrammed or unavailable, a Software Trap will be triggered. A Software Trap can be triggered by a temporary hardware condition such as a brownout or power supply glitch. The Software Trap has the highest priority of all interrupts. When a Software Trap occurs, the STPND bit is set. The GIE bit is not affected and the pending bit (not accessible by the user) is used to inhibit other interrupts and to direct the program to the ST service routine with the VIS instruction. Nothing can interrupt a Software Trap service routine except for another Software Trap. The STPND can be reset only by the RPND instruction or a chip Reset. The Software Trap indicates an unusual or unknown error condition. Generally, returning to normal execution at the point where the Software Trap occurred cannot be done reliably. Therefore, the Software Trap service routine should reinitialize the stack pointer and perform a recovery procedure that restarts the software at some known point, similar to a device Reset, but not necessarily performing all the same functions as a device Reset. The routine must also execute the RPND instruction to reset the STPND flag. Otherwise, all other interrupts will be locked out. To the extent possible, the interrupt routine should record or indicate the context of the device so that the cause of the Software Trap can be determined. If the user wishes to return to normal execution from the point at which the Software Trap was triggered, the user must first execute RPND, followed by RETSK rather than RETI or RET. This is because the return address stored on the stack is the address of the INTR instruction that triggered the interrupt. The program must skip that instruction in order to proceed with the next one. Otherwise, an infinite loop of Software Traps and returns will occur. Programming a return to normal execution requires careful consideration. If the Software Trap routine is interrupted by another Software Trap, the RPND instruction in the service routine for the second Software Trap will reset the STPND www.national.com 28 flag; upon return to the first Software Trap routine, the STPND flag will have the wrong state. This will allow maskable interrupts to be acknowledged during the servicing of the first Software Trap. To avoid problems such as this, the user program should contain the Software Trap routine to perform a recovery procedure rather than a return to normal execution. Under normal conditions, the STPND flag is reset by a RPND instruction in the Software Trap service routine. If a programming error or hardware condition (brownout, power supply glitch, etc.) sets the STPND flag without providing a way for it to be cleared, all other interrupts will be locked out. To alleviate this condition, the user can use extra RPND instructions in the main program and in the WATCHDOG service routine (if present). There is no harm in executing extra RPND instructions in these parts of the program. 8.5 PORT L INTERRUPTS Port L provides the user with an additional eight fully selectable, edge sensitive interrupts which are all vectored into the same service subroutine. The interrupt from Port L shares logic with the wake up circuitry. The register WKEN allows interrupts from Port L to be individually enabled or disabled. The register WKEDG specifies the trigger condition to be either a positive or a negative edge. Finally, the register WKPND latches in the pending trigger conditions. The GIE (Global Interrupt Enable) bit enables the interrupt function. A control flag, LPEN, functions as a global interrupt enable for Port L interrupts. Setting the LPEN flag will enable interrupts and vice versa. A separate global pending flag is not needed since the register WKPND is adequate. Since Port L is also used for waking the device out of the HALT or IDLE modes, the user can elect to exit the HALT or IDLE modes either with or without the interrupt enabled. If he elects to disable the interrupt, then the device will restart execution from the instruction immediately following the instruction that placed the microcontroller in the HALT or IDLE modes. In the other case, the device will first execute the interrupt service routine and then revert to normal operation. (See HALT MODE for clock option wakeup information.) 8.6 INTERRUPT SUMMARY The device uses the following types of interrupts, listed below in order of priority: 1. The Software Trap non-maskable interrupt, triggered by the INTR (00 opcode) instruction. The Software Trap is acknowledged immediately. This interrupt service routine can be interrupted only by another Software Trap. The Software Trap should end with two RPND instructions followed by a restart procedure. 2. Maskable interrupts, triggered by an on-chip peripheral block or an external device connected to the device. Under ordinary conditions, a maskable interrupt will not interrupt any other interrupt routine in progress. A maskable interrupt routine in progress can be interrupted by the non-maskable interrupt request. A maskable interrupt routine should end with an RETI instruction or, prior to restoring context, should return to execute the VIS instruction. This is particularly useful when exiting long interrupt service routiness if the time between interrupts is short. In this case the RETI instruction would only be executed when the default VIS routine is reached. 9.0 WATCHDOG/Clock Monitor Each device contains a user selectable WATCHDOG and clock monitor. The following section is applicable only if WATCHDOG feature has been selected by mask option. The WATCHDOG is designed to detect the user program getting stuck in infinite loops resulting in loss of program control or “runaway” programs. The WATCHDOG logic contains two separate service windows. While the user programmable upper window selects the WATCHDOG service time, the lower window provides protection against an infinite program loop that contains the WATCHDOG service instruction. The Clock Monitor is used to detect the absence of a clock or a very slow clock below a specified rate on the CKI pin. The WATCHDOG consists of two independent logic blocks: WD UPPER and WD LOWER. WD UPPER establishes the upper limit on the service window and WD LOWER defines the lower limit of the service window. Servicing the WATCHDOG consists of writing a specific value to a WATCHDOG Service Register named WDSVR which is memory mapped in the RAM. This value is composed of three fields, consisting of a 2-bit Window Select, a 5-bit Key Data field, and the 1-bit Clock Monitor Select field. Table 5 shows the WDSVR register. TABLE 5. WATCHDOG Service Register (WDSVR) Window Select X 7 X 6 0 5 1 4 Key Data 1 3 0 2 0 1 Clock Monitor Y 0 9.1 CLOCK MONITOR The Clock Monitor aboard the device can be selected or deselected under program control. The Clock Monitor is guaranteed not to reject the clock if the instruction cycle clock (1/ tC) is greater or equal to 10 kHz. This equates to a clock input rate on CKI of greater or equal to 100 kHz. 9.2 WATCHDOG/CLOCK MONITOR OPERATION The WATCHDOG and Clock Monitor are disabled during reset. The device comes out of reset with the WATCHDOG armed, the WATCHDOG Window Select bits (bits 6, 7 of the WDSVR Register) set, and the Clock Monitor bit (bit 0 of the WDSVR Register) enabled. Thus, a Clock Monitor error will occur after coming out of reset, if the instruction cycle clock frequency has not reached a minimum specified value, including the case where the oscillator fails to start. The WDSVR register can be written to only once after reset and the key data (bits 5 through 1 of the WDSVR Register) must match to be a valid write. This write to the WDSVR register involves two irrevocable choices: (i) the selection of the WATCHDOG service window (ii) enabling or disabling of the Clock Monitor. Hence, the first write to WDSVR Register involves selecting or deselecting the Clock Monitor, select the WATCHDOG service window and match the WATCHDOG key data. Subsequent writes to the WDSVR register will compare the value being written by the user to the WATCHDOG service window value and the key data (bits 7 through 1) in the WDSVR Register. Table 7 shows the sequence of events that can occur. The user must service the WATCHDOG at least once before the upper limit of the service window expires. The WATCHDOG may not be serviced more than once in every lower limit of the service window. The WATCHDOG has an output pin associated with it. This is the WDOUT pin, on pin 1 of the port G. WDOUT is active low and must be externally connected to the RESET pin or to some other external logic which handles WATCHDOG event. The WDOUT pin has a weak pullup in the inactive state. This pull-up is sufficient to serve as the connection to VCC for systems which use the internal Power On Reset. Upon triggering the WATCHDOG, the logic will pull the WDOUT (G1) pin low for an additional 16 tC–32 tC cycles after the signal level on WDOUT pin goes below the lower Schmitt trigger threshold. After this delay, the WDOUT output will go high. The WATCHDOG service window will restart when the WDOUT pin goes high. A WATCHDOG service while the WDOUT signal is active will be ignored. The state of the WDOUT pin is not guaranteed on reset, but if it powers up low then the WATCHDOG will time out and WDOUT will go high. The Clock Monitor forces the G1 pin low upon detecting a clock frequency error. The Clock Monitor error will continue until the clock frequency has reached the minimum specified value, after which the G1 output will go high following 16 tC–32 tC clock cycles. The Clock Monitor generates a continual Clock Monitor error if the oscillator fails to start, or fails to reach the minimum specified frequency. The specification for the Clock Monitor is as follows: 1/tC > 10 kHz — No clock rejection. 1/tC < 10 Hz — Guaranteed clock rejection. The lower limit of the service window is fixed at 256 instruction cycles. Bits 7 and 6 of the WDSVR register allow the user to pick an upper limit of the service window. Table 6 shows the four possible combinations of lower and upper limits for the WATCHDOG service window. This flexibility in choosing the WATCHDOG service window prevents any undue burden on the user software. Bits 5, 4, 3, 2 and 1 of the WDSVR register represent the 5-bit Key Data field. The key data is fixed at 01100. Bit 0 of the WDSVR Register is the Clock Monitor Select bit. TABLE 6. WATCHDOG Service Window Select WDSVR WDSVR Bit 7 0 0 1 1 x x Bit 6 0 1 0 1 x x Clock Monitor x x x x 0 1 Service Window (Lower-Upper Limits) 2048–8k tC Cycles 2048–16k tC Cycles 2048–32k tC Cycles 2048–64k tC Cycles Clock Monitor Disabled Clock Monitor Enabled 29 www.national.com 9.0 WATCHDOG/Clock Monitor Key Data Match Don’t Care Mismatch Don’t Care Window Data Match Mismatch Don’t Care Don’t Care (Continued) TABLE 7. WATCHDOG Service Actions Clock Monitor Match Don’t Care Don’t Care Mismatch Valid Service: Restart Service Window Error: Generate WATCHDOG Output Error: Generate WATCHDOG Output Error: Generate WATCHDOG Output Action 9.3 WATCHDOG AND CLOCK MONITOR SUMMARY The following salient points regarding the WATCHDOG and CLOCK MONITOR should be noted: • Both the WATCHDOG and CLOCK MONITOR detector circuits are inhibited during RESET. • Following RESET, the WATCHDOG and CLOCK MONITOR are both enabled, with the WATCHDOG having the maximum service window selected. • The WATCHDOG service window and CLOCK MONITOR enable/disable option can only be changed once, during the initial WATCHDOG service following RESET. • The initial WATCHDOG service must match the key data value in the WATCHDOG Service register WDSVR in order to avoid a WATCHDOG error. • Subsequent WATCHDOG services must match all three data fields in WDSVR in order to avoid WATCHDOG errors. • The correct key data value cannot be read from the WATCHDOG Service register WDSVR. Any attempt to read this key data value of 01100 from WDSVR will read as key data value of all 0’s. • The WATCHDOG detector circuit is inhibited during both the HALT and IDLE modes. • The CLOCK MONITOR detector circuit is active during both the HALT and IDLE modes. Consequently, the device inadvertently entering the HALT mode will be detected as a CLOCK MONITOR error (provided that the CLOCK MONITOR enable option has been selected by the program). • With the single-pin R/C oscillator option selected and the CLKDLY bit reset, the WATCHDOG service window will resume following HALT mode from where it left off before entering the HALT mode. • With the crystal oscillator option selected, or with the single-pin R/C oscillator option selected and the CLKDLY bit set, the WATCHDOG service window will be set to its selected value from WDSVR following HALT. Consequently, the WATCHDOG should not be serviced for at least 2048 instruction cycles following HALT, but must be serviced within the selected window to avoid a WATCHDOG error. • The IDLE timer T0 is not initialized with external RESET. • The user can sync in to the IDLE counter cycle with an IDLE counter (T0) interrupt or by monitoring the T0PND flag. The T0PND flag is set whenever the selected bit of the IDLE counter toggles (every 4, 8, 16, 32 or 64k instruction cycles). The user is responsible for resetting the T0PND flag. • A hardware WATCHDOG service occurs just as the device exits the IDLE mode. Consequently, the WATCHDOG should not be serviced for at least 2048 instruction cycles following IDLE, but must be serviced within the selected window to avoid a WATCHDOG error. • Following RESET, the initial WATCHDOG service (where the service window and the CLOCK MONITOR enable/ disable must be selected) may be programmed anywhere within the maximum service window (65,536 instruction cycles) initialized by RESET. Note that this initial WATCHDOG service may be programmed within the initial 2048 instruction cycles without causing a WATCHDOG error. 9.4 DETECTION OF ILLEGAL CONDITIONS The device can detect various illegal conditions resulting from coding errors, transient noise, power supply voltage drops, runaway programs, etc. Reading of undefined ROM gets zeroes. The opcode for software interrupt is 00. If the program fetches instructions from undefined ROM, this will force a software interrupt, thus signaling that an illegal condition has occurred. The subroutine stack grows down for each call (jump to subroutine), interrupt, or PUSH, and grows up for each return or POP. The stack pointer is initialized to RAM location 06F Hex during reset. Consequently, if there are more returns than calls, the stack pointer will point to addresses 070 and 071 Hex (which are undefined RAM). Undefined RAM from addresses 070 to 07F (Segment 0), and all other segments (i.e., Segments 4 … etc.) is read as all 1’s, which in turn will cause the program to return to address 7FFF Hex. It is recommended that the user either leave this location unprogrammed or place an INTR instruction (all 0’s) in this location to generate a software interrupt signaling an illegal condition. Thus, the chip can detect the following illegal conditions: 1. 2. Executing from undefined ROM. Over “POP”ing the stack by having more returns than calls. When the software interrupt occurs, the user can re-initialize the stack pointer and do a recovery procedure before restarting (this recovery program is probably similar to that following reset, but might not contain the same program initialization procedures). The recovery program should reset the software interrupt pending bit using the RPND instruction. www.national.com 30 10.0 MICROWIRE/PLUS MICROWIRE/PLUS is a serial SPI compatible synchronous communications interface. The MICROWIRE/PLUS capability enables the device to interface with MICROWIRE/PLUS or SPI peripherals (i.e. A/D converters, display drivers, EEPROMs etc.) and with other microcontrollers which support the MICROWIRE/PLUS or SPI interface. It consists of an 8-bit serial shift register (SIO) with serial data input (SI), serial data output (SO) and serial shift clock (SK). Figure 21 shows a block diagram of the MICROWIRE/PLUS logic. The shift clock can be selected from either an internal source or an external source. Operating the MICROWIRE/PLUS arrangement with the internal clock source is called the Master mode of operation. Similarly, operating the MICROWIRE/ PLUS arrangement with an external shift clock is called the Slave mode of operation. The CNTRL register is used to configure and control the MICROWIRE/PLUS mode. To use the MICROWIRE/PLUS, the MSEL bit in the CNTRL register is set to one. In the master mode, the SK clock rate is selected by the two bits, SL0 and SL1, in the CNTRL register. Table 8 details the different clock rates that may be selected. TABLE 8. MICROWIRE/PLUS Master Mode Clock Select SL1 0 0 1 SL0 0 1 x SK Period 2 x tC 4 x tC 8 x tC 10.1 MICROWIRE/PLUS OPERATION Setting the BUSY bit in the PSW register causes the MICROWIRE/PLUS to start shifting the data. It gets reset when eight data bits have been shifted. The user may reset the BUSY bit by software to allow less than 8 bits to shift. If enabled, an interrupt is generated when eight data bits have been shifted. The device may enter the MICROWIRE/PLUS mode either as a Master or as a Slave. Figure 21 shows how two microcontroller devices and several peripherals may be interconnected using the MICROWIRE/PLUS arrangements. WARNING The SIO register should only be loaded when the SK clock is in the idle phase. Loading the SIO register while the SK clock is in the active phase, will result in undefined data in the SIO register. Setting the BUSY flag when the input SK clock is in the active phase while in the MICROWIRE/PLUS is in the slave mode may cause the current SK clock for the SIO shift register to be narrow. For safety, the BUSY flag should only be set when the input SK clock is in the idle phase. 10.1.1 MICROWIRE/PLUS Master Mode Operation In the MICROWIRE/PLUS Master mode of operation the shift clock (SK) is generated internally. The MICROWIRE Master always initiates all data exchanges. The MSEL bit in the CNTRL register must be set to enable the SO and SK functions onto the G Port. The SO and SK pins must also be selected as outputs by setting appropriate bits in the Port G configuration register. In the slave mode, the shift clock stops after 8 clock pulses. Table 9 summarizes the bit settings required for Master mode of operation. Where tC is the instruction cycle clock DS100973-32 FIGURE 21. MICROWIRE/PLUS Application 31 www.national.com 10.0 MICROWIRE/PLUS (Continued) 10.1.2 MICROWIRE/PLUS Slave Mode Operation In the MICROWIRE/PLUS Slave mode of operation the SK clock is generated by an external source. Setting the MSEL bit in the CNTRL register enables the SO and SK functions onto the G Port. The SK pin must be selected as an input and the SO pin is selected as an output pin by setting and resetting the appropriate bits in the Port G configuration register. Table 9 summarizes the settings required to enter the Slave mode of operation. TABLE 9. MICROWIRE/PLUS Mode Settings This table assumes that the control flag MSEL is set. G4 (SO) Config. Bit 1 0 1 0 G5 (SK) Config. Bit 1 1 0 0 G4 Fun. SO TRISTATE SO TRISTATE G5 Fun. Int. SK Int. SK Ext. SK Ext. SK MICROWIRE/PLUS Master MICROWIRE/PLUS Master MICROWIRE/PLUS Slave MICROWIRE/PLUS Slave Operation The user must set the BUSY flag immediately upon entering the Slave mode. This ensures that all data bits sent by the Master is shifted properly. After eight clock pulses the BUSY flag is clear, the shift clock is stopped, and the sequence may be repeated. 10.1.3 Alternate SK Phase Operation and SK Idle Polarity The device allows either the normal SK clock or an alternate phase SK clock to shift data in and out of the SIO register. In both the modes the SK idle polarity can be either high or low. The polarity is selected by bit 5 of Port G data register. In the normal mode data is shifted in on the rising edge of the SK clock and the data is shifted out on the falling edge of the SK clock. In the alternate SK phase operation, data is shifted in on the falling edge of the SK clock and shifted out on the rising edge of the SK clock. Bit 6 of Port G configuration register selects the SK edge. A control flag, SKSEL, allows either the normal SK clock or the alternate SK clock to be selected. Resetting SKSEL causes the MICROWIRE/PLUS logic to be clocked from the normal SK signal. Setting the SKSEL flag selects the alternate SK clock. The SKSEL is mapped into the G6 configuration bit. The SKSEL flag will power up in the reset condition, selecting the normal SK signal. TABLE 10. MICROWIRE/PLUS Shift Clock Polarity and Sample/Shift Phase Port G SK Phase Normal Alternate Alternate Normal G6 (SKSEL) Config. Bit 0 1 0 1 G5 Data Bit 0 0 1 1 SO Clocked Out On: SK Falling Edge SK Rising Edge SK Rising Edge SK Falling Edge SI Sampled On: SK Rising Edge SK Falling Edge SK Falling Edge SK Rising Edge SK Idle Phase Low Low High High DS100973-33 FIGURE 22. MICROWIRE/PLUS SPI Mode Interface Timing, Normal SK Mode, SK Idle Phase being Low DS100973-34 FIGURE 23. MICROWIRE/PLUS SPI Mode Interface Timing, Alternate SK Mode, SK Idle Phase being Low www.national.com 32 10.0 MICROWIRE/PLUS (Continued) DS100973-35 FIGURE 24. MICROWIRE/PLUS SPI Mode Interface Timing, Alternate SK Mode, SK Idle Phase being High DS100973-31 FIGURE 25. MICROWIRE/PLUS SPI Mode Interface Timing, Normal SK Mode, SK Idle Phase being High 33 www.national.com 11.0 Memory Map All RAM, ports and registers (except A and PC) are mapped into data memory address space. Address S/ADD REG 0000 to 006F 0070 to 007F xx80 to xxBF xxC7 xxC8 xxC9 xxCA xxCB xxCC xxCD to xxCE xxCF xxD0 xxD1 xxD2 xxD3 xxD4 xxD5 xxD6 xxD7 to xxDF xxE0 xxE1 to xxE5 xxE6 xxE7 xxE8 xxE9 xxEA xxEB xxEC xxED xxEE xxEF xxF0 to xxFB xxFC xxFD xxFE xxFF 0100–017F On-Chip RAM bytes (112 bytes) Unused RAM Address Space (Reads As All Ones) Unused RAM Address Space (Reads Undefined Data) WATCHDOG Service Register (Reg:WDSVR) MIWU Edge Select Register (Reg:WKEDG) MIWU Enable Register (Reg:WKEN) MIWU Pending Register (Reg:WKPND) Reserved Reserved Reserved Idle Timer Window Length (Reg:ITMR) Port L Data Register Port L Configuration Register Port L Input Pins (Read Only) Reserved Port G Data Register Port G Configuration Register Port G Input Pins (Read Only) Reserved EERAM Control Register E2CFG Reserved for EE Control Registers Timer T1 Autoload Register T1RB Lower Byte Timer T1 Autoload Register T1RB Upper Byte ICNTRL Register MICROWIRE/PLUS Shift Register Timer T1 Lower Byte Timer T1 Upper Byte Timer T1 Autoload Register T1RA Lower Byte Timer T1 Autoload Register T1RA Upper Byte CNTRL Control Register PSW Register On-Chip RAM Mapped as Registers X Register SP Register B Register S Register On-Chip 128 EERAM Bytes Contents Note: Reading memory locations 0070H–007FH (Segment 0) will return all ones. Reading unused memory locations 0080H–00BFH (Segment 0) will return undefined data. Reading memory locations from other Segments (i.e., Segment 2, Segment 3, … etc.) will return undefined data. www.national.com 34 12.0 Instruction Set 12.1 INTRODUCTION This section defines the instruction set of the COPSAx7 Family members. It contains information about the instruction set features, addressing modes and types. 12.2 INSTRUCTION FEATURES The strength of the instruction set is based on the following features: The available addressing modes are: • • • Direct Register B or X Indirect Register B or X Indirect with Post-Incrementing/ Decrementing • • • • • • Mostly single-byte opcode instructions minimize program size. One instruction cycle for the majority of single-byte instructions to minimize program execution time. Many single-byte, multiple function instructions such as DRSZ. Three memory mapped pointers: two for register indirect addressing, and one for the software stack. Sixteen memory mapped registers that allow an optimized implementation of certain instructions. Ability to set, reset, and test any individual bit in data memory address space, including the memory-mapped I/O ports and registers. Register-Indirect LOAD and EXCHANGE instructions with optional automatic post-incrementing or decrementing of the register pointer. This allows for greater efficiency (both in cycle time and program code) in loading, walking across and processing fields in data memory. Unique instructions to optimize program size and throughput efficiency. Some of these instructions are DRSZ, IFBNE, DCOR, RETSK, VIS and RRC. • Immediate • Immediate Short • Indirect from Program Memory The addressing modes are described below. Each description includes an example of an assembly language instruction using the described addressing mode. Direct. The memory address is specified directly as a byte in the instruction. In assembly language, the direct address is written as a numerical value (or a label that has been defined elsewhere in the program as a numerical value). Example: Load Accumulator Memory Direct LD A,05 Reg/Data Memory Accumulator Memory Location Contents Before XX Hex A6 Hex Contents After A6 Hex A6 Hex • • 0005 Hex Register B or X Indirect. The memory address is specified by the contents of the B Register or X register (pointer register). In assembly language, the notation [B] or [X] specifies which register serves as the pointer. Example: Exchange Memory with Accumulator, B Indirect X A,[B] Reg/Data Memory Accumulator Memory Location 0005 Hex B Pointer 05 Hex 05 Hex Register B or X Indirect with Post-Incrementing/ Decrementing. The relevant memory address is specified by the contents of the B Register or X register (pointer register). The pointer register is automatically incremented or decremented after execution, allowing easy manipulation of memory blocks with software loops. In assembly language, the notation [B+], [B−], [X+], or [X−] specifies which register serves as the pointer, and whether the pointer is to be incremented or decremented. Example: Exchange Memory with Accumulator, B Indirect with Post-Increment X A,[B+] Reg/Data Memory Accumulator Memory Location 0005 Hex B Pointer 05 Hex 06 Hex Intermediate. The data for the operation follows the instruction opcode in program memory. In assembly language, the number sign character (#) indicates an immediate operand. Contents Before 03 Hex 62 Hex Contents After 62 Hex 03 Hex Contents Before 01 Hex 87 Hex Contents After 87 Hex 01 Hex 12.3 ADDRESSING MODES The instruction set offers a variety of methods for specifying memory addresses. Each method is called an addressing mode. These modes are classified into two categories: operand addressing modes and transfer-of-control addressing modes. Operand addressing modes are the various methods of specifying an address for accessing (reading or writing) data. Transfer-of-control addressing modes are used in conjunction with jump instructions to control the execution sequence of the software program. 12.3.1 Operand Addressing Modes The operand of an instruction specifies what memory location is to be affected by that instruction. Several different operand addressing modes are available, allowing memory locations to be specified in a variety of ways. An instruction can specify an address directly by supplying the specific address, or indirectly by specifying a register pointer. The contents of the register (or in some cases, two registers) point to the desired memory location. In the immediate mode, the data byte to be used is contained in the instruction itself. Each addressing mode has its own advantages and disadvantages with respect to flexibility, execution speed, and program compactness. Not all modes are available with all instructions. The Load (LD) instruction offers the largest number of addressing modes. 35 www.national.com 12.0 Instruction Set (Continued) Example: Load Accumulator Immediate LD A,#05 Reg/Data Memory Contents Before Contents After The transfer-of-control addressing modes are described below. Each description includes an example of a Jump instruction using a particular addressing mode, and the effect on the Program Counter bytes of executing that instruction. Jump Relative. In this 1-byte instruction, six bits of the instruction opcode specify the distance of the jump from the current program memory location. The distance of the jump can range from −31 to +32. A JP+1 instruction is not allowed. The programmer should use a NOP instead. Example: Jump Relative JP 0A Reg PCU Contents Before 02 Hex Contents After 02 Hex Accumulator XX Hex 05 Hex Immediate Short. This is a special case of an immediate instruction. In the “Load B immediate” instruction, the 4-bit immediate value in the instruction is loaded into the lower nibble of the B register. The upper nibble of the B register is reset to 0000 binary. Example: Load B Register Immediate Short LD B,#7 Reg/Data Memory Contents Before Contents After B Pointer 12 Hex 07 Hex Indirect from Program Memory. This is a special case of an indirect instruction that allows access to data tables stored in program memory. In the “Load Accumulator Indirect” (LAID) instruction, the upper and lower bytes of the Program Counter (PCU and PCL) are used temporarily as a pointer to program memory. For purposes of accessing program memory, the contents of the Accumulator and PCL are exchanged. The data pointed to by the Program Counter is loaded into the Accumulator, and simultaneously, the original contents of PCL are restored so that the program can resume normal execution. Example: Load Accumulator Indirect LAID Reg/Data Memory PCU PCL Accumulator Memory Location 041F Hex 12.3.2 Tranfer-of-Control Addressing Modes Program instructions are usually executed in sequential order. However, Jump instructions can be used to change the normal execution sequence. Several transfer-of-control addressing modes are available to specify jump addresses. A change in program flow requires a non-incremental change in the Program Counter contents. The Program Counter consists of two bytes, designated the upper byte (PCU) and lower byte (PCL). The most significant bit of PCU is not used, leaving 15 bits to address the program memory. Different addressing modes are used to specify the new address for the Program Counter. The choice of addressing mode depends primarily on the distance of the jump. Farther jumps sometimes require more instruction bytes in order to completely specify the new Program Counter contents. The available transfer-of-control addressing modes are: Contents Before 04 Hex 35 Hex 1F Hex 25 Hex Contents After 04 Hex 36 Hex 25 Hex 25 Hex PCL 05 Hex 0F Hex Jump Absolute. In this 2-byte instruction, 12 bits of the instruction opcode specify the new contents of the Program Counter. The upper three bits of the Program Counter remain unchanged, restricting the new Program Counter address to the same 4 kbyte address space as the current instruction. (This restriction is relevant only in devices using more than one 4 kbyte program memory space.) Example: Jump Absolute JMP 0125 Reg PCU Contents Before 0C Hex Contents After 01 Hex PCL 77 Hex 25 Hex Jump Absolute Long. In this 3-byte instruction, 15 bits of the instruction opcode specify the new contents of the Program Counter. Example: Jump Absolute Long JMP 03625 Reg/ Memory PCU PCL Contents Before 42 Hex 36 Hex Contents After 36 Hex 25 Hex • • • • Jump Relative Jump Absolute Jump Absolute Long Jump Indirect www.national.com 36 12.0 Instruction Set (Continued) Jump Indirect. In this 1-byte instruction, the lower byte of the jump address is obtained from a table stored in program memory, with the Accumulator serving as the low order byte of a pointer into program memory. For purposes of accessing program memory, the contents of the Accumulator are written to PCL (temporarily). The data pointed to by the Program Counter (PCH/PCL) is loaded into PCL, while PCH remains unchanged. Example: Jump Indirect JID Reg/ Memory PCU PCL Accumulator Memory Location 32 Hex 32 Hex 0126 Hex The VIS instruction is a special case of the Indirect Transfer of Control addressing mode, where the double-byte vector associated with the interrupt is transferred from adjacent addresses in program memory into the Program Counter in order to jump to the associated interrupt service routine. 12.4 INSTRUCTION TYPES The instruction set contains a wide variety of instructions. The available instructions are listed below, organized into related groups. Some instructions test a condition and skip the next instruction if the condition is not true. Skipped instructions are executed as no-operation (NOP) instructions. 12.4.1 Arithmetic Instructions The arithmetic instructions perform binary arithmetic such as addition and subtraction, with or without the Carry bit. Add (ADD) Add with Carry (ADC) Subtract (SUB) Subtract with Carry (SUBC) Increment (INC) Decrement (DEC) Decimal Correct (DCOR) Clear Accumulator (CLR) Set Carry (SC) Reset Carry (RC) 12.4.2 Transfer-of-Control Instructions The transfer-of-control instructions change the usual sequential program flow by altering the contents of the Program Counter. The Jump to Subroutine instructions save the Program Counter contents on the stack before jumping; the Return instructions pop the top of the stack back into the Program Counter. Jump Relative (JP) Jump Absolute (JMP) Jump Absolute Long (JMPL) Jump Indirect (JID) Jump to Subroutine (JSR) 37 Jump to Subroutine Long (JSRL) Return from Subroutine (RET) Return from Subroutine and Skip (RETSK) Return from Interrupt (RETI) Software Trap Interrupt (INTR) Vector Interrupt Select (VIS) 12.4.3 Load and Exchange Instructions The load and exchange instructions write byte values in registers or memory. The addressing mode determines the source of the data. Load (LD) Load Accumulator Indirect (LAID) Exchange (X) 12.4.4 Logical Instructions The logical instructions perform the operations AND, OR, and XOR (Exclusive OR). Other logical operations can be performed by combining these basic operations. For example, complementing is accomplished by exclusiveORing the Accumulator with FF Hex. Logical AND (AND) Logical OR (OR) Exclusive OR (XOR) 12.4.5 Accumulator Bit Manipulation Instructions The Accumulator bit manipulation instructions allow the user to shift the Accumulator bits and to swap its two nibbles. Rotate Right Through Carry (RRC) Rotate Left Through Carry (RLC) Swap Nibbles of Accumulator (SWAP) 12.4.6 Stack Control Instructions Push Data onto Stack (PUSH) Pop Data off of Stack (POP) 12.4.7 Memory Bit Manipulation Instructions The memory bit manipulation instructions allow the user to set and reset individual bits in memory. Set Bit (SBIT) Reset Bit (RBIT) Reset Pending Bit (RPND) 12.4.8 Conditional Instructions The conditional instruction test a condition. If the condition is true, the next instruction is executed in the normal manner; if the condition is false, the next instruction is skipped. If Equal (IFEQ) If Not Equal (IFNE) If Greater Than (IFGT) If Carry (IFC) If Not Carry (IFNC) If Bit (IFBIT) If B Pointer Not Equal (IFBNE) And Skip if Zero (ANDSZ) Decrement Register and Skip if Zero (DRSZ) Contents Before 01 Hex C4 Hex 26 Hex Contents After 01 Hex 32 Hex 26 Hex www.national.com 12.0 Instruction Set 12.4.9 No-Operation Instruction (Continued) C HC GIE VU VL Registers 1 Bit of PSW Register for Carry 1 Bit of PSW Register for Half Carry 1 Bit of PSW Register for Global Interrupt Enable Interrupt Vector Upper Byte Interrupt Vector Lower Byte Symbols [B] Memory Indirectly Addressed by B Register Memory Indirectly Addressed by X Register Direct Addressed Memory Direct Addressed Memory or [B] Direct Addressed Memory or [B] or Immediate Data 8-Bit Immediate Data Register Memory: Addresses F0 to FF (Includes B, X and SP) Bit Number (0 to 7) Loaded with Exchanged with [X] MD Mem Meml Imm Reg Bit ← The no-operation instruction does nothing, except to occupy space in the program memory and time in execution. No-Operation (NOP) Note: The VIS is a special case of the Indirect Transfer of Control addressing mode, where the double byte vector associated with the interrupt is transferred from adjacent addresses in the program memory into the program counter (PC) in order to jump to the associated interrupt service routine. 12.5 REGISTER AND SYMBOL DEFINITION The following abbreviations represent the nomenclature used in the instruction description and the COP8 cross-assembler. Registers A B X SP PC PU PL 8-Bit Accumulator Register 8-Bit Address Register 8-Bit Address Register 8-Bit Stack Pointer Register 15-Bit Program Counter Register Upper 7 Bits of PC Lower 8 Bits of PC ↔ 12.6 INSTRUCTION SET SUMMARY ADD ADC SUBC AND ANDSZ OR XOR IFEQ IFEQ IFNE IFGT IFBNE DRSZ SBIT RBIT IFBIT RPND X X LD LD LD LD LD X X A,Mem A,[X] A,Meml A,[X] B,Imm Mem,Imm Reg,Imm A, [B ± ] A, [X ± ] A,Meml A,Meml A,Meml A,Meml A,Imm A,Meml A,Meml MD,Imm A,Meml A,Meml A,Meml ADD ADD with Carry Subtract with Carry Logical AND Logical AND Immed., Skip if Zero Logical OR Logical EXclusive OR IF EQual IF EQual IF Not Equal IF Greater Than If B Not Equal Decrement Reg., Skip if Zero Set BIT Reset BIT IF BIT Reset PeNDing Flag EXchange A with Memory EXchange A with Memory [X] LoaD A with Memory LoaD A with Memory [X] LoaD B with Immed. LoaD Memory Immed. LoaD Register Memory Immed. EXchange A with Memory [B] EXchange A with Memory [X] A ←A + Meml A ←A + Meml + C, C← Carry, HC ←Half Carry A ←A − MemI + C, C← Carry, HC ←Half Carry A ←A and Meml Skip next if (A and Imm) = 0 A ←A or Meml A ←A xor Meml Compare MD and Imm, Do next if MD = Imm Compare A and Meml, Do next if A = Meml Compare A and Meml, Do next if A ≠ Meml Compare A and Meml, Do next if A > Meml Do next if lower 4 bits of B ≠ Imm Reg ←Reg − 1, Skip if Reg = 0 1 to bit, Mem (bit = 0 to 7 immediate) 0 to bit, Mem If bit #, A or Mem is true do next instruction Reset Software Interrupt Pending Flag A ↔Mem A ↔[X] A ←Meml A ←[X] B ←Imm Mem ←Imm Reg ←Imm A↔[B], (B ←B ± 1) A↔[X], (X ←X ± 1) # Reg #,Mem #,Mem #,Mem www.national.com 38 12.0 Instruction Set LD LD LD CLR INC DEC LAID DCOR RRC RLC SWAP SC RC IFC IFNC POP PUSH VIS JMPL JMP JP JSRL JSR JID RET RETSK RETI INTR NOP Addr. Addr. Disp. Addr. Addr. A A A A A A A, [B ± ] A, [X ± ] [B ± ],Imm A A A (Continued) A←[B], (B ←B ± 1) A←[X], (X ←X ± 1) [B] ←Imm, (B ←B ± 1) A←0 A←A + 1 A←A − 1 A ←ROM (PU,A) A ←BCD correction of A (follows ADC, SUBC) C →A7→… →A0→C C ←A7←…←A0←C, HC ←A0 A7…A4↔A3…A0 C ←1, HC ←1 C ←0, HC ←0 IF C is true, do next instruction If C is not true, do next instruction SP ←SP + 1, A←[SP] [SP] ←A, SP←SP − 1 PU ←[VU], PL ←[VL] PC ←ii (ii = 15 bits, 0 to 32k) PC9…0 ←i (i = 12 bits) PC ←PC + r (r is −31 to +32, except 1) [SP] ←PL, [SP−1]←PU,SP−2, PC ←ii [SP] ←PL, [SP−1]←PU,SP−2, PC9…0←i PL ←ROM (PU,A) SP + 2, PL ←[SP], PU ←[SP−1] SP + 2, PL←[SP],PU ←[SP−1], skip next instruction SP + 2, PL ←[SP],PU ←[SP−1],GIE ←1 [SP] ←PL, [SP−1]←PU, SP−2, PC ←0FF PC ←PC + 1 LoaD A with Memory [B] LoaD A with Memory [X] LoaD Memory [B] Immed. CLeaR A INCrement A DECrement A Load A InDirect from ROM Decimal CORrect A Rotate A Right thru C Rotate A Left thru C SWAP nibbles of A Set C Reset C IF C IF Not C POP the stack into A PUSH A onto the stack Vector to Interrupt Service Routine Jump absolute Long Jump absolute Jump relative short Jump SubRoutine Long Jump SubRoutine Jump InDirect RETurn from subroutine RETurn and SKip RETurn from Interrupt Generate an Interrupt No OPeration 39 www.national.com 12.0 Instruction Set (Continued) Instructions Using A & C CLRA INCA DECA LAID DCORA RRCA RLCA SWAPA SC RC IFC IFNC Immed. 2/2 2/2 2/2 2/2 2/2 2/2 2/2 2/2 PUSHA POPA ANDSZ 1/1 1/1 1/1 1/3 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/3 1/3 2/2 12.7 INSTRUCTION EXECUTION TIME Most instructions are single byte (with immediate addressing mode instructions taking two bytes). Most single byte instructions take one cycle time to execute. Skipped instructions require x number of cycles to be skipped, where x equals the number of bytes in the skipped instruction opcode. See the BYTES and CYCLES per INSTRUCTION table for details. Bytes and Cycles per Instruction The following table shows the number of bytes and cycles for each instruction in the format of byte/cycle. Arithmetic and Logic Instructions [B] ADD ADC SUBC AND OR XOR IFEQ IFGT IFBNE DRSZ SBIT RBIT IFBIT RPND 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/3 3/4 3/4 3/4 Direct 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Transfer of Control Instructions JMPL JMP JP JSRL JSR JID VIS RET RETSK RETI INTR NOP 3/4 2/3 1/3 3/5 2/5 1/3 1/5 1/5 1/5 1/5 1/7 1/1 Memory Transfer Instructions Register Indirect [B] X A, (Note 27) LD A, (Note 27) LD B, Imm LD B, Imm LD Mem, Imm LD Reg, Imm IFEQ MD, Imm Note 27: = > Memory location addressed by B or X or directly. Direct Immed. Register Indirect Auto Incr. & Decr. [B+, B−] [X+, X−] 1/3 1/3 (If B < 16) (If B > 15) 2/2 [X] 1/3 1/3 2/3 2/3 2/2 1/1 2/2 1/1 1/1 1/2 1/2 2/2 3/3 2/3 3/3 www.national.com 40 12.8 OPCODE TABLE Upper Nibble D DRSZ 0F0 DRSZ 0F1 DRSZ 0F2 DRSZ 0F3 DRSZ 0F4 DRSZ 0F5 DRSZ 0F6 DRSZ 0F7 * NOP IFNE A,[B] LD A,[X+] LD A,[X−] LD Md,#i DIR LD A,[X] * * LD B,#i RETI SBIT 7,[B] LD A,[B] LD [B],#i RET SBIT 6,[B] JSRL LD A,Md RETSK SBIT 5,[B] RBIT 5,[B] RBIT 6,[B] RBIT 7,[B] JMPL X A,Md POPA SBIT 4,[B] RBIT 4,[B] LD B,#03 LD B,#02 LD B,#01 LD B,#00 LD A,[B−] LD [B−],#i DECA SBIT 3,[B] RBIT 3,[B] LD B,#04 LD A,[B+] LD [B+],#i INCA SBIT 2,[B] RBIT 2,[B] LD B,#05 IFBNE 0A IFBNE 0B IFBNE 0C IFBNE 0D IFBNE 0E IFBNE 0F IFEQ Md,#i IFNE A,#i IFNC SBIT 1,[B] RBIT 1,[B] LD B,#06 IFBNE 9 RLCA LD A,#i IFC SBIT 0,[B] RBIT 0,[B] LD B,#07 IFBNE 8 JSR x800–x8FF JSR x900–x9FF * OR A,#i OR A,[B] IFBIT PUSHA 7,[B] LD B,#08 IFBNE 7 JSR x700–x7FF DRSZ 0F8 DRSZ 0F9 DRSZ 0FA DRSZ 0FB DRSZ 0FC DRSZ 0FD DRSZ 0FE DRSZ 0FF X A,[X] X A,[B] XOR A,#i XOR A,[B] IFBIT DCORA 6,[B] LD B,#09 IFBNE 6 JSR x600–x6FF RPND JID AND A,#i AND A,[B] IFBIT SWAPA LD 5,[B] B,#0A IFBNE 5 JSR x500–x5FF VIS LAID ADD A,#i ADD A,[B] IFBIT 4,[B] CLRA LD B,#0B IFBNE 4 JSR x400–x4FF X A,[X−] X A,[B−] IFGT A,#i IFGT A,[B] IFBIT 3,[B] * LD B,#0C IFBNE 3 JSR x300–x3FF JMP JP+20 JP+4 x300–x3FF JMP JP+21 JP+5 x400–x4FF JMP JP+22 JP+6 x500–x5FF JMP JP+23 JP+7 x600–x6FF JMP JP+24 JP+8 x700–x7FF JMP JP+25 JP+9 x800–x8FF 3 4 5 6 7 8 JMP JP+26 JP+10 9 x900–x9FF JSR JMP JP+27 JP+11 A xA00–xAFF xA00–xAFF JSR JMP JP+28 JP+12 B xB00–xBFF xB00–xBFF JSR JMP JP+29 JP+13 C xC00–xCFF xC00–xCFF JSR JMP JP+30 JP+14 D xD00–xDFF xD00–xDFF JSR JMP JP+31 JP+15 E xE00–xEFF xE00–xEFF JSR JMP JP+32 JP+16 F xF00–xFFF xF00–xFFF X A,[X+] X A,[B+] IFEQ A,#i IFEQ A,[B] IFBIT 2,[B] * LD B,#0D IFBNE 2 JSR x200–x2FF JMP JP+19 JP+3 x200–x2FF 2 * SC SUBC A, #i SUBC A,[B] IFBIT 1,[B] * LD B,#0E IFBNE 1 JSR x100–x1FF JMP JP+18 JP+2 x100–x1FF 1 RRCA RC ADC A,#i ADC A,[B] IFBIT ANDSZ 0,[B] A, #i LD B,#0F IFBNE 0 JSR x000–x0FF JMP JP+17 INTR x000–x0FF 0 C B A 9 8 7 6 5 4 3 2 1 0 F E JP−15 JP−31 LD 0F0, #i JP−14 JP−30 LD 0F1, #i 12.0 Instruction Set JP−13 JP−29 LD 0F2, #i JP−12 JP−28 LD 0F3, #i (Continued) JP−11 JP−27 LD 0F4, #i JP−10 JP−26 LD 0F5, #i JP−9 JP−25 LD 0F6, #i JP−8 JP−24 LD 0F7, #i JP−5 JP−21 LD 0FA, #i JP−4 JP−20 LD 0FB, #i JP−3 JP−19 LD 0FC, #i JP−2 JP−18 LD 0FD, #i JP−1 JP−17 LD 0FE, #i JP−0 JP−16 LD 0FF, #i www.national.com Where, i is the immediate data Md is a directly addressed memory location * is an unused opcode The opcode 60 Hex is also the opcode for IFBIT #i,A Lower Nibble 41 JP−7 JP−23 LD 0F8, #i JP−6 JP−22 LD 0F9, #i 13.0 Mask Options For COP8SEC5 The mask options for this device are described below. These options are programmed at the same time as the ROM pattern and therefore must be submitted with the ROM pattern. OPTION 1: Clock configuration = 1 Crystal Oscillator (CKI/10) G7 (CKO) is clock crystal/resonator 14.0 Development Support 14.1 OVERVIEW National is engaged with an international community of independent 3rd party vendors who provide hardware and software development tool support. Through National’s interaction and guidance, these tools cooperate to form a choice of solutions that fits each developer’s needs. This section provides a summary of the tool and development kits currently available. Up-to-date information, selection guides, free tools, demos, updates, and purchase information can be obtained at our web site at: www.national.com/cop8. 14.2 SUMMARY OF TOOLS COP8 Evaluation Tools generator output to CKI is the clock input = 2 Single-pin R/C Controlled Oscillator G7 is available as a HALT restart and/or general purpose input CKI is the clock input OPTION 2: HALT = 1 Enable HALT mode = 2 Disable HALT mode OPTION 3: WATCHDOG = 1 Enable WATCHDOG output on Pin G1 = 2 Disable WATCHDOG output on G1 and Enable standard I/O on Pin G1 OPTION 4: BONDING = 1 Reserved = 2 20 pin SO = 3 16 pin SO (Note: ROM Mask prototypes of 16 pin SO devices will be provided in 16 pin ceramic DIP package) 13.1 Options for COP8SER7 COP8SER7 is only available in two versions: COP8SER7XXM8–XE Crystal oscillator, HALT enabled, WATCHDOG enabled. COP8SER7XXM8–RE R/C oscillator, HALT enabled, WATCHDOG enabled. • COP8–NSEVAL: Free Software Evaluation package for Windows. A fully integrated evaluation environment for COP8, including versions of WCOP8 IDE (Integrated Development Environment), COP8-NSASM, COP8-MLSIM, COP8C, DriveWay™ COP8, Manuals, and other COP8 information. • COP8–MLSIM: Free Instruction Level Simulator tool for Windows. For testing and debugging software instructions only (No I/O or interrupt support). • COP8–EPU: Very Low cost COP8 Evaluation & Programming Unit. Windows based evaluation and hardware-simulation tool, with COP8 device programmer and erasable samples. Includes COP8-NSDEV, Driveway COP8 Demo, MetaLink Debugger, I/O cables and power supply. • COP8–EVAL-HIxx: Low cost target application evaluation and development board for COP8Sx Families, from Hilton Inc. Real-time environment with integrated A/D, Temp Sensor, and Peripheral I/O. • COP8–EVAL-ICUxx: Very Low cost evaluation and design test board for COP8ACC and COP8SGx Families, from ICU. Real-time environment with add-on A/D, D/A, and EEPROM. Includes software routines and reference designs. • Manuals, Applications Notes, Literature: Available free from our web site at: www.national.com/cop8. COP8 Integrated Software/Hardware Design Development Kits • COP8-EPU: Very Low cost Evaluation & Programming Unit. Windows based development and hardwaresimulation tool for COPSx/xG families, with COP8 device programmer and samples. Includes COP8-NSDEV, Driveway COP8 Demo, MetaLink Debugger, cables and power supply. • COP8-DM: Moderate cost Debug Module from MetaLink. A Windows based, real-time in-circuit emulation tool with COP8 device programmer. Includes COP8-NSDEV, DriveWay COP8 Demo, MetaLink Debugger, power supply, emulation cables and adapters. COP8 Development Languages and Environments • COP8-NSASM: Free COP8 Assembler v5 for Win32. Macro assembler, linker, and librarian for COP8 software development. Supports all COP8 devices. (DOS/Win16 v4.10.2 available with limited support). (Compatible with WCOP8 IDE, COP8C, and DriveWay COP8). www.national.com 42 14.0 Development Support • (Continued) COP8 Productivity Enhancement Tools COP8-NSDEV: Very low cost Software Development Package for Windows. An integrated development environment for COP8, including WCOP8 IDE, COP8C (limited version), COP8-NSASM, COP8-MLSIM. COP8C: Moderately priced C Cross-Compiler and Code Development System from Byte Craft (no code limit). Includes BCLIDE (Byte Craft Limited Integrated Development Environment) for Win32, editor, optimizing C CrossCompiler, macro cross assembler, BC-Linker, and MetaLink tools support. (DOS/SUN versions available; Compiler is installable under WCOP8 IDE; Compatible with DriveWay COP8). EWCOP8-KS: Very Low cost ANSI C-Compiler and Embedded Workbench from IAR (Kickstart version: COP8Sx/Fx only with 2k code limit; No FP). A fully integrated Win32 IDE, ANSI C-Compiler, macro assembler, editor, linker, Liberian, C-Spy simulator/debugger, PLUS MetaLink EPU/DM emulator support. EWCOP8-AS: Moderately priced COP8 Assembler and Embedded Workbench from IAR (no code limit). A fully integrated Win32 IDE, macro assembler, editor, linker, librarian, and C-Spy high-level simulator/debugger with I/O and interrupts support. (Upgradeable with optional C-Compiler and/or MetaLink Debugger/Emulator support). EWCOP8-BL: Moderately priced ANSI C-Compiler and Embedded Workbench from IAR (Baseline version: All COP8 devices; 4k code limit; no FP). A fully integrated Win32 IDE, ANSI C-Compiler, macro assembler, editor, linker, librarian, and C-Spy high-level simulator/debugger. (Upgradeable; CWCOP8-M MetaLink tools interface support optional). EWCOP8: Full featured ANSI C-Compiler and Embedded Workbench for Windows from IAR (no code limit). A fully integrated Win32 IDE, ANSI C-Compiler, macro assembler, editor, linker, librarian, and C-Spy high-level simulator/debugger. (CWCOP8-M MetaLink tools interface support optional). EWCOP8-M: Full featured ANSI C-Compiler and Embedded Workbench for Windows from IAR (no code limit). A fully integrated Win32 IDE, ANSI C-Compiler, macro assembler, editor, linker, librarian, C-Spy high-level simulator/debugger, PLUS MetaLink debugger/hardware interface (CWCOP8-M). • • WCOP8 IDE: Very Low cost IDE (Integrated Development Environment) from KKD. Supports COP8C, COP8NSASM, COP8-MLSIM, DriveWay COP8, and MetaLink debugger under a common Windows Project Management environment. Code development, debug, and emulation tools can be launched from the project window framework. DriveWay-COP8: Low cost COP8 Peripherals Code Generation tool from Aisys Corporation. Automatically generates tested and documented C or Assembly source code modules containing I/O drivers and interrupt handlers for each on-chip peripheral. Application specific code can be inserted for customization using the integrated editor. (Compatible with COP8-NSASM, COP8C, and WCOP8 IDE.) COP8-UTILS: Free set of COP8 assembly code examples, device drivers, and utilities to speed up code development. • • • • COP8-MLSIM: Free Instruction Level Simulator tool for Windows. For testing and debugging software instructions only (No I/O or interrupt support). COP8 Real-Time Emulation Tools • • • COP8-DM: MetaLink Debug Module. A moderately priced real-time in-circuit emulation tool, with COP8 device programmer. Includes MetaLink Debugger, power supply, emulation cables and adapters. • IM-COP8: MetaLink iceMASTER ® . A full featured, realtime in-circuit emulator for COP8 devices. Includes COP8-NSDEV, Driveway COP8 Demo, MetaLink Windows Debugger, and power supply. Package-specific probes and surface mount adaptors are ordered separately. COP8 Device Programmer Support • • • MetaLink’s EPU and Debug Module include development device programming capability for COP8 devices. Third-party programmers and automatic handling equipment cover needs from engineering prototype and pilot production, to full production environments. Factory programming available for high-volume requirements. • • 43 www.national.com 14.0 Development Support Vendor National Tools COP8-NSEVAL COP8-NSASM COP8-MLSIM COP8-NSDEV COP8-EPU COP8-DM Development Devices IM-COP8 MetaLink COP8-EPU COP8-DM (Continued) 14.3 TOOLS ORDERING NUMBERS FOR THE COP8SEx FAMILY DEVICES Order Number COP8-NSEVAL COP8-NSASM COP8-MLSIM COP8-NSDEV Not available for this device Contact metaLink COP8SER7 Contact MetaLink Not available for this device DM5-COP8-SEx (15 MHz), plus PS-10, plus DM-COP8/xxx (ie. 28D) MHW-CNVxx (xx = 33, 34 etc.) MHW-COP8-PGMA-DS IM-COP8 IM-COP8-AD-464 (-220) (10 MHz maximum) PC-COP8SE28DW-AD-10 PC-COP8SE40DW-AD-10 MHW-SOICxx (xx = 16, 20, 28) ICU or National KKD IAR Byte Craft Aisys COP8-EVAL-ICUxx Not available for this device WCOP8-IDE EWCOP8-xx COP8C DriveWay COP8 WCOP8-IDE See summary above COP8C DriveWay COP8 Contact vendors VL L-H M L L-H Included in EPU and DM Included all software and manuals Included all software and manuals Included all software and manuals For approved programmer listings and vendor information, go to our OTP support page at: www.national.com/cop8 M Included p/s (PS-10), target cable of choice (DIP or SOIC; i.e. DM-COP8/28D), 16/20/28/40 DIP/SO and 44 PLCC programming sockets. Add target adapter (if needed) DM target converters for 20SO/28SO; (i.e. MHW-CNV38 for 20 pin DIP to SO package converter) For programming 16/20/28 SOIC and 44 PLCC on the EPU Base unit 10 MHz; -220 = 220V; add probe card (required) and target adapter (if needed); included software and manuals 10 MHz 28 DIP probe card; 2.5V to 6.0V 10 MHz 40 DIP probe card; 2.5V to 6.0V 16 or 20 or 28 pin SOIC adapter for probe card VL 32k Eraseable or OTP devices Cost Free Free Free VL Web site download Included in EPU and DM. Web site download Included in EPU and DM. Web site download Included in EPU and DM. Order CD from website Notes DM Target Adapters L L H IM Probe Card M M L OTP Programmers Cost: Free; VL = < $100; L = $100 - $300; M = $300 - $1k; H = $1k - $3k; VH = $3k - $5k www.national.com 44 14.0 Development Support 14.4 WHERE TO GET TOOLS (Continued) Tools are ordered directly from the following vendors. Please go to the vendor’s web site for current listings of distributors. Vendor Aisys Home Office U.S.A.: Santa Clara, CA 1-408-327-8820 fax: 1-408-327-8830 Byte Craft U.S.A. 1-519-888-6911 fax: 1-519-746-6751 IAR Sweden: Uppsala +46 18 16 78 00 fax: +46 18 16 78 38 www.iar.se info@iar.se info@iar.com info@iarsys.co.uk info@iar.de U.S.A.: San Francisco 1-415-765-5500 fax: 1-415-765-5503 U.K.: London +44 171 924 33 34 fax: +44 171 924 53 41 Germany: Munich +49 89 470 6022 fax: +49 89 470 956 ICU Sweden: Polygonvaegen +46 8 630 11 20 fax: +46 8 630 11 70 KKD MetaLink Denmark: U.S.A.: Chandler, AZ 1-800-638-2423 fax: 1-602-926-1198 www.icu.se support@icu.se support @icu.ch www.kkd.dk www.metaice.com sales @metaice.com support @metaice.com bbs: 1-602-962-0013 www.metalink.de National U.S.A.: Santa Clara, CA 1-800-272-9959 fax: 1-800-737-7018 www.national.com/cop8 support @nsc.com europe.support @nsc.com Germany: Kirchseeon 80-91-5696-0 fax: 80-91-2386 islanger@metalink.de Distributors Worldwide Europe: +49 (0) 180 530 8585 fax: +49 (0) 180 530 8586 Distributors Worldwide Switzeland: Hoehe +41 34 497 28 20 fax: +41 34 497 28 21 www.bytecraft.com info @bytecraft.com Distributors Electronic Sites www.aisysinc.com info@aisysinc.com Other Main Offices Distributors The following companies have approved COP8 programmers in a variety of configurations. Contact your local office or distributor. You can link to their web sites and get the latest listing of approved programmers from National’s COP8 OTP Support page at: www.national.com/cop8. Advantech; Advin; BP Microsystems; Data I/O; Hi-Lo Systems; ICE Technology; Lloyd Research; Logical Devices; MQP; Needhams; Phyton; SMS; Stag Programmers; System General; Tribal Microsystems; Xeltek. 14.5 CUSTOMER SUPPORT Complete product information and technical support is available from National’s customer response centers, and from our on-line COP8 customer support sites. 45 www.national.com Physical Dimensions inches (millimeters) unless otherwise noted Molded SO Wide Body Package (WM) Order Number COP8SEC516M, NS Package Number M16B Molded SO Wide Body Package (WM) Order Number COP8SEC520M, NS Package Number M20B www.national.com 46 COP8SE Family, 8-Bit CMOS ROM Based and OTP Microcontrollers with 4k Memory and 128 Bytes EERAM Notes LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com www.national.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: sea.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.