COP912C

COP912C 8-Bit Microcontroller August 2000 COP912C 8-Bit Microcontroller General Description Note: COP8SA devices are instruction set and pinout compatible supersets of the COP912C devices, and are replacements for these in new designs when possible. The COP912C ROM based microcontrollers are integrated COP8(tm) Base core devices with smaller memory (768 bytes), and fewer on-board features. These single-chip CMOS devices are suited for lower-functionality applications where system cost is of prime consideration. Pin and software compatible (different Vcc range) 4k/32k OTP versions are available (COP87LxxCJ/RJ Family). Erasable windowed versions are available for use with a range of COP8(tm) software and hardware development tools. RAM (bytes) 64 64 Family features include an 8-bit memory mapped architecture, 10MHz CKI with 2.5us(912C) or 2us(912CH) instruction cycle, one multi-function 16-bit timer/counter with PWM, MICROWIRE/PLUS(tm) serial I/O, power saving HALT mode, three clock modes, high current outputs, software selectable I/O options, multi-volt operation and 20 pin packages. Devices included in this datasheet are: Device COP912C COP912CH Memory (bytes) 768 ROM 768ROM I/O Pins 16 16 Packages 20 DIP/SOIC 20 DIP/SOIC Temperature 0 to +70˚C 0 to +70˚C Comments 2.3v - 4.0v 4.0v - 5.5v Key Features n Lowest cost COP8 microcontroller n 16-bit multi-function timer supporting — PWM mode — External event counter mode — Input capture mode n 768 bytes of ROM n 64 bytes of RAM n Versatile and easy to use instruction set n 8-bit Stack Pointer (SP) — stack in RAM n Two 8-bit Register Indirect Memory Pointers (B, X) Fully Static CMOS n Low current drain (typically < 1 µA) n Single supply operation: 2.3V to 4.0V or 4.0V to 5.5V n Temperature range: 0˚C to +70˚C I/O Features n Memory mapped I/O n Software selectable I/O options (TRI-STATE ® Output, Push-Pull Output, Weak Pull-Up Input, High Impedance Input) n Schmitt trigger inputs on Port G n MICROWIRE/PLUS™ Serial I/O n Packages: 20 DIP/SO with 16 I/O pins Development Support n Emulation and OTP devices n Real time emulation and full program debug offered by MetaLink Development System Applications n n n n n n n n n Electronic keys and switches Remote Control Timers Alarms Small industrial control units Low cost slave controllers Temperature meters Small domestic appliances Toys and games CPU/Instruction Set Features n Instruction cycle time of 2 µs for COP912CH and 2.5 µs for COP912C n Three multi-sourced interrupts servicing — External Interrupt with selectable edge — Timer interrupt — Software interrupt TRI-STATE ® is a registered trademark of National Semiconductor Corporation. COP8™, MICROWIRE/PLUS™, WATCHDOG™ and MICROWIRE™ are trademarks of National Semiconductor Corporation. PC ® is a registered trademark of International Business Machines Corp. iceMaster™ is a trademark of MetaLink Corporation. © 2000 National Semiconductor Corporation DS012060 www.national.com COP912C Block Diagram DS012060-1 www.national.com 2 COP912C Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) Voltage at Any Pin 6.0V −0.3V to VCC +0.3V Total Current into VCC Pin (Source) Total Current out of GND Pin (Sink) Storage Temperature Range 80 mA 80 mA −65˚C to +150˚C Note 1: Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings. DC Electrical Characteristics COP912C/COP912CH; 0˚C ≤ TA ≤ +70˚C unless other specified Parameter Operating Voltage 912C 912CH Power Supply Ripple 1 (Note 2) Supply Current (Note 3) CKI = 4 MHz CKI = 4 MHz HALT Current INPUT LEVELS (VIH, VIL) Reset, CKI: Logic High Logic Low All Other Inputs Logic High Logic Low Hi-Z Input Leakage/TRI-STATE Leakage Input Pullup Current G-Port Hysteresis Output Current Levels Source (Push-Pull Mode) Sink (Push-Pull Mode) Allowable Sink/Source Current Per Pin Input Capacitance (Note 4) Load Capacitance on D2 (Note 4) Note 2: Rate of voltage change must be less then 0.5 V/ms. Note 3: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open. Note 4: Characterized, not tested. Conditions Min 2.3 4.0 Typ Max 4.0 5.5 0.1 VCC 6.0 2.5 Units V V V mA mA µA Peak to Peak VCC = 5.5V, tc = 2.5 µs VCC = 4.0V, tc = 2.5 µs VCC = 5.5V, CKI = 0 MHz 5 x POWER SUPPLY RISE TIME FIGURE 3. Recommended Reset Circuit OSCILLATOR CIRCUITS The device can be driven by a clock input which can be between DC and 5 MHz. CRYSTAL OSCILLATOR By selecting CKO as a clock output, CKI and CKO can be connected to create a crystal controlled oscillator. Table 1 shows the component values required for various standard crystal values. 7 HALT MODE The device is a fully static device. The device enters the HALT mode by writing a one to the G7 bit of the G data register. Once in the HALT mode, the internal circuitry does not receive any clock signal and is therefore frozen in the exact state it was in when halted. In this mode the chip will only draw leakage current. The device supports two different ways of exiting the HALT mode. The first method is with a low to high transition on the CKO (G7) pin. This method precludes the use of the crystal clock configuration (since CKO is a dedicated output), and so may be used either with an RC clock configuration (or an external clock configuration). The second method of exiting the HALT mode is to pull the RESET low. Note: To allow clock resynchronization, it is necessary to program two NOP’s immediately after the device comes out of the HALT mode. The user must program two NOP’s following the “enter HALT mode” (set G7 data bit) instruction. MICROWIRE/PLUS MICROWIRE/PLUS is a serial synchronous communications interface. The MICROWIRE/PLUS capability enables the device to interface with any of National Semiconductor’s MICROWIRE peripherals (i.e., A/D converters, display drivwww.national.com COP912C Functional Description (Continued) SK Divide Clock Rates SL1 0 0 1 SL0 0 1 x SK 2 x tc 4 x tc 8 x tc ers, EEPROMS etc.) and with other microcontrollers which support the MICROWIRE interface. It consists of an 8-bit serial shift register (SIO) with serial data input (SI), serial data output (SO) and serial shift clock (SK). Figure 5 shows a block diagram of the MICROWIRE logic. The shift clock can be derived from either the internal source or from an external source. Operating the MICROWIRE arrangement with the internal clock source is called the Master mode of operation. Similarly, operating the MICROWIRE arrangement with an external shift clock is called the Slave mode of operation. The CNTRL register is used to configure and control the MICROWIRE mode. To use the MICROWIRE, the MSEL bit in the CNTRL register is set to one. The SK clock rate is selected by the two bits, SL0 and SL1, in the CNTRL register. The following table details the different clock rates that may be selected. Where tc is the instruction cycle clock. MICROWIRE/PLUS OPERATION Setting the BUSY bit in the PSW register causes the MICROWIRE/PLUS to start shifting the data. It gets reset when eight data bits have been shifted. The user may reset the BUSY bit by software to allow less than 8 bits to shift. The device may enter the MICROWIRE/PLUS mode either as a Master or as a Slave. Figure 5 shows how two microcontrollers and several peripherals may be interconnected using the MICROWIRE/PLUS arrangement. DS012060-7 FIGURE 5. MICROWIRE/PLUS Application WARNING: The SIO register should only be loaded when the SK clock is low. Loading the SIO register while the SK clock is high will result in undefined data in the SIO register. Setting the BUSY flag when the input SK clock is high in the MICROWIRE/PLUS slave mode may cause the current SK clock for the SIO shift register to be narrow. For safety, the BUSY flag should only be set when the input SK clock is low. G4 (SO) Config. Bit 1 0 G5 (SK) Config. Bit 0 0 G4 Pin SO TRI-STATE G5 Pin Ext. SK Ext. SK G6 Pin Operation SI MICROWIRE Slave SI MICROWIRE Slave Table 3 summarizes the settings required to enter the Master/Slave modes of operations. The table assumes that the control flag MSEL is set. TABLE 3. MICROWIRE/PLUS G Port Configuration G4 (SO) Config. Bit 1 0 G5 (SK) Config. Bit 1 1 SO TRI-STATE Int. SK Int. SK SI MICROWIRE Master SI MICROWIRE Master G4 Pin G5 Pin G6 Pin Operation MICROWIRE/PLUS MASTER MODE OPERATION In MICROWIRE/PLUS Master mode operation, the SK shift clock is generated internally. The MSEL bit in the CNTRL register must be set to allow the SK and SO functions onto the G5 and G4 pins. The G5 and G4 pins must also be selected as outputs by setting the appropriate bits in the Port G configuration register. The MICROWIRE Master mode always initiates all data exchanges. The MSEL bit in the CNTRL register is set to enable MICROWIRE/PLUS. G4 and G5 are selected as output. www.national.com 8 COP912C Functional Description (Continued) DS012060-10 FIGURE 7. Timer in PWM Mode EXTERNAL EVENT COUNTER MODE In this mode, the timer becomes a 16-bit external event counter, clocked from an input signal applied to the G3 input. The maximum frequency for this G3 input clock is 250 kHz (half of the 0.5 MHz instruction cycle clock). When the external event counter underflows, the value in the autoreload register is copied into the timer. This timer underflow may also be used to generate an interrupt. Bit 5 of the CNTRL register is used to select whether the external event counter clocks on positive or negative edges from the G3 input. Consequently, half cycles of an external input signal could be counted. The External Event counter mode is shown in Figure 8. DS012060-8 FIGURE 6. MICROWIRE/PLUS Block Diagram MICROWIRE/PLUS SLAVE MODE In MICROWIRE/PLUS Slave mode operation, the SK shift clock is generated by an external source. Setting the MSEL bit in the CNTRL register enables the SO and SK functions onto the G port. The SK pin must be selected as an input and the SO pin as an output by resetting and setting their respective bits in the G port configuration register. The user must set the BUSY flag immediately upon entering the slave mode. This will ensure that all data bits sent by the master will be shifted in properly. After eight clock pulses, the BUSY flag will be cleared and the sequence may be repeated. Note: In the Slave mode the SIO register does not stop shifting even after the busy flag goes low. Since SK is an external output, the SIO register stops shifting only when SK is turned off by the master. Note: Setting the BUSY flag when the input SK clock is high in the MICROWIRE/PLUS slave mode may cause the current SK clock for the SIO register to be narrow. When the BUSY flag is set, the MICROWIRE logic becomes active with the internal SIO shift clock enabled. If SK is high in slave mode, this will cause the internal shift clock to go from low in standby mode to high in active mode. This generates a rising edge, and causes one bit to be shifted into the SIO register from the SI input. For safety, the BUSY flag should only be set when the input SK clock is low. Note: The SIO register must be loaded only when the SK shift clock is low. Loading the SIO register while the SK clock is high will result in undefined data in the SIO register. DS012060-11 FIGURE 8. Timer in External Event Mode Timer/Counter The device has an on board 16-bit timer/counter (organized as two 8-bit registers) with an associated 16-bit autoreload/ capture register (also organized as two 8-bit registers). Both are read/write registers. The timer has three modes of operation: PWM (PULSE WIDTH MODULATION) MODE The timer counts down at the instruction cycle rate (2 µs max). When the timer count underflows, the value in the autoreload register is copied into the timer. Consequently, the timer is programmable to divide by any value from 1 to 65536. Bit 5 of the timer CNTRL register selects the timer underflow to toggle the G3 output. This allows the user to generate a square wave output or a pulse-width-modulated output. The timer underflow can also be enabled to interrupt the processor. The timer PWM mode is shown in Figure 7. INPUT CAPTURE MODE In this mode, the timer counts down at the instruction clock rate. When an external edge occurs on pin G3, the value in the timer is copied into the capture register. Consequently, the time of an external edge on the G3 pin is “captured”. Bit 5 of the CNTRL register is used to select the polarity of the external edge. This external edge capture can also be programmed to generate an interrupt. The duration of an input signal can be computed by capturing the time of the leading edge, saving this captured value, changing the capture edge, capturing the time of the trailing edge, and then subtracting this trailing edge time from the earlier leading edge time. The Input Capture mode is shown in Figure 9. 9 www.national.com COP912C Timer/Counter (Continued) Table 4 below details the TIMER modes of operation and their associated interrupts. Bit 4 of CNTRL is used to start and stop the timer/counter. Bits 5, 6 and 7 of the CNTRL register select the timer modes. The ENTI (Enable Timer Interrupt) and TPND (Timer Interrupt Pending) bits in the PSW register are used to control the timer interrupts. Care must be taken when reading from and writing to the timer and its associated autoreload/capture register. The timer and autoreload/capture register are both 16-bit, but they are read from and written to one byte at a time. It is recommended that the timer be stopped before writing a new value into it. The timer may be read “on the fly” without stopping it if suitable precautions are taken. One method of reading the timer “on the fly” is to read the upper byte of the timer first, and then read the lower byte. If the most significant bit of the lower byte is then tested and found to be high, then the upper byte of the timer should be read again and this new value used. DS012060-12 FIGURE 9. Timer in Input Capture Mode TABLE 4. Timer Modes and Control Bits CNTRL Bits 7 0 0 0 0 1 1 1 1 6 0 0 1 1 0 0 1 1 5 0 1 0 1 0 1 0 1 Operation Mode External Event Counter with Autoreload Register External Event Counter with Autoreload Register Not Allowed Not Allowed Timer with Autoreload Register Timer with Autoreload Register and Toggle TIO Out Timer with Capture Register Timer with Capture Register Timer Interrupt Timer Underflow Timer Underflow Not Allowed Not Allowed Timer Underflow Timer Underflow TIO Positive Edge TIO Negative Edge Timer Counts On TIO Positive Edge TIO Negative Edge Not Allowed Not Allowed tc tc tc tc TIMER APPLICATION EXAMPLE The timer has an autoreload register that allows any frequency to be programmed in the timer PWM mode. The timer underflow can be programmed to toggle output bit G3, and may also be programmed to generate a timer interrupt. Consequently, a fully programmable PWM output may be easily generated. The timer counts down and when it underflows, the value from the autoreload register is copied into the timer. The CNTRL register is programmed to both toggle the G3 output and generate a timer interrupt when the timer underflows. Following each timer interrupt, the user’s program alternately loads the values of the “on” time and the “off” time into the timer autoreload register. Consequently, a pulse-width-modulated (PWM) output waveform is generated to a resolution of one instruction cycle time. This PWM application example is shown in Figure 10. DS012060-13 FIGURE 10. Timer Based PWM Application Interrupts There are three interrupt sources: 1. A maskable interrupt on external G0 input positive or negative edge sensitive under software control 2. A maskable interrupt on timer underflow or timer capture 3. A non-maskable software/error interrupt on opcode zero. The GIE (global interrupt enable) bit enables the interrupt function. This is used in conjunction with ENI and ENTI to select one or both of the interrupt sources. This bit is reset when interrupt is acknowledged. ENI and ENTI bits select external and timer interrupt respectively. Thus the user can select either or both sources to interrupt the microcontroller when GIE is enabled. IEDG se- www.national.com 10 COP912C Interrupts (Continued) lects the external interrupt edge (1 = rising edge, 0 = falling edge). The user can get an interrupt on both rising and falling edges by toggling the state of IEDG bit after each interrupt. IPND and TPND bits signal which interrupt is pending. After interrupt is acknowledged, the user can check these two bits to determine which interrupt is pending. The user can prioritize the interrupt and clear the pending bit that corresponds to the interrupt being serviced. The user can also enable GIE at this point for nesting interrupts. Two things have to be kept in mind when using the software interrupt. The first is that executing a simple RET instruction will take the program control back to the software interrupt instruction itself. In other words, the program will be stuck in an infinite loop. To avoid the infinite loop, the software interrupt service routine should end with a RETSK instruction or with a JMP instruction. The second thing to keep in mind is that unlike the other interrupt sources, the software interrupt does not reset the GIE bit. This means that the device can be interrupted by other interrupt sources while servicing the software interrupt. Interrupts push the PC to the stack, reset the GIE bit to disable further interrupts and branch to address 00FF. The RETI instruction will pop the stack to PC and set the GIE bit to enable further interrupts. The user should use the RETI or the RET instruction when returning from a hardware (maskable) interrupt subroutine. The user should use the RETSK instruction when returning from a software interrupt subroutine to avoid an infinite loop situation. The software interrupt is a special kind of non-maskable interrupt which occurs when the INTR instruction (opcode 00 used to acknowledge interrupts) is fetched from ROM and placed inside the instruction register. This may happen when the PC is pointing beyond the available ROM address space or when the stack is over-popped. When the software interrupt occurs, the user can re-initialize the stack pointer and do a recovery procedure (similar to reset, but not necessarily containing all of the same initialization procedures) before restarting. Hardware and Software interrupts are treated differently. The software interrupt is not gated by the GIE bit. However, it has the lowest arbitration ranking. Also the fact that all interrupts vector to the same address 00FF Hex means that a software interrupt happening at the same time as a hardware interrupt will be missed. Note: There is always the possibility of an interrupt occurring during an instruction which is attempting to reset the GIE bit or any other interrupt enable bit. If this occurs when a single cycle instruction is being used to reset the interrupt enable bit, the interrupt enable bit will be reset but an interrupt may still occur. This is because interrupt processing is started at the same time as the interrupt bit is being reset. To avoid this scenario, the user should always use a two, three, or four cycle instruction to reset interrupt enable bits. DS012060-14 FIGURE 11. Interrupt Block Diagram DETECTION OF ILLEGAL CONDITIONS Reading of undefined ROM gets zeroes. The opcode for software interrupt is zero. If the program fetches instructions from undefined ROM, this will force a software interrupt, thus signalling that an illegal condition has occurred. Note: A software interrupt is acted upon only when a timer or external interrupt is not pending as hardware interrupts have priority over software interrupt. In addition, the Global Interrupt bit is not set when a software interrupt is being serviced thereby opening the door for the hardware interrupts to occur. The subroutine stack grows down for each call and grows up for each return. If the stack pointer is initialized to 2F Hex, then if there are more returns than calls, the stack pointer will point to addresses 30 and 31 (which are undefined RAM). Undefined RAM is read as all 1’s, thus, the program will return to address FFFF. This is a undefined ROM location and the instruction fetched will generate a software interrupt signalling an illegal condition. The device can detect the following illegal conditions: 1. Executing from undefined ROM 2. Over “POP”ing the stack by having more returns than calls. Illegal conditions may occur from coding errors, “brown out” voltage drops, static, supply noise, etc. When the software interrupt occurs, the user can re-initialize the stack pointer and do a recovery procedure before restarting (this recovery program is probably similar to RESET but might not clear the RAM). Examination of the stack can help in identifying the source of the error. For example, upon a software interrupt, 11 if the SP = 30, 31 it implies that the stack was over “POP”ed (with the SP=2F hex initially). If the SP contains a legal value (less than or equal to the initialized SP value), then the value in the PC gives a clue as to where in the user program an attempt to access an illegal (an address over 300 Hex) was made. The opcode returned in this case is 00 which is a software interrupt. The detection of illegal conditions is illustrated with an example: 0043 CLRA 0044 RC 0045 JMP 04FF 0046 NOP When the device is executing this program, it seemingly “locks-up” having executed a software interrupt. To debug this condition, the user takes a look at the SP and the contents of the stack. The SP has a legal value and the contents of the stack are 04FF. The perceptive user immediately realizes that an illegal ROM location (04FF) was accessed and the opcode returned (00) was a software interrupt. Another way to decode this is to run a trace and follow the sequence of steps that ended in a software interrupt. The damaging jump statement is changed. www.national.com COP912C Control Registers CNTRL REGISTER (ADDRESS X’00EE) The Timer and MICROWIRE control register contains the following bits: SL1 and SL0 Select the MICROWIRE clock divide-by IEDG MSEL TRUN TC1 TC2 TC3 7 TC1 TC2 TC3 TRUN MSEL IEDG SL1 Address 30 to 7F 80 to BF C0 to CF D0 D1 D2 D3 D4 D5 D6 D7 D8 to DB DC to DF E0 to EF E0 to E7 E8 E9 EA EB EC ED EE EF F0 to FF FC FD FE Contents Unused RAM Address Space (Reads as all ones) Expansion Space for On-Chip EERAM (Reads Undefined Data) Expansion Space for I/O and Registers Port L Data Register Port L Configuration Register Port L Input Pins (read only) Reserved for Port L Port G Data Register Port G Configuration Register Port G Input Pins (read only) Reserved Reserved Reserved On-Chip Functions and Registers Reserved for Future Parts Reserved MICROWIRE Shift Register Timer Lower Byte Timer Upper Byte Timer Autoreload Register Lower Byte Timer Autoreload Register Upper Byte CNTRL Control Register PSW Register On-Chip RAM Mapped as Registers (16 Bytes) X Register SP Register B Register (00 = 2, 01 = 4, 1x = 8) External interrupt edge polarity select Selects G5 and G4 as MICROWIRE signals SK and SO respectively Used to start and stop the timer/counter (1 = run, 0 = stop) Timer Mode Control Bit Timer Mode Control Bit Timer Mode Control Bit 0 SL0 PSW REGISTER (ADDRESS X’00EF) The PSW register contains the following select bits: GIE Global interrupt enable (enables interrupts) ENI External interrupt enable BUSY MICROWIRE busy shifting flag IPND External interrupt pending ENTI Timer interrupt enable TPND Timer interrupt pending (timer underflow or capture edge) C Carry Flip/flop HC Half carry Flip/flop 7 HC C TPND ENTI IPND BUSY ENI 0 GIE The Half-Carry bit is also effected by all the instructions that effect the Carry flag. The flag values depend upon the instruction. For example, after executing the ADC instruction the values of the Carry and the Half-Carry flag depend upon the operands involved. However, instructions like SET C and RESET C will set and clear both the carry flags. Table 5 lists out the instructions that effect the HC and the C flags. TABLE 5. Instructions Effecting HC and C Flags Instr. ADC SUBC SETC RESET C RRC HC Flag Depends on Operands Depends on Operands Set Set Depends on Operands C Flag Depends on Operands Depends on Operands Set Set Depends on Operands Reading other unused memory locations will return undefined data. Addressing Modes The device has ten addressing modes, six for operand addressing and four for transfer of control. OPERAND ADDRESSING MODES Register Indirect This is the “normal” addressing mode for the chip. The operand is the data memory addressed by the B or X pointer. Register Indirect With Auto Post Increment Or Decrement This addressing mode is used with the LD and X instructions. The operand is the data memory addressed by the B or X pointer. This is a register indirect mode that automatically post increments or post decrements the B or X pointer after executing the instruction. Direct The instruction contains an 8-bit address field that directly points to the data memory for the operand. Immediate The instruction contains an 8-bit immediate field as the operand. Short Immediate 12 MEMORY MAP All RAM, ports and registers (except A and PC) are mapped into data memory address space. TABLE 6. Memory Map Address 00 to 2F Contents On-chip RAM Bytes (48 Bytes) www.national.com COP912C Addressing Modes (Continued) Instruction Set REGISTER AND SYMBOL DEFINITIONS Registers A B X SP S PC PU PL C HC GIE 8-Bit Accumulator Register 8-Bit Address Register 8-Bit Address Register 8-Bit Stack Pointer Register 8-Bit Data Segment Address Register 15-Bit Program Counter Register Upper 7 Bits of PC Lower 8 Bits of PC 1-Bit of PSW Register for Carry 1-Bit of PSW Register for Half Carry 1-Bit of PSW Register for Global Interrupt Enable This addressing mode issued with the LD B,# instruction, where the immediate # is less than 16. The instruction contains a 4-bit immediate field as the operand. Indirect This addressing mode is used with the LAID instruction. The contents of the accumulator are used as a partial address (lower 8 bits of PC) for accessing a data operand from the program memory. TRANSFER OF CONTROL ADDRESSING MODES Relative This mode is used for the JP instruction with the instruction field being added to the program counter to produce the next instruction address. JP has a range from −31 to +32 to allow a one byte relative jump (JP + 1 is implemented by a NOP instruction). There are no “blocks” or “pages” when using JP since all 15 bits of the PC are used. Absolute This mode is used with the JMP and JSR instructions with the instruction field of 12 bits replacing the lower 12 bits of the program counter (PC). This allows jumping to any location in the current 4k program memory segment. Absolute Long This mode is used with the JMPL and JSRL instructions with the instruction field of 15 bits replacing the entire 15 bits of the program counter (PC). This allows jumping to any location in the entire 32k program memory space. Indirect This mode is used with the JID instruction. The contents of the accumulator are used as a partial address (lower 8 bits of PC) for accessing a location in the program memory. The contents of this program memory location serves as a partial address (lower 8 bits of PC) for the jump to the next instruction. Symbols [B] [X] MD Mem MemI Imm Reg Bit ← Memory Indirectly Addressed by B Register Memory Indirectly Addressed by X Register Direct Addressed Memory Direct Addressed Memory, or B Direct Addressed Memory, B, or Immediate Data 8-Bit Immediate Data Register Memory: Addresses F0 to FF (Includes B, X, and SP) Bit Number (0 to 7) Loaded with Exchanged with ↔ TABLE 7. Instruction Set Instr ADD ADC SUBC AND OR XOR IFEQ IFGT IFBNE DRSZ SBIT RBIT IFBIT X LD LD LD X X A, MemI A, MemI A, MemI A, MemI A, MemI A, MemI A, MemI A, MemI Add Add with Carry Subtract with Carry Logical AND Logical OR Logical Exclusive-OR IF Equal IF Greater than IF B not Equal Decrement Reg, Skip if Zero Set Bit Reset Bit If Bit Exchange A with Memory Load A with Memory Load Direct Memory Immed. Load Register Memory Immed. Exchange A with Memory [B] Exchange A with Memory [X] Function Register Operation A←A + MemI A← A + MemI + C, C← Carry A← A − MemI + C, C← Carry A←A and MemI A← A or MemI A←A xor MemI Compare A and MemI, Do Next if A = MemI Compare A and MemI, Do Next if A > MemI Do Next If Lower 4 Bits of B not = Imm Reg←Reg - 1, Skip if Reg Goes to Zero 1 to Mem.Bit (Bit = 0 to 7 Immediate) 0 to Mem.Bit (Bit = 0 to 7 Immediate) If Mem.Bit is True, Do Next Instruction A↔Mem A←MemI Mem← Imm Reg← Imm A↔[B] (B←B ± 1) A↔[X] (X←X ± 1) # Reg #, Mem #, Mem #, Mem A, Mem A, MemI Mem, Imm Reg, Imm A, [B ± ] A, [X ± ] 13 www.national.com COP912C Instruction Set Instr LD LD LD CLRA INC DEC LAID DCOR RRC SWAP SC RC IFC IFNC JMPL JMP JP JSRL JSR JID RET RETSK RETI INTR NOP Addr. Addr. Disp. Addr. Addr. A A A A A (Continued) TABLE 7. Instruction Set (Continued) Function Load A with Memory [B] Load A with Memory [X] Load Memory Immediate Clear A Increment A Decrement A Load A Indirect from ROM Decimal Correct A Rotate Right Through Carry Swap Nibbles of A Set C Reset C If C If Not C Jump Absolute Long Jump Absolute Jump Relative Short Jump Subroutine Long Jump Subroutine Jump Indirect Return from Subroutine Return and Skip Return from Interrupt Generate an Interrupt No Operation A, [B ± ] A, [X ± ] [B ± ], Imm Register Operation ← [B] (B← B ± 1) A A← [X] (X← X ± 1) [B]← Imm (B← B ± 1) A←0 A←A + 1 A←A − 1 A← ROM(PU, A) A← BCD Correction (follows ADC, SUBC) C→ A7 →… → A0 → C A7…A4↔A3…A0 C←1 C←0 If C is True, do Next Instruction If C is not True, do Next Instruction PC← ii (ii = 15 Bits, 0k to 32k) PC11…PC0← i (i = 12 Bits) PC15…PC12 Remain Unchanged PC← PC + r (r is −31 to +32, not 1) [SP]← PL, [SP−1]← PU, SP−2, PC← ii [SP]←PL, [SP−1]← PU, SP−2, PC11..PC0← ii PL← ROM(PU, A) SP+2, PL← [SP], PU← [SP−1] SP+2, PL← [SP], PU←[SP−1], Skip next Instr. SP+2, PL← [SP], PU← [SP−1], GIE←1 [SP]← PL, [SP−1]← PU, SP−2, PC←0FF PC←PC+1 • • • Most instructions are single byte (with immediate addressing mode instructions requiring two bytes). Most single byte instructions take one cycle time to execute. Instr IFGT IFBNE DRSZ SBIT RBIT IFBIT [B] 1/1 1/1 1/1 1/1 1/1 1/1 Direct 3/4 1/3 3/4 3/4 3/4 Immediate 2/2 2/2 Skipped instructions require x number of cycles to be skipped, where x equals the number of bytes in the skipped instruction opcode. The following tables show the number of bytes and cycles for each instruction in the format byte/cycle. Arithmetic and Logic Instructions (Bytes/Cycles) Instr ADD ADC SUBC AND OR XOR IFEQ IFNE [B] 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 Direct 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 2/2 2/2 2/2 2/2 2/2 2/2 2/2 Immediate Instructions Using A and C (Bytes/Cycles) Instr CLRA INCA DECA LAID DCOR RRCA SWAPA SC RC Bytes/Cycles 1/1 1/1 1/1 1/3 1/1 1/1 1/1 1/1 1/1 www.national.com 14 COP912C Instruction Set Instr IFC IFNC (Continued) JP JSRL JSR JID RET RETSK RETI Bytes/Cycles 3/4 2/3 INTR NOP Instr Bytes/Cycles 1/3 3/5 2/5 1/3 1/5 1/5 1/5 1/7 1/1 Instructions Using A and C (Bytes/Cycles) (Continued) Bytes/Cycles 1/1 1/1 Transfer of Control Instructions (Bytes/Cycles) Instr JMPL JMP Memory Transfer Instructions (Bytes/Cycles) Register Indirect [B] X A, a Register Indirect Direct 2/3 2/3 Immed. 1/2 1/2 2/2 1/1 3/3 2/3 b Instr Auto Incr and Decr [B+, B−] [X+, X−] [X] 1/1 1/1 1/3 1/3 2/2 LD A,* LD B,Imm LD B,Imm LD Mem,Imm LD Reg,Imm 1/3 1/3 2/2 2/3c a. Memory location addressed by B or X directly b. IF B < 16 c. IF B > 15 15 www.national.com COP912C DRSZ 0FB DRSZ 0FC LD Md,#i DIR LD A,(X) * * LD A,(B) LD B,#i * JSRL LD A,Md JMPL X A,Md * RETSK RET RETI DRSZ 0FD DRSZ 0FE DRSZ 0FF LD LD LD A,(X−) A,(B−) (B−),#i SBIT 3,(B) SBIT 4,(B) SBIT 5,(B) SBIT 6,(B) SBIT 7,(B) RBIT 3,(B) RBIT 4,(B) RBIT 5,(B) RBIT 6,(B) RBIT 7,(B) JSR JMP JP+28 JP+12 B 0B00–0BFF 0B00–0BFF LD B, 3 IFBNE 0C LD B, 2 IFBNE 0D LD B, 1 IFBNE 0E LD B, 0 IFBNE 0F JSR JMP JP+29 JP+13 C 0C00–0CFF 0C00–0CFF JSR JMP JP+30 JP+14 D 0D00–0DFF 0D00–0DFF JSR JMP JP+31 JP+15 E 0E00–0EFF 0E00–0EFF JSR JMP JP+32 JP+16 F 0F00–0FFF 0F00–0FFF JP−3 JP−19 LD 0FC, #i JP−2 JP−18 LD 0FD, #i JP−1 JP−17 LD 0FE, #i JP−0 JP−16 LD 0FF, #i LOWER NIBBLE BITS 3–0 www.national.com UPPER NIBBLE BITS 7–4 C DRSZ 0F0 DRSZ 0F1 DRSZ 0F2 IFBIT A, (B) IFBIT 3,(B) IFBIT 4,(B) IFBIT SWAPA 5,(B) IFBIT DCORA LD B, 9 6,(B) IFBIT 7,(B) SBIT 0,(B) SBIT 1,(B) SBIT 2,(B) RBIT 2,(B) RBIT 1,(B) RBIT 0,(B) LD B, 7 LD B, 6 * LD B, 8 IFBNE 7 IFBNE 8 IFBNE 9 LD B, 5 IFBNE 0A LD B, 4 IFBNE 0B IFBNE 6 LD B, 0A IFBNE 5 CLRA LD B, 0B IFBNE 4 * LD B, 0C IFBNE 3 * LD B, 0D IFBNE 2 DRSZ 0F3 DRSZ 0F4 DRSZ 0F5 DRSZ 0F6 DRSZ 0F7 DRSZ 0F8 DRSZ 0F9 * LD LD LD A,(X+) A,(B+) (B+),#i DECA INCA * * IFNC DRSZ 0FA NOP * LD A,#i IFC * * OR A,#i OR A,(B) X A,(X) X A,(B) XOR A,#i XOR A,(B) * JID AND A,#i AND A,(B) * LAID ADD A,#i ADD A,(B) XA, (X−) XA, (B−) IFGT A,#i IFGT A,(B) XA, (X+) XA, (X+) IFEQA, #i IFEQ, #i * SC SUBCA, SUBCA, IFBIT #i (B) 1, (B) * LD B, 0E IFBNE 1 RRCA RC ADCA, 3I ADCA, (B) IFBIT 0, (B) * LD B, 0F IFBNE 0 B A 9 8 7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 JSR JMP JP+24 JP+8 0700–07FF 0700–07FF JSR JMP JP+25 JP+9 0800–08FF 0800–08FF 7 8 JSR JMP JP+26 JP+10 9 0900–09FF 0900–09FF JSR JMP JP+27 JP+11 A 0A00–0AFF 0A00–0AFF JSR JMP JP+17 INTR 0000–00FF 0000–00FF JSR JMP JP+18 JP+2 0100–01FF 0100–01FF JSR JMP JP+19 JP+3 0200–02FF 0200–02FF JSR JMP JP+20 JP+4 0300–03FF 0300–03FF JSR JMP JP+21 JP+5 0400–04FF 0400–04FF JSR JMP JP+22 JP+6 0500–05FF 0500–05FF JSR JMP JP+23 JP+7 0600–06FF 0600–06FF F E D Instruction Set JP−15 JP−31 LD 0F0, #i JP−14 JP−30 LD 0F1, #i (Continued) JP−13 JP−29 LD 0F2, #i JP−12 JP−28 LD 0F3, #i JP−11 JP−27 LD 0F4, #i JP−10 JP−26 LD 0F5, #i JP−9 JP−25 LD 0F6, #i JP−8 JP−24 LD 0F7, #i 16 JP−7 JP−23 LD 0F8, #i JP−6 JP−22 LD 0F9, #i JP−5 JP−21 LD 0FA, #i JP−4 JP−20 LD 0FB, #i COP912C Option List The mask programmable options are listed out below. The options are programmed at the same time as the ROM pattern to provide the user with hardware flexibility to use a variety of oscillator configuration. OPTION 1: = 1 Crystal =2 = 3 R/C CKI INPUT (CKI/10) CKO for crystal configuration NA (CKI/10) CKO available as G7 input OPTION 2: BONDING = 1 NA = 2 NA = 3 20 pin DIP package = 4 20 pin SO package = 5 NA The following option information is to be sent to National along with the EPROM. Option Data Option 1 Value__is: CKI Input Option 2 Value__is: COP Bonding COP8 Starter Kits and Hardware Target Solutions • COP8-EVAL-xxx: A variety of Multifunction Evaluation, Design Test, and Target Boards for COP8 Families. Realtime target design environments with a selection of peripherals and features including multi I/O, LCD display, keyboard, A/D, D/A, EEPROM, USART, LEDs, and bread-board area. Quickly design, test, and implement a custom target system (some target boards are standalone, and ready for mounting into a standard enclosure), or just evaluate and test your code. Includes COP8NSDEV with IDE and Assembler, software routines, reference designs, and source code (no p/s). COP8 Software Development Languages and Integrated Environments • COP8-NSDEV: National’s COP8 Software Development package for Windows on CD. A fully Integrated Development Environment for COP8. Includes a fully licensed WCOP8 IDE, COP8-NSASM. Plus Manuals, Applications Software, and other COP8 technical information. COP8C: ByteCraft - C Cross-Compiler and Code Development System. Includes BCLIDE (Integrated Development Environment) for Win32, editor, optimizing C CrossCompiler, macro cross assembler, BC-Linker, and MetaLinktools support. (DOS/SUN versions available; Compiler is linkable under WCOP8 IDE; Compatible with DriveWay COP8) • COP8 Tools Overview National is engaged with an international community of independent 3rd party vendors who provide hardware and software development tool support. Through National’s interaction and guidance, these tools cooperate to form a choice of tools that fits each developer’s needs. This section provides a summary of the tool and development kits currently available. Up-to-date information, selection guides, free tools, demos, updates, and purchase information can be obtained at our web site at: www.national.com/cop8. SUMMARY OF TOOLS COP8 Evaluation Software and Reference Designs EWCOP8, EWCOP8-M, EWCOP8-BL: IAR - ANSI C-Compiler and Embedded Workbench. (M version includes MetaLink debugger support) (BL version: 4k code limit; no FP). A fully integrated Win32 IDE, ANSI C-Compiler, macro assembler, editor, linker, librarian, and C-Spy high-level simulator/debugger. COP8 Development Productivity Tools • • DriveWay-COP8: Aisys Corporation - COP8 Peripherals Code Generation tool. Automatically generates tested and documented C or Assembly source code modules containing I/O drivers and interrupt handlers for each onchip peripheral. Application specific code can be inserted for customization using the integrated editor. (Compatible with COP8-NSASM, COP8C, and WCOP8 IDE.) COP8-UTILS: COP8 assembly code examples, device drivers, and utilities to speed up code development. (Included with COP8-NSDEV and COP8-NSEVAL.) • COP8–NSEVAL: Software Evaluation package for Windows. A fully integrated evaluation environment for COP8. Includes WCOP8 IDE evaluation version (Integrated Development Environment), COP8-NSASM (Full COP8 Assembler), COP8-MLSIM (COP8 Instruction Level Simulator), COP8C Compiler Demo, DriveWay™ COP8 Device-Driver-Builder Demo, Manuals, Applications Software, and other COP8 technical information. COP8–REF-xx: Reference Designs for COP8 Families. Realtime hardware environment with a variety of functions for demonstrating the various capabilities and features of specific COP8 device families. Run Win 95 demo reference software and exercise specific device capabilities. Includes PCB with pre-programmed COP8, 9v battery for stand-alone operation, assembly listing, full applications source code, BOM, and schematics. (Add COP8-NSEVAL and an OTP programmer to implement your own software ideas in Assembly Code.) • • WCOP8 IDE: KKD - COP8 IDE (Integrated Development Environment). Supports COP8C, COP8-NSASM, COP8MLSIM, DriveWay COP8, and MetaLink debugger under a common Windows Project Management environment. Code development, debug, and emulation tools can be launched from a single project window framework. (Included in COP8-NSDEV and COP8-NSEVAL.) COP8 Hardware Debug Tools • • COP8xx-DM: Metalink COP8 Debug Module for nonflash COP8 Families. Windows based development and real-time in-circuit emulation tool, with 100 frame trace, 32k s/w breaks, Enhanced User Interface, MetaLinkDebugger, and COP8 OTP Programmer with sockets. Includes COP8-NSDEV, power supply, DIP and/or SMD emulation cables and adapters. 17 www.national.com COP912C COP8 Tools Overview • (Continued) • IM-COP8: MetaLink iceMASTER ® for non-flash COP8 devices. Windows based, full featured real-time in-circuit emulator, with 4k trace, 32k s/w breaks, and MetaLinkWindows Debugger. Includes COP8-NSDEV and power supply. Package-specific probes and surface mount adaptors are ordered separately. (Add COP8-PM and adapters for OTP programming.) COP8 Development and OTP Programming Tools Development: Metalink’s Debug Module includes development device programming capability for COP8 devices. Many other third-party programmers are approved for development and engineering use. Production: Third-party programmers and automatic handling equipment cover needs from engineering prototype and pilot production, to full production environments. Factory Programming: Factory programming available for high-volume requirements. • • • COP8-PM: COP8 Development Programming Module. Windows programming tool for COP8 OTP Families. Includes 40 DIP programming socket, control software, RS232 cable, and power supply. (SMD and 87Lxx programming adapters are extra.) WHERE TO GET TOOLS Tools are ordered directly from the following vendors. Please go to the vendor’s web site for current listings of distributors. Vendor Aisys Home Office U.S.A.: Santa Clara, CA 1-408-327-8820 fax: 1-408-327-8830 Byte Craft U.S.A. 1-519-888-6911 fax: 1-519-746-6751 IAR Sweden: Uppsala +46 18 16 78 00 fax: +46 18 16 78 38 www.iar.se info@iar.se info@iar.com info@iarsys.co.uk info@iar.de U.S.A.: San Francisco 1-415-765-5500 fax: 1-415-765-5503 U.K.: London +44 171 924 33 34 fax: +44 171 924 53 41 Germany: Munich +49 89 470 6022 fax: +49 89 470 956 ICU Sweden: Polygonvaegen +46 8 630 11 20 fax: +46 8 630 11 70 KKD MetaLink Denmark: U.S.A.: Chandler, AZ 1-800-638-2423 fax: 1-602-926-1198 www.icu.se support@icu.se support@icu.ch www.kkd.dk www.metaice.com sales@metaice.com support@metaice.com bbs: 1-602-962-0013 www.metalink.de National U.S.A.: Santa Clara, CA 1-800-272-9959 fax: 1-800-737-7018 www.national.com/cop8 support@nsc.com europe.support@nsc.com Germany: Kirchseeon 80-91-5696-0 fax: 80-91-2386 islanger@metalink.de Distributors Worldwide Europe: +49 (0) 180 530 8585 fax: +49 (0) 180 530 8586 Distributors Worldwide Switzeland: Hoehe +41 34 497 28 20 fax: +41 34 497 28 21 www.bytecraft.com info@bytecraft.com Distributors Electronic Sites www.aisysinc.com info @aisysinc.com Other Main Offices Distributors The following companies have approved COP8 programmers in a variety of configurations. Contact your local office or distributor. You can link to their web sites and get the latest listing of approved programmers from National’s COP8 OTP Support page at: www.national.com/cop8. Advantech; Dataman; EE tools; Minato; BP Microsystems; Data I/O; Hi-Lo Systems; ICE Technology; Lloyd Research; Logical Devices; MQP; Needhams; Phyton; SMS; Stag Programmers; System General; Tribal Microsystems; Xeltek. CUSTOMER SUPPORT Complete product information and technical support is available from National’s customer response centers, and from our on-line COP8 customer support sites. www.national.com 18 COP912C Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Molded Small Outline Package (M) Order Number COP912C-XXX/WM, COP912CH-XXX/WM NS Package Number M20B 20-Lead Molded Dual-In-Line Package (N) Order Number COP912C-XXX/N, COP912CH-XXX/N NS Package Number N20A 19 www.national.com COP912C 8-Bit Microcontroller Notes LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com www.national.com National Semiconductor Europe Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: ap.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.