CP3CN23

CP3CN23 Connectivity Processor with Bluetooth and Dual CAN Interfaces FINAL JULY 2004 CP3CN23 Reprogrammable Connectivity Processor with Dual CAN Interfaces 1.0 General Description trade-off between battery size and operating time for handheld and portable applications. In addition to providing the features needed for the next generation of embedded products, the CP3CN23 is backed up by the software resources designers need for rapid time-tomarket, including an operating system, peripheral drivers, reference designs, and an integrated development environment. National Semiconductor offers a complete and industryproven application development environment for CP3CN23 applications, including the IAR Embedded Workbench, iSYSTEM winIDEA and iC3000 Active Emulator, and Application Software. The CP3CN23 connectivity processor combines high performance with the massive integration needed for embedded applications. A powerful RISC core with on-chip SRAM and Flash memory provides high computing bandwidth, hardware communications peripherals provide high-I/O bandwidth, and an external bus provides system expandability. On-chip communications peripherals include: dual CAN controllers, Microwire/Plus, SPI, ACCESS.bus, quad UART, 12-bit A/D converter, and Advanced Audio Interface (AAI). Additional on-chip peripherals include Random Number Generator (RNG), DMA controller, CVSD/PCM conversion module, Timing and Watchdog Unit, Versatile Timer Unit, Multi-Function Timer, and Multi-Input Wake-Up (MIWU) unit. Hand-held devices can be both smaller and lower in cost for maximum consumer appeal. The low voltage and advanced power-saving modes achieve new design points in the Block Diagram Clock Generator 12 MHz and 32 kHz Oscillator PLL and Clock Generator Power-on-Reset CR16C CPU Core 256K Bytes Flash Program Memory 8K Bytes Flash Data 32K Bytes Static RAM Dual CAN 2.0B Controller Serial Debug Interface CPU Core Bus Bus Interface Unit DMA Controller Peripheral Bus Controller Interrupt Control Unit CVSD/PCM Converter Power Management Timing and Watchdog Unit Random Number Generator Peripheral Bus GPIO Audio Interface Microwiire/ SPI Quad UART ACCESS .bus Versatile Timer Unit Muti-Function Timer Multi-Input Wake-Up 8-Channel 12-bit ADC DS310 TRI-STATE is a registered trademark of National Semiconductor Corporation. ©2004 National Semiconductor Corporation www.national.com CP3CN23 Table of Contents 1.0 2.0 3.0 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 3.20 3.21 3.22 CR16C CPU Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input/Output Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Interface Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Control Unit (ICU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multi-Input Wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CAN Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quad UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Advanced Audio interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CVSD/PCM Conversion Module. . . . . . . . . . . . . . . . . . . . . . . . . . . 12-bit Analog to Digital Converter. . . . . . . . . . . . . . . . . . . . . . . . . . Random Number Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Microwire/SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ACCESS.bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multi-Function Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing and Watchdog Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . Versatile Timer Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Triple Clock and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Debug Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Development Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 4 4 4 4 5 5 5 5 5 5 6 6 6 6 6 6 6 7 7 7 17.0 CAN Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 17.1 17.2 17.3 17.4 17.5 17.6 17.7 17.8 17.9 17.10 17.11 17.12 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Basic CAN Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Message Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Acceptance Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Receive Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Transmit Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Time Stamp Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 CAN Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 System Start-Up and Multi-Input Wake-Up. . . . . . . . . . . . . . . . . 113 Usage Hint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Audio Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Audio Interface Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bit Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Frame Clock Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Audio Interface Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Communication Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Audio Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCM Conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CVSD Conversion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCM to CVSD Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CVSD to PCM Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DMA Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Freeze. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CVSD/PCM Converter Registers . . . . . . . . . . . . . . . . . . . . . . . . Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Baud Rate Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Microwire Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Microwire Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . ACB Protocol Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ACB Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . ACCESS.bus Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . Usage Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TWM Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer T0 Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watchdog Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TWM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watchdog Programming Procedure . . . . . . . . . . . . . . . . . . . . . . Timer Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer I/O Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 116 119 119 119 121 124 131 131 132 132 132 132 132 133 133 136 136 141 145 148 150 151 151 152 154 156 158 162 165 165 166 166 168 169 170 175 175 176 18.0 Advanced Audio Interface . . . . . . . . . . . . . . . . . . . . 116 18.1 18.2 18.3 18.4 18.5 18.6 18.7 19.0 CVSD/PCM Conversion Module . . . . . . . . . . . . . . . 131 19.1 19.2 19.3 19.4 19.5 19.6 19.7 19.8 19.9 4.0 5.0 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 CPU Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1 5.2 5.3 5.4 5.5 5.6 5.7 General-Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dedicated Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . Processor Status Register (PSR) . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Register (CFG). . . . . . . . . . . . . . . . . . . . . . . . . . . . Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stacks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Environment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Interface Unit (BIU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BIU Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait and Hold States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 15 16 17 18 19 19 24 25 25 25 28 20.0 UART Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 20.1 20.2 20.3 20.4 6.0 Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.1 6.2 6.3 6.4 6.5 21.0 Microwire/SPI Interface . . . . . . . . . . . . . . . . . . . . . . 148 21.1 21.2 21.3 21.4 21.5 7.0 System Configuration Registers . . . . . . . . . . . . . . . 29 7.1 7.2 7.3 Module Configuration Register (MCFG) . . . . . . . . . . . . . . . . . . . . 29 Module Status Register (MSTAT). . . . . . . . . . . . . . . . . . . . . . . . . 30 Software Reset Register (SWRESET) . . . . . . . . . . . . . . . . . . . . . 30 Flash Memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Memory Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Information Block Words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Memory Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . Channel Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transfer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Software DMA Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DMA Controller Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . Non-Maskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maskable Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nested Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Crystal Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Main Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slow Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Auxiliary Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock and Reset Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Active Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Save Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High-Frequency Oscillator and PLL Control . . . . . . . . . . . . . . . . . Power Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . Switching Between Power Modes . . . . . . . . . . . . . . . . . . . . . . . . 31 31 32 34 35 41 41 42 43 43 43 47 47 47 50 50 52 53 53 53 54 54 54 54 54 56 56 57 57 57 57 59 22.0 ACCESS.bus Interface . . . . . . . . . . . . . . . . . . . . . . . 154 22.1 22.2 22.3 22.4 8.0 Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.1 8.2 8.3 8.4 8.5 23.0 Timing and Watchdog Module . . . . . . . . . . . . . . . . 165 23.1 23.2 23.3 23.4 23.5 9.0 DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.1 9.2 9.3 9.4 9.5 9.6 24.0 Multi-Function Timer . . . . . . . . . . . . . . . . . . . . . . . . 169 24.1 24.2 24.3 24.4 24.5 10.0 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.1 10.2 10.3 10.4 10.5 25.0 26.0 27.0 28.0 Versatile Timer Unit (VTU) . . . . . . . . . . . . . . . . . . . . 179 25.1 25.2 VTU Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 VTU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 11.0 Triple Clock and Reset . . . . . . . . . . . . . . . . . . . . . . . 51 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 11.9 Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Register Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . 202 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . 212 28.1 28.2 28.3 28.4 28.5 28.6 28.7 28.8 28.9 28.10 28.11 28.12 28.13 28.14 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Memory On-Chip Programming . . . . . . . . . . . . . . . . . . . . Output Signal Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock and Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Advanced Audio Interface (AAI) Timing . . . . . . . . . . . . . . . . . . . Microwire/SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ACCESS.bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multi-Function Timer (MFT) Timing . . . . . . . . . . . . . . . . . . . . . . Versatile Timing Unit (VTU) Timing . . . . . . . . . . . . . . . . . . . . . . External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 212 213 214 215 215 217 218 219 221 226 229 230 231 12.0 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . 56 12.1 12.2 12.3 12.4 12.5 12.6 12.7 29.0 30.0 31.0 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 29.1 29.2 LQFP-128 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 LQFP-144 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 13.0 14.0 15.0 Multi-Input Wake-Up . . . . . . . . . . . . . . . . . . . . . . . . . 61 13.1 13.2 14.1 14.2 15.1 15.2 15.3 15.4 15.5 Multi-Input Wake-Up Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Programming Procedures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Port Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Open-Drain Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Touchscreen Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Operation in Power-Saving Modes . . . . . . . . . . . . . . . . . . . Freeze . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 73 75 75 75 Input/Output Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . 67 12-Bit Analog to Digital Converter . . . . . . . . . . . . . . 71 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 245 16.0 Random Number Generator (RNG) . . . . . . . . . . . . . 80 16.1 16.2 Freeze . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Random Number Generator Register Set . . . . . . . . . . . . . . . . . . 81 www.national.com 2 CP3CN23 2.0 Features Extensive Power and Clock Management Support On-chip Phase Locked Loop Support for multiple clock options Dual clock and reset Power-down modes CPU Features Fully static RISC processor core, capable of operating from 0 to 24 MHz with zero wait/hold states Minimum 41.7 ns instruction cycle time with a 24-MHz internal clock frequency, based on a 12-MHz external input Flexible I/O 47 independently vectored peripheral interrupts Up to 56 general-purpose I/O pins (shared with on-chip peripheral I/O) On-Chip Memory Programmable I/O pin characteristics: TRI-STATE out256K bytes reprogrammable Flash program memory put, push-pull output, weak pull-up input, high-imped8K bytes Flash data memory ance input 32K bytes of static RAM data memory Schmitt triggers on general-purpose inputs Addresses up to 12M bytes of external memory Multi-Input Wake-Up (MIWU) capability Broad Range of Hardware Communications Peripherals Power Supply ACCESS.bus serial bus (compatible with Philips I2C bus) I/O port operation at 2.5V to 3.3V Dual CAN interface with 15 message buffers conforming Core logic operation at 2.5V to CAN specification 2.0B active On-chip power-on reset 8/16-bit SPI, Microwire/Plus serial interface Four-channel Universal Asynchronous Receiver/Trans- Temperature Range mitter (UART), one channel has USART capability -40°C to +85°C (Industrial) Advanced Audio Interface (AAI) to connect to external 8/ Packages 13-bit PCM Codecs as well as to ISDN-Controllers LQFP-128, LQFP-144 through the IOM-2 interface (slave only) CVSD/PCM converter supporting one bidirectional audio Complete Development Environment connection Pre-integrated hardware and software support for rapid General-Purpose Hardware Peripherals prototyping and production Integrated environment 12-bit A/D Converter (ADC) Project manager Dual 16-bit Multi-Function Timer (MFT) Multi-file C source editor Versatile Timer Unit with four subsystems (VTU) High-level C source debugger Four-channel DMA controller Comprehensive, integrated, one-stop technical support Timing and Watchdog Unit Random Number Generator peripheral CP3CN23 Connectivity Processor Selection Guide NSID CP3CN23G18NEP CP3CN23G18NEPNOPB CP3CN23G18NEPX CP3CN23G18NEPXNOPB CP3CN23Y98NEP CP3CN23Y98NEPNOPB CP3CN23Y98NEPX CP3CN23Y98NEPXNOPB Speed Temp. Range (MHz) 24 24 24 24 24 24 24 24 -40° to +85°C -40° to +85°C -40° to +85°C -40° to +85°C -40° to +85°C -40° to +85°C -40° to +85°C -40° to +85°C Program Flash (Kbytes) 256 256 256 256 256 256 256 256 Data Flash (Kbytes) 8 8 8 8 8 8 8 8 SRAM (Kbytes) 32 32 32 32 32 32 32 32 External Address Lines 0 0 0 0 23 23 23 23 I/Os 56 56 56 56 50 50 50 50 Package Type LQFP-128 LQFP-128 LQFP-128 LQFP-128 LQFP-144 LQFP-144 LQFP-144 LQFP-144 NEP - Erased part (serial number in Information Block 1); X - Tape and reel; NOPB - No lead solder 3 www.national.com CP3CN23 3.0 Device Overview 3.3 INPUT/OUTPUT PORTS The device has up to 50 software-configurable I/O pins, organized into seven ports called Port B, Port C, Port E, Port G, Port H, Port I, and Port J. Each pin can be configured to operate as a general-purpose input or general-purpose output. In addition, many I/O pins can be configured to operate as inputs or outputs for on-chip peripheral modules such as the UART, timers, or Microwire/SPI interface. The I/O pin characteristics are fully programmable. Each pin can be configured to operate as a TRI-STATE output, pushpull output, weak pull-up input, or high-impedance input. The CP3CN23 connectivity processor is a complete microcomputer with all system timing, interrupt logic, program memory, data memory, and I/O ports included on-chip, making it well-suited to a wide range of embedded applications. The block diagram on page 1 shows the major on-chip components of the CP3CN23 devices. 3.1 CR16C CPU CORE The CP3CN23 device implements the CR16C CPU core module. The high performance of the CPU core results from the implementation of a pipelined architecture with a twobytes-per-cycle pipelined system bus. As a result, the CPU can support a peak execution rate of one instruction per clock cycle. For more information, please refer to the CR16C Programmer’s Reference Manual (document number 424521772101, which may be downloaded from National’s web site at http://www.national.com). 3.4 BUS INTERFACE UNIT The Bus Interface Unit (BIU) controls access to internal/external memory and I/O. It determines the configured parameters for bus access (such as the number of wait states for memory access) and issues the appropriate bus signals for each requested access. The BIU uses a set of control registers to determine how many wait states and hold states are used when accessing Flash program memory and the I/O area. At start-up, the configuration registers are set for slowest possible memory access. To achieve fastest possible program execution, appropriate values must be programmed. These settings vary with the clock frequency and the type of off-chip device being accessed. 3.2 MEMORY The CP3CN23 devices support a uniform linear address space of up to 16 megabytes. Three types of on-chip memory occupy specific regions within this address space, along with any external memory: 256K bytes of Flash program memory 8K bytes of Flash data memory 32K bytes of static RAM Up to 12M bytes of external memory (144-pin devices) The 256K bytes of Flash program memory are used to store the application program and real-time operating system. The Flash memory has security features to prevent unintentional programming and to prevent unauthorized access to the program code. This memory can be programmed with an external programming unit or with the device installed in the application system (in-system programming). 3.5 INTERRUPT CONTROL UNIT (ICU) The ICU receives interrupt requests from internal and external sources and generates interrupts to the CPU. An interrupt is an event that temporarily stops the normal flow of program execution and causes a separate interrupt handler to be executed. After the interrupt is serviced, CPU execution continues with the next instruction in the program following the point of interruption. The 8K bytes of Flash data memory are used for non-vola- Interrupts from the timers, UARTs, Microwire/SPI interface, tile storage of data entered by the end-user, such as config- and Multi-Input Wake-Up, are all maskable interrupts; they uration settings. can be enabled or disabled by software. There are 47 The 32K bytes of static RAM are used for temporary storage maskable interrupts, assigned to 47 linear priority levels. of data and for the program stack and interrupt stack. Read and write operations can be byte-wide or word-wide, depending on the instruction executed by the CPU. The highest-priority interrupt is the Non-Maskable Interrupt (NMI), which is generated by a signal received on the NMI input pin. Up to 12M bytes of external memory can be added on an 3.6 MULTI-INPUT WAKE-UP external bus. The external bus is only available on devices The two Multi-Input Wake-Up (MIWU) modules can be used in 144-pin packages. for two purposes: to provide inputs for waking up (exiting) For Flash program and data memory, the device internally from the Halt, Idle, or Power Save mode, and to provide gengenerates the necessary voltages for programming. No ad- eral-purpose edge-triggered maskable interrupts to the levditional power supply is required. el-sensitive interrupt control unit (ICU) inputs. Each 16channel module generates four programmable interrupts to the ICU, for a total of 8 ICU inputs generated from 32 MIWU inputs. Channels can be individually enabled or disabled, and programmed to respond to positive or negative edges. www.national.com 4 CP3CN23 3.7 CAN INTERFACE 3.11 Two CAN modules provide Full CAN 2.0B class, CAN serial bus interface for applications that require a high-speed (up to 1 Mbits per second) or a low-speed interface with CAN bus master capability. The data transfer between CAN and the CPU is established by 15 memory-mapped message buffers, which can be individually configured as receive or transmit buffers. An incoming message is filtered by two masks, one for the first 14 message buffers and another one for the 15th message buffer to provide a basic CAN path. A priority decoder allows any buffer to have the highest or lowest transmit priority. Remote transmission requests can be processed automatically by automatic reconfiguration to a receiver after transmission or by automated transmit scheduling upon reception. In addition, a time stamp counter (16bits wide) is provided to support real-time applications. The CAN modules are fast core bus peripherals, which allow single-cycle byte or word read/write access. A set of diagnostic features (such as loopback, listen only, and error identification) support the development with the CAN module and provide a sophisticated error management tool. The CAN receivers can trigger a wake-up condition out of the low-power modes through the Multi-Input Wake-Up module. 12-BIT ANALOG TO DIGITAL CONVERTER This device contains an 8-channel, multiplexed input, successive approximation, 12-bit Analog-to-Digital Converter. It supports both Single Ended and Differential modes of operation. The integrated 12-bit ADC provides the following features: 8-channel, multiplexed input 4 differential channels Single-ended and differential external filtering capability 12-bit resolution; 11-bit accuracy 15-microsecond conversion time Support for 4-wire touchscreen applications External start trigger Programmable start delay after start trigger Poll or interrupt on done The ADC is compatible with 4-wire resistive touchscreen applications and is intended to provide the resolution necessary to support handwriting recognition. Low-ohmic touchscreen drivers are provided internally on the ADC[3:0] pins. Pendown detection is also provided. The ADC provides several options for the voltage reference source. The positive reference can be ADVCC (internal), VREFP, ADC0, or ADC3. The negative reference can be ADVCC (internal), ADC1, or ADC2. 3.8 QUAD UART Four UART modules support a wide range of programmable Two specific analog channel selection modes are supportbaud rates and data formats, parity generation, and several ed. These are as follows: error detection schemes. The baud rate is generated onAllow any specific channel to be selected at one time. chip, under software control. One UART channel supports The A/D Converter performs the specific conversion rehardware flow control, DMA, and USART capability (synquested and stops. chronous mode). Allow any differential channel pair to be selected at one The UARTs offer a wake-up condition from the low-power time. The A/D Converter performs the specific differential modes using the Multi-Input Wake-Up module. conversion requested and stops. 3.9 ADVANCED AUDIO INTERFACE The audio interface provides a serial synchronous, full-duplex interface to CODECs and similar serial devices. Transmit and receive paths operate asynchronously with respect to each other. Each path uses three signals for communication: shift clock, frame synchronization, and data. In both Single-Ended and Differential modes, there is the capability to connect the analog multiplexer output and A/D converter input to external pins. This provides the ability to externally connect a common filter/signal conditioning circuit for the A/D Converter. 3.12 RANDOM NUMBER GENERATOR When the receiver and transmitter use separate shift clocks RNG peripheral for use in Trusted Computer Peripheral Apand frame sync signals, the interface operates in its asyn- plications (TCPA) to improve the authenticity, integrity, and chronous mode. Alternatively, the transmit and receive path privacy of Internet-based communication and commerce. can share the same shift clock and frame sync signals for synchronous mode operation. 3.10 CVSD/PCM CONVERSION MODULE The CVSD/PCM module performs conversion between CVSD data and PCM data, in which the CVSD encoding is as defined in the Bluetooth specification and the PCM data can be 8-bit µ-Law, 8-bit A-Law, or 13-bit to 16-bit Linear. 5 www.national.com CP3CN23 3.13 MICROWIRE/SPI 3.17 VERSATILE TIMER UNIT The Microwire/SPI (MWSPI) interface module supports synchronous serial communications with other devices that conform to Microwire or Serial Peripheral Interface (SPI) specifications. It supports 8-bit and 16-bit data transfers. The Versatile Timer Unit (VTU) module contains four independent timer subsystems, each operating in either dual 8bit PWM configuration, as a single 16-bit PWM timer, or a 16-bit counter with two input capture channels. Each of the The Microwire interface allows several devices to communi- four timer subsystems offer an 8-bit clock prescaler to accate over a single system consisting of four wires: serial in, commodate a wide range of frequencies. serial out, shift clock, and slave enable. At any given time, 3.18 TRIPLE CLOCK AND RESET the Microwire interface operates as the master or a slave. The Microwire interface supports the full set of slave select The Triple Clock and Reset module generates a high-speed main System Clock from an external crystal network. It also for multi-slave implementation. provides the main system reset signal and a power-on reset In master mode, the shift clock is generated on-chip under function. software control. In slave mode, a wake-up out of a lowpower mode may be triggered using the Multi-Input Wake- This module generates a slow System Clock (32.768 kHz) from an optional external crystal network. The Slow Clock is Up module. used for operating the device in a low-power mode. The 3.14 ACCESS.BUS INTERFACE 32.768 kHz external crystal network is optional, because The ACCESS.bus interface module (ACB) is a two-wire se- the low speed System Clock can be derived from the highrial interface compatible with the ACCESS.bus physical lay- speed clock by a prescaler. Also, two independent clocks dier. It is also compatible with Intel’s System Management vided down from the high speed clock are available on outBus (SMBus) and Philips’ I2C bus. The ACB module can be put pins. configured as a bus master or slave, and it can maintain bi- The Triple Clock and Reset module provides the clock sigdirectional communications with both multiple master and nals required for the operation of the various CP3CN23 onslave devices. chip modules. From external crystal networks, it generates The ACCESS.bus receiver can trigger a wake-up condition the Main Clock, which can be scaled up to 24 MHz from an out of the low-power modes through the Multi-Input Wake- external 12 MHz input clock, and a 32.768 kHz secondary System Clock. The 12 MHz external clock is primarily used Up module. as the reference frequency for the on-chip PLL. The clock 3.15 MULTI-FUNCTION TIMER for modules which require a fixed clock rate (e.g. the CVSD/ The Multi-Function Timer (MFT) module contains a pair of PCM transcoder) is also generated through prescalers from 16-bit timer/counter registers. Each timer/counter unit can the 12 MHz clock. The PLL may be used to drive the highspeed System Clock through a prescaler. Alternatively, the be configured to operate in any of the following modes: high speed System Clock can be derived directly from the — Processor-Independent Pulse Width Modulation 12 MHz Main Clock. (PWM) mode: Generates pulses of a specified width and duty cycle and provides a general-purpose timer/ In addition, this module generates the device reset by using reset input signals coming from an external reset and varicounter. — Dual Input Capture mode: Measures the elapsed time ous on-chip modules. between occurrences of external event and provides 3.19 POWER MANAGEMENT a general-purpose timer/counter. — Dual Independent Timer mode: Generates system The Power Management Module (PMM) improves the effitiming signals or counts occurrences of external ciency of the device by changing the operating mode and power consumption to match the required level of activity. events. — Single Input Capture and Single Timer mode: Provides one external event counter and one system timer. The device can operate in any of four power modes: — Active: The device operates at full speed using the high-frequency clock. All device functions are fully operational. — Power Save: The device operates at reduced speed using the Slow Clock. The CPU and some modules can continue to operate at this low speed. — Idle: The device is inactive except for the Power Management Module and Timing and Watchdog Module, which continue to operate using the Slow Clock. — Halt: The device is inactive but still retains its internal state (RAM and register contents). 3.16 TIMING AND WATCHDOG MODULE The Timing and Watchdog Module (TWM) contains a RealTime timer and a Watchdog unit. The Real-Time Clock Timing function can be used to generate periodic real-time based system interrupts. The timer output is one of 16 inputs to the Multi-Input Wake-Up module which can be used to exit from a power-saving mode. The Watchdog unit is designed to detect the application program getting stuck in an infinite loop resulting in loss of program control or “runaway” programs. When the watchdog triggers, it resets the device. The TWM is clocked by the low-speed System Clock. www.national.com 6 CP3CN23 3.20 DMA CONTROLLER 3.21 SERIAL DEBUG INTERFACE The Direct Memory Access Controller (DMAC) can speed up data transfer between memory and I/O devices or between two memories, relative to data transfers performed directly by the CPU. A method called cycle-stealing allows the CPU and the DMAC to share the CPU bus efficiently. The DMAC implements four independent DMA channels. DMA requests from a primary and a secondary source are recognized for each DMA channel, as well as a software DMA request issued directly by the CPU. Table 1 shows the DMA channel assignment on the CP3CN23 architecture. The following on-chip modules can assert a DMA request to the DMAC: • • • • CR16C (Software DMA request) USART Advanced Audio Interface CVSD/PCM Converter The Serial Debug Interface module (SDI module) provides a JTAG-based serial link to an external debugger, for example running on a PC. In addition, the SDI module integrates an on-chip debug module, which allows the user to set up to eight hardware breakpoints on instruction execution and data transfer. The SDI module can act as a CPU bus master to access all memory mapped resources, such as RAM and peripherals. Therefore it also allows for fast program code download into the on-chip Flash program memory using the JTAG interface. 3.22 DEVELOPMENT SUPPORT Table 1 shows how the four DMA channels are assigned to the modules listed above. Table 1 Channel DMA Channel Assignment Peripheral Reserved UART0 UART0 Unused AAI CVSD/PCM AAI CVSD/PCM Transaction Read/Write Read Write N/A Read Read Write Write In addition to providing the features needed for the next generation of embedded products, the CP3CN23 devices are backed up by the software resources designers need for rapid product development, including an operating system, peripheral drivers, reference designs, and an integrated development environment. National Semiconductor offers a complete and industryproven application development environment for CP3CN23 applications, including the IAR Embedded Workbench, iSYSTEM winIDEA and iC3000 Active Emulator, and Application Software. See your National Semiconductor sales representative for current information on availability and features of emulation equipment and evaluation boards. Primary/ Secondary Primary 0 Secondary Primary 1 Secondary Primary 2 Secondary Primary 3 Secondary The interface can handle data words of either 8- or 16-bit length and data frames can consist of up to four slots. In the normal mode of operation, the interface only transfers one word at a periodic rate. In the network mode, the interface transfers multiple words at a periodic rate. The periodic rate is also called a data frame and each word within one frame is called a slot. The beginning of each new data frame is marked by the frame sync signal. 7 www.national.com CP3CN23 4.0 Signal Descriptions X1CKI/BBCLK X1CKO X2CKI X2CKO 1 1 1 12 MHz Crystal or Ext. Clock 32.768 kHz Crystal PB[7:0] PC[7:0] 8 8 12 MHz Crystal GPIO or Ext. Clock 32.768 kHz Crystal 1 1 1 X1CKI/BBCLK X1CKO X2CKI X2CKO AVCC AGND ADVCC ADGND VCC GND IOVCC IOGND RESET TMS TDI TDO TCK RDY ENV0 ENV1 ENV2 PG7/TA Power Supply 1 6 6 15 14 AVCC AGND ADVCC ADGND VCC GND IOVCC IOGND RESET TMS TDI TDO TCK RDY ENV0 ENV1 ENV2 PG7/TA CP3CN23 (LQFP-128) PGO PG1 PG3 PG4 PG5 PE0/RXD0 PE1/TXD0 PE2/RTS PE3/CTS PE4/CKX/TB PH0/RXD1/WUI11 PH1/TXD1/WUI12 GPIO Power Supply 1 6 6 10 11 CP3CN23 (LQFP-144) PB[7:0] PC[7:0] A[22:0] SEL0 SEL1 SEL2 SELIO WR0 WR1 RD 8 8 23 External Bus Interface PGO PG1 PG3 PG4 PG5 PE0/RXD0 PE1/TXD0 PE2/RTS PE3/CTS PE4/CKX/TB PH0/RXD1/WUI11 PH1/TXD1/WUI12 GPIO Chip Reset Chip Reset JTAG I/F to Debugger/ Programmer JTAG I/F to Debugger/ Programmer UART0 UART0 Mode Selection UART0/MFT Mode Selection UART1/MIWU MFT UART2/MIWU UART0/MFT UART1/MIWU MFT ADC/ Touchscreen ACCESS.bus PH2/RXD1/WUI13 ADC0/TSX+ PH3/TXD1/WUI14 ADC1/TSY+ PH4/RXD1/WUI15 ADC2/TSXPH5/TXD1/WUI16 ADC3/TSYADC4/MUXOUT0 ADC5/MUXOUT1 PF0/MSK/TIO1 ADC6 PF1/MDIDO/TIO2 ADC7/ADCIN PF2/MDODO/TIO3 PJ7/ASYNC/ PF3/MWCS/TIO4 WUI9 VREFP PF4/SCK/TIO5 PF5/SFS/TIO6 PF6/STD/TIO7 SDA PF7/SRD/TIO8 SCL PE5/SRFS/NMI PH6/CAN0RX/ WUI17 PH7/CAN0TX PE6/CAN1RX PE7/CAN1TX PG2/SRCLK PJ0/WUI18 PJ1/WUI19 PJ2/WUI20 PJ3/WUI21 PJ4/WUI22 PJ5/WUI23 PJ6/WUI24 PG6/WUI10 UART3/MIWU ADC/ Touchscreen Microwire/ SPI/ VTU AAI/ VTU ACCESS.bus AAI/NMI AAI CAN0 bus PH2/RXD1/WUI13 ADC0/TSX+ PH3/TXD1/WUI14 ADC1/TSY+ PH4/RXD1/WUI15 ADC2/TSXPH5/TXD1/WUI16 ADC3/TSYADC4/MUXOUT0 ADC5/MUXOUT1 PF0/MSK/TIO1 ADC6 PF1/MDIDO/TIO2 ADC7/ADCIN PF2/MDODO/TIO3 PJ7/ASYNC/ PF3/MWCS/TIO4 WUI9 VREFP PF4/SCK/TIO5 PF5/SFS/TIO6 PF6/STD/TIO7 SDA PF7/SRD/TIO8 SCL PE5/SRFS/NMI PH6/CAN0RX/ WUI17 PH7/CAN0TX PE6/CAN1RX PE7/CAN1TX PG2/SRCLK PJ0/WUI18 PG6/WUI10 UART2/MIWU UART3/MIWU Microwire/ SPI/ VTU AAI/ VTU AAI/NMI AAI CAN0 bus MIWU CAN1 bus CAN1 bus MIWU DS307 Figure 1. CP3CN23 Device SIgnals Some pins may be enabled as general-purpose I/O-port pins or as alternate functions associated with specific peripherals or interfaces. These pins may be individually configured as port pins, even when the associated peripheral or interface is enabled. Table 2 describes the device signals for the LQFP-128 package. Table 3 describes the device signals for the LQFP-144 package. www.national.com 8 CP3CN23 Table 2 CP3CN23 LQFP-128 Signal Descriptions Name X1CKI X1CKO X2CKI X2CKO RESET ENV0 ENV1 ENV2 TMS TCK TDI TDO RDY VCC GND IOVCC IOGND AVCC AGND ADVCC ADGND SCL SDA ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 Pins 1 1 1 1 1 1 1 1 1 1 1 1 1 6 6 16 15 1 1 1 1 1 1 1 1 1 1 1 1 1 1 I/O Input Output Input Output Input I/O I/O I/O Input Input Input Output Output Input Input Input Input Input Input Input Input I/O I/O I/O I/O I/O I/O I/O I/O Input Input Primary Function 12 MHz Oscillator Input 12 MHz Oscillator Output 32 kHz Oscillator Input 32 kHz Oscillator Output Chip general reset Special mode select input with internal pull-up during reset Special mode select input with internal pull-up during reset Special mode select input with internal pull-up during reset JTAG Test Mode Select (with internal weak pull-up) JTAG Test Clock Input (with internal weak pull-up) JTAG Test Data Input (with internal weak pull-up) JTAG Test Data Output NEXUS Ready Output 2.5V Core Logic Power Supply Core Ground 2.5–3.3V I/O Power Supply I/O Ground PLL Analog Power Supply PLL Analog Ground ADC Analog Power Supply ADC Analog Ground ACCESS.bus Clock ACCESS.bus Serial Data ADC Input Channel 0 ADC Input Channel 1 ADC Input Channel 2 ADC Input Channel 3 ADC Input Channel 4 ADC Input Channel 5 ADC Input Channel 6 ADC Input Channel 7 Alternate Name BBCLK None None None None PLLCLK CPUCLK SLOWCLK None None None None None None None None None None None None None None None TSX+ TSY+ TSXTSYMUXOUT0 MUXOUT1 None ADCIN Alternate Function BB reference clock for the RF Interface None None None None PLL Clock Output CPU Clock Output Slow Clock Output None None None None None None None None None None None None None None None Touchscreen X+ contact Touchscreen Y+ contact Touchscreen X- contact Touchscreen Y- contact Analog Multiplexer Output 0 Analog Multiplexer Output 1 None ADC Input (in MUX mode) 9 www.national.com CP3CN23 Name VREFP PB[7:0] PC[7:0] PE0 PE1 PE2 PE3 PE4 Pins 1 8 8 1 1 1 1 1 I/O Input I/O I/O I/O I/O I/O I/O I/O Primary Function ADC Positive Voltage Reference Generic I/O Generic I/O Generic I/O Generic I/O Generic I/O Generic I/O Generic I/O Alternate Name None None None RXD0 TXD0 RTS CTS CKX TB SRFS None None None Alternate Function UART Channel 0 Receive Data Input UART Channel 0 Transmit Data Output UART Channel 0 Ready-To-Send Output UART Channel 0 Clear-To-Send Input UART Channel 0 Clock Input Multi Function Timer Port B AAI Receive Frame Sync Non-Maskable Interrupt Input UART Channel 0 Ready-To-Send Output UART Channel 0 Clear-To-Send Input SPI Shift Clock Versatile Timer Channel 1 SPI Master In Slave Out Versatile Timer Channel 2 SPI Master Out Slave In Versatile Timer Channel 3 SPI Slave Select Input Versatile Timer Channel 4 AAI Clock Versatile Timer Channel 5 AAI Frame Synchronization Versatile Timer Channel 6 AAI Transmit Data Output Versatile Timer Channel 7 AAI Receive Data Input Versatile Timer Channel 8 None None AAI Receive Clock None None None Multi-Input Wake-Up Channel 10 Multi Function Timer Port A PE5 PE6 PE7 PF0 1 1 1 1 I/O I/O I/O I/O Generic I/O NMI Generic I/O Generic I/O Generic I/O TIO1 MDIDO CAN1RX CAN1TX MSK PF1 1 I/O Generic I/O TIO2 MDODI PF2 1 I/O Generic I/O TIO3 MWCS PF3 1 I/O Generic I/O TIO4 SCK PF4 1 I/O Generic I/O TIO5 SFS PF5 1 I/O Generic I/O TIO6 STD PF6 1 I/O Generic I/O TIO7 SRD PF7 PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 1 1 1 1 1 1 1 1 1 I/O I/O I/O I/O I/O I/O I/O I/O I/O Generic I/O TIO8 Generic I/O Generic I/O Generic I/O Generic I/O Generic I/O Generic I/O Generic I/O Generic I/O 10 None None SRCLK None None None WUI10 TA www.national.com CP3CN23 Name Pins I/O Primary Function Alternate Name RXD1 Alternate Function UART Channel 1 Receive Data Input Multi-Input Wake-Up Channel 11 UART Channel 1 Transmit Data Output Multi-Input Wake-Up Channel 12 UART Channel 2 Receive Data Input Multi-Input Wake-Up Channel 13 UART Channel 2 Transmit Data Output Multi-Input Wake-Up Channel 14 UART Channel 3 Receive Data Input Multi-Input Wake-Up Channel 15 UART Channel 3 Transmit Data Output Multi-Input Wake-Up Channel 16 CAN Receive Input Multi-Input Wake-Up Channel 17 CAN Transmit Output Multi-Input Wake-Up Channel 18 Multi-Input Wake-Up Channel 19 Multi-Input Wake-Up Channel 20 Multi-Input Wake-Up Channel 21 Multi-Input Wake-Up Channel 22 Multi-Input Wake-Up Channel 23 Multi-Input Wake-Up Channel 24 Start convert signal to ADC Multi-Input Wake-Up Channel 9 PH0 1 I/O Generic I/O WUI11 TXD1 PH1 1 I/O Generic I/O WUI12 RXD2 PH2 1 I/O Generic I/O WUI13 TXD2 PH3 1 I/O Generic I/O WUI14 RXD3 PH4 1 I/O Generic I/O WUI15 TXD3 PH5 1 I/O Generic I/O WUI16 CAN0RX PH6 PH7 PJ0 PJ1 PJ2 PJ3 PJ4 PJ5 PJ6 PJ7 1 1 1 1 1 1 1 1 1 1 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Generic I/O WUI17 Generic I/O Generic I/O Generic I/O Generic I/O Generic I/O Generic I/O Generic I/O Generic I/O Generic I/O WUI9 CAN0TX WUI18 WUI19 WUI20 WUI21 WUI22 WUI23 WUI24 ASYNC 11 www.national.com CP3CN23 Table 3 CP3CN23 LQFP-144 Signal Descriptions Name X1CKI X1CKO X2CKI X2CKO RESET ENV0 ENV1 ENV2 TMS TCK TDI TDO RDY VCC GND IOVCC IOGND AVCC AGND ADVCC ADGND SCL SDA ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 Pins 1 1 1 1 1 1 1 1 1 1 1 1 1 6 6 10 11 1 1 1 1 1 1 1 1 1 1 1 1 1 1 I/O Input Output Input Output Input I/O I/O I/O Input Input Input Output Output Input Input Input Input Input Input Input Input I/O I/O I/O I/O I/O I/O I/O I/O Input Input Primary Function 12 MHz Oscillator Input 12 MHz Oscillator Output 32 kHz Oscillator Input 32 kHz Oscillator Output Chip general reset Special mode select input with internal pull-up during reset Special mode select input with internal pull-up during reset Special mode select input with internal pull-up during reset JTAG Test Mode Select (with internal weak pull-up) JTAG Test Clock Input (with internal weak pull-up) JTAG Test Data Input (with internal weak pull-up) JTAG Test Data Output NEXUS Ready Output 2.5V Core Logic Power Supply Core Ground 2.5–3.3V I/O Power Supply I/O Ground PLL Analog Power Supply PLL Analog Ground ADC Analog Power Supply ADC Analog Ground ACCESS.bus Clock ACCESS.bus Serial Data ADC Input Channel 0 ADC Input Channel 1 ADC Input Channel 2 ADC Input Channel 3 ADC Input Channel 4 ADC Input Channel 5 ADC Input Channel 6 ADC Input Channel 7 Alternate Name BBCLK None None None None PLLCLK CPUCLK SLOWCLK None None None None None None None None None None None None None None None TSX+ TSY+ TSXTSYMUXOUT0 MUXOUT1 None ADCIN Alternate Function BB reference clock for the RF Interface None None None None PLL Clock Output CPU Clock Output Slow Clock Output None None None None None None None None None None None None None None None Touchscreen X+ contact Touchscreen Y+ contact Touchscreen X- contact Touchscreen Y- contact Analog Multiplexer Output 0 Analog Multiplexer Output 1 None ADC Input (in MUX mode) www.national.com 12 CP3CN23 Name VREFP PB[7:0] PC[7:0] A[22:0] SEL0 SEL1 SEL2 SELIO WR0 WR1 RD PE0 PE1 PE2 PE3 PE4 Pins 1 8 8 23 1 1 1 1 1 1 1 1 1 1 1 1 I/O Input I/O I/O Output Output Output Output Output Output Output Output I/O I/O I/O I/O I/O Primary Function ADC Positive Voltage Reference Generic I/O Generic I/O External Address Bus Bits 0 to 22 Chip Select for Zone 0 Chip Select for Zone 1 Chip Select for Zone 2 Chip Select for I/O Zone External Memory Write Low Byte External Memory Write High Byte External Memory Read Generic I/O Generic I/O Generic I/O Generic I/O Generic I/O Alternate Name None D[7:0] D[8:15] None None None None None None None None RXD0 TXD0 RTS CTS CKX TB SRFS None Alternate Function External Data Bus Bits 0 to 7 External Data Bus Bits 8 to 15 None None None None None None None None UART0 Receive Data Input UART0 Transmit Data Output UART0 Ready-To-Send Output UART0 Clear-To-Send Input UART0 Clock Input Multi Function Timer Port B AAI Receive Frame Sync Non-Maskable Interrupt Input UART Channel 0 Ready-To-Send Output UART Channel 0 Clear-To-Send Input SPI Shift Clock Versatile Timer Channel 1 SPI Master In Slave Out Versatile Timer Channel 2 SPI Master Out Slave In Versatile Timer Channel 3 SPI Slave Select Input Versatile Timer Channel 4 AAI Clock Versatile Timer Channel 5 AAI Frame Synchronization Versatile Timer Channel 6 AAI Transmit Data Output Versatile Timer Channel 7 AAI Receive Data Input Versatile Timer Channel 8 www.national.com PE5 PE6 PE7 PF0 1 1 1 1 I/O I/O I/O I/O Generic I/O NMI Generic I/O Generic I/O Generic I/O TIO1 MDIDO CAN1RX CAN1TX MSK PF1 1 I/O Generic I/O TIO2 MDODI PF2 1 I/O Generic I/O TIO3 MWCS PF3 1 I/O Generic I/O TIO4 SCK PF4 1 I/O Generic I/O TIO5 SFS PF5 1 I/O Generic I/O TIO6 STD PF6 1 I/O Generic I/O TIO7 SRD PF7 1 I/O Generic I/O TIO8 13 CP3CN23 Name PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 PH0 Pins 1 1 1 1 1 1 1 1 1 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Primary Function Generic I/O Generic I/O Generic I/O Generic I/O Generic I/O Generic I/O Generic I/O Generic I/O Generic I/O Alternate Name None None SRCLK None None None WUI10 TA RXD1 WUI11 TXD1 None None Alternate Function AAI Receive Clock None None None Multi-Input Wake-Up Channel 10 Multi Function Timer Port A UART Channel 1 Receive Data Input Multi-Input Wake-Up Channel 11 UART Channel 1 Transmit Data Output Multi-Input Wake-Up Channel 12 UART Channel 2 Receive Data Input Multi-Input Wake-Up Channel 13 UART Channel 2 Transmit Data Output Multi-Input Wake-Up Channel 14 UART Channel 3 Receive Data Input Multi-Input Wake-Up Channel 15 UART Channel 3 Transmit Data Output Multi-Input Wake-Up Channel 16 CAN Receive Input Multi-Input Wake-Up Channel 17 CAN Transmit Output Multi-Input Wake-Up Channel 18 Start Convert Signal to ADC Multi-Input Wake-Up Channel 9 PH1 1 I/O Generic I/O WUI12 RXD2 PH2 1 I/O Generic I/O WUI13 TXD2 PH3 1 I/O Generic I/O WUI14 RXD3 PH4 1 I/O Generic I/O WUI15 TXD3 PH5 1 I/O Generic I/O WUI16 CAN0RX PH6 PH7 PJ0 PJ7 1 1 1 1 I/O I/O I/O I/O Generic I/O WUI17 Generic I/O Generic I/O Generic I/O WUI9 CAN0TX WUI18 ASYNC www.national.com 14 CP3CN23 5.0 CPU Architecture The CP3CN23 uses the CR16C third-generation 16-bit When the CFG.SR bit is clear, register pairs are grouped CompactRISC processor core. The CPU implements a Rein the manner used by native CR16C software: (R1,R0), duced Instruction Set Computer (RISC) architecture that al(R2,R1) ... (R11,R10), (R12_L, R11), R12, R13, RA, SP. lows an effective execution rate of up to one instruction per R12, R13, RA, and SP are 32-bit registers for holding adclock cycle. For a detailed description of the CPU16C archidresses greater than 16 bits. tecture, see the CompactRISC CR16C Programmer’s Ref- With the recommended calling convention for the architecerence Manual which is available on the National ture, some of these registers are assigned special hardware Semiconductor web site (http://www.nsc.com). and software functions. Registers R0 to R13 are for generalThe CR16C CPU core includes these internal registers: purpose use, such as holding variables, addresses, or index values. The SP register holds a pointer to the program runGeneral-purpose registers (R0-R13, RA, and SP) Dedicated address registers (PC, ISP, USP, and INT- time stack. The RA register holds a subroutine return address. The R12 and R13 registers are available to hold base BASE) addresses used in the index addressing mode. Processor Status Register (PSR) Configuration Register (CFG) The R0-R11, PSR, and CFG registers are 16 bits wide. The R12, R13, RA, SP, ISP and USP registers are 32 bits wide. The PC register is 24 bits wide. Figure 2 shows the CPU registers. Dedicated Address Registers 15 0 23 31 PC ISPH ISPL USPH USPL INTBASEH INTBASEL General-Purpose Registers 15 0 R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 RA SP DS004 If a general-purpose register is specified by an operation that is 8 bits long, only the lower byte of the register is used; the upper part is not referenced or modified. Similarly, for word operations on register pairs, only the lower word is used. The upper word is not referenced or modified. 5.2 DEDICATED ADDRESS REGISTERS The CR16C has four dedicated address registers to implement specific functions: the PC, ISP, USP, and INTBASE registers. 5.2.1 Program Counter (PC) Register Processor Status Register 15 0 PSR Configuration Register 15 0 CFG 31 The 24-bit value in the PC register points to the first byte of the instruction currently being executed. CR16C instructions are aligned to even addresses, therefore the least significant bit of the PC is always 0. At reset, the PC is initialized to 0 or an optional predetermined value. When a warm reset occurs, value of the PC prior to reset is saved in the (R1,R0) general-purpose register pair. 5.2.2 Interrupt Stack Pointer (ISP) The 32-bit ISP register points to the top of the interrupt stack. This stack is used by hardware to service exceptions (interrupts and traps). The stack pointer may be accessed Figure 2. CPU Registers as the ISP register for initialization. The interrupt stack can Some register bits are designated as “reserved.” Software be located anywhere in the CPU address space. The ISP must write a zero to these bit locations when it writes to the cannot be used for any purpose other than the interrupt register. Read operations from reserved bit locations return stack, which is used for automatic storage of the CPU registers when an exception occurs and restoration of these undefined values. registers when the exception handler returns. The interrupt 5.1 GENERAL-PURPOSE REGISTERS stack grows downward in memory. The least significant bit The CompactRISC CPU features 16 general-purpose regis- and the 8 most significant bits of the ISP register are always ters. These registers are used individually as 16-bit oper- 0. ands or as register pairs for operations on addresses 5.2.3 User Stack Pointer (USP) greater than 16 bits. The USP register points to the top of the user-mode proGeneral-purpose registers are defined as R0 through gram stack. Separate stacks are available for user and suR13, RA, and SP. pervisor modes, to support protection mechanisms for Registers are grouped into pairs based on the setting of multitasking software. The processor mode is controlled by the Short Register bit in the Configuration Register the U bit in the PSR register (which is called PSR.U in the (CFG.SR). When the CFG.SR bit is set, the grouping of shorthand convention). Stack grow downward in memory. If register pairs is upward-compatible with the architecture the USP register points to an illegal address (any address of the earlier CR16A/B CPU cores: (R1,R0), (R2,R1) ... greater than 0x00FF_FFFF) and the USP is used for stack (R11,R10), (R12_L, R11), (R13_L, R12_L), (R14_L, access, an IAD trap is taken. R13_L) and SP. (R14_L, R13_L) is the same as (RA,ERA). 15 www.national.com CP3CN23 5.2.4 Interrupt Base Register (INTBASE) N The INTBASE register holds the address of the dispatch table for exceptions. The dispatch table can be located anywhere in the CPU address space. When loading the INTBASE register, bits 31 to 24 and bit 0 must written with 0. 5.3 PROCESSOR STATUS REGISTER (PSR) E The PSR provides state information and controls operating modes for the CPU. The format of the PSR is shown below. 15 12 11 10 9 I PE 8 7 6 5 F 4 3 2 1 0 Reserved 0NZ 0UL TC C T L U F Z The Carry bit indicates whether a carry or borrow occurred after addition or subtraction. 0 – No carry or borrow occurred. 1 – Carry or borrow occurred. The Trace bit enables execution tracing, in which a Trace trap (TRC) is taken after every instruction. Tracing is automatically disabled during the execution of an exception handler. 0 – Tracing disabled. 1 – Tracing enabled. The Low bit indicates the result of the last comparison operation, with the operands interpreted as unsigned integers. 0 – Second operand greater than or equal to first operand. 1 – Second operand less than first operand. The User Mode bit controls whether the CPU is in user or supervisor mode. In supervisor mode, the SP register is used for stack operations. In user mode, the USP register is used instead. User mode is entered by executing the Jump USR instruction. When an exception is taken, the exception handler automatically begins execution in supervisor mode. The USP register is accessible using the Load Processor Register (LPR/LPRD) instruction in supervisor mode. In user mode, an attempt to access the USP register generates a UND trap. 0 – CPU is executing in supervisor mode. 1 – CPU is executing in user mode. The Flag bit is a general condition flag for signalling exception conditions or distinguishing the results of an instruction, among other thing uses. For example, integer arithmetic instructions use the F bit to indicate an overflow condition after an addition or subtraction operation. The Zero bit is used by comparison operations. In a comparison of integers, the Z bit is set if the two operands are equal. If the operands are unequal, the Z bit is cleared. 0 – Source and destination operands unequal. 1 – Source and destination operands equal. P I The Negative bit indicates the result of the last comparison operation, with the operands interpreted as signed integers. 0 – Second operand greater than or equal to first operand. 1 – Second operand less than first operand. The Local Maskable Interrupt Enable bit enables or disables maskable interrupts. If this bit and the Global Maskable Interrupt Enable (I) bit are both set, all interrupts are enabled. If either of these bits is clear, only the nonmaskable interrupt is enabled. The E bit is set by the Enable Interrupts (EI) instruction and cleared by the Disable Interrupts (DI) instruction. 0 – Maskable interrupts disabled. 1 – Maskable interrupts enabled. The Trace Trap Pending bit is used together with the Trace (T) bit to prevent a Trace (TRC) trap from occurring more than once for one instruction. At the beginning of the execution of an instruction, the state of the T bit is copied into the P bit. If the P bit remains set at the end of the instruction execution, the TRC trap is taken. 0 – No trace trap pending. 1 – Trace trap pending. The Global Maskable Interrupt Enable bit is used to enable or disable maskable interrupts. If this bit and the Local Maskable Interrupt Enable (E) bit are both set, all maskable interrupts are taken. If either bit is clear, only the non-maskable interrupt is taken. Unlike the E bit, the I bit is automatically cleared when an interrupt occurs and automatically set upon completion of an interrupt handler. 0 – Maskable interrupts disabled. 1 – Maskable interrupts enabled. Bits Z, C, L, N, and F of the PSR are referenced from assembly language by the condition code in conditional branch instructions. A conditional branch instruction may cause a branch in program execution, based on the value of one or more of these PSR bits. For example, one of the Bcond instructions, BEQ (Branch EQual), causes a branch if the PSR.Z bit is set. On reset, bits 0 through 11 of the PSR are cleared, except for the PSR.E bit, which is set. On warm reset, the values of each bit before reset are copied into the R2 general-purpose register. Bits 4 and 8 of the PSR have a constant value of 0. Bits 12 through 15 are reserved. In general, status bits are modified only by specific instructions. Otherwise, status bits maintain their values throughout instructions which do not implicitly affect them. www.national.com 16 CP3CN23 5.4 CONFIGURATION REGISTER (CFG) The CFG register is used to enable or disable various operating modes and to control optional on-chip caches. Because the CP3CN23 does not have cache memory, the cache control bits in the CFG register are reserved. All CFG bits are cleared on reset. 15 Reserved 10 9 8 7 6 0 5 Reserved 2 1 0 0 0 SR ED 0 ED SR The Extended Dispatch bit selects whether the size of an entry in the interrupt dispatch table (IDT) is 16 or 32 bits. Each entry holds the address of the appropriate exception handler. When the IDT has 16-bit entries, and all exception handlers must reside in the first 128K of the address space. The location of the IDT is held in the INTBASE register, which is not affected by the state of the ED bit. 0 – Interrupt dispatch table has 16-bit entries. 1 – Interrupt dispatch table has 32-bit entries. The Short Register bit enables a compatibility mode for the CR16B large model. In the CR16C core, registers R12, R13, and RA are extended to 32 bits. In the CR16B large model, only the lower 16 bits of these registers are used, and these “short registers” are paired together for 32-bit operations. In this mode, the (RA, R13) register pair is used as the extended RA register, and address displacements relative to a single register are supported with offsets of 0 and 14 bits in place of the index addressing with these displacements. 0 – 32-bit registers are used. 1 – 16-bit registers are used (CR16B mode). 17 www.national.com CP3CN23 5.5 ADDRESSING MODES The CR16C CPU core implements a load/store architecture, in which arithmetic and logical instructions operate on register operands. Memory operands are made accessible in registers using load and store instructions. For efficient implementation of I/O-intensive embedded applications, the architecture also provides a set of bit operations that operate on memory operands. The load and store instructions support these addressing modes: register/pair, immediate, relative, absolute, and index addressing. When register pairs are used, the lower bits are in the lower index register and the upper bits are in the higher index register. When the CFG.SR bit is clear, the 32bit registers R12, R13, RA, and SP are also treated as register pairs. References to register pairs in assembly language use parentheses. With a register pair, the lower numbered register pair must be on the right. For example, jump (r5, r4) load $4(r4,r3), (r6,r5) load $5(r12), (r13) The instruction set supports the following addressing modes: Register/Pair Mode In register/pair mode, the operand is held in a general-purpose register, or in a general-purpose register pair. For example, the following instruction adds the contents of the low byte of register r1 to the contents of the low byte of r2, and places the result in the low byte register r2. The high byte of register r2 is not modified. ADDB R1, R2 Immediate In immediate mode, the operand is a conMode stant value which is encoded in the instruction. For example, the following instruction multiplies the value of r4 by 4 and places the result in r4. MULW $4, R4 Relative Mode In relative mode, the operand is addressed using a relative value (displacement) encoded in the instruction. This displacement is relative to the current Program Counter (PC), a general-purpose register, or a register pair. In branch instructions, the displacement is always relative to the current value of the PC Register. For example, the following instruction causes an unconditional branch to an address 10 ahead of the current PC. BR *+10 Index Mode In another example, the operand resides in memory. Its address is obtained by adding a displacement encoded in the instruction to the contents of register r5. The address calculation does not modify the contents of register r5. LOADW 12(R5), R6 The following example calculates the address of a source operand by adding a displacement of 4 to the contents of a register pair (r5, r4) and loads this operand into the register pair (r7, r6). r7 receives the high word of the operand, and r6 receives the low word. LOADD 4(r5, r4), (r7, r6) In index mode, the operand address is calculated with a base address held in either R12 or R13. The CFG.SR bit must be clear to use this mode. For relative mode operands, the memory address is calculated by adding the value of a register pair and a displacement to the base address. The displacement can be a 14 or 20-bit unsigned value, which is encoded in the instruction. For absolute mode operands, the memory address is calculated by adding a 20-bit absolute address encoded in the instruction to the base address. In the following example, the operand address is the sum of the displacement 4, the contents of the register pair (r5,r4), and the base address held in register r12. The word at this address is loaded into register r6. LOADW [r12]4(r5, r4), r6 Absolute Mode In absolute mode, the operand is located in memory, and its address is encoded in the instruction (normally 20 or 24 bits). For example, the following instruction loads the byte at address 4000 into the lower 8 bits of register r6. LOADB 4000, r6 For additional information on the addressing modes, see the CompactRISC CR16C Programmer's Reference Manual. www.national.com 18 CP3CN23 5.6 STACKS 5.7 INSTRUCTION SET A stack is a last-in, first-out data structure for dynamic storage of data and addresses. A stack consists of a block of memory used to hold the data and a pointer to the top of the stack. As more data is pushed onto a stack, the stack grows downward in memory. The CR16C supports two types of stacks: the interrupt stack and program stacks. Table 4 lists the operand specifiers for the instruction set, and Table 5 is a summary of all instructions. For each instruction, the table shows the mnemonic and a brief description of the operation performed. In the mnemonic column, the lower-case letter “i” is used to indicate the type of integer that the instruction operates on, either “B” for byte or “W” for word. For example, the notation 5.6.1 Interrupt Stack ADDi for the “add” instruction means that there are two The processor uses the interrupt stack to save and restore forms of this instruction, ADDB and ADDW, which operate the program state during the exception handling. Hardware on bytes and words, respectively. automatically pushes this data onto the interrupt stack before entering an exception handler. When the exception Similarly, the lower-case string “cond” is used to indicate the handler returns, hardware restores the processor state with type of condition tested by the instruction. For example, the data popped from the interrupt stack. The interrupt stack notation Jcond represents a class of conditional jump instructions: JEQ for Jump on Equal, JNE for Jump on Not pointer is held in the ISP register. Equal, etc. For detailed information on all instructions, see 5.6.2 Program Stack the CompactRISC CR16C Programmer's Reference ManuThe program stack is normally used by software to save and al. restore register values on subroutine entry and exit, hold loTable 4 Key to Operand Specifiers cal and temporary variables, and hold parameters passed between the calling routine and the subroutine. The only Operand Specifier Description hardware mechanisms which operate on the program stack are the PUSH, POP, and POPRET instructions. abs Absolute address 5.6.3 User and Supervisor Stack Pointers disp imm Iposition Rbase Rdest Rindex RPbase, RPbasex RPdest RPlink Rposition Rproc Rprocd RPsrc RPtarget Rsrc, Rsrc1, Rsrc2 To support multitasking operating systems, support is provided for two program stack pointers: a user stack pointer and a supervisor stack pointer. When the PSR.U bit is clear, the SP register is used for all program stack operations. This is the default mode when the user/supervisor protection mechanism is not used, and it is the supervisor mode when protection is used. When the PSR.U bit is set, the processor is in user mode, and the USP register is used as the program stack pointer. User mode can only be entered using the JUSR instruction, which performs a jump and sets the PSR.U bit. User mode is exited when an exception is taken and re-entered when the exception handler returns. In user mode, the LPRD instruction cannot be used to change the state of processor registers (such as the PSR). Displacement (numeric suffix indicates number of bits) Immediate operand (numeric suffix indicates number of bits) Bit position in memory Base register (relative mode) Destination register Index register Base register pair (relative mode) Destination register pair Link register pair Bit position in register 16-bit processor register 32-bit processor register Source register pair Target register pair Source register 19 www.national.com CP3CN23 Table 5 Instruction Set Summary Mnemonic MOVi MOVXB MOVZB MOVXW MOVZW MOVD Operands Rsrc/imm, Rdest Rsrc, Rdest Rsrc, Rdest Rsrc, RPdest Rsrc, RPdest imm, RPdest RPsrc, RPdest ADD[U]i ADDCi ADDD MACQWa MACSWa MACUWa MULi MULSB MULSW MULUW SUBi SUBD SUBCi CMPi CMPD BEQ0i BNE0i ANDi ANDD ORi ORD Scond XORi XORD ASHUi Rsrc/imm, Rdest Rsrc/imm, Rdest RPsrc/imm, RPdest Rsrc1, Rsrc2, RPdest Rsrc1, Rsrc2, RPdest Rsrc1, Rsrc2, RPdest Rsrc/imm, Rdest Rsrc, Rdest Rsrc, RPdest Rsrc, RPdest Rsrc/imm, Rdest RPsrc/imm, RPdest Rsrc/imm, Rdest Rsrc/imm, Rdest RPsrc/imm, RPdest Rsrc, disp Rsrc, disp Rsrc/imm, Rdest RPsrc/imm, RPdest Rsrc/imm, Rdest RPsrc/imm, RPdest Rdest Rsrc/imm, Rdest RPsrc/imm, RPdest Rsrc/imm, Rdest Move Move with sign extension Move with zero extension Move with sign extension Move with zero extension Move immediate to register-pair Move between register-pairs Add Add with carry Add with RP or immediate. Multiply signed Q15: RPdest := RPdest + (Rsrc1 × Rsrc2) Multiply signed and add result: RPdest := RPdest + (Rsrc1 × Rsrc2) Multiply unsigned and add result: RPdest := RPdest + (Rsrc1 × Rsrc2) Multiply: Rdest(8) := Rdest(8) × Rsrc(8)/imm Rdest(16) := Rdest(16) × Rsrc(16)/imm Multiply: Rdest(16) := Rdest(8) × Rsrc(8) Multiply: RPdest := RPdest(16) × Rsrc(16) Multiply: RPdest := RPdest(16) × Rsrc(16); Subtract: (Rdest := Rdest - Rsrc/imm) Subtract: (RPdest := RPdest - RPsrc/imm) Subtract with carry: (Rdest := Rdest - Rsrc/imm) Compare Rdest - Rsrc/imm Compare RPdest - RPsrc/imm Compare Rsrc to 0 and branch if EQUAL Compare Rsrc to 0 and branch if NOT EQUAL Logical AND: Rdest := Rdest & Rsrc/imm Logical AND: RPdest := RPsrc & RPsrc/imm Logical OR: Rdest := Rdest | Rsrc/imm Logical OR: Rdest := RPdest | RPsrc/imm Save condition code as boolean Logical exclusive OR: Rdest := Rdest ^ Rsrc/imm Logical exclusive OR: Rdest := RPdest ^ RPsrc/imm Arithmetic left/right shift Description www.national.com 20 CP3CN23 Table 5 Instruction Set Summary Mnemonic ASHUD LSHi LSHD SBITi Operands Rsrc/imm, RPdest Rsrc/imm, Rdest Rsrc/imm, RPdest Iposition, disp(Rbase) Iposition, disp(RPbase) Iposition, (Rindex)disp(RPbasex) Iposition, abs Iposition, (Rindex)abs CBITi Iposition, disp(Rbase) Iposition, disp(RPbase) Iposition, (Rindex)disp(RPbasex) Iposition, abs Iposition, (Rindex)abs TBIT TBITi Rposition/imm, Rsrc Iposition, disp(Rbase) Iposition, disp(RPbase) Iposition, (Rindex)disp(RPbasex) Iposition, abs Iposition, (Rindex)abs LPR LPRD SPR SPRD Bcond Rsrc, Rproc RPsrc, Rprocd Rproc, Rdest Rprocd, RPdest disp9 disp17 disp24 BAL BR RPlink, disp24 disp9 disp17 disp24 EXCP Jcond JAL vector RPtarget RA, RPtarget, RPlink, RPtarget JUMP JUSR RPtarget RPtarget Jump Jump and set PSR.U Trap (vector) Conditional Jump to a large address Jump and link to a large address Branch and link Branch Load processor register Load double processor register Store processor register Store 32-bit processor register Conditional branch Test a bit in a register Test a bit in memory Clear a bit in memory Description Arithmetic left/right shift Logical left/right shift Logical left/right shift Set a bit in memory (Because this instruction treats the destination as a readmodify-write operand, it not be used to set bits in writeonly registers.) 21 www.national.com CP3CN23 Table 5 Instruction Set Summary Mnemonic RETX PUSH POP POPRET LOADi imm, Rsrc, RA imm, Rdest, RA imm, Rdest, RA disp(Rbase), Rdest abs, Rdest (Rindex)abs, Rdest (Rindex)disp(RPbasex), Rdest disp(RPbase), Rdest LOADD disp(Rbase), Rdest abs, Rdest (Rindex)abs, Rdest (Rindex)disp(RPbasex), Rdest disp(RPbase), Rdest STORi Rsrc, disp(Rbase) Rsrc, disp(RPbase) Rsrc, abs Rsrc, (Rindex)disp(RPbasex) Rsrc, (Rindex)abs STORD RPsrc, disp(Rbase) RPsrc, disp(RPbase) RPsrc, abs RPsrc, (Rindex)disp(RPbasex) RPsrc, (Rindex)abs STOR IMM imm4, disp(Rbase) imm4, disp(RPbase) imm4, (Rindex)disp(RPbasex) imm4, abs imm4, (Rindex)abs LOADM LOADMP STORM imm3 imm3 STORM imm3 Load 1 to 8 registers (R2-R5, R8-R11) from memory starting at (R0) Load 1 to 8 registers (R2-R5, R8-R11) from memory starting at (R1, R0) Store 1 to 8 registers (R2-R5, R8-R11) to memory starting at (R2) Operands Return from exception Push “imm” number of registers on user stack, starting with Rsrc and possibly including RA Restore “imm” number of registers from user stack, starting with Rdest and possibly including RA Restore registers (similar to POP) and JUMP RA Load (register relative) Load (absolute) Load (absolute index relative) Load (register relative index) Load (register pair relative) Load (register relative) Load (absolute) Load (absolute index relative) Load (register pair relative index) Load (register pair relative) Store (register relative) Store (register pair relative) Store (absolute) Store (register pair relative index) Store (absolute index) Store (register relative) Store (register pair relative) Store (absolute) Store (register pair index relative) Store (absolute index relative) Store unsigned 4-bit immediate value extended to operand length in memory Description www.national.com 22 CP3CN23 Table 5 Instruction Set Summary Mnemonic STORMP DI EI EIWAIT NOP WAIT imm3 Operands Description Store 1 to 8 registers (R2-R5, R8-R11) to memory starting at (R7,R6) Disable maskable interrupts Enable maskable interrupts Enable maskable interrupts and wait for interrupt No operation Wait for interrupt 23 www.national.com CP3CN23 6.0 Memory are reserved and must not be read or written. The BIU zones are regions of the address space that share the same control bits in the Bus Interface Unit (BIU). The CP3CN23 supports a uniform 16M-byte linear address space. Table 6 lists the types of memory and peripherals that occupy this memory space. Unlisted address ranges Table 6 CP3CN23 Memory Map Start Address 00 0000h 04 0000h 0D 0000h 0D 2000h 0E 0000h 0E 8000h 0E F000h 0E F140h 0E F200h 0E F320h 10 0000h 40 0000h 80 0000h FF 0000h FF F200h FF F600h FF FB00h FF FC00h End Address 03 FFFFh 0C FFFFh 0D 1FFFh 0D FFFFh 0E 7FFFh 0E EFFFh 0E F13Fh 0E F1FFh 0E F33Fh 0F FFFFh 3F FFFFh 7F FFFFh FE FFFFh FF F1FFh FF F5FFh FF FAFFh FF FBFFh FF FFFFh Size in Bytes 256K 576K 8K 56K 32K 28K 320 192 320 67K 3072K 4096K 8128K 61952 1K 1280 256 1K Description On-chip Flash Program Memory, including Boot Memory Reserved On-chip Flash Data Memory Reserved System RAM Reserved CAN0 Buffers and Registers Reserved CAN1 Buffers and Registers Reserved Reserved External Memory Zone 1 External Memory Zone 2 Reserved Peripherals and Other I/O Ports BIU, DMA, Flash interfaces I/O Expansion Peripherals and Other I/O Ports N/A IN/A I/O Zone N/A Static Zone 1 Static Zone 2 N/A BIU Zone Static Zone 0 (mapped internally in IRE and ERE mode; mapped to the external bus in DEV mode) 6.1 OPERATING ENVIRONMENT The operating environment controls whether external memory is supported and whether the reset vector jumps to a code space intended to support In-System Programming (ISP). Up to 12M of external memory space is available. The operating mode of the device is controlled by the states on the ENV[2:0] pins at reset and the states of the EMPTY bits in the Protection Word, as shown in Table 7. Internal pullups on the ENV[2:0] pins select IRE mode or ISP mode if these pins are allowed to float. When ENV[2:0] = 111b, IRE mode is selected unless the EMPTY bits in the Protection word indicate that the program flash memory is empty (unprogrammed), in which case ISP mode is selected. When ENV[2:0] = 011b, ERE mode is selected unless the EMPTY bits indicate that the program flash memory is empty, in which case ISP mode is selected. When ENV[2:0] = 110b, ISP mode is selected without regard to the states of the EMPTY bits. See Section 8.4.2 for more details. In the DEV environment, the on-chip flash memory is disabled, and the corresponding region of the address space is mapped to external memory. DEVINT mode is equivalent to DEV mode but maps static memory zone 0 to the on-chip memory. www.national.com 24 CP3CN23 6.4 Table 7 Operating Environment Selection ENV[2:0] EMPTY 111 011 000 001 110 111 011 No No N/A N/A N/A Yes Yes Operating Environment Internal ROM enabled (IRE) mode External ROM enabled (ERE) mode Development (DEV) mode Development (DEVINT) mode with internal memory In-System-Programming (ISP) mode In-System-Programming (ISP) mode In-System-Programming (ISP) mode BIU CONTROL REGISTERS The BIU has a set of control registers that determine how many wait cycles and hold cycles are to be used for accessing memory. During initialization of the system, these registers should be programmed with appropriate values so that the minimum allowable number of cycles is used. This number varies with the clock frequency. There are five BIU control registers, as listed in Table 8. These registers control the bus cycle configuration used for accessing the various on-chip memory types. Table 8 Bus Control Registers Name BCFG IOCFG SZCFG0 SZCFG1 SZCFG2 6.4.1 Address FF F900h FF F902h FF F904h FF F906h FF F908h Description BIU Configuration Register I/O Zone Configuration Register Static Zone 0 Configuration Register Static Zone 1 Configuration Register Static Zone 2 Configuration Register 6.2 BUS INTERFACE UNIT (BIU) The BIU controls the interface between the CPU core bus and those on-chip modules which are mapped into BIU zones. These on-chip modules are the flash program memory and the I/O zone. The BIU controls the configured parameters for bus access (such as the number of wait states for memory access) and issues the appropriate bus signals for the requested access. 6.3 BUS CYCLES There are four types of data transfer bus cycles: Normal read Fast read Early write Late write The type of data cycle used in a particular transaction depends on the type of CPU operation (a write or a read), the type of memory or I/O being accessed, and the access type programmed into the BIU control registers (early/late write or normal/fast read). For read operations, a basic normal read takes two clock cycles, and a fast-read bus cycle takes one clock cycle. Normal read bus cycles are enabled by default after reset. For write operations, a basic late-write bus cycle takes two clock cycles, and a basic early-write bus cycle takes three clock cycles. Early-write bus cycles are enabled by default after reset. However, late-write bus cycles are needed for ordinary write operations, so this configuration must be changed by software (see Section 6.4.1). In certain cases, one or more additional clock cycles are added to a bus access cycle. There are two types of additional clock cycles for ordinary memory accesses, called internal wait cycles (TIW) and hold (Thold) cycles. A wait cycle is inserted in a bus cycle just after the memory address has been placed on the address bus. This gives the accessed memory more time to respond to the transaction request. A hold cycle is inserted at the end of a bus cycle. This holds the data on the data bus for an extended number of clock cycles. BIU Configuration Register (BCFG) The BCFG register is a byte-wide, read/write register that selects early-write or late-write bus cycles. At reset, the register is initialized to 07h. The register format is shown below. 7 Reserved 3 2 1 1 1 0 EWR EWR The Early Write bit controls write cycle timing. 0 – Late-write operation (2 clock cycles to write). 1 – Early-write operation. At reset, the BCFG register is initialized to 07h, which selects early-write operation. However, late-write operation is required for normal device operation, so software must change the register value to 06h. Bits 1 and 2 of this register must always be set when writing to this register. 25 www.national.com CP3CN23 6.4.2 I/O Zone Configuration Register (IOCFG) 6.4.3 Static Zone 0 Configuration Register (SZCFG0) The IOCFG register is a word-wide, read/write register that controls the timing and bus characteristics of accesses to the 256-byte I/O Zone memory space (FF FB00h to FF FBFFh). The registers associated with Port B and Port C reside in the I/O memory array. At reset, the register is initialized to 069Fh. The register format is shown below. 7 BW 6 5 4 3 2 WAIT 0 The SZCFG0 register is a word-wide, read/write register that controls the timing and bus characteristics of Zone 0 memory accesses. Zone 0 is used for the on-chip flash memory (including the boot area, program memory, and data memory). At reset, the register is initialized to 069Fh. The register format is shown below. 7 BW 6 WBR 5 RBE 4 3 2 WAIT 0 Reserved HOLD HOLD 15 Reserved 10 9 IPST 8 Res. 15 Reserved 12 11 FRE 10 9 8 Res. IPRE IPST WAIT HOLD BW IPST The Memory Wait Cycles field specifies the number of TIW (internal wait state) clock cycles added for each memory access, ranging from 000 binary for no additional TIW wait cycles to 111 binary for seven additional TIW wait cycles. The Memory Hold Cycles field specifies the number of Thold clock cycles used for each memory access, ranging from 00b for no Thold cycles to 11b for three Thold clock cycles. The Bus Width bit defines the bus width of the IO Zone. 0 – 8-bit bus width. 1 – 16-bit bus width (default) The Post Idle bit controls whether an idle cycle follows the current bus cycle, when the next bus cycle accesses a different zone. No idle cycles are required for on-chip accesses. 0 – No idle cycle (recommended). 1 – Idle cycle. WAIT HOLD RBE WBR BW FRE IPST The Memory Wait field specifies the number of TIW (internal wait state) clock cycles added for each memory access, ranging from 000b for no additional TIW wait cycles to 111b for seven additional TIW wait cycles. These bits are ignored if the SZCFG0.FRE bit is set. The Memory Hold field specifies the number of Thold clock cycles used for each memory access, ranging from 00b for no Thold cycles to 11b for three Thold clock cycles. These bits are ignored if the SZCFG0.FRE bit is set. The Read Burst Enable enables burst cycles on 16-bit reads from 8-bit bus width regions of the address space. Because the flash program memory is required to be 16-bit bus width, the RBE bit is a don’t care bit. This bit is ignored when the SZCFG0.FRE bit is set. 0 – Burst read disabled. 1 – Burst read enabled. The Wait on Burst Read bit controls if a wait state is added on burst read transaction. This bit is ignored, when SZCFG0.FRE bit is set or when SZCFG0.RBE is clear. 0 – No TBW on burst read cycles. 1 – One TBW on burst read cycles. The Bus Width bit controls the bus width of the zone. The flash program memory must be configured for 16-bit bus width. 0 – 8-bit bus width. 1 – 16-bit bus width (required). The Fast Read Enable bit controls whether fast read bus cycles are used. A fast read operation takes one clock cycle. A normal read operation takes at least two clock cycles. 0 – Normal read cycles. 1 – Fast read cycles. The Post Idle bit controls whether an idle cycle follows the current bus cycle, when the next bus cycle accesses a different zone. No idle cycles are required for on-chip accesses. 0 – No idle cycle (recommended). 1 – Idle cycle inserted. www.national.com 26 CP3CN23 IPRE The Preliminary Idle bit controls whether an idle cycle is inserted prior to the current bus cycle, when the new bus cycle accesses a different zone. No idle cycles are required for onchip accesses. 0 – No idle cycle (recommended). 1 – Idle cycle inserted. Static Zone 1 Configuration Register (SZCFG1) IPST IPRE 6.4.4 The SZCFG1 register is a word-wide, read/write register that controls the timing and bus characteristics for off-chip accesses selected with the SEL1 output signal. At reset, the register is initialized to 069Fh. The register format is shown below. 7 BW 6 WBR 5 RBE 4 3 2 WAIT 0 The Post Idle bit controls whether an idle cycle follows the current bus cycle, when the next bus cycle accesses a different zone. 0 – No idle cycle. 1 – Idle cycle inserted. The Preliminary Idle bit controls whether an idle cycle is inserted prior to the current bus cycle, when the new bus cycle accesses a different zone. 0 – No idle cycle. 1 – Idle cycle inserted. Static Zone 2 Configuration Register (SZCFG2) 6.4.5 The SZCFG2 register is a word-wide, read/write register that controls the timing and bus characteristics for off-chip accesses selected with the SEL2 output signal. At reset, the register is initialized to 069Fh. The register format is shown below. 7 BW 6 WBR 5 RBE 4 3 2 WAIT 0 HOLD 15 Reserved 12 11 FRE 10 9 8 Res. IPRE IPST HOLD WAIT HOLD RBE WBR BW FRE The Memory Wait field specifies the number of TIW (internal wait state) clock cycles added for each memory access, ranging from 000b for no additional TIW wait cycles to 111b for seven additional TIW wait cycles. These bits are ignored if the SZCFG1.FRE bit is set. The Memory Hold field specifies the number of Thold clock cycles used for each memory access, ranging from 00b for no Thold cycles to 11b for three Thold clock cycles. These bits are ignored if the SZCFG1.FRE bit is set. The Read Burst Enable enables burst cycles on 16-bit reads from 8-bit bus width regions of the address space. This bit is ignored when the SZCFG1.FRE bit is set or the SZCFG1.BW is clear. 0 – Burst read disabled. 1 – Burst read enabled. The Wait on Burst Read bit controls if a wait state is added on burst read transaction. This bit is ignored, when SZCFG1.FRE bit is set or when SZCFG1.RBE is clear. 0 – No TBW on burst read cycles. 1 – One TBW on burst read cycles. The Bus Width bit controls the bus width of the zone. 0 – 8-bit bus width. 1 – 16-bit bus width. The Fast Read Enable bit controls whether fast read bus cycles are used. A fast read operation takes one clock cycle. A normal read operation takes at least two clock cycles. 0 – Normal read cycles. 1 – Fast read cycles. 15 Reserved 12 11 FRE 10 9 8 Res. IPRE IPST WAIT HOLD RBE WBR BW The Memory Wait field specifies the number of TIW (internal wait state) clock cycles added for each memory access, ranging from 000b for no additional TIW wait cycles to 111b for seven additional TIW wait cycles. These bits are ignored if the SZCFG2.FRE bit is set. The Memory Hold field specifies the number of Thold clock cycles used for each memory access, ranging from 00b for no Thold cycles to 11b for three Thold clock cycles. These bits are ignored if the SZCFG2.FRE bit is set. The Read Burst Enable enables burst cycles on 16-bit reads from 8-bit bus width regions of the address space. This bit is ignored when the SZCFG2.FRE bit is set or the SZCFG2.BW is clear. 0 – Burst read disabled. 1 – Burst read enabled. The Wait on Burst Read bit controls if a wait state is added on burst read transaction. This bit is ignored, when SZCFG2.FRE bit is set or when SZCFG2.RBE is clear. 0 – No TBW on burst read cycles. 1 – One TBW on burst read cycles. The Bus Width bit controls the bus width of the zone. 0 – 8-bit bus width. 1 – 16-bit bus width. 27 www.national.com CP3CN23 FRE IPST IPRE The Fast Read Enable bit controls whether fast read bus cycles are used. A fast read operation takes one clock cycle. A normal read operation takes at least two clock cycles. 0 – Normal read cycles. 1 – Fast read cycles. The Post Idle bit controls whether an idle cycle follows the current bus cycle, when the next bus cycle accesses a different zone. 0 – No idle cycle. 1 – Idle cycle inserted. The Preliminary Idle bit controls whether an idle cycle is inserted prior to the current bus cycle, when the new bus cycle accesses a different zone. 0 – No idle cycle. 1 – Idle cycle inserted. 6.5 WAIT AND HOLD STATES The number of wait cycles and hold cycles inserted into a bus cycle depends on whether it is a read or write operation, the type of memory or I/O being accessed, and the control register settings. 6.5.1 Flash Program/Data Memory When the CPU accesses the Flash program and data memory (address ranges 000000h–03FFFFh and 0E0000h– 0E1FFFh), the number of added wait and hold cycles depends on the type of access and the BIU register settings. In fast-read mode (SZCFG0.FRE=1), a read operation is a single cycle access. This limits the maximum CPU operating frequency to 24 MHz. For a read operation in normal-read mode (SZCFG0.FRE=0), the number of inserted wait cycles is specified in the SZCFG0.WAIT field. The total number of wait cycles is the value in the WAIT field plus 1, so it can range from 1 to 8. The number of inserted hold cycles is specified in the SCCFG0.HOLD field, which can range from 0 to 3. For a write operation in fast read mode (SZCFG0.FRE=1), the number of inserted wait cycles is 1. No hold cycles are used. For a write operation normal read mode (SZCFG0.FRE=0), the number of wait cycles is equal to the value written to the SZCFG0.WAIT field plus 1 (in the late write mode) or 2 (in the early write mode). The number of inserted hold cycles is equal to the value written to the SCCFG0.HOLD field, which can range from 0 to 3. 6.5.2 RAM Memory Read and write accesses to on-chip RAM is performed within a single cycle, without regard to the BIU settings. The RAM address is in the range of 0E 0000h–0E 7FFFh and 0E 8000h–0E 91FFh. 6.5.3 Access to Peripherals When the CPU accesses on-chip peripherals in the range of 0E F000h–0E F1FFh and FF 0000h–FF FBFFh, one wait cycle and one preliminary idle cycle is used. No hold cycles are used. The IOCFG register determines the access timing for the address range FF FB00h–FF FBFFh. www.national.com 28 CP3CN23 7.0 System Configuration Registers 7.1 The system configuration registers control and provide status for certain aspects of device setup and operation, such as indicating the states sampled from the ENV[2:0] inputs. The system configuration registers are listed in Table 9. Table 9 Name MCFG MSTAT System Configuration Registers Address FF F910h FF F914h Description Module Configuration Register Module Status Register MODULE CONFIGURATION REGISTER (MCFG) The MCFG register is a byte-wide, read/write register that selects the clock output features of the device. The register must be written in active mode only, not in power save, HALT, or IDLE mode. However, the register contents are preserved during all power modes. The MCFG register format is shown below. 7 Res. 6 5 4 3 2 1 0 MEM_IO_ MISC_IO_ SCLK MCLK PLLCLK EXI Res. SPEED SPEED OE OE OE OE EXIOE The EXIOE bit controls whether the external bus is enabled in the IRE environment for implementing the I/O Zone (FF FB00h–FF FBFFh). 0 – External bus disabled. 1 – External bus enabled. PLLCLKOE The PLLCLKOE bit controls whether the PLL clock is driven on the ENV0/PLLCLK pin. 0 – ENV0/PLLCLK pin is high impedance. 1 – PLL clock driven on the ENV0/PLLCLK pin. MCLKOE The MCLKOE bit controls whether the Main Clock is driven on the ENV1/CPUCLK pin. 0 – ENV1/CPUCLK pin is high impedance. 1 – Main Clock is driven on the ENV1/CPUCLK pin. SCLKOE The SCLKOE bit controls whether the Slow Clock is driven on the ENV2/SLOWCLK pin. 0 – ENV2/SLOWCLK pin is high impedance. 1 – Slow Clock is driven on the ENV2/SLOWCLK pin. MISC_IO_SPEED The MISC_IO_SPEED bit controls the slew rate of the output drivers for the ENV[2:0], RDY, and TDO pins. To minimize noise, the slow slew rate is recommended. 0 – Fast slew rate. 1 – Slow slew rate. MEM_IO_SPEED The MEM_IO_SPEED bit controls the slew rate of the output drivers for the A[22:0], RD, SEL[2:0], SELIO, WR[1:0], PB[7:0], and PC[7:0] pins. Memory speeds for the CP3CN23 are characterized with fast slew rate. Slow slew rate reduces the available memory access time by 5 ns. 0 – Fast slew rate. 1 – Slow slew rate. 29 www.national.com CP3CN23 7.2 MODULE STATUS REGISTER (MSTAT) 7.3 The MSTAT register is a byte-wide, read-only register that indicates the general status of the device. The MCFG regis- The SWRESET register is a byte-wide, write-only register ter format is shown below. which provides a mechanism for software to initiate a reset into ISP mode without regard to the status of the EMPTY bits in the flash protection word. This form of reset is only al7 6 5 4 3 2 0 lowed when all of the following conditions are true: ISPRST WDRST Res. DPGMBUSY PGMBUSY OENV2:0 The device is in IRE or ERE mode BOOTAREA is defined (has a value other than 1111b) in the Protection Word (see Section 8.4.2 for more details). OENV2:0 The Operating Environment bits hold the ISPE is set in the flash protection word, indicating that states sampled from the ENV[2:0] input pins there is ISP code in the flash at reset. These states are controlled by external hardware at reset and are held constant in the register until the next reset. PGMBUSY The Flash Programming Busy bit is automatically set when either the program memory or the data memory is being programmed or erased. It is clear when neither of the memories is busy. When this bit is set, software must not attempt to program or erase either of these two memories. This bit is a copy of the FMBUSY bit in the FMSTAT register. 0 – Flash memory is not busy. 1 – Flash memory is busy. DPGMBUSY The Data Flash Programming Busy indicates that the flash data memory is being erased or a pipelined programming sequence is currently ongoing. Software must not attempt to perform any write access to the flash program memory at this time, without also polling the FSMSTAT.FMFULL bit in the flash memory interface. The DPGMBUSY bit is a copy of the FMBUSY bit in the FSMSTAT register. 0 – Flash data memory is not busy. 1 – Flash data memory is busy. WDRST The Watchdog Reset bit indicates that a Watchdog timer reset has occurred. Write a 1 to this bit to clear it. Power-on reset also clears this bit. 0 – No Watchdog timer reset has occurred since this bit was last cleared. 1 – A Watchdog timer reset has occurred since this bit was last cleared. ISPRST The Software ISP Reset bit indicates that a software ISP reset has occurred since the bit was last cleared. This bit is cleared by a SWRESET(CLR) sequence or a power-on reset. 0 – No software ISP reset has occurred since this bit was last cleared. 1 – A software ISP reset has occurred since this bit was last cleared. To initiate a reset under these conditions, it is necessary to write the value E1h to the SWRESET register, followed within 127 clock cycles by the value 3Eh. The reset then follows immediately. This sequence is called SWRESET(ISP). Once the device has been reset into ISP mode by SWRESET(ISP), any subsequent reset (other than internal or external power-on reset) will cause the part to reset into ISP mode because the EMPTY bits in the Protection Word continue to be ignored. A second set of special values written to the SWRESET register will cause a reset out of ISP mode (whether or not the device is currently in ISP mode). This can be used as a simple software reset. In this case, no conditions are checked. To initiate reset out of ISP mode, write the value E1h to the SWRESET register, followed within 127 clock cycles by the value 0Eh. The reset then follows immediately. This sequence is called SWRESET(CLR). This reset also cancels the effect of any previous SWRESET(ISP), so subsequent resets will check the EMPTY bits to determine whether to enter ISP mode. The ISP reset behaves similarly to the Watchdog reset, for example, if the flash interface is busy when reset is asserted, the reset to the clock module is delayed until the flash operations are completed. SOFTWARE RESET REGISTER (SWRESET) www.national.com 30 CP3CN23 8.0 Flash Memory The flash memory consists of the flash program memory and the flash data memory. The flash program memory is further divided into the Boot Area and the Code Area. default (after reset) all bits in the FM0WER, FM1WER, and FSM0WER registers are cleared, which disables write access by the CPU to all sections. Write access to a section is A special protection scheme is applied to the lower portion enabled by setting the corresponding write enable bit. After of the flash program memory, called the Boot Area. The completing a programming or erase operation, software Boot Area always starts at address 0 and ranges up to a should clear all write enable bits to protect the flash program programmable end address. The maximum boot area ad- memory against any unintended writes. dress which can be selected is 00 77FFh. The intended use 8.1.2 Global Protection of this area is to hold In-System-Programming (ISP) rouThe WRPROT field in the Protection Word controls global tines or essential application routines. The Boot Area is alwrite protection. The Protection Word is located in a special ways protected against CPU write access, to avoid flash memory outside of the CPU address space. If a majorunintended modifications. ity of the bits in the 3-bit WRPROT field are clear, write proThe Code Area is intended to hold the application code and tection is enabled. Enabling this mode prevents the CPU constant data. The Code Area begins with the next byte af- from writing to flash memory. ter the Boot Area. Table 10 summarizes the properties of The RDPROT field in the Protection Word controls global the regions of flash memory mapped into the CPU address read protection. If a majority of the bits in the 3-bit RDPROT space. field are clear, read protection is enabled. Enabling this Table 10 Flash Memory Areas mode prevents reading by an external debugger through the serial debug interface or by an external flash programmer. Read Area Address Range Write Access CPU read access is not affected by the RDPROT bits. Access 8.2 FLASH MEMORY ORGANIZATION Boot Area 0–BOOTAREA - 1 Yes No Write access only if section write enable bit is set and global write protection is disabled. Write access only if section write enable bit is set and global write protection is disabled. Code BOOTAREA–03 FFFFh Area Yes Each of the flash memories are divided into main blocks and information blocks. The main blocks hold the code or data used by application software. The information blocks hold factory parameters, protection settings, and other devicespecific data. The main blocks are mapped into the CPU address space. The information blocks are accessed indirectly through a register-based interface. Separate sets of registers are provided for accessing flash program memory (FM registers) and flash data memory (FSM registers). The flash program memory consists of two main blocks and two data blocks, as shown in Table 11. The flash data memory consists of one main block and one information block. Table 11 Flash Memory Blocks Name Main Block 0 Address Range 00 0000h–01 FFFFh (CPU address space) 000h–07Fh (address register) 02 0000h–03 FFFFh (CPU address space) 080h–0FFh (address register) 0D 0000h–0D 1FFFh (CPU address space) 000h–07Fh (address register) Function Flash Program Memory Function Word, Factory Parameters Flash Program Memory Protection Word, User Data Flash Data Memory User Data Data Area 0D 0000h–0D 1FFFh Yes 8.1 FLASH MEMORY PROTECTION Information Block 0 Main Block 1 Information Block 1 Main Block 2 Information Block 2 The memory protection mechanisms provide both global and section-level protection. Section-level protection against CPU writes is applied to individual 8K-byte sections of the flash program memory and 512-byte sections of the flash data memory. Section-level protection is controlled through read/write registers mapped into the CPU address space. Global write protection is applied at the device level, to disable flash memory writes by the CPU. Global write protection is controlled by the encoding of bits stored in the flash memory array. 8.1.1 Section-Level Protection Each bit in the Flash Memory Write Enable (FM0WER and FM1WER) registers enables or disables write access to a corresponding section of flash program memory. Write access to the flash data memory is controlled by the bits in the Flash Slave Memory Write Enable (FSM0WER) register. By 31 www.national.com CP3CN23 8.2.1 Main Block 0 and 1 8.2.4 Main Block 2 Main Block 0 and Main Block 1 hold the 256K-byte program space, which consists of the Boot Area and Code Area. Each block consists of sixteen 8K-byte sections. Write access by the CPU to Main Block 0 and Main Block 1 is controlled by the corresponding bits in the FM0WER and FM1WER registers, respectively. The least significant bit in each register controls the section at the lowest address. 8.2.2 Information Block 0 Main Block 2 holds the 8K-byte data area, which consists of sixteen 512-byte sections. Write access by the CPU to Main Block 2 is controlled by the corresponding bits in the FSM0WER register. The least significant bit in the register controls the section at the lowest address. 8.2.5 Information Block 2 Information Block 0 contains 128 bytes, of which one 16-bit word has a dedicated function, called the Function Word. The Function Word resides at address 07Eh. The remaining Information Block 0 locations are used to hold factory parameters. Software only has read access to Information Block 0 through a register-based interface. The Function Word and the factory parameters are protected against CPU writes. Table 12 shows the structure of Information Block 0. Table 12 Information Block 0 Name Function Word Other (Used for Factory Parameters) 8.2.3 Address Range 07Eh–07Fh Yes 000h–07Dh No Read Access Write Access Information Block 2 contains 128 bytes, which can be used to store user data. The CPU can always read Information Block 2. The CPU can write Information Block 2 only when global write protection is disabled. Erasing Information Block 2 also erases Main Block 2. 8.3 FLASH MEMORY OPERATIONS Flash memory programming (erasing and writing) can be performed on the flash data memory while the CPU is executing out of flash program memory. Although the CPU can execute out of flash data memory, it cannot erase or write the flash program memory while executing from flash data memory. To erase or write the flash program memory, the CPU must be executing from the on-chip static RAM or offchip memory. An erase operation is required before programming. An erase operation sets all of the bits in the erased region. A programming operation clears selected bits. The programming mechanism is pipelined, so that a new write request can be loaded while a previous request is in progress. When the FMFULL bit in the FMSTAT or FSMSTAT register is clear, the pipeline is ready to receive a new request. New requests may be loaded after checking only the FMFULL bit. 8.3.1 Main Block Read Information Block 1 Information Block 1 contains 128 bytes, of which one 16-bit word has a dedicated function, called the Protection Word. The Protection Word resides at address 0FEh. It controls the global protection mechanisms and the size of the Boot Area. The Protection Word can be written by the CPU, however the changes only become valid after the next device reset. The remaining Information Block 1 locations can be used to store other user data. Erasing Information Block 1 also erases Main Block 1. Table 13 shows the structure of the Information Block 1. Table 13 Information Block 1 Name Protection Word Other (User Data) Address Range 0FEh–0FFh Yes 080h–0FDh Read Access Write Access Write access only if section write enable bit is set and global write protection is disabled. Read accesses from flash program memory can only occur when the flash program memory is not busy from a previous write or erase operation. Read accesses from the flash data memory can only occur when both the flash program memory and the flash data memory are not busy. Both byte and word read operations are supported. 8.3.2 Information Block Read Information block data is read through the register-based interface. Only word read operations are supported and the read address must be word-aligned (LSB = 0). The following steps are used to read from an information block: 1. Load the word address in the Flash Memory Information Block Address (FMIBAR) or Flash Slave Memory Information Block Address (FSMIBAR) register. 2. Read the data word by reading out the Flash Memory Information Block Data (FMIBDR) or Flash Slave Memory Information Block Data (FSMIBDR) register. www.national.com 32 CP3CN23 8.3.3 Main Block Page Erase 8.3.6 Main Block Write A flash erase operation sets all of the bits in the erased region. Pages of a main block can be individually erased if their write enable bits are set. This method cannot be used to erase the boot area, if defined. Each page in Main Block 0 and 1 consists of 1024 bytes (512 words). Each page in Main Block 2 consists of 512 bytes (256 words). To erase a page, the following steps are performed: 1. Verify that the Flash Memory Busy (FMBUSY) bit in the FMSTAT or FSMSTAT register is clear. 2. Prevent accesses to the flash memory while erasing is in progress. 3. Set the Page Erase (PER) bit in the FMCTRL or FSMCTRL register. 4. Write to an address within the desired page. 5. Wait until the FMBUSY bit becomes clear again. 6. Check the Erase Error (EERR) bit in the FMSTAT or FSMSTAT register to confirm successful erase of the page. 7. Repeat steps 4 through 6 to erase additional pages. 8. Clear the PER bit. 8.3.4 Main Block Module Erase Writing is only allowed when global write protection is disabled. Writing by the CPU is only allowed when the write enable bit is set for the sector which contains the word to be written. The CPU cannot write the Boot Area. Only wordwide write access to word-aligned addresses is supported. The following steps are performed to write a word: 1. Verify that the Flash Memory Busy (FMBUSY) bit in the FMSTAT or FSMSTAT register is clear. 2. Prevent accesses to the flash memory while the write is in progress. 3. Set the Program Enable (PE) bit in the FMCTRL or FSMCTRL register. 4. Write a word to the desired word-aligned address. This starts a new pipelined programming sequence. The FMBUSY bit becomes set while the write operation is in progress. The FMFULL bit in the FMSTAT or FSMSTAT register becomes set if a previous write operation is still in progress. 5. Wait until the FMFULL bit becomes clear. 6. Repeat steps 4 and 5 for additional words. 7. Wait until the FMBUSY bit becomes clear again. 8. Check the programming error (PERR) bit in the FMSTAT or FSMSTAT register to confirm successful programming. 9. Clear the Program Enable (PE) bit. A module erase operation can be used to erase an entire main block. All sections within the block must be enabled for writing. If a boot area is defined in the block, it cannot be erased. The following steps are performed to erase a main 8.3.7 Information Block Write block: 1. Verify that the Flash Memory Busy (FMBUSY) bit in the Writing is only allowed when global write protection is disabled. Writing by the CPU is only allowed when the write enFMSTAT or FSMSTAT register is clear. 2. Prevent accesses to the flash memory while erasing is able bit is set for the sector which contains the word to be written. The CPU cannot write Information Block 0. Only in progress. 3. Set the Module Erase (MER) bit in the FMCTRL or word-wide write access to word-aligned addresses is supported. The following steps are performed to write a word: FSMCTRL register. 4. Write to any address within the desired main block. 5. Wait until the FMBUSY bit becomes clear again. 6. Check the Erase Error (EERR) bit in the FMSTAT or FSMSTAT register to confirm successful erase of the block. 7. Clear the MER bit. 8.3.5 Information Block Module Erase Erasing an information block also erases the corresponding main block. If a boot area is defined in the main block, neither block can be erased. Page erase is not supported for information blocks. The following steps are performed to erase an information block: 1. Verify that the Flash Memory Busy (FMBUSY) bit in the FMSTAT or FSMSTAT register is clear. 2. Prevent accesses to the flash memory while erasing is in progress. 3. Set the Module Erase (MER) bit in the FMCTRL or FSMCTRL register. 4. Load the FMIBAR or FSMIBAR register with any address within the block, then write any data to the FMIBDR or FSMIBDR register. 5. Wait until the FMBUSY bit becomes clear again. 6. Check the Erase Error (EERR) bit in the FMSTAT or FSMSTAT register to confirm successful erase of the block. 7. Clear the MER bit. 1. Verify that the Flash Memory Busy (FMBUSY) bit in the FMSTAT or FSMSTAT register is clear. 2. Prevent accesses to the flash memory while the write is in progress. 3. Set the Program Enable (PE) bit in the FMCTRL or FSMCTRL register. 4. Write the desired target address into the FMIBAR or FSMIBAR register. 5. Write the data word into the FMIBDR or FSMIBDR register. This starts a new pipelined programming sequence. The FMBUSY bit becomes set while the write operation is in progress. The FMFULL bit in the FMSTAT or FSMSTAT register becomes set if a previous write operation is still in progress. 6. Wait until the FMFULL bit becomes clear. 7. Repeat steps 4 through 6 for additional words. 8. Wait until the FMBUSY bit becomes clear again. 9. Check the programming error (PERR) bit in the FMSTAT or FSMSTAT register to confirm successful programming. 10. Clear the Program Enable (PE) bit. 33 www.national.com CP3CN23 8.4 INFORMATION BLOCK WORDS Two words in the information blocks are dedicated to hold settings that affect the operation of the system: the Function Word in Information Block 0 and the Protection Word in Information Block 1. 8.4.1 Function Word Table 14 lists all possible boot area encodings. Table 14 Boot Area Encodings BOOT AREA 1111 1110 1101 1100 1011 Size of the Boot Area No Boot Area defined 2K bytes 4K bytes 6K bytes 8K bytes 10K bytes 12K bytes 14K bytes 16K bytes 18K bytes 20K bytes 22K bytes 24K bytes 26K bytes 28K bytes 30K bytes Code Area Start Address 00 0000h 00 0800h 00 1000h 00 1800h 00 2000h 00 2800h 00 3000h 00 3800h 00 4000h 00 4800h 00 5000h 00 5800h 00 6000h 00 6800h 00 7000h 00 7800h The Function Word resides in the Information Block 0 at address 07Eh. At reset, the Function Word is copied into the FMAR0 register. 15 Reserved 0 8.4.2 Protection Word 1010 1001 1000 0111 0110 0101 The Protection Word resides in Information Block 1 at address 0FEh. At reset, the Protection Word is copied into the FMAR1 register. 15 13 12 10 9 7 6 4 3 1 0 WRPROT RDPROT ISPE EMPTY BOOTAREA BOOTAREA The BOOTAREA field specifies the size of the Boot Area. The Boot Area starts at address 0 and ends at the address specified by this field. The inverted bits of the BOOTAREA field count the number of 2048-byte blocks to be reserved as the Boot Area. The maximum Boot Area size is 30K bytes (address range 0 to 77FFh). The end of the Boot Area defines the start of the Code Area. If the device starts in ISP mode and there is no Boot Area defined EMPTY (encoding 1111b), the device is kept in reset. 0100 0011 0010 0001 0000 ISPE The EMPTY field indicates whether the flash program memory has been programmed or should be treated as blank. If a majority of the three EMPTY bits are clear, the flash program memory is treated as programmed. If a majority of the EMPTY bits are set, the flash program memory is treated as empty. If the ENV[1:0] inputs (see Section 6.1) are sampled high at reset and the EMPTY bits indicate the flash program memory is empty, the device will begin execution in ISP mode. The device enters ISP mode without regard to the EMPTY status if ENV0 is driven low and ENV1 is driven high. The ISPE field indicates whether the Boot Area is used to hold In-System-Programming routines or user application routines. If a majority of the three ISPE bits are set, the Boot Area is intended to store ISP routines. If majority of the ISPE bits are clear, the Boot Area holds user application routines. Table 15 summarizes all possible EMPTY, ISPE, and Boot Area settings and the corresponding start-up operation for each combination. In DEV mode, the EMPTY bit settings are ignored and the CPU always starts executing from address 0. www.national.com 34 CP3CN23 Table 15 CPU Reset Behavior EMPTY ISPE Boot Area Start-Up Operation Device starts in IRE/ ERE mode from Code Area start address Device starts in IRE/ ERE mode from Code Area start address Table 16 Flash Memory Interface Registers Program Memory FMIBAR FF F940h FMIBDR FF F942h FM0WER FF F944h FM1WER FF F946h FMCTRL FF F94Ch FMSTAT FF F94Eh FMPSR FF F950h FMSTART FF F952h FMTRAN FF F954h FMPROG FF F956h FMPERASE FF F958h FMMERASE0 FF F95Ah FMEND FF F95Eh FMMEND FF F960h FMRCV FF F962h FMAR0 FF F964h FMAR1 FF F966h FMAR2 FF F968h Data Memory FSMIBAR FF F740h FSMIBDR FF F742h FSM0WER FF F744h N/A FSMCTRL FF F74Ch FSMSTAT FF F74Eh FSMPSR FF F750h FSMSTART FF F752h FSMTRAN FF F754h FSMPROG FF F756h FSMPERASE FF F758h FSMMERASE0 FF F75Ah FSMEND FF F75Eh FSMMEND FF F760h FSMRCV FF F762h FSMAR0 FF F764h FSMAR1 FF F766h FSMAR2 FF F768h Description Flash Memory Information Block Address Register Flash Memory Information Block Address Register Flash Memory 0 Write Enable Register Flash Memory 1 Write Enable Register Flash Memory Control Register Flash Memory Status Register Flash Memory Prescaler Register Flash Memory Start Time Reload Register Flash Memory Transition Time Reload Register Flash Memory Programming Time Reload Register Flash Memory Page Erase Time Reload Register Flash Memory Module Erase Time Reload Register 0 Flash Memory End Time Reload Register Flash Memory Module Erase End Time Reload Register Flash Memory Recovery Time Reload Register Flash Memory Auto-Read Register 0 Flash Memory Auto-Read Register 1 Flash Memory Auto-Read Register 2 Not Empty ISP Defined Not Empty ISP Not Defined Not Empty No ISP Device starts in IRE/ Don’t Care ERE mode from address 0 Defined Not Defined Don’t Care Device starts in ISP mode from Code Area start address Device starts in ISP mode and is kept in its reset state Empty ISP Empty Empty RDPROT ISP No ISP WRPROT The RDPROT field controls the global read protection mechanism for the on-chip flash program memory. If a majority of the three RDPROT bits are clear, the flash program memory is protected against read access from the serial debug interface or an external flash programmer. CPU read access is not affected by the RDPROT bits. If a majority of the RDPROT bits are set, read access is allowed. The WRPROT field controls the global write protection mechanism for the on-chip flash program memory. If a majority of the three WRPROT bits are clear, the flash program memory is protected against write access from any source and read access from the serial debug interface. If a majority of the WRPROT bits are set, write access is allowed. 8.5 FLASH MEMORY INTERFACE REGISTERS There is a separate interface for the program flash and data flash memories. The same set of registers exist in both interfaces. In most cases they are independent of each other, but in some cases the program flash interface controls the interface for both memories, as indicated in the following sections. Table 16 lists the registers. 35 www.national.com CP3CN23 8.5.1 Flash Memory Information Block Address Register (FMIBAR/FSMIBAR) 8.5.3 Flash Memory 0 Write Enable Register (FM0WER/FSM0WER) The FMIBAR register specifies the 8-bit address for read or write access to an information block. Because only word access to the information blocks is supported, the least significant bit (LSB) of the FMIBAR must be 0 (word-aligned). The hardware automatically clears the LSB, without regard to the value written to the bit. The FMIBAR register is cleared after device reset. The CPU bus master has read/write access to this register. 15 Reserved 8 7 IBA 0 The FM0WER register controls section-level write protection for the first half of the flash program memory. The FMS0WER registers controls section-level write protection for the flash data memory. Each data block is divided into 16 8K-byte sections. Each bit in the FM0WER and FSM0WER registers controls write protection for one of these sections. The FM0WER and FSM0WER registers are cleared after device reset, so the flash memory is write protected after reset. The CPU bus master has read/write access to this registers. 15 FM0WE 0 IBA The Information Block Address field holds the word-aligned address of an information block location accessed during a read or write FM0WEn transaction. The LSB of the IBA field is always clear. Flash Memory Information Block Data Register (FMIBDR/FSMIBDR) 8.5.2 The Flash Memory 0 Write Enable n bits control write protection for a section of a flash memory data block. The address mapping of the register bits is shown below. Bit 0 1–14 15 Logical Address Range 00 0000h–00 1FFFh ... 01 E000h–01 FFFFh The FMIBDR register holds the 16-bit data for read or write access to an information block. The FMIBDR register is cleared after device reset. The CPU bus master has read/ write access to this register. 15 IBD 0 8.5.4 Flash Memory 1 Write Enable Register (FM1WER) IBD The Information Block Data field holds the data word for access to an information block. For write operations the IBD field holds the data word to be programmed into the information block location specified by the IBA address. During a read operation from an information block, the IBD field receives the data word read from the location specified by the IBA address. The FM1WER register controls write protection for the second half of the program flash memory. The data block is divided into 16 8K-byte sections. Each bit in the FM1WER register controls write protection for one of these sections. The FM1WER register is cleared after device reset, so the flash memory is write protected after reset. The CPU bus master has read/write access to this registers. 15 FM1WE 0 FM1WEn The Flash Memory 1 Write Enable n bits control write protection for a section of a flash memory data block. The address mapping of the register bits is shown below. Bit 0 1–14 15 Logical Address Range 02 0000h–02 1FFFh ... 03 E000h–03 FFFFh www.national.com 36 CP3CN23 8.5.5 Flash Data Memory 0 Write Enable Register (FSM0WER) DISVRF The FSM0WER register controls write protection for the flash data memory. The data block is divided into 16 512byte sections. Each bit in the FSM0WER register controls write protection for one of these sections. The FSM0WER register is cleared after device reset, so the flash memory is write protected after reset. The CPU bus master has read/ write access to this registers. 15 FSM0WE 0 IENPROG FSM0WEn The Flash Data Memory 0 Write Enable n bits control write protection for a section of a flash PE memory data block. The address mapping of the register bits is shown below. Bit 0 1–14 15 Logical Address Range 0D 0000h–0D 01FFh ... 0D 1E00h–0D 1FFFh PER 8.5.6 Flash Memory Control Register (FMCTRL/ FSMCTRL) This register controls the basic functions of the Flash program memory. The register is clear after device reset. The CPU bus master has read/write access to this register. 7 6 5 4 3 2 1 0 MER PER PE IENPROG DISVRF Res. CWD LOWPRW LOWPRW CWD The Low Power Mode controls whether flash program memory is operated in low-power mode, which draws less current when data is read. This is accomplished be only accessing MER the flash program memory during the first half of the clock period. The low-power mode must not be used at System Clock frequencies above 25 MHz, otherwise a read access may return undefined data. This bit must not be changed while the flash program memory is busy being programmed or erased. 0 – Normal mode. 1 – Low-power mode. The CPU Write Disable bit controls whether the CPU has write access to flash memory. This bit must not be changed while FMBUSY is set. 0 – The CPU has write access to the flash memory 1 – An external debugging tool is the current “owner” of the flash memory interface, so write accesses by the CPU are inhibited. The Disable Verify bit controls the automatic verification feature. This bit must not be changed while the flash program memory is busy being programmed or erased. 0 – New flash program memory contents are automatically verified after programming. 1 – Automatic verification is disabled. The Interrupt Enable for Program bit is clear after reset. The flash program and data memories share a single interrupt channel but have independent interrupt enable control bits. 0 – No interrupt request is asserted to the ICU when the FMFULL bit is cleared. 1 – An interrupt request is made when the FMFULL bit is cleared and new data can be written into the write buffer. The Program Enable bit controls write access of the CPU to the flash program memory. This bit must not be altered while the flash program memory is busy being programmed or erased. The PER and MER bits must be clear when this bit is set. 0 – Programming the flash program memory by the CPU is disabled. 1 – Programming the flash program memory is enabled. The Page Erase Enable bit controls whether a a valid write operation triggers an erase operation on a 1024-byte page of flash memory. Page erase operations are only supported for the main blocks, not the information blocks. A page erase operation on an information block is ignored and does not alter the information block. When the PER bit is set, the PE and MER bits must be clear. This bit must not be changed while the flash program memory is busy being programmed or erased. 0 – Page erase mode disabled. Write operations are performed normally. 1 – A valid write operation to a word location in program memory erases the page that contains the word. The Module Erase Enable bit controls whether a valid write operation triggers an erase operation on an entire block of flash memory. If an information block is written in this mode, both the information block and its corresponding main block are erased. When the MER bit is set, the PE and PER bits must be clear. This bit must not be changed while the flash program memory is busy being programmed or erased. 0 – Module erase mode disabled. Write operations are performed normally. 1 – A valid write operation to a word location in a main block erases the block that contains the word. A valid write operation to a word location in an information block erases the block that contains the word and its associated main block. 37 www.national.com CP3CN23 8.5.7 Flash Memory Status Register (FMSTAT/ FSMSTAT) DERR This register reports the currents status of the on-chip Flash memory. The FLSR register is clear after device reset. The CPU bus master has read/write access to this register. 7 5 4 3 2 1 0 Reserved DERR FMFULL FMBUSY PERR EERR 8.5.8 The Data Loss Error bit indicates that a buffer overrun has occurred during a programming sequence. After a data loss error occurs, software can clear the DERR bit by writing a 1 to it. Writing a 0 to the DERR bit has no effect. Software must not change this bit while the flash program memory is busy being programmed or erased. 0 – No data loss error occurred. 1 – Data loss error occurred. Flash Memory Prescaler Register (FMPSR/ FSMPSR) EERR PERR FMBUSY FMFULL The Erase Error bit indicates whether an error has occurred during a page erase or module (block) erase. After an erase error occurs, software can clear the EERR bit by writing a 1 to it. Writing a 0 to the EERR bit has no effect. Software must not change this bit while the flash program memory is busy being programmed or erased. 0 – The erase operation was successful. 1 – An erase error occurred. The Program Error bit indicates whether an error has occurred during programming. After a programming error occurs, software can clear the PERR bit by writing a 1 to it. Writing a 0 to the PERR bit has no effect. Software must not change this bit while the flash program memory is busy being programmed or erased. 0 – The programming operation was successful. 1 – A programming error occurred. The Flash Memory Busy bit indicates whether the flash memory (either main block or information block) is busy being programmed or erased. During that time, software must not request any further flash memory operations. If such an attempt is made, the CPU is stopped as long as the FMBUSY bit is active. The CPU must not attempt to read from program memory (including instruction fetches) while it is busy. 0 – Flash memory is ready to receive a new erase or programming request. 1 – Flash memory busy with previous erase or programming operation. The Flash Memory Buffer Full bit indicates whether the write buffer for programming is full or not. When the buffer is full, new erase and write requests may not be made. The IENPROG bit can be enabled to trigger an interrupt when the buffer is ready to receive a new request. 0 – Buffer is ready to receive new erase or write requests. 1 – Buffer is full. No new erase or write requests can be accepted. The FMPSR register is a byte-wide read/write register that selects the prescaler divider ratio. The CPU must not modify this register while an erase or programming operation is in progress (FMBUSY is set). At reset, this register is initialized to 04h if the flash memory is idle. The CPU bus master has read/write access to this register. 7 Reserved 5 4 FTDIV 0 FTDIV 8.5.9 The prescaler divisor scales the frequency of the System Clock by a factor of (FTDIV + 1). Flash Memory Start Time Reload Register (FMSTART/FSMSTART) The FMSTART/FSMSTART register is a byte-wide read/ write register that controls the program/erase start delay time. Software must not modify this register while a program/erase operation is in progress (FMBUSY set). At reset, this register is initialized to 18h if the flash memory is idle. The CPU bus master has read/write access to this register. 7 FTSTART 0 FTSTART The Flash Timing Start Delay Count field generates a delay of (FTSTART + 1) prescaler output clocks. www.national.com 38 CP3CN23 8.5.10 Flash Memory Transition Time Reload Register (FMTRAN/FSMTRAN) 8.5.13 Flash Memory Module Erase Time Reload Register 0 (FMMERASE0/FSMMERASE0) The FMTRAN/FMSTRAN register is a byte-wide read/write register that controls some program/erase transition times. Software must not modify this register while program/erase operation is in progress (FMBUSY set). At reset, this register is initialized to 30h if the flash memory is idle. The CPU bus master has read/write access to this register. 7 FTTRAN 0 The FMMERASE0/FSMMERASE0 register is a byte-wide read/write register that controls the module erase pulse width. Software must not modify this register while a program/erase operation is in progress (FMBUSY set). At reset, this register is initialized to EAh if the flash memory is idle. The CPU bus master has read/write access to this register. 7 FTMER 0 FTTRAN The Flash TIming Transition Count field specifies a delay of (FTTRAN + 1) prescaler output clocks. Flash Memory Programming Time Reload Register (FMPROG/FSMPROG) FTMER 8.5.11 The Flash Timing Module Erase Pulse Width field specifies a module erase pulse width of 4096 × (FTMER + 1) prescaler output clocks. Flash Memory End Time Reload Register (FMEND/FSMEND) 8.5.14 The FMPROG/FSMPROG register is a byte-wide read/write register that controls the programming pulse width. Software must not modify this register while a program/erase operation is in progress (FMBUSY set). At reset, this register is initialized to 16h if the flash memory is idle. The CPU bus master has read/write access to this register. 7 FTPROG 0 The FMEND/FSMEND register is a byte-wide read/write register that controls the delay time after a program/erase operation. Software must not modify this register while a program/erase operation is in progress (FMBUSY set). At reset, this register is initialized to 18h when the flash memory on the chip is idle. The CPU bus master has read/write access to this register. 7 FTEND 0 FTPROG The Flash Timing Programming Pulse Width field specifies a programming pulse width of 8 × (FTPROG + 1) prescaler output clocks. FTEND 8.5.12 Flash Memory Page Erase Time Reload Register (FMPERASE/FSMPERASE) 8.5.15 The Flash Timing End Delay Count field specifies a delay of (FTEND + 1) prescaler output clocks. Flash Memory Module Erase End Time Reload Register (FMMEND/FSMMEND) The FMPERASE/FSMPERASE register is a byte-wide read/write register that controls the page erase pulse width. Software must not modify this register while a program/ erase operation is in progress (FMBUSY set). At reset, this register is initialized to 04h if the flash memory is idle. The CPU bus master has read/write access to this register. 7 FTPER 0 The FMMEND/FSMMEND register is a byte-wide read/write register that controls the delay time after a module erase operation. Software must not modify this register while a program/erase operation is in progress (FMBUSY set). At reset, this register is initialized to 3Ch if the flash memory is idle. The CPU bus master has read/write access to this register. 7 0 FTMEND FTPER The Flash Timing Page Erase Pulse Width field specifies a page erase pulse width of 4096 × (FTPER + 1) prescaler output clocks. FTMEND The Flash Timing Module Erase End Delay Count field specifies a delay of 8 × (FTMEND + 1) prescaler output clocks. 39 www.national.com CP3CN23 8.5.16 Flash Memory Recovery Time Reload Register (FMRCV/FSMRCV) 8.5.18 Flash Memory Auto-Read Register 1 (FMAR1/ FSMAR1) The FMRCV/FSMRCV register is a byte-wide read/write register that controls the recovery delay time between two flash memory accesses. Software must not modify this register while a program/erase operation is in progress (FMBUSY set). At reset, this register is initialized to 04h if the flash memory is idle. The CPU bus master has read/write access to this register. 7 FTRCV 0 The FMAR1 register contains a copy of the Protection Word from Information Block 1. The Protection Word is sampled at reset. The contents of the FMAR1 register define the current Flash memory protection settings. The CPU bus master has read-only access to this register. The FSMAR1 register has the same value as the FMAR1 register. The format is the same as the format of the Protection Word (see Section 8.4.2). 15 13 12 10 9 7 6 4 3 1 0 WRPROT RDPROT ISPE EMPTY BOOTAREA 1 FTRCV The Flash Timing Recovery Delay Count field specifies a delay of (FTRCV + 1) prescaler output clocks. Flash Memory Auto-Read Register 0 (FMAR0/ FSMAR0) 8.5.19 Flash Memory Auto-Read Register 2 (FMAR2/ FSMAR2) 8.5.17 The FMAR0/FSMAR0 register contains a copy of the Function Word from Information Block 0. The Function Word is sampled at reset. The CPU bus master has read-only access to this register. The FSMAR0 register has the same The FSMAR2 register has the same value as the FMAR2 register. value as the FMAR0 register 15 Reserved 0 7 CADR7:0 0 The FMAR2 register is a word-wide read-only register, which is loaded during reset. It is used to build the Code Area start address. At reset, the CPU executes a branch, using the contents of the FMAR2 register as displacement. The CPU bus master has read-only access to this register. 15 CADR15 14 CADR14:11 11 10 CADR10:8 8 CADR10:0 The Code Area Start Address (bits 10:0) contains the lower 11 bits of the Code Area start address. The CADR10:0 field has a fixed value of 0. CADR14:11 The Code Area Start Address (bits 14:11) are loaded during reset with the inverted value of BOOTAREA3:0. CADR15 The Code Area Start Address (bits 15) contains the upper bit of the Code Area start address. The CADR15 field has a fixed value of 0. www.national.com 40 CP3CN23 9.0 DMA Controller Table 17 DMA Channel Assignment Channel 0 (Primary) 0 (Secondary) 1 (Primary) 1 (Secondary) 2 (Primary) 2 (Secondary) 3 (Primary) 3 (Secondary) Peripheral Reserved USART USART Reserved Audio Interface CVSD/PCM Transcoder Audio Interface CVSD/PCM Transcoder Transaction N/A R W N/A R R W W Register N/A RXBUF TXBUF N/A ARDR0 PCMOUT ATDR0 PCMIN The DMA Controller (DMAC) has a register-based programming interface, as opposed to an interface based on I/O control blocks. After loading the registers with source and destination addresses, as well as block size and type of operation, a DMAC channel is ready to respond to DMA transfer requests. A request can only come from on-chip peripherals or software, not external peripherals. On receiving a DMA transfer request, if the channel is enabled, the DMAC performs the following operations: 1. Arbitrates to become master of the CPU bus. 2. Determines priority among the DMAC channels, one clock cycle before T1 of the DMAC transfer cycle. (T1 is the first clock cycle of the bus cycle.) Priority among the DMAC channels is fixed in descending order, with Channel 0 having the highest priority. 3. Executes data transfer bus cycle(s) selected by the values held in the control registers of the channel being serviced, and according to the accessed memory address. The DMAC acknowledges the request during the bus cycle that accesses the requesting device. 4. If the transfer of a block is terminated, the DMAC does the following: Updates the termination bits. Generates an interrupt (if enabled). Goes to step 6. 5. If DMRQn is still active, and the Bus Policy is “continuous”, returns to step 3. 6. Returns mastership of the CPU bus to the CPU. Each DMAC channel can be programmed for direct (flyby) or indirect (memory-to-memory) data transfers. Once a DMAC transfer cycle is in progress, the next transfer request is sampled when the DMAC acknowledge is de-asserted, then on the rising edge of every clock cycle. The configuration of either address freeze or address update (increment or decrement) is independent of the number of transferred bytes, transfer direction, or number of bytes in each DMAC transfer cycle. All these can be configured for each channel by programming the appropriate control registers. Each DMAC channel has eight control registers. DMAC channels are described hereafter with the suffix n, where n = 0 to 3, representing the channel number in the registernames. 9.2 TRANSFER TYPES The DMAC uses two data transfer modes, Direct (Flyby) and Indirect (Memory-to-Memory). The choice of mode depends on the required bus performance and whether direct mode is available for the transfer. Indirect mode must be used when the source and destination have differing bus widths, when both the source and destination are in memory, and when the destination does not support direct mode. 9.2.1 Direct (Flyby) Transfers In direct mode each data item is transferred using a single bus cycle, without reading the data into the DMAC. It provides the fastest transfer rate, but it requires identical source and destination bus widths. The DMAC cannot use Direct cycles between two memory devices. One of the devices must be an I/O device that supports the Direct (Flyby) mechanism, as shown in Figure 3. Bus State T1 CLK T2 Tidle T1 DMRQ[3:0] 9.1 CHANNEL ASSIGNMENT ADDR ADCA Table 17 shows the assignment of the DMA channels to different tasks. Four channels can be shared by a primary and an secondary function. However, only one source at a time can be enabled. If a channel is used for memory block transfers, other resources must be disabled. DMACK[3:0] DS005 Figure 3. Direct DMA Cycle Followed by a CPU Cycle 41 www.national.com CP3CN23 Direct mode supports two bus policies: intermittent and continuous. In intermittent mode, the DMAC gives bus mastership back to the CPU after every cycle. In continuous mode, the DMAC remains bus master until the transfer is completed. The maximum bus throughput in intermittent mode is one transfer for every three System Clock cycles. The maximum bus throughput in continuous mode is one transfer for every clock cycle. The I/O device which made the DMA request is called the implied I/O device. The other device can be either memory or another I/O device, and is called the addressed device. Because only one address is required in direct mode, this address is taken from the corresponding ADCAn counter. The DMAC channel generates either a read or a write bus cycle, as controlled by the DMACNTLn.DIR bit. When the DMACNTLn.DIR bit is clear, a read bus cycle from the addressed device is performed, and the data is written to the implied I/O device. When the DMACNTLn.DIR bit is set, a write bus cycle to the addressed device is performed, and the data is read from the implied I/O device. The configuration of either address freeze or address update (increment or decrement) is independent of the number of transferred bytes, transfer direction, or number of bytes in each DMAC transfer cycle. All these can be configured for each channel by programming the appropriate control register. Whether 8 or 16 bits are transferred in each cycle is selected by the DMACNTLn.TCS register bit. After the data item has been transferred, the BLTCn counter is decremented by one. The ADCAn counter is updated according to the INCA and ADA fields in the DMACNTLn register. 9.2.2 Indirect (Memory-To-Memory) Transfers 9.3 OPERATION MODES The DMAC operates in three different block transfer modes: single transfer, double buffer, and auto-initialize. 9.3.1 Single Transfer Operation This mode provides the simplest way to accomplish a single block data transfer. Initialization 1. Write the block transfer addresses and byte count into the corresponding ADCAn, ADCBn, and BLTCn counters. 2. Clear the DMACNTLn.OT bit to select non-auto-initialize mode. Clear the DMASTAT.VLD bit by writing a 1 to it. 3. Set the DMACNTLn.CHEN bit to activate the channel and enable it to respond to DMA transfer requests. Termination When the BLTCn counter reaches 0: 1. The transfer operation terminates. 2. The DMASTAT.TC and DMASTAT.OVR bits are set, and the DMASTAT.CHAC bit is cleared. 3. An interrupt is generated if enabled by the DMACNTLn.ETC or DMACNTLn.EOVR bits. The DMACNTLn.CHEN bit must be cleared before loading the DMACNTLn register to avoid prematurely starting a new DMA transfer. 9.3.2 Double Buffer Operation This mode allows software to set up the next block transfer while the current block transfer proceeds. Initialization 1. Write the block transfer addresses and byte count into the ADCAn, ADCBn, and BLTCn counters. 2. Clear the DMACNTLn.OT bit to select non-auto-initialize mode. Clear the DMASTAT.VLD bit by writing a 1 to it. 3. Set the DMACNTLn.CHEN bit. This activates the channel and enables it to respond to DMA transfer requests. 4. While the current block transfer proceeds, write the addresses and byte count for the next block into the ADRAn, ADRBn, and BLTRn registers. The BLTRn register must be written last, because it sets the DMASTAT.VLD bit which indicates that all the parameters for the next transfer have been updated. In indirect (memory-to-memory) mode, data transfers use two consecutive bus cycles. The data is first read into a temporary register, and then written to the destination in the following cycle. This mode is slower than the direct (flyby) mode, but it provides support for different source and destination bus widths. Indirect mode must be used for transfers between memory devices. If an intermittent bus policy is used, the maximum throughput is one transfer for every five clock cycles. If a continuous bus policy is used, maximum throughput is one transfer for every two clock cycles. When the DMACNTLn.DIR bit is 0, the first bus cycle reads data from the source using the ADCAn counter, while the Continuation/Termination second bus cycle writes the data into the destination using When the BLTCn counter reaches 0: the ADCBn counter. When the DMACNTLn.DIR bit is set, the first bus cycle reads data from the source using the AD- 1. The DMASTAT.TC bit is set. CBn counter, while the second bus cycle writes the data into 2. An interrupt is generated if enabled by the DMACNTLn.ETC bit. the destination addressed by the ADCAn counter. 3. The DMAC channel checks the value of the VLD bit. The number of bytes transferred in each cycle is taken from the DMACNTLn.TCS register bit. After the data item has If the DMASTAT.VLD bit is set: been transferred, the BLTCn counter is decremented by 1. The channel copies the ADRAn, ADRBn, and BLTRn one. The ADCAn and ADCBn counters are updated accordvalues into the ADCAn, ADCBn, and BLTCn registers. ing to the INCA, INCB, ADA, and ADB fields in the 2. The DMASTAT.VLD bit is cleared. DMACNTLn register. 3. The next block transfer is started. www.national.com 42 CP3CN23 If the DMASTAT.VLD bit is clear: 1. 2. 3. 4. The transfer operation terminates. The channel sets the DMASTAT.OVR bit. The DMASTAT.CHAC bit is cleared. An interrupt is generated if enabled DMACNTLn.EOVR bit. by the The DMACNTLn.CHEN bit must be cleared before loading the DMACNTLn register to avoid prematurely starting a new DMA transfer. Note: The ADCBn and ADRBn registers are used only in indirect (memory-to-memory) transfer. In direct (flyby) 9.5 DEBUG MODE mode, the DMAC does not use them and therefore does not When the FREEZE signal is active, all DMA operations are copy ADRBn into ADCBn. stopped. They will start again when the FREEZE signal 9.3.3 Auto-Initialize Operation goes inactive. This allows breakpoints to be used in debug This mode allows the DMAC to continuously fill the same systems. memory area without software intervention. For each channel, use the software DMA transfer request only when the corresponding hardware DMA request is inactive and no terminal count interrupt is pending. Software can poll the DMASTAT.CHAC bit to determine whether the DMA channel is already active. After verifying the DMASTATn.CHAC bit is clear (channel inactive), check the DMASTATn.TC (terminal count) bit. If the TC bit is clear, then no terminal count condition exists and therefore no terminal count interrupt is pending. If the channel is not active and no terminal count interrupt is pending, software may request a DMA transfer. 9.6 DMA CONTROLLER REGISTER SET Initialization There are four identical sets of DMA controller registers, as 1. Write the block addresses and byte count into the ADlisted in Table 18. CAn, ADCBn, and BLTCn counters, as well as the Table 18 DMA Controller Registers ADRAn, ADRBn, and BLTRn registers. 2. Set the DMACNTLn.OT bit to select auto-initialize Name Address Description mode. 3. Set the DMACNTLn.CHEN bit to activate the channel Device A Address and enable it to respond to DMA transfer requests. ADCA0 FF F800h Counter Register Continuation Device A Address ADRA0 FF F804h When the BLTCn counter reaches 0: Register 1. The contents of the ADRAn, ADRBn, and BLTRn regisDevice B Address ters are copied to the ADCAn, ADCBn, and BLTCn ADCB0 FF F808h Counter Register counters. 2. The DMAC channel checks the value of the DMASDevice B Address ADRB0 FF F80Ch TAT.TC bit. Register If the DMASTAT.TC bit is set: Block Length BLTC0 FF F810h 1. The DMASTAT.OVR bit is set. Counter Register 2. A level interrupt is generated if enabled by the BLTR0 FF F814h Block Length Register DMACNTLn.EOVR bit. 3. The operation is repeated. DMACNTL0 FF F81Ch DMA Control Register If the DMASTAT.TC bit is clear: DMASTAT0 FF F81Eh DMA Status Register 1. The DMASTAT.TC bit is set. 2. A level interrupt is generated if enabled by the Device A Address ADCA1 FF F820h DMACNTLn.ETC bit. Counter Register 3. The DMAC operation is repeated. Device A Address ADRA1 FF F824h Termination Register The DMA transfer is terminated when the Device B Address ADCB1 FF F828h DMACNTLn.CHEN bit is cleared. Counter Register 9.4 SOFTWARE DMA REQUEST ADRB1 BLTC1 BLTR1 DMACNTL1 DMASTAT1 FF F82Ch FF F830h FF F834h FF F83Ch FF F83Eh In addition to the hardware requests from I/O devices, a DMA transfer request can also be initiated by software. A software DMA transfer request must be used for block copying between memory devices. When the DMACNTLn.SWRQ bit is set, the corresponding DMA channel receives a DMA transfer request. When the DMACNTLn.SWRQ bit is clear, the software DMA transfer request of the corresponding channel is inactive. Device B Address Register Block Length Counter Register Block Length Register DMA Control Register DMA Status Register 43 www.national.com CP3CN23 Table 18 DMA Controller Registers Name ADCA2 ADRA2 ADCB2 ADRB2 BLTC2 BLTR2 DMACNTL2 DMASTAT2 ADCA3 ADRA3 ADCB3 ADRB3 BLTC3 BLTR3 DMACNTL3 DMASTAT3 9.6.1 Address FF F840h FF F844h FF F848h FF F84Ch FF F850h FF F854h FF F85Ch FF F85Eh FF F860h FF F864h FF F868h FF F86Ch FF F870h FF F874h FF F87Ch FF F87Eh Description Device A Address Counter Register Device A Address Register Device B Address Counter Register Device B Address Register Block Length Counter Register Block Length Register DMA Control Register DMA Status Register Device A Address Counter Register Device A Address Register Device B Address Counter Register Device B Address Register Block Length Counter Register Block Length Register DMA Control Register DMA Status Register 9.6.2 Device A Address Register (ADRAn) The Device A Address register is a 32-bit, read/write register. It holds the 24-bit starting address of either the next source data block, or the next destination data area, according to the DIR bit in the DMACNTLn register. The upper 8 bits of the ADRAn register are reserved and always clear. 31 24 23 Device A Address 0 Reserved 9.6.3 Device B Address Counter Register (ADCBn) The Device B Address Counter register is a 32-bit, read/ write register. It holds the current 24-bit address of either the source data item, or the destination location, according to the DIR bit in the CNTLn register. The ADCBn register is updated after each transfer cycle by INCB field of the DMACNTLn register according to ADB bit of the DMACNTLn register. In direct (flyby) mode, this register is not used. The upper 8 bits of the ADCBn register are reserved and always clear. 31 24 23 Device B Address Counter 0 Reserved 9.6.4 Device B Address Register (ADRBn) The Device B Address register is a 32-bit, read/write register. It holds the 24-bit starting address of either the next source data block or the next destination data area, according to the DIR bit in the CNTLn register. In direct (flyby) mode, this register is not used. The upper 8 bits of the ADCRBn register are reserved and always clear. 31 24 23 Device B Address 0 Reserved Device A Address Counter Register (ADCAn) 9.6.5 Block Length Counter Register (BLTCn) The Block Length Counter register is a 16-bit, read/write register. It holds the current number of DMA transfers to be executed in the current block. BLTCn is decremented by one after each transfer cycle. A DMA transfer may consist of 1 or 2 bytes, as selected by the DMACNTLn.TCS bit. 15 Block Length Counter Note: 0000h is interpreted as 216-1 transfer cycles. 0 The Device A Address Counter register is a 32-bit, read/ write register. It holds the current 24-bit address of either the source data item or the destination location, depending on the state of the DIR bit in the CNTLn register. The ADA bit of DMACNTLn register controls whether to adjust the pointer in the ADCAn register by the step size specified in the INCA field of DMACNTLn register. The upper 8 bits of the ADCAn register are reserved and always clear. 31 24 23 Device A Address Counter 0 Reserved www.national.com 44 CP3CN23 9.6.6 Block Length Register (BLTRn) DIR The Block Length register is a 16-bit, read/write register. It holds the number of DMA transfers to be performed for the next block. Writing this register automatically sets the DMASTAT.VLD bit. 15 Block Length Note: 0000h is interpreted as 216-1 transfer cycles. 9.6.7 DMA Control Register (DMACNTLn) BPC 0 OT The DMA Control register n is a word-wide, read/write register that controls the operation of DMA channel n. This register is cleared at reset. Reserved bits must be written with 0. 7 BPC 6 OT 5 DIR 4 IND 3 2 1 0 TCS EOVR ETC CHEN 15 Res. 14 13 12 ADB 11 10 9 8 SWRQ INCB INCA ADA SWRQ CHEN ETC EOVR TCS IND The Channel Enable bit must be set to enable any DMA operation on this channel. Writing a 1 to this bit starts a new DMA transfer even if it is currently a 1. If all DMACNTLn.CHEN bits are clear, the DMA clock is disabled to reduce power. 0 – Channel disabled. 1 – Channel enabled. If the Enable Interrupt on Terminal Count bit is set, it enables an interrupt when the DMASTAT.TC bit is set. 0 – Interrupt disabled. 1 – Interrupt enabled. If the Enable Interrupt on OVR bit is set, it enables an interrupt when the DMASTAT.OVR bit is set. 0 – Interrupt disabled. 1 – Interrupt enabled. The Transfer Cycle Size bit specifies the number of bytes transferred in each DMA transfer cycle. In direct (fly-by) mode, undefined results occur if the TCS bit is not equal to the addressed memory bus width. 0 – Byte transfers (8 bits per cycle). 1 – Word transfers (16 bits per cycle). The Direct/Indirect Transfer bit specifies the transfer type. 0 – Direct transfer (flyby). 1 – Indirect transfer (memory-to-memory). ADA INCA ADB INCB The Transfer Direction bit specifies the direction of the transfer relative to Device A. 0 – Device A (pointed to by the ADCAn register) is the source. In Fly-By mode a read transaction is initialized. 1 – Device A (pointed to by the ADCAn register) is the destination. In Fly-By mode a write transaction is initialized. The Operation Type bit specifies the operation mode of the DMA controller. 0 – Single-buffer mode or double-buffer mode enabled. 1 – Auto-Initialize mode enabled. The Bus Policy Control bit specifies the bus policy applied by the DMA controller. The operation mode can be either intermittent (cycle stealing) or continuous (burst). 0 – Intermittent operation. The DMAC channel relinquishes the bus after each transaction, even if the request is still asserted. 1 – Continuous operation. The DMAC channel n uses the bus continuously as long as the request is asserted. This mode can only be used for software DMA requests. For hardware DMA requests, the BPC bit must be clear. The Software DMA Request bit is written with a 1 to initiate a software DMA request. Writing a 0 to this bit deactivates the software DMA request. The SWRQ bit must only be written when the DMRQ signal for this channel is inactive (DMASTAT.CHAC = 0). 0 – Software DMA request is inactive. 1 – Software DMA request is active. If the Device A Address Control bit is set, it enables updating the Device A address. 0 – ADCAn address unchanged. 1 – ADCAn address incremented or decremented, according to INCA field of DMACNTLn register. The Increment/Decrement ADCAn field specifies the step size for the Device A address increment/decrement. 00 – Increment ADCAn register by 1. 01 – Increment ADCAn register by 2. 10 – Decrement ADCAn register by 1. 11 – Decrement ADCAn register by 2. If the Device B Address Control bit is set, it enables updating the Device B Address. 0 – ADCBn address unchanged. 1 – ADCBn address incremented or decremented, according to INCB field of DMACNTLn register. The Increment/Decrement ADCBn field specifies the step size for the Device B address increment/decrement. 00 – Increment ADCBn register by 1. 01 – Increment ADCBn register by 2. 10 – Decrement ADCBn register by 1. 11 – Decrement ADCBn register by 2. 45 www.national.com CP3CN23 9.6.8 DMA Status Register (DMASTAT) The DMA status register is a byte-wide, read register that holds the status information for the DMA channel n. This register is cleared at reset. The reserved bits always return zero when read. The VLD, OVR and TC bits are sticky (once set by the occurrence of the specific condition, they remain set until explicitly cleared by software). These bits can be individually cleared by writing 1 to the bit positions in the DMASTAT register to be cleared. Writing 0 to these bits has no effect 7 Reserved 4 3 2 1 0 TC VLD CHAC OVR TC OVR CHAC VLD The Terminal Count bit indicates whether the transfer was completed by a terminal count condition (BLTCn Register reached 0). 0 – Terminal count condition did not occur. 1 – Terminal count condition occurred. The behavior of the Channel Overrun bit depends on the operation mode (single buffer, double buffer, or auto-initialize) of the DMA channel. In double-buffered mode (DMACNTLn.OT = 0): The OVR bit is set when the present transfer is completed (BLTCn = 0), but the parameters for the next transfer (address and block length) are not valid (DMASTAT.VLD = 0). In auto-initialize mode (DMACNTLn.OT = 1): The OVR bit is set when the present transfer is completed (BLTCn = 0), and the DMASTAT.TC bit is still set. In single-buffer mode: Operates in the same way as double-buffer mode. In single-buffered mode, the DMASTAT.VLD bit should always be clear, so it will also be set when the DMASTAT.TC bit is set. Therefore, the OVR bit can be ignored in this mode. The Channel Active bit continuously indicates the active or inactive status of the channel, and therefore, it is read only. Data written to the CHAC bit is ignored. 0 – Channel inactive. 1 – Indicates that the channel is active (CHEN bit in the CNTLn register is 1 and BLTCn > 0) The Transfer Parameters Valid bit specifies whether the transfer parameters for the next block to be transferred are valid. Writing the BLTRn register automatically sets this bit. The bit is cleared in the following cases: The present transfer is completed and the ADRAn, ADRBn (indirect mode only), and BLTR registers are copied to the ADCAn, ADCBn (indirect mode only), and BLTCn registers. Writing 1 to the VLD bit. www.national.com 46 CP3CN23 10.0 Interrupts Interrupt vector numbers are always positive, in the range 10h to 3Fh. The IVCT register contains the interrupt vector of the enabled and pending interrupt with the highest priority. The interrupt vector 10h corresponds to IRQ0 and the lowest priority, while the vector 3Fh corresponds to IRQ47 and the highest priority. The CPU performs an interrupt acThe priorities of the maskable interrupts are hardwired and knowledge bus cycle on receiving a maskable interrupt retherefore fixed. The implemented interrupts are named quest from the ICU. During the interrupt acknowledge cycle, IRQ0 through IRQ47, in which IRQ0 has the lowest priority a byte is read from address FF FE00h (IVCT register). The and IRQ47 has the highest priority. (IRQ0 is not implement- byte is used as an index into the Dispatch Table to detered, so IRQ1 is the lowest priority interrupt that normally may mine the address of the interrupt handler. occur.) Because IRQ0 is not connected to any interrupt source, it The Interrupt Control Unit (ICU) receives interrupt requests from internal and external sources and generates interrupts to the CPU. Interrupts from the timers, UARTs, Microwire/ SPI interface, and Multi-Input Wake-Up module are all maskable interrupts. The highest-priority interrupt is the Non-Maskable Interrupt (NMI), which is triggered by a falling edge received on the NMI input pin. 10.2.1 Maskable Interrupt Processing 10.1 NON-MASKABLE INTERRUPTS The Interrupt Control Unit (ICU) receives the external NMI input and generates the NMI signal driven to the CPU. The NMI input is an asynchronous input with Schmitt trigger characteristics and an internal synchronization circuit, therefore no external synchronizing circuit is needed. The NMI pin triggers an exception on its falling edge. 10.1.1 Non-Maskable Interrupt Processing would seem that the interrupt vector would never return the value 10h. If it does return a value of 10h, the entry in the dispatch table should point to a default interrupt handler that handles this error condition. One possible condition for this to occur is deassertion of the interrupt before the interrupt acknowledge cycle. 10.3 INTERRUPT CONTROLLER REGISTERS Table 19 Interrupt Controller Registers Name IVCT Address FF FE00h Description Interrupt Vector Register Non-Maskable Interrupt Status Register External NMI Trap Control and Status Register Interrupt Status Register 0 Interrupt Status Register 1 Interrupt Status Register 2 Interrupt Enable and Mask Register 0 Interrupt Enable and Mask Register 1 Interrupt Enable and Mask Register 2 Table 19 lists the ICU registers. The CPU performs an interrupt acknowledge bus cycle when beginning to process a non-maskable interrupt. At reset, NMI interrupts are disabled and must remain disabled until software initializes the interrupt table, interrupt base register (INTBASE), and the interrupt mode. The external NMI interrupt is enabled by setting the EXNMI.ENLCK bit and will remain enabled until a reset occurs. Alternatively, the external NMI interrupt can be enabled by setting the EXNMI.EN bit and will remain enabled until an interrupt event or a reset occurs. NMISTAT FF FE02h 10.2 MASKABLE INTERRUPTS EXNMI FF FE04h The ICU receives level-triggered interrupt request signals from 47 sources and generates a vectored interrupt to the CPU when required. Priority among the implemented interrupt sources (named IRQ1 through IRQ47) is fixed. The maskable interrupts are globally enabled and disabled by the E bit in the PSR register. The EI and DI instructions are used to set (enable) and clear (disable) this bit. The global maskable interrupt enable bit (I bit in the PSR) must also be set before any maskable interrupts are taken. Each interrupt source can be individually enabled or disabled under software control through the ICU interrupt enable registers and also through interrupt enable bits in the peripherals that request the interrupts. The ICU supports IRQ0, but in the CP3CN23 it is not connected to any interrupt source. ISTAT0 ISTAT1 ISTAT2 IENAM0 IENAM1 IENAM2 FF FE0Ah FF FE0Ch FF FE20h FF FE0Eh FF FE10h FF FE22h 47 www.national.com CP3CN23 10.3.1 Interrupt Vector Register (IVCT) 10.3.3 The IVCT register is a byte-wide read-only register which reports the encoded value of the highest priority maskable interrupt that is both asserted and enabled. The valid range is from 10h to 3Fh. The register is read by the CPU during an interrupt acknowledge bus cycle, and INTVECT is valid during that time. It may contain invalid data while INTVECT is updated. 7 0 6 0 5 INTVECT 0 External NMI Trap Control and Status Register (EXNMI) The EXNMI register is a byte-wide read/write register. It indicates the current value of the NMI pin and controls the NMI interrupt trap generation based on a falling edge of the NMI pin. TST, EN and ENLCK are cleared on reset. When writing to this register, all reserved bits must be written with 0 for the device to function properly 7 Reserved 3 2 ENLCK 1 PIN 0 EN INTVECT The Interrupt Vector field indicates the highest priority interrupt which is both asserted and enabled. EN 10.3.2 Non-Maskable Interrupt Status Register (NMISTAT) The NMISTAT register is a byte-wide read-only register. It holds the status of the current pending Non-Maskable Interrupt (NMI) requests. On the CP3CN23, the external NMI input is the only source of NMI interrupts. The NMISTAT register is cleared on reset and each time its contents are read. 7 Reserved 1 0 EXT EXT The External NMI request bit indicates whether an external non-maskable interrupt request has occurred. Refer to the description of the EXNMI register below for additional details. 0 – No external NMI request. 1 – External NMI request has occurred. PIN ENLCK The EXNMI trap enable bit is one of two bits that can be used to enable NMI interrupts. The bit is cleared by hardware at reset and whenever the NMI interrupt occurs (EXNMI.EXT set). It is intended for applications where the NMI input toggles frequently but nested NMI traps are not desired. For these applications, the EN bit needs to be re-enabled before exiting the trap handler. When used this way, the ENLCK bit should never be set. The EN bit can be set and cleared by software (software can set this bit only if EXNMI.EXT is cleared), and should only be set after the interrupt base register and the interrupt stack pointer have been set up. 0 – NMI interrupts not enabled by this bit (but may be enabled by the ENLCK bit). 1 – NMI interrupts enabled. The PIN bit indicates the state (non-inverted) on the NMI input pin. This bit is read-only, data written into it is ignored. 0 – NMI pin not asserted. 1 – NMI pin asserted. The EXNMI trap enable lock bit is used to permanently enable NMI interrupts. Only a device reset can clear the ENLCK bit. This allows the external NMI feature to be enabled after the interrupt base register and the interrupt stack pointer have been set up. When the ENLCK bit is set, the EN bit is ignored. 0 – NMI interrupts not enabled by this bit (but may be enabled by the EN bit). 1 – NMI interrupts enabled. www.national.com 48 CP3CN23 10.3.4 Interrupt Enable and Mask Register 0 (IENAM0) 10.3.7 Interrupt Status Register 0 (ISTAT0) The IENAM0 register is a word-wide read/write register which holds bits that individually enable and disable the maskable interrupt sources IRQ1 through IRQ15. The register is initialized to FFFFh at reset. 15 IENA 1 0 Res. The ISTAT0 register is a word-wide read-only register. It indicates which maskable interrupt inputs to the ICU are active. These bits are not affected by the state of the corresponding IENA bits. 15 IST 1 0 Res. IENA Each Interrupt Enable bit enables or disables the corresponding interrupt request IRQ1 through IRQ15, for example IENA15 controls IRQ15. Because IRQ0 is not used, IENA0 is ignored. 0 – Interrupt is disabled. 1 – Interrupt is enabled. Interrupt Enable and Mask Register 1 (IENAM1) IST The Interrupt Status bits indicate if a maskable interrupt source is signalling an interrupt request. IST15:1 correspond to IRQ15 to IRQ1 respectively. Because the IRQ0 interrupt is not used, bit 0 always reads back 0. 0 – Interrupt is not active. 1 – Interrupt is active. Interrupt Status Register 1 (ISTAT1) 10.3.5 10.3.8 The IENAM1 register is a word-wide read/write register which holds bits that individually enable and disable the maskable interrupt sources IRQ16 through IRQ31. The register is initialized to FFFFh at reset. 15 IENA 0 The ISTAT1 register is a word-wide read-only register. It indicates which maskable interrupt inputs into the ICU are active. These bits are not affected by the state of the corresponding IENA bits. 15 IST 0 IENA Each Interrupt Enable bit enables or disables the corresponding interrupt request IRQ16 through IRQ31, for example IENA31 controls IRQ31. 0 – Interrupt is disabled. 1 – Interrupt is enabled. Interrupt Enable and Mask Register 2 (IENAM2) IST The Interrupt Status bits indicate if a maskable interrupt source is signalling an interrupt request. IST31:16 correspond to IRQ31 to IRQ16, respectively. 0 – Interrupt is not active. 1 – Interrupt is active. Interrupt Status Register 2 (ISTAT2) 10.3.6 10.3.9 The IENAM2 register is a word-wide read/write register which holds bits that individually enable and disable the maskable interrupt sources IRQ32 through IRQ47. The register is initialized to FFFFh at reset. 15 IENA 0 The ISTAT2 register is a word-wide read-only register. It indicates which maskable interrupt inputs into the ICU are active. These bits are not affected by the state of the corresponding IENA bits. 15 IST 0 IENA Each Interrupt Enable bit enables or disables the corresponding interrupt request IRQ32 through IRQ47, for example IENA47 controls IRQ47. 0 – Interrupt is disabled. 1 – Interrupt is enabled. IST The Interrupt Status bits indicate if a maskable interrupt source is signalling an interrupt request. IST47:32 correspond to IRQ47 to IRQ32, respectively. 0 – Interrupt is not active. 1 – Interrupt is active. 49 www.national.com CP3CN23 10.4 MASKABLE INTERRUPT SOURCES Table 20 shows the interrupts assigned to various on-chip maskable interrupts. The priority of simultaneous maskable interrupts is linear, with IRQ47 having the highest priority. Table 20 Maskable Interrupts Assignment IRQ Number IRQ47 IRQ46 IRQ45 IRQ44 IRQ43 IRQ42 IRQ41 IRQ40 IRQ39 IRQ38 IRQ37 IRQ36 IRQ35 IRQ34 IRQ33 IRQ32 IRQ31 IRQ30 IRQ29 IRQ28 IRQ27 IRQ26 IRQ25 IRQ24 IRQ23 IRQ22 IRQ21 IRQ20 IRQ19 IRQ18 IRQ17 IRQ16 IRQ15 www.national.com Description TWM (Timer 0) Reserved Reserved Reserved Reserved Reserved Reserved Reserved DMA Channel 0 DMA Channel 1 DMA Channel 2 DMA Channel 3 CAN0 Advanced Audio Interface (AAI) UART0 RX CVSD/PCM Converter ACCESS.bus TA (Timer input A) TB (Timer input B) VTUA (VTU Interrupt Request 1) VTUB (VTU Interrupt Request 2) VTUC (VTU Interrupt Request 3) VTUD (VTU Interrupt Request 4) Microwire/SPI RX/TX UART0 TX UART0 CTS CAN1 UART1 RX UART1 TX UART2 RX UART2 TX UART3 RX UART3 TX 50 IRQ Number IRQ14 IRQ13 IRQ12 IRQ11 IRQ10 IRQ9 IRQ8 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 IRQ0 Reserved ADC (Done) Description MIWU Interrupt 0 MIWU Interrupt 1 MIWU Interrupt 2 MIWU Interrupt 3 MIWU Interrupt 4 MIWU Interrupt 5 MIWU Interrupt 6 MIWU Interrupt 7 Reserved Random Number Generator (RNG) Reserved Flash Program/Data Memory Reserved All reserved interrupt vectors should point to default or error interrupt handlers. 10.5 NESTED INTERRUPTS Nested NMI interrupts are always enabled. Nested maskable interrupts are disabled by default, however an interrupt handler can allow nested maskable interrupts by setting the I bit in the PSR. The LPR instruction is used to set the I bit. Nesting of specific maskable interrupts can be allowed by disabling interrupts from sources for which nesting is not allowed, before setting the I bit. Individual maskable interrupt sources can be disabled using the IENAM0 and IENAM1 registers. Any number of levels of nested interrupts are allowed, limited only by the available memory for the interrupt stack. CP3CN23 11.0 Triple Clock and Reset The Triple Clock and Reset module generates a 12 MHz Main Clock and a 32.768 kHz Slow Clock from external crystal networks or external clock sources. It provides various clock signals for the rest of the chip. It also provides the main system reset signal, a power-on reset function, Main TWM (Invalid Watchdog Service) Flash Interface (Program/Erase Busy) External Reset Reset Clock prescalers to generate two additional low-speed clocks, and a 32-kHz oscillator start-up delay. Figure 4 is block diagram of the Triple Clock and Reset module. Device Reset Reset Module Stretched Reset Power-On-Reset Module (POR) Stop Main Osc. Preset X1CKI Stop Main Osc Start-Up-Delay 14-Bit Timer X1CKO High Frequency Oscillator Good Main Clock 4-Bit Aux1 Prescaler 4-Bit Aux2 Prescaler Auxiliary Clock 1 Auxiliary Clock 2 Main Clock Div. by 2 8-Bit Prescaler Mux Slow Clock Slow Clock Prescaler Low Frequency Oscillator X2CKI Slow Clock Select Start-Up-Delay 8-Bit Timer Time-out Good Slow Clock X2CKO Preset Stop Slow Osc Bypass 32 kHz Osc Fast Clock Prescaler 4-Bit Prescaler Mux System Clock Fast Clock Select Mux PLL Clock PLL (x3, x4, or x5) Bypass PLL Good PLL Clock Stop PLL Stop PLL DS006 Figure 4. Triple Clock and Reset Module 51 www.national.com CP3CN23 11.1 EXTERNAL CRYSTAL NETWORK X1CKI An external crystal network is connected to the X1CKI and X1CKO pins to generate the Main Clock, unless an external clock signal is driven on the X1CKI pin. A similar external crystal network may be used at pins X2CKI and X2CKO for the Slow Clock. If an external crystal network is not used for the Slow Clock, the Slow Clock is generated by dividing the fast Main Clock. The crystal network you choose may require external components different from the ones specified in this datasheet. In this case, consult with National’s engineers for the component specifications The crystals and other oscillator components must be placed close to the X1CKI/X1CKO and X2CKI/X2CKO device input pins to keep the printed trace lengths to an absolute minimum. Figure 5 shows the external crystal network for the X1CKI and X1CKO pins. Figure 6 shows the external crystal network for the X2CKI and X2CKO pins. Table 21 shows the component specifications for the main crystal network, and Table 22 shows the component specifications for the 32.768 kHz crystal network. C1 12 MHz Crystal X1CKO C2 GND DS189 Figure 5. Main Clock External Crystal Network X2CKI C1 32.768 kHz Crystal X2CKO C2 GND DS215 Figure 6. Slow Clock External Crystal Network Table 21 Component Values of the High Frequency Crystal Circuit Component Crystal Parameters Resonance Frequency Type Max. Serial Resistance Max. Shunt Capacitance Load Capacitance Capacitance Values 12 MHz ± 20 ppm AT-Cut 50 Ω 7 pF 22 pF 22 pF Tolerance N/A Capacitor C1, C2 20% www.national.com 52 CP3CN23 Table 22 Component Values of the Low Frequency Crystal Circuit Component Crystal Parameters Resonance Frequency Type Maximum Serial Resistance Maximum Shunt Capacitance Load Capacitance Min. Q factor Capacitor C1, C2 Capacitance Values 32.768 kHz Parallel N-Cut or XY-bar 40 kΩ 2 pF 12.5 pF 40000 25 pF Tolerance N/A 20% Choose capacitor component values in the tables to obtain the specified load capacitance for the crystal when combined with the parasitic capacitance of the trace, socket, and package (which can vary from 0 to 8 pF). As a guideline, the load capacitance is: C1 × C2 CL = --------------------- + Cparasitic C1 + C2 C2 > C1 C1 can be trimmed to obtain the desired load capacitance. The start-up time of the 32.768 kHz oscillator can vary from one to six seconds. The long start-up time is due to the high Q value and high serial resistance of the crystal necessary to minimize power consumption in Power Save mode. the Good Slow Clock signal, which indicates that the Slow Clock is stable. For systems that do not require a reduced power consumption mode, the external crystal network may be omitted for the Slow Clock. In that case, the Slow Clock can be synthesized by dividing the Main Clock by a prescaler factor. The prescaler circuit consists of a fixed divide-by-2 counter and a programmable 8-bit prescaler register. This allows a choice of clock divisors ranging from 2 to 512. The resulting Slow Clock frequency must not exceed 100 kHz. A software-programmable multiplexer selects either the prescaled Main Clock or the 32.768 kHz oscillator as the Slow Clock. At reset, the prescaled Main Clock is selected, ensuring that the Slow Clock is always present initially. Selection of the 32.768 kHz oscillator as the Slow Clock dis11.2 MAIN CLOCK ables the clock prescaler, which allows the CLK1 oscillator The Main Clock is generated by the 12-MHz high-frequency to be turned off, which reduces power consumption and raoscillator or driven by an external signal (typically the diated emissions. This can be done only if the module deLMX5251 RF chip). It can be stopped by the Power Man- tects a toggling low-speed oscillator. If the low-speed agement Module to reduce power consumption during peri- oscillator is not operating, the prescaler remains available ods of reduced activity. When the Main Clock is restarted, a as the Slow Clock source. 14-bit timer generates a Good Main Clock signal after a 11.4 PLL CLOCK start-up delay of 32,768 clock cycles. This signal is an indiThe PLL Clock is generated by the PLL from the 12 MHz cator that the high-frequency oscillator is stable. Main Clock by applying a multiplication factor of ×3, ×4, or The Stop Main Osc signal from the Power Management ×5. Module stops and starts the high-frequency oscillator. When this signal is asserted, it presets the 14-bit timer to To enable the PLL: 3FFFh and stops the high-frequency oscillator. When the 1. Set the PLL multiplication factor in PRFSC.MODE. signal goes inactive, the high-frequency oscillator starts and 2. Clear the PLL power-down bit CRCTRL.PLLPWD. the 14-bit timer counts down from its preset value. When the timer reaches zero, it stops counting and asserts the Good 3. Clear the high-frequency clock select bit CRCTRL.FCLK. Main Clock signal. 4. Read CRCTRL.FCLK, and go back to step 3 if not clear. 11.3 SLOW CLOCK The CRCTRL.FCLK bit will be clear only after the PLL has The Slow Clock is necessary for operating the device in restabilized, so software must repeat step 3 until the bit is duced power modes and to provide a clock source for modclear. The clock source can be switched back to the Main ules such as the Timing and Watchdog Module. Clock by setting the CRCTRL.FCLK bit. The Slow Clock operates in a manner similar to the Main The PRSFC register must not be modified while the System Clock. The Stop Slow Osc signal from the Power ManageClock is derived from the PLL Clock. The System Clock ment Module stops and starts the low-frequency (32.768 must be derived from the low-frequency oscillator clock kHz) oscillator. When this signal is asserted, it presets a 6while the MODE field is modified. bit timer to 3Fh and disables the low-frequency oscillator. When the signal goes inactive, the low-frequency oscillator starts, and the 6-bit timer counts down from its preset value. When the timer reaches zero, it stops counting and asserts 53 www.national.com CP3CN23 11.5 SYSTEM CLOCK The System Clock drives most of the on-chip modules, including the CPU. Typically, it is driven by the Main Clock, but it can also be driven by the PLL. In either case, the clock signal is passed through a programmable divider (scale factors from ÷1 to ÷16). rise time. The time constant also should exceed the stabilization time for the high-frequency oscillator. 11.9 CLOCK AND RESET REGISTERS Table 23 Clock and Reset Registers Name Address FF FC40h FF FC42h FF FC44h FF FC46h Description Clock and Reset Control Register High Frequency Clock Prescaler Register Low Frequency Clock Prescaler Register Auxiliary Clock Prescaler Register Table 23 lists the clock and reset registers. 11.6 AUXILIARY CLOCKS Auxiliary Clock 1 and Auxiliary Clock 2 are generated from Main Clock for use by certain peripherals. Auxiliary Clock 1 is available for the Advanced Audio Interface. Auxiliary Clock 2 is available for the CVSD/PCM transcoder and the 12-bit ADC. The Auxiliary clocks may be configured to keep these peripherals running when the System Clock is slowed down or suspended during low-power modes. CRCTRL PRSFC PRSSC PRSAC 11.9.1 11.7 POWER-ON RESET The Power-On Reset circuit generates a system reset signal at power-up and holds the signal active for a period of time to allow the crystal oscillator to stabilize. The circuit detects a power turn-on condition, which presets a 14-bit timer driven by Main Clock to a value of 3FFFh. This preset value is defined in hardware and not programmable. Once oscillation starts and the clock becomes active, the timer starts counting down. When the count reaches zero, the 14-bit timer stops counting and the internal reset signal is deactivated (unless the RESET pin is held low). The circuit sets a power-on reset bit on detection of a poweron condition. The CPU can read this bit to determine whether a reset was caused by a power-up or by the RESET input. Note: The Power-On Reset circuit cannot be used to detect a drop in the supply voltage. Clock and Reset Control Register (CRCTRL) The CRCTRL register is a byte-wide read/write register that controls the clock selection and contains the power-on reset status bit. At reset, the CRCTRL register is initialized as described below: 7 6 5 4 3 2 1 0 Reserved POR ACE2 ACE1 PLLPWD FCLK SCLK SCLK 11.8 EXTERNAL RESET The active-low RESET input can be used to reset the device at any time. When the signal goes low, it generates an internal system reset signal that remains active until the RESET FCLK signal goes high again. There is no internal pullup on this input, so it must be driven or pulled high externally for proper device operation. If the VCC power supply has slow rise-time. it may be necessary to use an external reset circuit to insure proper device initialization. Figure 7 shows an example of an external reset circuit. IOVCC IOVCC R CP3BT2x PLLPWD RESET C GND DS216 Figure 7. External Reset Circuit The value of R should be less than 50K ohms. The RC time constant of the circuit should be 5 times the power supply The Slow Clock Select bit controls the clock source used for the Slow Clock. 0 – Slow Clock driven by prescaled Main Clock. 1 – Slow Clock driven by 32.768 kHz oscillator. The Fast Clock Select bit selects between the 12 MHz Main Clock and the PLL as the source used for the System Clock. After reset, the Main Clock is selected. Attempting to switch to the PLL while the PLLPWD bit is set (PLL is turned off) is ignored. Attempting to switch to the PLL also has no effect if the PLL output clock has not stabilized. 0 – The System Clock prescaler is driven by the output of the PLL. 1 – The System Clock prescaler is driven by the 12-MHz Main Clock. This is the default after reset. The PLL Power-Down bit controls whether the PLL is active or powered down (Stop PLL signal asserted). When this bit is set, the on-chip PLL stays powered-down. Otherwise it is powered-up or it can be controlled by the Power Management Module, respectively. Before software can power-down the PLL in Active mode by setting the PLLPWD bit, the FCLK bit must be set. Attempting to set the PLLPWD bit while the FCLK bit is clear is ignored. The www.national.com 54 CP3CN23 ACE1 ACE2 POR FCLK bit cannot be cleared until the PLL clock has stabilized. After reset this bit is set. 0 – PLL is active. 1 – PLL is powered down. When the Auxiliary Clock Enable bit is set and a stable Main Clock is provided, the Auxiliary Clock 1 prescaler is enabled and generates the first Auxiliary Clock. When the ACE1 bit is clear or the Main Clock is not stable, Auxiliary Clock 1 is stopped. Auxiliary Clock 1 is used as the clock input for the Advanced Audio Interface. After reset this bit is clear. 0 – Auxiliary Clock 1 is stopped. 1 – Auxiliary Clock 1 is active if the Main Clock is stable. When the Auxiliary Clock Enable 2 bit is set and a stable Main Clock is provided, the Auxiliary Clock 2 prescaler is enabled and generates Auxiliary Clock 2. When the ACE2 bit is clear or the Main Clock is not stable, the Auxiliary Clock 2 is stopped. Auxiliary Clock 2 is used as the clock input for the CVSD/PCM transcoder and the A/D converter. After reset this bit is clear. 0 – Auxiliary Clock 2 is stopped. 1 – Auxiliary Clock 2 is active if the Main Clock is stable. Power-On-Reset - The Power-On-Reset bit is set when a power-turn-on condition has been detected. This bit can only be cleared by software, not set. Writing a 1 to this bit will be ignored, and the previous value of the bit will be unchanged. 0 – Software cleared this bit. 1 – Software has not cleared his bit since the last reset. High Frequency Clock Prescaler Register (PRSFC) low-frequency oscillator clock while the MODE field is modified. Output Frequency (from 12 MHz input clock) Reserved Reserved Reserved 36 MHz 48 MHz 60 MHz Reserved Reserved MODE2:0 Description 000 001 010 011 100 101 110 111 11.9.3 Reserved Reserved Reserved 3× Mode 4× Mode 5× Mode Reserved Reserved Low Frequency Clock Prescaler Register (PRSSC) The PRSSC register is a byte-wide read/write register that holds the clock divisor used to generate the Slow Clock from the Main Clock. The register is initialized to B6h at reset. 7 SCDIV 0 SCDIV 11.9.2 The PRSFC register is a byte-wide read/write register that holds the 4-bit clock divisor used to generate the high-frequency clock. In addition, the upper three bits are used to control the operation of the PLL. The register is initialized to 4Fh at reset (except in PROG mode.) 7 Res 6 MODE 4 3 FCDIV 0 The Slow Clock Divisor field specifies a divisor to be used when generating the Slow Clock from the Main Clock. The Main Clock is divided by a value of (2 × (SCDIV + 1)) to obtain the Slow Clock. At reset, the SCDIV register is initialized to B6h, which generates a Slow Clock rate of 32786.89 Hz. This is about 0.5% faster than a Slow Clock generated from an external 32768 Hz crystal network. Auxiliary Clock Prescaler Register (PRSAC) 11.9.4 The PRSAC register is a byte-wide read/write register that holds the clock divisor values for prescalers used to generate the two auxiliary clocks from the Main Clock. The register is initialized to FFh at reset. 4 ACDIV2 3 ACDIV2 0 FCDIV MODE 7 The Fast Clock Divisor specifies the divisor used to obtain the high-frequency System Clock from the PLL or Main Clock. The divisor is (FCDIV + 1). The PLL MODE field specifies the operation ACDIV1 mode of the on-chip PLL. After reset the MODE bits are initialized to 100b, so the PLL is configured to generate a 48-MHz clock. This register must not be modified when the ACDIV2 System Clock is derived from the PLL Clock. The System Clock must be derived from the The Auxiliary Clock Divisor 1 field specifies the divisor to be used for generating Auxiliary Clock 1 from the Main Clock. The Main Clock is divided by a value of (ACDIV1 + 1). The Auxiliary Clock Divisor 2 field specifies the divisor to be used for generating Auxiliary Clock 2 from the Main Clock. The Main Clock is divided by a value of (ACDIV2 + 1). www.national.com 55 CP3CN23 12.0 Power Management The Power Management Module (PMM) improves the efficiency of the CP3CN23 by changing the operating mode (and therefore the power consumption) according to the required level of device activity. The device implements four power modes: Active Power Save Idle Halt Table 24 summarizes the differences between power modes: the state of the high-frequency oscillator (on or off), the System Clock source (clock used by most modules), and the clock source used by the Timing and Watchdog Module (TWM). The high-frequency oscillator generates the 12-MHz Main Clock, and the low-frequency oscillator generates a 32.768 kHz clock. The Slow Clock can be driven by the 32.768 kHz clock or a scaled version of the Main Clock. Table 24 Power Mode Operating Summary Mode Active High-Frequency Oscillator On System Clock TWM Clock * The Analog/Digital Converter (ADC) module is not automatically disabled by entering Halt mode, however its clock is stopped so no conversions may be performed in Halt mode. For maximum power savings, software must disable the ADC module before entering Halt mode. A module shown as On/Off in Table 25 may be enabled or disabled by software. A module shown as Active continues to operate even while its clock is suspended, which allows wake-up events to be processed during Idle and Halt modes. The Random Number Generator (RNG) module has two oscillators which operate independently of the rest of the system. For maximum power savings, software must disable these oscillators. 12.1 ACTIVE MODE Main Clock Slow Clock Slow Clock None None Slow Clock Slow Clock None Power Save On or Off Idle Halt On or Off Off In Active mode, the high-frequency oscillator is active and generates the 12-MHz Main Clock. The 32.768 kHz oscillator is active and may be used to generate the Slow Clock. The PLL can be active or inactive, as required. Most on-chip modules are driven by the System Clock. The System Clock can be the PLL Clock after a programmable divider or the 12-MHz Main Clock. The activity of peripheral modules is controlled by their enable bits. Power consumption can be reduced in this mode by selectively disabling modules and by executing the WAIT instruction. When the WAIT instruction is executed, the CPU stops executing new instructions until it receives an interrupt signal. After reset, the CP3CN23 is in Active Mode. The low-frequency oscillator continues to operate in all four modes and power must be provided continuously to the device power supply pins. In Halt mode, however, Slow Clock does not toggle, and as a result, the TWM timer and Watchdog Module do not operate. For the Power Save and Idle modes, the high-frequency oscillator can be turned on or off under software control, as long as the low-frequency oscillator is used to drive Slow Clock. Table 25 shows the clock sources used by the CP3CN23 device modules and their behavior in each power mode. Table 25 Module Activity Summary Power Mode Module Power Active Save On On On On On/Off On On On Idle Off Halt Off Clock Source System System 12.2 POWER SAVE MODE In Power Save mode, Slow Clock is used as the System Clock which drives the CPU and most on-chip modules. If Slow Clock is driven by the 32.768 kHz oscillator and no onchip module currently requires the 12-MHz Main Clock, software can disable the high-frequency oscillator to further reduce power consumption. Auxiliary Clocks 1 and 2 can be turned off under software control before switching to a reduced power mode, or they may remain active as long as Main Clock is also active. If the system does not require the PLL output clock, the PLL can be disabled. Alternatively, the Main Clock and the PLL can also be controlled by the Hardware Clock Control function, if enabled. The clock architecture is described in Section 11.0. In Power Save mode, some modules are disabled or their operation is restricted. Other modules, including the CPU, continue to function normally, but operate at a reduced clock rate. Details of each module’s activity in Power Save mode are described in each module’s descriptions. It is recommended to keep CPU activity at a minimum by executing the WAIT instruction to guarantee low power consumption in the system. CPU MIWU PMM TWM AAI Active Active On On Active Slow Clock Off Off Off Off* Off Slow Clock Aux 1 Clock Aux 2 Clock Aux 2 Clock System On/Off On/Off On/Off CVSD/PCM On/Off On/Off On/Off ADC All Others On/Off On/Off On/Off On/Off On/Off Off www.national.com 56 CP3CN23 12.3 IDLE MODE 12.6 POWER MANAGEMENT REGISTERS In Idle mode, the System Clock is disabled and therefore the Table 26 lists the power management registers. clock is stopped to most modules of the device. The PLL Table 26 Power Management Registers and the high-frequency oscillator may be disabled as controlled by register bits. The low-frequency oscillator remains Name Address Description active. The Power Management Module (PMM) and the Timing and Watchdog Module (TWM) continue to operate Power Management PMMCR FF FC60h off the Slow Clock. Auxiliary Clocks 1 and 2 can be turned Control Register off under software control before switching to a power savPower Management ing mode, or they remain active as long as Main Clock is PMMSR FF FC62h Status Register also active. Alternatively, the 12 MHz Main Clock and the PLL can also be controlled by the Hardware Clock Control function, if enabled. 12.6.1 Power Management Control Register (PMMCR) 12.4 The Power Management Control/Status Register (PMMCR) is a byte-wide, read/write register that controls the operating In Halt mode, all the device clocks, including the System power mode (Active, Power Save, Idle, or Halt) and enables Clock, Main Clock, and Slow Clock, are disabled. The highor disables the high-frequency oscillator in the Power Save frequency oscillator and PLL are turned off. The low-freand Idle modes. At reset, the non-reserved bits of this regquency oscillator continues to operate, however its circuitry ister are cleared. The format of the register is shown below. is optimized to guarantee lowest possible power consumption. This mode allows the device to reach the absolute min7 6 5 4 3 2 1 0 imum power consumption without losing its state (memory, registers, etc.). Reserved DHC DMC WBPSM HALT IDLE PSM HALT MODE 12.5 HIGH-FREQUENCY OSCILLATOR AND PLL CONTROL Altogether, two mechanisms control whether the high-frequency oscillator is active, and three mechanisms control whether the PLL is active: PSM Disable Bits: The DMC and DHC bits in the PMMCR register may be used to disable the high-frequency oscillator and PLL, respectively, in Power Save and Idle modes. When used to disable the high-frequency oscillator or PLL, the DMC and DHC bits override the HCC mechanism. Power Management Mode: Halt mode disables the high-frequency oscillator and PLL. Active Mode enables them. The DMC and DHC bits and the HCC mechanism IDLE have no effect in Active or Halt mode. PLL Power Down Bit: The PLLPWD bit in the CRCTRL register can be used to disable the PLL in all modes. This bit does not affect the high-frequency oscillator. If the Power Save Mode bit is clear and the WBPSM bit is clear, writing 1 to the PSM bit causes the device to start the switch to Power Save mode. If the WBPSM bit is set when the PSM bit is written with 1, entry into Power Save mode is delayed until execution of a WAIT instruction. The PSM bit becomes set after the switch to Power Save mode is complete. The PSM bit can be cleared by software, and it can be cleared by hardware when a hardware wake-up event is detected. 0 – Device is not in Power Save mode. 1 – Device is in Power Save mode. The Idle Mode bit indicates whether the device has entered Idle mode. The WBPSM bit must be set to enter Idle mode. When the IDLE bit is written with 1, the device enters IDLE mode at the execution of the next WAIT instruction. The IDLE bit can be set and cleared by software. It is also cleared by the hardware when a hardware wake-up event is detected. 0 – Device is not in Idle mode. 1 – Device is in Idle mode. 57 www.national.com CP3CN23 HALT WBPSM The Halt Mode bit indicates whether the de- DMC vice is in Halt mode. Before entering Halt mode, the WBPSM bit must be set. When the HALT bit is written with 1, the device enters the Halt mode at the execution of the next WAIT instruction. When in HALT mode, the PMM stops the System Clock and then turns off the PLL and the high-frequency oscillator. The HALT bit can be set and cleared by software. The Halt mode is exited by a hardware wake-up event. When this signal is set high, the oscillator is started. After the oscillator has stabilized, the HALT bit is cleared by the hardware. DHC 0 – Device is not in Halt mode. 1 – Device is in Halt mode. When the Wait Before Power Save Mode bit is clear, a switch from Active mode to Power Save mode only requires setting the PSM bit. When the WBPSM bit is set, a switch from Active mode to Power Save, Idle, or Halt mode is performed by setting the PSM, IDLE or HALT bit, respectively, and then executing a WAIT instruction. Also, if the DMC or DHC bits are set, the high-frequency oscillator and PLL may be disabled only after a WAIT instruction is executed and the Power Save, Idle, or Halt mode is entered. 0 – Mode transitions may occur immediately. 1 – Mode transitions are delayed until the next WAIT instruction is executed. The Disable Main Clock bit may be used to disable the high-frequency oscillator in Power Save and Idle modes. In Active mode, the high-frequency oscillator is enabled without regard to the DMC value. In Halt mode, the high-frequency oscillator is disabled without regard to the DMC value. The DMC bit is cleared by hardware when a hardware wakeup event is detected. 0 – High-frequency oscillator is only disabled in Halt mode or when disabled by the HCC mechanism. 1 – High-frequency oscillator is also disabled in Power Save and Idle modes. The Disable High-Frequency (PLL) Clock bit and the CRCTRL.PLLPWD bit may be used to disable the PLL in Power Save and Idle modes. When the DHC bit is clear (and PLLPWD = 0), the PLL is enabled in these modes. If the DHC bit is set, the PLL is disabled in Power Save and Idle mode. In Active mode with the CRCTRL.PLLPWD bit set, the PLL is enabled without regard to the DHC value. In Halt mode, the PLL is disabled without regard to the DMC value. The DHC bit is cleared by hardware when a hardware wake-up event is detected. 0 – PLL is disabled only by entering Halt mode or setting the CRCTRL.PLLPWD bit. 1 – PLL is also disabled in Power Save or Idle mode. www.national.com 58 CP3CN23 12.6.2 Power Management Status Register (PMMSR) 12.7 SWITCHING BETWEEN POWER MODES The Management Status Register (PMMR) is a byte-wide, read/write register that provides status signals for the various clocks. The reset value of PMSR register bits 0 to 2 depend on the status of the clock sources monitored by the PMM. The upper 5 bits are clear after reset. The format of the register is shown below. 7 Reserved 3 2 1 0 OLC Switching from a higher to a lower power consumption mode is performed by writing an appropriate value to the Power Management Control/Status Register (PMMCR). Switching from a lower power consumption mode to the Active mode is usually triggered by a hardware interrupt. Figure 8 shows the four power consumption modes and the events that trigger a transition from one mode to another. Reset WBPSM = 1 & HAL = 1 & T "WAIT" Active Mode WBPSM = 0 & PSM = 1 or WBPSM = 1 & PSM = 1 & "WAIT" OHC OMC OLC OMC OHC The Oscillating Low Frequency Clock bit indicates whether the low-frequency oscillator is producing a stable clock. When the low-frequency oscillator is unavailable, the PMM will not switch to Power Save, Idle, or Halt mode. 0 – Low-frequency oscillator is unstable, disabled, or not oscillating. 1 – Low-frequency oscillator is available. The Oscillating Main Clock bit indicates whether the high-frequency oscillator is producing a stable clock. When the high-frequency oscillator is unavailable, the PMM will not switch to Active mode. 0 – High-frequency oscillator is unstable, disabled, or not oscillating. 1 – High-frequency oscillator is available. The Oscillating High Frequency (PLL) Clock bit indicates whether the PLL is producing a stable clock. Because the PMM tests the stability of the PLL clock to qualify power mode state transitions, a stable clock is indicated when the PLL is disabled. This removes the stability of the PLL clock from the test when the PLL is disabled. When the PLL is enabled but unstable, the PMM will not switch to Active mode. 0 – PLL is enabled but unstable. 1 – PLL is stable or disabled (CRCTRL.PLLPWD = 0). WBPSM = 1 & IDLE = 1 & "WAIT" Power Save Mode HW Event WBPSM = 1 & IDLE = 1 & "WAIT" Idle Mode IDLE = 1 HW Event Halt Mode Note: HW Event = MIWU wake-up or NMI HW Event DS008 Figure 8. Power Mode State Diagram Some of the power-up transitions are based on the occurrence of a wake-up event. An event of this type can be either a maskable interrupt or a non-maskable interrupt (NMI). All of the maskable hardware wake-up events are monitored by the Multi-Input Wake-Up (MIWU) Module, which is active in all modes. Once a wake-up event is detected, it is latched until an interrupt acknowledge cycle occurs or a reset is applied. A wake-up event causes a transition to the Active mode and restores normal clock operation, but does not start execution of the program. It is the interrupt handler associated with the wake-up source (MIWU or NMI) that causes program execution to resume. 12.7.1 Active Mode to Power Save Mode A transition from Active mode to Power Save mode is performed by writing a 1 to the PMMCR.PSM bit. The transition to Power Save mode is either initiated immediately or at execution of the next WAIT instruction, depending on the state of the PMMCR.WBPSM bit. For an immediate transition to Power Save mode (PMMCR.WBPSM = 0), the CPU continues to operate using the low-frequency clock. The PMMCR.PSM bit becomes set when the transition to the Power Save mode is completed. For a transition at the next WAIT instruction (PMMCR.WBPSM = 1), the CPU continues to operate in Active mode until it executes a WAIT instruction. At execution of the WAIT instruction, the device enters the Power Save mode, and the CPU waits for the next interrupt event. In this case, the PMMCR.PSM bit becomes set when it is written, even before the WAIT instruction is executed. 59 www.national.com CP3CN23 12.7.2 Entering Idle Mode 12.7.6 Wake-Up Transition to Active Mode Entry into Idle mode is performed by writing a 1 to the PM- A hardware wake-up event switches the device directly from MCR.IDLE bit and then executing a WAIT instruction. The Power Save, Idle, or Halt mode to Active mode. Hardware PMMCR.WBPSM bit must be set before the WAIT instruc- wake-up events are: tion is executed. Idle mode can be entered only from the AcNon-Maskable Interrupt (NMI) tive or Power Save mode. Valid wake-up event on a Multi-Input Wake-Up channel 12.7.3 Disabling the High-Frequency Clock When a wake-up event occurs, the on-chip hardware perWhen the low-frequency oscillator is used to generate the forms the following steps: Slow Clock, power consumption can be reduced further in 1. Clears the PMMCR.DMC bit, which enables the highthe Power Save or Idle mode by disabling the high-frequenfrequency clock (if it was disabled). cy oscillator. This is accomplished by writing a 1 to the PM- 2. Waits for the PMMSR.OMC bit to become set, which inMCR.DHC bit before executing the WAIT instruction that dicates that the high-frequency clock is operating and puts the device in the Power Save or Idle mode. The highis stable. frequency clock is turned off only after the device enters the 3. Clears the PMMCR.DHC bit, which enables the PLL. Power Save or Idle mode. 4. Waits for the PMMSR.OHC bit to become set. The CPU operates on the low-frequency clock in Power 5. Switches the device into Active mode. Save mode. It can turn off the high-frequency clock at any 12.7.7 Power Mode Switching Protection time by writing a 1 to the PMMCR.DHC bit. The high-frequency oscillator is always enabled in Active mode and al- The Power Management Module has several mechanisms ways disabled in Halt mode, without regard to the to protect the device from malfunctions caused by missing or unstable clock signals. PMMCR.DHC bit setting. Immediately after power-up and entry into Active mode, software must wait for the low-frequency clock to become stable before it can put the device in Power Save mode. It should monitor the PMMSR.OLC bit for this purpose. Once this bit is set, Slow Clock is stable and Power Save mode can be entered. 12.7.4 Entering Halt Mode The PMMSR.OHC, PMMSR.OMC, and PMMSR.OLC bits indicate the current status of the PLL, high-frequency oscillator, and low-frequency oscillator, respectively. Software can check the appropriate bit before switching to a power mode that requires the clock. A set status bit indicates an operating, stable clock. A clear status bit indicates a clock that is disabled, not available, or not yet stable. (Except in the case of the PLL, which has a set status bit when disabled.) During a power mode transition, if there is a request to switch to a mode with a clear status bit, the switch is delayed until that bit is set by the hardware. Entry into Halt mode is accomplished by writing a 1 to the PMMCR.HALT bit and then executing a WAIT instruction. The PMMCR.WBPSM bit must be set before the WAIT instruction is executed. Halt mode can be entered only from Active or Power Save mode. 12.7.5 When the system is built without an external crystal network Software-Controlled Transition to Active Mode for the low-frequency clock, Main Clock is divided by a presA transition from Power Save mode to Active mode can be caler factor to produce the low-frequency clock. In this situaccomplished by either a software command or a hardware ation, Main Clock is disabled only in the Halt mode, and wake-up event. The software method is to write a 0 to the cannot be disabled for the Power Save or Idle mode. PMMCR.PSM bit. The value of the register bit changes only after the transition to the Active mode is completed. Without an external crystal network for the low-frequency clock, the device comes out of Halt or Idle mode and enters If the high-frequency oscillator is disabled for Power Save Active mode with Main Clock driving Slow Clock. operation, the oscillator must be enabled and allowed to sta- Note: For correct operation in the absence of a low-frebilize before the transition to Active mode. To enable the quency crystal, the X2CKI pin must be tied low (not left floathigh-frequency oscillator, software writes a 0 to the PM- ing) so that the hardware can detect the absence of the MCR.DMC bit. Before writing a 0 to the PMMCR.PSM bit, crystal. software must first monitor the PMMSR.OMC bit to determine when the oscillator has stabilized. www.national.com 60 CP3CN23 13.0 Multi-Input Wake-Up The Multi-Input Wake-Up (MIWU) unit consists of two identical 16-channel modules. Each module can assert a wakeup signal for exiting from a low-power mode, and each can assert an interrupt request on any of four Interrupt Control Unit (ICU) channels assigned to that module. The modules operate independently, so each may assert an interrupt request to the ICU. Together, these modules provide 32 MIWU input channels and 8 interrupt request outputs. Each 16-channel module monitors its inputs for a softwareselectable trigger condition. On detection of a trigger condition, the module generates an interrupt request and if enabled, a wake-up request. A wake-up request can be used by the power management unit to exit the Halt, Idle, or Power Save mode and return to the Active mode. An interrupt request generates an interrupt to the CPU, which allows an interrupt handler to respond to MIWU events. rupt handler. Therefore, setting up the MIWU interrupt handler is essential for any wake-up operation. Each 16-channel module has four interrupt requests that can be routed to the ICU as shown in Figure 9. Each of the 16 channels can be programmed to activate one of these four interrupt requests. The 32 MIWU channels are named WUI0 through WUI31, as shown in Table 27. Each channel can be configured to trigger on rising or falling edges, as determined by the setting in the WK0EDG or WK1EDG register. Each trigger event is latched into the WK0PND or WK1PND register. If a trigger event is enabled by its respective bit in the WK0ENA or WK1ENA register, an active wake-up/interrupt signal is generated. Software can determine which channel has generated the active signal by reading the WK0PND or WK1PND register. The wake-up event only activates the clocks and CPU, but does not by itself initiate execution of any code. It is the in- The MIWU is active at all times, including the Halt mode. All terrupt request asserted by the MIWU that gets the CPU to device clocks are stopped in this mode. Therefore, detecting start executing code, by jumping to the corresponding inter- an external trigger condition and the subsequent setting of the pending bit are not synchronous to the System Clock. Peripheral Bus 15 ........... WK0IENA WK1IENA 0 WK0ICTL1/WK0ICTL2 WK1ICTL1/WK1ICTL2 WUI0 WUI16 0 4 MIWU Interrupt 3:0 MIWU Interrupt 7:4 Encoder WUI15 WUI31 WK0EDG WK1EDG 15 WK0PND WK1PND Wake-Up Signal To Power Mgt WK0ENA WK1ENA 15 ........... 0 DS218 Figure 9. Multi-Input Wake-Up Module Block Diagram 61 www.national.com CP3CN23 13.1 Table 27 MIWU Sources MIWU Channel WUI0 WUI1 WUI2 WUI3 WUI4 WUI5 WUI6 WUI7 WUI8 WUI9 WUI10 WUI11 WUI12 WUI13 WUI14 WUI15 WUI16 WUI17 WUI18 WUI19 WUI20 WUI21 WUI22 WUI23 WUI24 WUI25 WUI26 WUI27 WUI28 WUI29 WUI30 WUI31 Source TWM T0OUT ACCESS.bus CAN0RX MWCS UART0 CTS UART0 RXD Reserved AAI SFS Reserved PJ7 PG6 PH0 PH1 PH2 PH3 PH4 PH5 PH6 PJ0 PJ1 PJ2 PJ3 PJ4 PJ5 PJ6 Reserved UART1 RXD UART2 RXD UART3 RXD Reserved ADC Done CAN1RX MULTI-INPUT WAKE-UP REGISTERS Table 28 lists the MIWU registers. Table 28 Multi-Input Wake-Up Registers Name Address Description Wake-Up Edge Detection Register Module 0 Wake-Up Edge Detection Register Module 1 Wake-Up Enable Register Module 0 Wake-Up Enable Register Module 1 Wake-Up Interrupt Control Register 1 Module 0 Wake-Up Interrupt Control Register 1 Module 1 Wake-Up Interrupt Control Register 2 Module 0 Wake-Up Interrupt Control Register 2 Module 1 Wake-Up Pending Register Module 0 Wake-Up Pending Register Module 1 Wake-Up Pending Clear Register Module 0 Wake-Up Pending Clear Register Module 1 Wake-Up Interrupt Enable Register Module 0 Wake-Up Interrupt Enable Register Module 1 WK0EDG FF FC80h WK1EDG FF FCA0h WK0ENA FF FC82h WK1ENA FF FCA2h WK0ICTL1 FF FC84h WK1ICTL1 FF FCA4h WK0ICTL2 FF FC86h WK1ICTL2 FF FCA6h WK0PND FF FC88h WK1PND FF FCA8h WK0PCL FF FC8Ah WK1PCL FF FCAAh WK0IENA FF FC8Ch WK1IENA FF FCACh www.national.com 62 CP3CN23 13.1.1 Wake-Up Edge Detection Register (WK0EDG) 13.1.4 Wake-Up 1 Enable Register (WK1ENA) The WK0EDG register is a word-wide read/write register that controls the edge sensitivity of the MIWU channels. The WK0EDG register is cleared upon reset, which configures all channels to be triggered on rising edges. The register format is shown below. 15 WKED 0 The WK1ENA register is a word-wide read/write register that individually enables or disables wake-up events from the MIWU channels. The WK1ENA register is cleared upon reset, which disables all wake-up/interrupt channels. The register format is shown below. 15 WKEN 0 WKED The Wake-Up Enable bits enable and disable The Wake-Up Edge Detection bits control the WKEN the MIWU channels. The WKEN15:0 bits coredge sensitivity for MIWU channels. The respond to the WUI31:16 channels, respecWKED15:0 bits correspond to the WUI15:0 tively. channels, respectively. 0 – MIWU channel wake-up events disabled. 0 – Triggered on rising edge (low-to-high transition). 1 – MIWU channel wake-up events enabled. 1 – Triggered on falling edge (high-to-low 13.1.5 Wake-Up Interrupt Enable Register (WK0IENA) transition). The WK0IENA register is a word-wide read/write register 13.1.2 Wake-Up 1 Edge Detection Register (WK1EDG) that enables and disables interrupts from the MIWU chanThe WK1EDG register is a word-wide read/write register nels. The register format is shown below. that controls the edge sensitivity of the MIWU channels. The WK1EDG register is cleared upon reset, which configures 15 0 all channels to be triggered on rising edges. The register forWKIEN mat is shown below. 15 WKED 0 WKIEN WKED The Wake-Up Edge Detection bits control the edge sensitivity for MIWU channels. The WKED15:0 bits correspond to the WUI31:16 channels, respectively. 0 – Triggered on rising edge (low-to-high transition). 1 – Triggered on falling edge (high-to-low transition). Wake-Up Enable Register (WK0ENA) The Wake-Up Interrupt Enable bits control whether MIWU channels generate interrupts. The WKIEN15:0 bits correspond to the WUI15:0 channels, respectively. 0 – Interrupt disabled. 1 – Interrupt enabled. Wake-Up 1 Interrupt Enable Register (WK1IENA) 13.1.6 The WK1IENA register is a word-wide read/write register that enables and disables interrupts from the MIWU channels. The register format is shown below. 15 WKIEN 0 13.1.3 The WK0ENA register is a word-wide read/write register that individually enables or disables wake-up events from the MIWU channels. The WK0ENA register is cleared upon reset, which disables all wake-up/interrupt channels. The register format is shown below. 15 WKEN 0 WK1IEN The Wake-Up Interrupt Enable bits control whether MIWU channels generate interrupts. The WKIEN15:0 bits correspond to the WUI31:16 channels, respectively. 0 – Interrupt disabled. 1 – Interrupt enabled. WKEN The Wake-Up Enable bits enable and disable the MIWU channels. The WKEN15:0 bits correspond to the WUI15:0 channels, respectively. 0 – MIWU channel wake-up events disabled. 1 – MIWU channel wake-up events enabled. 63 www.national.com CP3CN23 13.1.7 Wake-Up Interrupt Control Register 1 (WK0ICTL1) 13.1.9 Wake-Up Interrupt Control Register 2 (WK0ICTL2) The WK0ICTL1 register is a word-wide read/write register that selects the interrupt request signal for the associated MIWU channels WUI7:0. At reset, the WK0ICTL1 register is cleared, which selects MIWU Interrupt Request 0 for all eight channels. The register format is shown below. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 The WK0ICTL2 register is a word-wide read/write register that selects the interrupt request signal for the associated MIWU channels WUI15:8. At reset, the WK2ICTL2 register is cleared, which selects MIWU Interrupt Request 0 for all eight channels. The register format is shown below. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WKIN WKIN WKIN WKIN WKIN WKIN WKIN WKIN TR7 TR6 TR5 TR4 TR3 TR2 TR1 TR0 WKIN WKIN WKIN WKIN WKIN WKIN WKIN WKIN TR15 TR14 TR13 TR12 TR11 TR10 TR9 TR8 WKINTR The Wake-Up Interrupt Request Select fields WKINTR select which of the four MIWU interrupt requests are activated for the corresponding channel. 00 – Selects MIWU interrupt request 0. 01 – Selects MIWU interrupt request 1. 10 – Selects MIWU interrupt request 2. 11 – Selects MIWU interrupt request 3. Wake-Up 1 Interrupt Control Register 1 (WK1ICTL1) The Wake-Up Interrupt Request Select fields select which of the four MIWU interrupt requests are activated for the corresponding channel. 00 – Selects MIWU interrupt request 0. 01 – Selects MIWU interrupt request 1. 10 – Selects MIWU interrupt request 2. 11 – Selects MIWU interrupt request 3. 13.1.8 13.1.10 Wake-Up 1 Interrupt Control Register 2 (WK1ICTL2) The WK1ICTL2 register is a word-wide read/write register that selects the interrupt request signal for the associated MIWU channels WUI31:24. At reset, the WK1ICTL2 register is cleared, which selects MIWU Interrupt Request 4 for all eight channels. The register format is shown below. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 The WK1ICTL1 register is a word-wide read/write register that selects the interrupt request signal for the associated MIWU channels WUI23:16. At reset, the WK1ICTL1 register is cleared, which selects MIWU Interrupt Request 4 for all eight channels. The register format is shown below. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WKIN WKIN WKIN WKIN WKIN WKIN WKIN WKIN TR23 TR22 TR21 TR20 TR19 TR18 TR17 TR16 WKIN WKIN WKIN WKIN WKIN WKIN WKIN WKIN TR31 TR30 TR29 TR28 TR27 TR26 TR25 TR24 WKINTR The Wake-Up Interrupt Request Select fields WKINTR select which of the four MIWU interrupt requests are activated for the corresponding channel. 00 – Selects MIWU interrupt request 4. 01 – Selects MIWU interrupt request 5. 10 – Selects MIWU interrupt request 6. 11 – Selects MIWU interrupt request 7. The Wake-Up Interrupt Request Select fields select which of the four MIWU interrupt requests are activated for the corresponding channel. 00 – Selects MIWU interrupt request 4. 01 – Selects MIWU interrupt request 5. 10 – Selects MIWU interrupt request 6. 11 – Selects MIWU interrupt request 7. www.national.com 64 CP3CN23 13.1.11 Wake-Up Pending Register (WK0PND) The WK0PND register is a word-wide read/write register in which the Multi-Input Wake-Up module latches any detected trigger conditions. The CPU can only write a 1 to any bit position in this register. If the CPU attempts to write a 0, it has no effect on that bit. To clear a bit in this register, the CPU must use the WK0PCL register. This implementation prevents a potential hardware-software conflict during a read-modify-write operation on the WK0PND register. This register is cleared upon reset. The register format is shown below. 15 WKPD 0 13.1.13 Wake-Up Pending Clear Register (WK0PCL) The WK0PCL register is a word-wide write-only register that lets the CPU clear bits in the WKPND register. Writing a 1 to a bit position in the WKPCL register clears the corresponding bit in the WKPND register. Writing a 0 has no effect. Do not modify this register with instructions that access the register as a read-modify-write operand, such as the bit manipulation instructions. Reading this register location returns undefined data. Therefore, do not use a read-modify-write sequence (such as the SBIT instruction) to set individual bits. Do not attempt to read the register, then perform a logical OR on the register value. Instead, write the mask directly to the register address. The register format is shown below. 15 0 WKCL WKPD The Wake-Up Pending bits indicate which MIWU channels have been triggered. The WKPD15:0 bits correspond to the WUI15:0 channels. Writing 1 to a bit sets it. WKCL 0 – Trigger condition did not occur. 1 – Trigger condition occurred. 13.1.12 Wake-Up 1 Pending Register (WK1PND) The WK1PND register is a word-wide read/write register in which the Multi-Input Wake-Up module latches any detected trigger conditions. The CPU can only write a 1 to any bit position in this register. If the CPU attempts to write a 0, it has no effect on that bit. To clear a bit in this register, the CPU must use the WK1PCL register. This implementation prevents a potential hardware-software conflict during a read-modify-write operation on the WK1PND register. This register is cleared upon reset. The register format is shown below. 15 WKPD 0 Writing 1 to a bit clears it. 0 – Writing 0 has no effect. 1 – Writing 1 clears the corresponding bit in the WKPD register. 13.1.14 Wake-Up 1 Pending Clear Register (WK1PCL) The WK1PCL register is a word-wide write-only register that lets the CPU clear bits in the WK1PND register. Writing a 1 to a bit position in the WK1PCL register clears the corresponding bit in the WK1PND register. Writing a 0 has no effect. Do not modify this register with instructions that access the register as a read-modify-write operand, such as the bit manipulation instructions. Reading this register location returns undefined data. Therefore, do not use a read-modify-write sequence (such as the SBIT instruction) to set individual bits. Do not attempt to read the register, then perform a logical OR on the register value. Instead, write the mask directly to the register address. The register format is shown below. 0 WKCL WKPD 15 The Wake-Up Pending bits indicate which MIWU channels have been triggered. The WKPD15:0 bits correspond to the WUI31:15 channels. Writing 1 to a bit sets it. 0 – Trigger condition did not occur. WKCL 1 – Trigger condition occurred. Writing 1 to a bit clears it. 0 – Writing 0 has no effect. 1 – Writing 1 clears the corresponding bit in the WK1PD register. 65 www.national.com CP3CN23 13.2 PROGRAMMING PROCEDURES To set up and use the Multi-Input Wake-Up function, use the following procedure. Performing the steps in the order shown will prevent false triggering of a wake-up condition. This same procedure should be used following a reset because the wake-up inputs are left floating, resulting in unknown data on the input pins. 1. Clear the WK0ENA and WK1ENA registers to disable the MIWU channels. 2. Write the WK0EDG and WK1EDG registers to select the desired type of edge sensitivity (clear for rising edge, set for falling edge). 3. Set all bits in the WK0PCL and WK0PCL registers to clear any pending bits in the WK0PND and WK1PND registers. 4. Set up the WK0ICTL1, WK1ICTL1, WK0ICTL2, and WK1ICTL2 registers to define the interrupt request signal used for each channel. 5. Set the bits in the WK0ENA and WK1ENA registers corresponding to the wake-up channels to be activated. To change the edge sensitivity of a wake-up channel, use the following procedure. Performing the steps in the order shown will prevent false triggering of a wake-up/interrupt condition. 1. Clear the WK0ENA or WK1ENA bit associated with the input to be reprogrammed. 2. Write the new value to the corresponding bit position in the WK0EDG or WK1EDG register to reprogram the edge sensitivity of the input. 3. Set the corresponding bit in the WK0PCL or WK1PCL register to clear the pending bit in the WK0PND or WK1PND register. 4. Set the same WK0ENA or WK1ENA bit to re-enable the wake-up function. www.national.com 66 CP3CN23 14.0 Input/Output Ports Each device has up to 50 software-configurable I/O pins, organized into 8-bit ports (not all bits are used in some ports). The ports are named Port B, Port C, Port E, Port F, Port G, Port H, and Port J. In addition to their general-purpose I/O capability, the I/O pins of Ports E, F, G, H, and J have alternate functions for use with on-chip peripheral modules such as the UART or the Multi-Input Wake-Up unit. The alternate functions of all I/O pins are shown in Table 83. Ports B and C are used as the 16-bit data bus when an external bus is enabled (144-pin devices only). This alternate function is selected by enabling the DEV or ERE operating environments, not by programming the port registers. Different pins within the same port can be individually configured to operate in different modes. Figure 10 is a diagram showing the I/O port pin logic. The register bits, multiplexers, and buffers allow the port pin to be configured into the various operating modes. The output buffer is a TRI-STATE buffer with weak pull-up capability. The weak pull-up, if used, prevents the port pin from going to an undefined state when it operates as an input. To reduce power consumption, input buffers configured for general-purpose I/O are only enabled when they are read. When configured for an alternate function, the input buffers are enabled continuously. To minimize power consumption, input signals to enabled buffers must be held within 0.2 volts of the VCC or GND voltage. The I/O pin characteristics are fully programmable. Each pin can be configured to operate as a TRI-STATE output, push- The electrical characteristics and drive capabilities of the inpull output, weak pull-up input, or high-impedance input. put and output buffers are described in Section 28.0. D PxALTS Register Q D PxALT Register Q VCC D PxWKPU Register Q Weak Pull-Up Enable Alt. A Device Direction Alt. B Device Direction D PxDIR Register Pin Alt. A Device Data Outout Alt. B Device Data Outout D PxDOUT Register Q Data Out Q Output Enable Alt. A Data Input PxDIN Register Alt. B Data Input 1 Data In Read Strobe Data In Analog Input DS190 Figure 10. I/O Port Pin Logic PxALT: Port alternate function register PxALTS: Port alternate function select register PxDIR: Port direction register PxDIN: Port data input register PxDOUT: Port data output register PxWPU: Port weak pull-up register PxHDRV: Port high drive strength register 14.1 PORT REGISTERS Each port has an associated set of memory-mapped registers used for controlling the port and for holding the port data: 67 www.national.com CP3CN23 Table 29 Port Registers Table 29 Port Registers Name PBALT PBDIR PBDIN PBDOUT PBWPU PBHDRV PBALTS PCALT PCDIR PCDIN PCDOUT PCWPU PCHDRV PCALTS PEALT PEDIR PEDIN PEDOUT PEWPU PEHDRV PEALTS PFALT PFDIR PFDIN PFDOUT PFWPU Address FF FB00h FF FB02h FF FB04h FF FB06h FF FB08h FF FB0Ah FF FB0Ch FF FB10h FF FB12h FF FB14h FF FB16h FF FB18h FF FB1Ah FF FB1Ch FF FCC0h FF FCC2h FF FCC4h FF FCC6h FF FCC8h FF FCCAh FF FCCCh FF FCE0h FF FCE2h FF FCE4h FF FCE6h FF FCE8h Description PFHDRV Port B Alternate Function Register PFALTS Port B Direction Register Port B Data Input Register Port B Data Output Register Port B Weak Pull-Up Register Port B High Drive Strength Register Port B Alternate Function Select Register PGHDRV Port C Alternate Function Register PGALTS Port C Direction Register Port C Data Input Register Port C Data Output Register Port C Weak Pull-Up Register Port C High Drive Strength Register Port C Alternate Function Select Register PHHDRV Port E Alternate Function Register PHALTS Port E Direction Register Port E Data Input Register Port E Data Output Register Port E Weak Pull-Up Register Port E High Drive Strength Register Port E Alternate Function Select Register PJHDRV Port F Alternate Function Register PJALTS Port F Direction Register Port F Data Input Register Port F Data Output Register Port F Weak Pull-Up Register FF F34Ch FF F34Ah PJALT PJDIR PJDIN PJDOUT PJWPU FF F340h FF F342h FF F344h FF F346h FF F348h FF F32Ch FF F32Ah PHALT PHDIR PHDIN PHDOUT PHWPU FF F320h FF F322h FF F324h FF F326h FF F328h FF F30Ch FF F30Ah PGALT PGDIR PGDIN PGDOUT PGWPU FF F300h FF F302h FF F304h FF F306h FF F308h FF FCECh FF FCEAh Name Address Description Port F High Drive Strength Register Port F Alternate Function Select Register Port G Alternate Function Register Port G Direction Register Port G Data Input Register Port G Data Output Register Port G Weak Pull-Up Register Port G High Drive Strength Register Port G Alternate Function Select Register Port H Alternate Function Register Port H Direction Register Port H Data Input Register Port H Data Output Register Port H Weak Pull-Up Register Port H High Drive Strength Register Port H Alternate Function Select Register Port J Alternate Function Register Port J Direction Register Port J Data Input Register Port J Data Output Register Port J Weak Pull-Up Register Port J High Drive Strength Register Port J Alternate Function Select Register In the descriptions of the ports and port registers, the lowercase letter “x” represents the port designation, either B, C, E, F, G, H, or J. For example, “PxDIR register” means any one of the port direction registers: PBDIR, PCDIR, PEDIR, PFDIR, PGDIR, PHDIR, or PJDIR. www.national.com 68 CP3CN23 All of the port registers are byte-wide read/write registers, except for the port data input registers, which are read-only registers. Each register bit controls the function of the corresponding port pin. For example, PGDIR.2 (bit 2 of the PGDIR register) controls the direction of port pin PG2. 14.1.1 Port Alternate Function Register (PxALT) 14.1.3 Port Data Input Register (PxDIN) The data input register (PxDIN) is a read-only register that returns the current state on each port pin. The CPU can read this register at any time even when the pin is configured as an output. 7 PxDIN 0 The PxALT registers control whether the port pins are used for general-purpose I/O or for their alternate function. Each port pin can be controlled independently. A clear bit in the alternate function register causes the corThe PxDIN bits indicate the state on the corresponding pin to be used for general-purpose I/O. In this PxDIN responding port pin. configuration, the output buffer is controlled by the direction 0 – Pin is low. register (PxDIR) and the data output register (PxDOUT). 1 – Pin is high. The input buffer is visible to software as the data input register (PxDIN). 14.1.4 Port Data Output Register (PxDOUT) A set bit in the alternate function register (PxALT) causes The data output register (PxDOUT) holds the data to be the corresponding pin to be used for its peripheral I/O funcdriven on output port pins. In this configuration, writing to tion. When the alternate function is selected, the output the register changes the output value. Reading the register buffer data and TRI-STATE configuration are controlled by returns the last value written to the register. signals from the on-chip peripheral device. A reset operation leaves the register contents unchanged. A reset operation clears the port alternate function regisAt power-up, the PxDOUT registers contain unknown valters, which initializes the pins as general-purpose I/O ports. ues. This register must be enabled before the corresponding alternate function is enabled. 7 0 7 PxALT PxDOUT PxALT The PxDOUT bits hold the data to be driven on pins configured as outputs in general-purpose I/O mode. 0 – Drive the pin low. 1 – Drive the pin high. 0 PxDOUT The PxALT bits control whether the corresponding port pins are general-purpose I/O ports or are used for their alternate function by an on-chip peripheral. 14.1.5 Port Weak Pull-Up Register (PxWPU) 0 – General-purpose I/O selected. 1 – Alternate function selected. The weak pull-up register (PxWPU) determines whether the port pins have a weak pull-up on the output buffer. The pull14.1.2 Port Direction Register (PxDIR) up device, if enabled by the register bit, operates in the genThe port direction register (PxDIR) determines whether eral-purpose I/O mode whenever the port output buffer is each port pin is used for input or for output. A clear bit in this disabled. In the alternate function mode, the pull-ups are alregister causes the corresponding pin to operate as an inways disabled. put, which puts the output buffer in the high-impedance state. A set bit causes the pin to operate as an output, which A reset operation clears the port weak pull-up registers, which disables all pull-ups. enables the output buffer. A reset operation clears the port direction registers, which initializes the pins as inputs. 7 PxDIR 0 PxWPU The PxWPU bits control whether the weak pull-up is enabled. 0 – Weak pull-up disabled. 1 – Weak pull-up enabled. 7 PxWPU 0 PxDIR The PxDIR bits select the direction of the corresponding port pin. 0 – Input. 1 – Output. 69 www.national.com CP3CN23 14.1.6 Port High Drive Strength Register (PxHDRV) Table 30 Port Pin PF5 PF6 PF7 PG0 Alternate Function Select PxALTS = 0 SFS STD SRD Reserved Reserved Reserved Reserved Reserved Reserved WUI10 TA UART1 RXD1 UART1 TXD1 UART2 RXD2 UART2 TXD2 UART3 RXD3 UART3 TXD3 CAN0RX CAN0TX WUI18 WUI19 WUI20 WUI21 WUI22 WUI23 WUI24 ASYNC PxALTS = 1 TIO6 TIO7 TIO8 Reserved Reserved SRCLK Reserved Reserved Reserved Reserved Reserved WUI11 WUI12 WUI13 WUI14 WUI15 WUI16 WUI17 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved WUI9 The PxHDRV register is a byte-wide, read/write register that controls the slew rate of the corresponding pins. The high drive strength function is enabled when the corresponding bits of the PxHDRV register are set. In both GPIO and alternate function modes, the drive strength function is enabled by the PxHDRV registers. At reset, the PxHDRV registers are cleared, making the ports low speed. 7 PxHDRV 0 PG1 PG2 PxHDRV The PxHDRV bits control whether output pins are driven with slow or fast slew rate. 0 – Slow slew rate. 1 – Fast slew rate. Port Alternate Function Select Register (PxALTS) PG3 PG4 PG5 PG6 PG7 PH0 PH1 PH2 14.1.7 The PxALTS register selects which of two alternate functions are selected for the port pin. These bits are ignored unless the corresponding PxALT bits are set. Each port pin can be controlled independently. 7 PxALTS 0 PH3 PH4 PH5 PxALTS The PxALTS bits select among two alternate functions. Table 30 shows the mapping of the PxALTS bits to the alternate functions. Unused PxALTS bits must be clear. Table 30 Alternate Function Select Port Pin PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 PF0 PF1 PF2 PF3 PF4 PxALTS = 0 UART0 RXD0 UART0 TXD0 UART0 RTS UART0 CTS UART0 CKX SRFS CAN1RX CAN1TX MSK MDIDO MDODI MWCS SCK PxALTS = 1 Reserved Reserved Reserved Reserved TB NMI Reserved Reserved TIO1 TIO2 TIO3 TIO4 TIO5 PH6 PH7 PJ0 PJ1 PJ2 PJ3 PJ4 PJ5 PJ6 PJ7 14.2 OPEN-DRAIN OPERATION A port pin can be configured to operate as an inverting open-drain output buffer. To do this, the CPU must clear the bit in the data output register (PxDOUT) and then use the port direction register (PxDIR) to set the value of the port pin. With the direction register bit set (direction = out), the value zero is forced on the pin. With the direction register bit clear (direction = in), the pin is placed in the TRI-STATE mode. If desired, the internal weak pull-up can be enabled to pull the signal high when the output buffer is in TRISTATE mode. www.national.com 70 CP3CN23 15.0 12-Bit Analog to Digital Converter The integrated 12-bit ADC provides the following features: 8-input analog multiplexer 8 single-ended channels or 4 differential channels External filtering capability 12-bit resolution with 11-bit accuracy Sign bit MUXOUT0 MUXOUT1 ADCIN 15-microsecond conversion time Support for resistive touchscreen interface Internal or external start trigger Programmable start delay after start trigger Poll or interrupt on done VREFP AVCC ADC0 ADC1 AGND ADC2 ADC3 Pen-Down Detector ADC0/TSX+ DRV ADC1/TSYDRV ADC2/TSXDRV ADC3/TSY+ DRV ADC4 ADCIN 12 Pen Down ADC7 Wake-Up (WUI30) Input + Multiplexer Int/Ext Multiplexer VREFP + 12-BIT ADC Clock Control Result VREFN PREF_CFG NREF_CFG TOUCH_CFG MUX_CFG ADC Clock ADC_DIV Start ADC SEQUENCER Done Interrupt (IRQ13) ASYNC TRIGGER DELAY1 CLKDIV DELAY2 4-Word FIFO ADC_CONTROL ADC_DELAY1 CLKSEL ADC_DELAY2 ADCRESLT System Bus Interface DS183 System Clock Auxiliary Clock 2 Figure 11. Analog to Digital Converter Block Diagram 12-Bit ADC—receives the output of the Internal/External Multiplexer and performs the analog to digital conversion. ADCRESLT Register—makes conversion results from the 12-Bit ADC available to the on-chip bus. The ADCRESLT register includes the software-visible end of a 4word FIFO used to queue conversion results. The configuration of the analog signal paths is controlled by fields in the ADCGCR register. The Input Multiplexer is controlled by the MUX_CFG field. The Internal/External Multiplexer is controlled by the ADCIN bit. The analog multiplexers for selecting the voltage references used by the ADC are controlled by the PREF_CFG and NREF_CFG fields. The low-ohmic drivers used for interface to resistive touchscreens are controlled by the TOUCH_CFG field. 15.1 FUNCTIONAL DESCRIPTION The ADC module consists of a 12-bit ADC converter and associated state machine, together with analog multiplexers to set up signal paths for sampling and voltage references, logic to control triggering of the converter, and a bus interface. 15.1.1 Data Path Up to 8 GPIO pins may be configured as 8 singled-ended analog inputs or 4 differential pairs. Analog/digital data passes through four main blocks in the ADC module between the input pins and the CPU bus: Input Multiplexer—an analog multiplexer that selects among the input channels. Internal/External Multiplexer—an analog multiplexer that selects between the output of the Input Multiplexer and the ADCIN external analog input. 71 www.national.com CP3CN23 The output of the Input Multiplexer is available externally as the MUXOUT0 and MUXOUT1 signals. In single-ended mode, only MUXOUT0 is used. In differential mode, MUXOUT0 is the positive side and MUXOUT1 is the negative side. The MUXOUT0 and MUXOUT1 outputs and the ADCIN external analog input are provided so that external signal conditioning circuits (such as filters) may be applied to the analog signals before conversion. The MUXOUT0, MUXOUT1, and ADCIN signals are alternate functions of GPIO pins used by the Input Multiplexer, so the number of available analog input channels is reduced when these signals are used. 15.1.2 Operation one system clock after the ADCRESLT register is read). Total conversion time is around 15 microseconds. The Done signal is also an input to the Multi-Input Wake-Up unit (WUI30). The MIWU input is asserted whenever the FIFO is not empty (but will deassert for one system clock after the ADCRESLT register is read). The wake-up output is provided so that the ADC module can bring the system out of a power-saving mode when a conversion operation is completed. It asserts earlier than the interrupt output. In the pen-down detection mode of the ADC, the wake-up output is ORed with the ADC pen-down detector output, to wake up on a pen-down event. 15.1.3 ADC Clock Generation The TRIGGER block may be configured to initiate a conversion from either of these sources: External ASYNC Input—an edge on the ASYNC input triggers a conversion. This input may be configured to be sensitive to rising or falling edges, as controlled by the POL bit in the ADCCNTRL register. ADCSTART Register—writing any value to the ADCSTART register triggers a conversion. The TRIGGER block incorporates a glitch filter to suppress transient spikes on the ASYNC input. The TRIGGER block will recognize ASYNC pulse widths of 10 ns or greater. Once a trigger event has been recognized, no further triggering is recognized until the conversion is completed. The DELAY2 block generates ADC Clock, which is the clock used internally by the ADC module. ADC Clock is derived from either: System Clock—a programmable divider is available to generate the 12 MHz clock required by the ADC from the System Clock. Auxiliary Clock 2—may be used to perform conversions when the System Clock is slowed down or suspended in low-power modes. The DELAY2 block receives the clock source selected by the CLKSEL bit of the ADCACR register and adds a number of asynchronous incremental delay units specified in the ADC_DELAY2 field of the ADCSCDLY register. This deWhen the ASYNC input is selected as the trigger source, it layed clock (ADC Clock) then drives the TRIGGER, 12-BIT may be configured for automatic or non-automatic mode, as ADC, and ADC SEQUENCER blocks. ADC Clock also controlled by the AUTO bit in the ADCCNTRL register: drives the ADC_DIV clock divider, which generates the Automatic Mode—a conversion is triggered by any clock which drives the DELAY1 block. qualified edge on the ASYNC input (unless a conversion Because the ADCRESLT FIFO is driven by System Clock is already in progress). (not ADC Clock), a conversion result will not propagate to Non-Automatic Mode—before a conversion may be the output of the FIFO when the System Clock is suspendtriggered from the ASYNC input, software must “prime” ed. the TRIGGER block by writing the ADCSTART register. 15.1.4 ADC Voltage References Once the TRIGGER block is primed, a conversion is triggered by any qualified edge on the ASYNC input. After The 12-BIT ADC block has positive and negative voltage the conversion is completed, no additional trigger events reference inputs, VREFP and VREFN. In single-ended will be recognized until software once again primes the mode, only VREFP is used. An analog multiplexer allows selecting an external VREFP pin, the analog supply voltage TRIGGER block by writing the ADCSTART register. AVCC, or the analog inputs ADC0 or ADC1 as the positive Once a trigger event is recognized, the DELAY1 block waits voltage reference, as controlled by the PREF_CFG field of for a programmable delay specified in the ADC_DELAY1 the ADCGCR register. Another analog multiplexer allows field of the ADCSCDLY register. Then, it asserts the Start selecting the analog ground AGND or the analog inputs signal to the ADC SEQUENCER block. ADC2 or ADC3 as the negative voltage reference, as conWhen the Start signal is received, the ADC SEQUENCER trolled by the NREF_CFG field of the ADCGCR register. block initiates the conversion in the 12-Bit ADC. After the conversion is complete, the result is loaded into the FIFO, 15.1.5 Pen-Down Detector and the Done signal is asserted. The ADCRESLT register includes the software-visible end of a 4-word FIFO, which allows up to 4 conversion results to be queued for reading. Reading the ADCRESLT register unloads the FIFO. If the FIFO overflows, a bit is set in the ADCRESLT register, and the most recent conversion data is lost. The Done signal is visible to software as the ADC_DONE bit in the ADCRESLT register. The Done signal is also an input to the interrupt controller (IRQ13). The interrupt will be asserted whenever the FIFO is not empty (but will deassert for www.national.com 72 A pen-down detector is provided on the ADC0 (TSX+) input of the ADC. It consists of a Schmitt-trigger receiver, with a minimum Vil of 0.7V. When pen-down detect mode is enabled by loading 101b into the TOUCH_CFG field of the ADCGCR register, the output of this detector is visible to software in the PEN_DOWN bit of the ADCRESLT register, and this output is ORed with the Done signal to become the wake-up input (WUI30) to the Multi-Input Wake-Up unit. CP3CN23 15.2 TOUCHSCREEN INTERFACE 15.2.1 Touchscreen Driver Configuration The ADC provides an interface for 4-wire resistive touchscreens with the resolution necessary for applications such as signature analysis. A typical touchscreen configuration is shown in Figure 12. An equivalent circuit for the touchscreen interface is shown in Figure 13. VCC TSX+/ADC0 TSY+/ADC1 TSX-/ADC2 TSY-/ADC3 6Ω 6Ω TSY+ TSX+ X Plate RX1 Y Plate RY1 RZ B To ADC A MUXOUT0 ADCIN DS186 TSXTSY6Ω 6Ω RX2 RY2 Figure 12. Touchscreen Interface A touchscreen consists of two resistive plates normally separated from each other. The TSX+ and TSX- signals are connected to opposite ends of the X plate, while the TSY+ and TSY- signals are connected to the Y plate. If the pen is DS187 down, the plates will be shorted together at the point of pen contact. The location of the pen is sensed by driving one Figure 13. Touchscreen Driver Equivalent Circuit end of a plate to VCC, driving the opposite end to ground, and sensing the voltage at the point of pen contact using the Low-ohmic drivers are provided to pull the TSX+ and TSY+ signals to VCC and the TSX- and TSY- signals to GND. The other plate. This is done twice, once for each coordinate. on-resistance of these drivers is specified to be 6 ohms. An external RC low-pass filter is used to remove noise couTwo measurements are used to produce one (x,y) position pled to the touchscreen signals from the display drivers. coordinate pair. To measure the x-coordinate, the TSX+ signal is pulled to VCC, the TSX- signal is pulled to GND, and the TSY+ and TSY- signals are undriven. A voltage divider is formed across the X plate, with the center tap of the divider being the point of pen contact, represented in Figure 13 by node A. With TSY+ and TSY- undriven, the voltage at node A can be measured by sampling either of the TSY+ or TSY- signals. This voltage will be proportional to the position of the pen contact on the X plate. The position of the pen contact on the Y plate is measured similarly, by driving the TSY+ signal to VCC, the TSY- signal to GND, and leaving the TSX+ and TSX- signals undriven. The voltage at node B can be sampled from either the TSX+ or TSX- signals. The TOUCH_CFG field of the ADCGCR register specifies the configuration of the drivers, with 010b used to sample node A and 001b used to sample node B. Typically, two consecutive measurements are made of each coordinate so that any interference coupled from the LCD column drivers is averaged out. The plate-to-plate resistance is shown in Figure 13 as RZ. This measurement is used as an indication of the force of pen contact. When 100b is loaded into the TOUCH_CFG field, the TSY+ signal is pulled to VCC and the TSX- signal is pulled to GND, to support measuring RZ. 73 www.national.com CP3CN23 15.2.2 Measuring Pen Force Solving for RY1, the resistance is: B RY1 = RYP ×  1 –  ------------     2047  Now that the resistance values RX2 and RY1 are known, it is possible to calculate the value of the plate-to-plate contact resistance, RZ, given the value measured at node C on the TSX+ input in Sample Z mode. Node C is a tap in a resistor-divider network composed of three resistors, such that: C RX2 ------------ = --------------------------------------------2047 RY1 + RZ + RX2 Solving for RZ, the resistance is: 2047 – C RZ =  RX2 ×  ----------------------   – RY1    C The resistance RZ is proportional to the force of pen contact. 15.2.3 Compensation for Driver Resistance Figure 14 shows equivalent circuits for the driver modes used to measure the X, Y, and Z coordinates, in which Z represents pen force. In this discussion, the ohmic resistance of the drivers is neglected (see Section 15.2.3), and series resistance between the node of interest and the ADC is ignored because it has no significant effect. VCC VCC VCC RY1 RX1 A RX2 RY1 B RY2 RZ C RX2 Sample X TOUCH_CFG = 001 Sample Y TOUCH_CFG = 010 Sample Z TOUCH_CFG = 100 DS188 Figure 14. Touchscreen Driver Modes In the following examples, the ADC is assumed to operate in single-ended mode to produce conversion values between 0 and 2047, however the same principles could be extended to differential mode to recover the full range of the ADC. In Sample X mode, the X plate is driven between VCC and ground, so that a value measured at node A on the TSY+ or TSY- inputs is the center tap of a resistor-divider network. The end-to-end resistance RXP of the X plate is: RXP = RX1 + RX2 Plate resistances between opposite electrodes range from 100 ohms to 1k ohm. Because of the 6-ohm driver resistance, some significant voltage drop will be experienced between, for example, TSX- and AGND. A 200-ohm plate will drop: 6  ----------------------------  × ( AVCC – AGND )  200 + 6 + 6 With a 2.5V supply, this is 70 mV. A 12-bit ADC has 4096 possible values, so each value covers a range of 610 µV at 2.5V. A voltage drop of 70 mV across each of the low-ohmic drivers reduces the number of available ADC values by: 70 mV × 2 -------------------------- = 230 610 uV This effective loss of resolution can be handled in a number The value measured at node A is proportional to the ratio of ways. between the resistance to ground and the resistance of the 1. The voltages on, for example, TSY+ and TSY- can be X plate: sampled before sampling TSX+ and TSX-. Then, scalA RX2 ing can be applied in software to convert the samples ------------ = -----------2047 RXP to the full (4096-bit) range. This technique will not recover any resolution, however it is worthy of some conSolving for RX2, the resistance is: sideration because touchscreen data is typically A RX2 = RXP ×  ------------  passed to two applications:  2047 Signature Analysis—only the raw data is required. No absolute positioning is necessary. Similarly, in Sample Y mode the value measured at node B Screen Overlay—for example, for cursor positioning. on the TSX+ or TSX- inputs is proportional to the ratio beIn this application, a scaling or calibration is performed tween the resistance to ground and the resistance RYP of to correctly overlay the touchscreen coordinates onto the Y plate: the display. Because of this calibration, it is not even B RY2 ------------ = -----------necessary to sample TSY+ and TSY-. 2047 RYP 2. The ADC has a positive voltage reference input which Because end-to-end resistance RYP of the Y plate is: can be internally connected to the TSY+ terminal. This means that the number of available ADC values is inRYP = RY1 + RY2 creased to: The previous equation can be rewritten as: 70 mV 4096 –  -------------------  = 3981 B RYP – RY1  610 uV  ------------ = -----------------------------2047 RYP Software scaling could be applied to this value if required (as with technique 1, above), but no additional resolution is achieved. www.national.com 74 CP3CN23 3. By extension, the ADC negative voltage reference can be internally connected to the TSY- terminal, to recover the full 4096 values. The Global Configuration Register (ADCGCR) provides the flexibility to implement any of these techniques. 15.5 ADC REGISTER SET Table 31 ADC Registers Name Address FF F3C0h FF F3C2h FF F3C4h FF F3C6h FF F3C8h FF F3CAh Description ADC Global Configuration Register ADC Auxiliary Configuration Register ADC Conversion Control Register ADC Start Conversion Register ADC Start Conversion Delay Register ADC Result Register Table 31 lists the ADC registers. 15.3 ADC OPERATION IN POWER-SAVING MODES ADCGCR ADCACR ADCCNTRL ADCSTART ADCSCDLY ADCRESLT To reduce the level of switching noise in the environment of the ADC, it is possible to operate the CP3CN23 in low-power modes, in which the System Clock is slowed or switched off. Under these conditions, Auxiliary Clock 2 can be selected as the clock source for the ADC module, however conversion results cannot be read by the system while the System Clock is suspended. The expected operation in power-saving modes is therefore: 1. ADC is configured and a conversion is primed or triggered. 2. A power-saving mode is entered. 3. ADC conversion completes and a wake-up signal is asserted to the MIWU unit. 4. Device wakes up and processes the conversion result. To conserve power, the ADC should be disabled before entering a low-power mode if its function is not required. 15.4 FREEZE The ADC module provides support for an In-System Emulator by means of a special FREEZE input. When FREEZE is asserted the module will exhibit the following specific behavior: The automatic clear-on-read function of the result register (ADCRESLT) is disabled. The FIFO is updated as usual, and an interrupt for a completed conversion can be asserted. 75 www.national.com CP3CN23 15.5.1 ADC Global Configuration Register (ADCGCR) MUX_CFG The ADCGCR register controls the basic operation of the interface. The CPU bus master has read/write access to the ADCGCR register. After reset this register is set to 0000h. 8 7 6 5 4 3 2 1 0 The Multiplexer Configuration field and the DIFF bit configure the analog circuits of the ADC module, as shown in Table 32. Table 32 MUX_CFG Operation Channels Selected (DIFF = 1) + 1 0 TOUCH_CFG MUX_CFG DIFF ADCIN CLKEN MUX_CFG Channel Selected, (DIFF = 0) 0 1 15 14 13 12 11 10 9 000 001 0 1 MUXOUTEN INTEN Res. NREF_CFG PREF_CFG CLKEN ADCIN DIFF 010 2 2 3 The Clock Enable bit controls whether the ADC module is running. When this bit is clear, 011 3 3 2 all ADC clocks are disabled, the ADC analog circuits are in a low-power state, and ADC 100 4 4 5 registers (other than the ADCGCR and AG101 5 5 4 CACR registers) are not writeable. Clearing this bit reinitializes the ADC state machine 110 6 6 7 and cancels any pending trigger event. When 111 7 7 6 this bit is set, the ADC clocks are enabled and the ADC analog circuits are powered up. The converter is operational within 0.25 µs of beFor best noise immunity in touchscreen appliing enabled. cations, channel 2 should be used for sam0 – ADC disabled. pling the X plate voltage, and channel 1 1 – ADC enabled. should be used for sampling the Y plate voltThe ADCIN bit selects the source of the ADC age. input. When the bit is clear, the source is the TOUCH_CFG The Touchscreen Configuration field controls 8-channel Input Multiplexer. When the bit is the configuration of the low-ohmic drivers for set, the source is the ADCIN pin. the TSX+, TSX-, TSY+, and TSY- signals, as 0 – ADC input is from 8-channel multiplexer. shown in Table 33. When TOUCH_CFG is 1 – ADC input is from ADCIN pin. 101b, the pen-down detector is enabled. The The Differential Operation Mode bit and the output of the pen-down detector is visible to MUX_CFG field configure the analog circuits software in the PEN_DOWN bit of the ADof the ADC module. When this bit is clear, the SRESLT register, and it is ORed with the ADC module operates in single-ended mode. Done signal to generate the wake-up signal When this bit is set, the ADC operates in difWUI30 passed to the MIWU unit. ferential mode. See Table 32 . 0 – Single-ended mode. 1 – Differential mode. Table 33 TOUCH_CFG Modes ADC2/TSXInactive Inactive Driven Low Inactive Driven Low Inactive Inactive ADC3/TSYInactive Driven Low Inactive Driven Low Inactive Driven Low inactive Mode None Sample Y Sample X Sample Z (1), Pre-Pen Down Sample Z (2) Pen-Down Detect Reserved TOUCH_CFG 000 001 010 011 100 101 11X ADC0/TSX+ Inactive Inactive Driven High Driven High Inactive Weakly Pulled High Inactive ADC1/TSY+ Inactive Driven High Inactive Inactive Driven High Inactive Inactive www.national.com 76 CP3CN23 PREF_CFG The Positive Voltage Reference Configuration field specifies the source of the ADC positive voltage reference, according to the following table: PREF_CFG 00 01 10 11 PREF Source Internal (AVCC) VREFP ADC0 ADC1 15.5.2 ADC Auxiliary Configuration Register (ADCACR) The ADCACR register is used to control the clock configuration and report the status of the ADC module. The CPU bus master has read/write access to the ADCACR register. After reset, this register is clear. 15 14 13 PRM 12 3 2 1 0 CNVT TRG Reserved CLKDIV CLKSEL CLKSEL NREF_CFG The Negative Voltage Reference Configuration field specifies the source of the ADC negative voltage reference, according to the following table: NREF_CFG 00 01 10 11 NREF source Internal (AGND) Reserved ADC2 ADC3 CLKDIV The Clock Select bit selects the clock source used by the DELAY2 block to generate the ADC clock. 0 – ADC clock derived from System Clock. 1 – ADC clock derived from Auxiliary Clock 2. The Clock Divisor field specifies the divisor applied to System Clock to generate the 12 MHz clock required by the ADC module. Only the System Clock is affected by this divisor. The divisor is not used when Auxiliary Clock 2 is selected as the clock source. CLKDIV 00 01 10 11 Clock Divisor 1 2 4 Reserved MUXOUTEN The MUXOUT Enable bit controls whether the output of the Input Multiplexer is available externally. In single-ended mode, the MUXOUT0 pin is active and the MUXOUT1 pin is disabled (TRI-STATE). In differential mode, both MUXOUT0 and MUXOUT1 are PRM active. 0 – MUXOUT0 and MUXOUT1 disabled. 1 – MUXOUT0 and MUXOUT1 enabled. INTEN The Interrupt Enable bit controls whether the ADC interrupt (IRQ13) is enabled. When enabled, the interrupt request is asserted when valid data is available in the ADCRESLT reg- TRG ister. This bit has no effect on the wake_up signal to the MIWU unit (WUI30). 0 – IRQ13 disabled. 1 – IRQ13 enabled. CNVT The ADC Primed bit is a read-only bit that indicates the ADC has been primed to perform a conversion by writing to the ADCSTART register. The bit is cleared after the conversion is completed. 0 – ADC has not been primed. 1 – ADC has been primed. The ADC Triggered bit is a read-only bit that indicates the ADC has been triggered. The bit is set during any pre-conversion delay. The bit is cleared after the conversion is completed. 0 – ADC has not been triggered. 1 – ADC has been triggered. The ADC Conversion bit is a read-only bit that indicates the ADC has been primed to perform a conversion, a valid internal or external trigger event has occurred, any pre-conversion delay has expired, and the ADC conversion is in progress. The bit is cleared after the conversion is completed. 0 – ADC is not performing a conversion. 1 – ADC conversion is in progress. 77 www.national.com CP3CN23 15.5.3 ADC Conversion Control Register (ADCCNTRL) 15.5.4 ADC Start Conversion Register (ADCSTART) The ADCCNTRL register specifies the trigger conditions for an ADC conversion. 15 Reserved 3 2 1 0 POL The ADCSTART register is a write-only register used by software to initiate an ADC conversion. Writing any value to this register will cause the ADC to initiate a conversion or prime the ADC to initiate a conversion, as controlled by the ADCCNTRL register. 15.5.5 ADC Start Conversion Delay Register (ADCSCDLY) AUTO EXT POL EXT AUTO The ASYNC Polarity bit specifies the polarity of edges which trigger ADC conversions. 0 – ASYNC input is sensitive to rising edges. 1 – ASYNC input is sensitive to falling edges. The External Trigger bit selects whether conversions are triggered by writing the ADCSTART register or activity on the ASYNC input. 0 – ADC conversions triggered by writing to the ADCSTART register. 1 – ADC conversions triggered by qualified edges on ASYNC input. The Automatic bit controls whether automatic mode is enabled, in which any qualified edge on the ASYNC input is recognized as a trigger event. When automatic mode is disabled, the ADC module must be “primed” before a qualified edge on the ASYNC input can trigger a conversion. To prime the ADC module, software must write the ADCSTART register with any value before an edge on the ASYNC input is recognized as a trigger event. After the conversion is completed, the ASYNC input will be ignored until software again writes the ADCSTART register. The AUTO bit is ignored when the EXT bit is 0. 0 – Automatic mode disabled. 1 – Automatic mode enabled. The ADCSCDLY register controls critical timing parameters for the operation of the ADC module. 15 14 13 5 4 0 ADC_DIV ADC_DELAY1 ADC_DELAY2 ADC_DELAY2 The ADC Delay 2 field specifies the delay between the ADC module clock source (either System Clock after a programmable divider or Auxiliary Clock 2) and the ADC clock. The range of effective values for this field is 0 to 20. Values above 20 produce the same delay as 20, which is about 42 ns. ADC_DELAY1 The ADC Delay 1 field specifies the number of clock periods by which the trigger event will be delayed before initiating a conversion. The timebase for this delay is the ADC clock (12 MHz) divided by the ADC_DIV divisor. The ADC_DELAY1 field has 9 bits, which corresponds to a maximum delay of 511 clock periods. ADC_DIV The ADC Clock Divisor field specifies the divisor applied to the ADC clock (12 MHz) to generate the clock used to drive the DELAY1 block. A field value of n results in a division ratio of n+1. With a module clock of 12 MHz, the maximum delay which can be provided by ADC_DIV and ADC_DELAY settings is: 1  -------------------  × 4 × 511 = 170 us  12 MHz www.national.com 78 CP3CN23 15.5.6 ADC Result Register (ADCRESLT) The ADCRESLT register includes the software-visible end of a 4-word FIFO. Conversion results are loaded into the FIFO from the 12-bit ADC and unloaded when software reads the ADCRESLT register. The ADCRESLT register is read-only. With the exception of the PEN_DOWN bit, the fields in this register are cleared when the register is read. 11 ADC_RESULT 0 15 14 13 12 SIGN ADC_DONE ADC_OFLW PEN_DOWN ADC_RESULT The ADC Result field holds a 12-bit value for the conversion result. If the ADC_DONE bit is clear, there is no valid result in this field, and the field will have a value of 0. The ADC_RESULT field and the SIGN bit together form the software-visible end of the ADC FIFO. SIGN The Sign bit indicates whether the - input has a voltage greater than the + input (differential mode only). For example if ADCGCR.MUX_CFG is 000b, ADC0 is the + input and ADC1 is the - input. If the voltage on ADC0 is greater than the voltage on ADC1, the SIGN bit will be 0; if the voltage on ADC0 is less than the voltage on ADC1, the SIGN bit will be 1. In single-ended mode, this bit always reads as 0. 0 – In differential mode, + input has a voltage greater than the - input. In single-ended mode, this bit is always 0. 1 – In differential mode, - input has a voltage greater than the + input. PEN_DOWN The Pen-Down bit indicates whether a pendown condition is being sensed. To enable pen-down detection, the TOUCH_CFG field of the ADCGCR register must be loaded with 101b. When pen-down detection is enabled and a pen-down condition is sensed, the PEN_DOWN bit is set. This bit is not carried through the FIFO, so its value represents the current status of the pen-down detector. When pen-down detection is enabled, the signal from the pen-down detector is ORed with the Done signal to generate the wake-up signal (WUI30) passed to the MIWU unit. If pendown detection is not enabled, this bit reads as 0. 0 – No pen-down condition is sensed, or pendown detection is disabled. 1 – Pen-down condition is sensed. ADC_OFLW The ADC FIFO Overflow bit indicates whether the 4-word FIFO behind the ADCRESLT register has overflowed. When this occurs, the most recent conversion result is lost. This bit is cleared when the ADCRESLT register is read. 0 – FIFO overflow has not occurred. 1 – FIFO overflow has occurred. ADC_DONE The ADC Done bit indicates when an ADC conversion has completed. When this bit is set, the data in the ADC_RESULT field is valid. When this bit is clear, there is no valid data in the ADC_RESULT field. The Done bit is cleared when the ADCRESLT register is read, but if there are queued conversion results in the FIFO, the Done bit will become set again after one System Clock period. 0 – No ADC conversion has completed since the ADCRESLT register was last read. 1 – An ADC conversion has completed since the ADCRESLT register was last read. 79 www.national.com CP3CN23 16.0 Random Number Generator (RNG) The RNG unit is a hardware “true random” number generator. When enabled, this unit provides up to 800 random bits per second. The bits are available for reading from a 16-bit register. The RNG unit includes two oscillators which operate independently of the System Clock: When a new 16-bit word of random data is available, it is loaded into the RNGD register. If enabled, an interrupt request (IRQ3) is asserted when the word is available for reading. When software reads the RNGD register, the register is cleared and the interrupt request is deasserted. The RNGCST register provides control and status bits for Fast Oscillator—a 24 MHz oscillator which drives a lin- the RNG module: ear feedback shift register (LFSR). RNG Enable—enables or disables the RNG oscillators. Slow Oscillator—an unstable oscillator which drives a Interrupt Mask—enables or disables the interrupt when flip-flop for sampling the pseudorandom bitstream from a new word of random data becomes available. the LFSR. This oscillator operates at approximately 115 Data Valid—indicates whether a new word is available. kHz, but it does not have a fixed frequency. By sampling the pseudorandom bitstream at random intervals, a random bitstream is synthesized. This bitstream is clocked into a 16-bit shift register. A programmable clock divider generates the clock signal for the shift register from the System Clock. 16.1 FREEZE The RNG module provides support for an In-System Emulator by means of a special FREEZE input. When FREEZE is asserted, the automatic clear-on-read function of the RNDGD register is disabled. RNGCST Q Enable Fast Osc. (~24 MHz) Clock 31-Bit LFSR D Q Sample Flip-Flop Clock D 16-Bit Shift Register Clock Slow Osc. (~115 kHz) (Unstable) RNGDIVH/RNGDIVL RNGD System Bus System Clock Sample Strobe Divider DS185 Figure 15. RNG Module Block Diagram www.national.com 80 CP3CN23 16.2 RANDOM NUMBER GENERATOR REGISTER SET Table 34 RNG Registers Name Address FF F280h FF F282h FF F284h FF F286h Description RNG Control and Status Register RNG Data Register RNG Divisor Register High RNG Divisor Register Low 16.2.2 RNG Data Register (RNGD) Table 31 lists the RNG registers. The RNGD register holds random data generated by the RNG module. After reading the register, it is cleared and the DVALID bit of the RNGCST register is cleared. When a new word of valid (random) data becomes available in the RNGD register, the DVALID bit is set and (if enabled) and interrupt request is asserted. 15 RNGD15:0 0 RNGCST RNGD RNGDIVH RNGDIVL 16.2.1 16.2.3 RNG Divisor Register High (RNGDIVH) This register holds the two most significant bits of the RNGDIV clock divisor. See the description of the RNGDIVL register. 15 Reserved 2 1 0 RNG Control and Status Register (RNGCST) RNGDIV17:16 The RNGCST register provides control and status bits for the RNG module. This register is cleared at reset. 15 Reserved 6 5 IMSK 4 Reserved 2 1 0 16.2.4 RNG Divisor Register Low (RNGDIVL) DVALID RNGE This register holds the 16 least significant bits the RNGDIV clock divisor. 15 RNGDIV15:0 0 RNGE DVALID IMASK The Random Number Generator Enable bit enables the operation of the RNG. When this bit is clear, the RNG module is disabled, and both RNG oscillators are suspended. 0 – RNG module disabled. 1 – RNG module enabled. The Data Valid bit indicates whether valid (random) data is available in the RNGD register. This bit is cleared when the RNGD register is read. 0 – RNGD register holds invalid data. 1 – RNGD register holds valid data. The Interrupt Mask bit controls whether an interrupt request (IRQ3) will be asserted when valid (random) data is available in the RNGD register. 0 – RNG interrupt disabled. 1 – RNG interrupt enabled. The RNGDIV clock divisor is used to generate the sampling strobe for loading random bits into the shift register. The divisor is applied to the System Clock source. The maximum frequency after division is 800 Hz. For example, a System Clock frequency of 24 MHz would require an RNGDIV value of 30,000 (7530h) or greater. The default RNGDIV value is 0000 83D6h. 81 www.national.com CP3CN23 17.0 CAN Module Each of the two CAN modules provides a Full CAN class, CAN (Controller Area Network) serial bus interface for low/ high speed applications. They support reception and transmission of extended frames with a 29-bit identifier, standard frames with an 11-bit identifier, applications that require high speed (up to 1 MBit/s), and a low-speed CAN interface with CAN master capability. Data transfer between the CAN bus and the CPU is handled by 15 message buffers, which can be individually configured as receive or transmit buffers. Every message buffer includes a status/control register which provides information about its current status and capabilities to configure the buffer. All message buffers are able to generate an interrupt on the reception of a valid frame or the successful transmission of a frame. In addition, an interrupt can be generated on bus errors. An incoming message is only accepted if the message identifier passes one of two acceptance filtering masks. The filtering mask can be configured to receive a single message ID for each buffer or a group of IDs for each receive buffer. One of the buffers uses a separate message filtering procedure. This provides the capability to establish a BASIC-CAN path. Remote transmission requests can be processed automatically by automatic reconfiguration to a receiver after transmission or by automated transmit scheduling upon reception. A priority decoder allows any buffer to have one of 16 transmit priorities including the highest or lowest absolute priority, for a total of 240 different transmit priorities. A decided bit time counter (16-bit wide) is provided to support real time applications. The contents of this counter are captured into the message buffer RAM on reception or transmission. The counter can be synchronized through the CAN network. This synchronization feature allows a reset of the counter after the reception or transmission of a message in buffer 0. Each CAN module is a fast CPU bus peripheral which allows single-cycle byte or word read/write access. The CPU controls the CAN module by programming the registers in the CAN register block. This includes initialization of the CAN baud rate, logic level of the CAN pins, and enable/disable of the CAN module. A set of diagnostic features, such as loopback, listen only, and error identification, support development with the CAN module and provide a sophisticated error management tool. Each CAN module implements the following features: CAN specification 2.0B — Standard data and remote frames — Extended data and remote frames — 0 to 8 bytes data length — Programmable bit rate up to 1 Mbit/s 15 message buffers, each configurable as receive or transmit buffers — Message buffers are 16-bit wide dual-port RAM — One buffer may be used as a BASIC-CAN path Remote Frame support — Automatic transmission after reception of a Remote Transmission Request (RTR) — Auto receive after transmission of a RTR Acceptance filtering www.national.com 82 — Two filtering capabilities: global acceptance mask and individual buffer identifiers — One of the buffers uses an independent acceptance filtering procedure Programmable transmit priority Interrupt capability — One interrupt vector for all message buffers (receive/ transmit/error) — Each interrupt source can be enabled/disabled 16-bit counter with time stamp capability on successful reception or transmission of a message Power Save capabilities with programmable Wake-Up over the CAN bus (alternate source for the Multi-Input Wake-Up module) Push-pull capability of the input/output pins Diagnostic functions — Error identification — Loopback and listen-only features for test and initialization purposes 17.1 FUNCTIONAL DESCRIPTION As shown in Figure 16, each CAN module consists of three blocks: the CAN core, interface management, and a dualported RAM containing the message buffers. There are two dedicated device pins for each CAN interface, CANnTX as the transmit output and CANnRX as the receive input. The CAN core implements the basic CAN protocol features such as bit-stuffing, CRC calculation/checking, and error management. It controls the transceiver logic and creates error signals according to the bus rules. In addition, it converts the data stream from the CPU (parallel data) to the serial CAN bus data. The interface management block is divided into the register block and the interface management processor. The register block provides the CAN interface with control information from the CPU and provides the CPU with status information from the CAN module. Additionally, it generates the interrupt to the CPU. The interface management processor is a state machine executing the CPU’s transmission and reception commands and controlling the data transfer between several message buffers and the RX/TX shift registers. 15 message buffers are memory mapped into RAM to transmit and receive data through the CAN bus. Eight 16-bit registers belong to each buffer. One of the registers contains control and status information about the message buffer configuration and the current state of the buffer. The other registers are used for the message identifier, a maximum of up to eight data bytes, and the time stamp information. During the receive process, the incoming message will be stored in a hidden receive buffer until the message is valid. Then, the buffer contents will be copied into the first message buffer which accepts the ID of the received message. CP3CN23 CANnTX CANnRX Wake-Up CTX 0 1 0 1 CRX CAN CORE Transceiver Logic BTL, RX shift, TX shift, CRC Bit Stream Processor Error Management Logic Control INTERFACE MANAGEMENT Interface Management Processor Acceptance Filtering Status RAM Data Control TX/RX Message Buffer 0 TX/RX Message Buffer 1 Interface Management Processor BTL CONFIG CAN PRESCALER CONTROL ACCEPTANCE MASKS TX/RX Message Buffer 14 CPU BUS DS281 Figure 16. CAN Block Diagram A CAN master module has the ability to set a specific bit called the “remote data request bit” (RTR) in a frame. Such This section provides a generic overview of the basic cona message is also called a “Remote Frame”. It causes ancepts of the Controller Area Network (CAN). other module, either another master or a slave which acThe CAN protocol is a message-based protocol that allows cepts this remote frame, to transmit a data frame after the a total of 2032 (211 - 16) different messages in the standard remote frame has been completed. format and 512 million (229 - 16) different messages in the Additional modules can be added to an existing network extended frame format. without a configuration change. These modules can either Every CAN Frame is broadcast on the common bus. Each perform completely new functions requiring new data, or module receives every frame and filters out the frames process existing data to perform a new functionality. which are not required for the module's task. For example, As the CAN network is message oriented, a message can if a dashboard sends a request to switch on headlights, the be used as a variable which is automatically updated by the CAN module responsible for brake lights must not process controlling processor. If any module cannot process inforthis message. mation, it can send an overload frame. 17.2 BASIC CAN CONCEPTS 83 www.national.com CP3CN23 The CAN protocol allows several transmitting modules to start a transmission at the same time as soon as they detect the bus is idle. During the start of transmission, every node monitors the bus line to detect whether its message is over- written by a message with a higher priority. As soon as a transmitting module detects another module with a higher priority accessing the bus, it stops transmitting its own frame and switches to receive mode, as shown in Figure 17. TxPIN MODULE A RxPIN TxPIN MODULE B RxPIN BUS LINE RECESSIVE DOMINANT MODULE A SUSPENDS TRANSMISSION DS019 Figure 17. CAN Message Arbitration If a data or remote frame loses arbitration on the bus due to 17.2.2 CAN Frame Fields a higher-prioritized data or remote frame, or if it is destroyed Data and remote frames consist of the following bit fields: by an error frame, the transmitting module will automatically Start of Frame (SOF) retransmit it until the transmission is successful or software Arbitration Field has canceled the transmit request. Control Field If a transmitted message loses arbitration, the CAN module Data Field will restart transmission at the next possible time with the CRC Field message which has the highest internal transmit priority. ACK Field EOF Field 17.2.1 CAN Frame Types Communication via the CAN bus is basically established by means of four different frame types: Data Frame Remote Frame Error Frame Overload Frame Data and remote frames can be used in both standard and extended frame format. If no message is being transmitted, i.e., the bus is idle, the bus is kept at the “recessive” level. Remote and data frames are non-return to zero (NRZ) coded with bit-stuffing in every bit field, which holds computable information for the interface, i.e., start of frame, arbitration field, control field, data field (if present), and CRC field. Error and overload frames are also NRZ coded, but without bit-stuffing. After five consecutive bits of the same value (including inserted stuff bits), a stuff bit of the inverted value is inserted into the bit stream by the transmitter and deleted by the receiver. The following shows the stuffed and destuffed bit stream for consecutive ones and zeros. Original or 10000011111 . . . unstuffed bit stream Stuffed bit stream (stuff bits in bold) 01111100000 . . . Start of Frame (SOF) The Start of Frame (SOF) indicates the beginning of data and remote frames. It consists of a single “dominant” bit. A node is only allowed to start transmission when the bus is idle. All nodes have to synchronize to the leading edge (first edge after the bus was idle) caused by the SOF of the node which starts transmission first. Arbitration Field The Arbitration field consists of the identifier field and the RTR (Remote Transmission Request) bit. For extended frames there is also a SRR (Substitute Remote Request) and a IDE (ID Extension) bit inserted between ID18 and ID17 of the identifier field. The value of the RTR bit is “dominant” in a data frame and “recessive” in a remote frame. Control Field The Control field consists of six bits. For standard frames it starts with the ID Extension bit (IDE) and a reserved bit (RB0). For extended frames, the control field starts with two reserved bits (RB1, RB0). These bits are followed by the 4bit Data Length Code (DLC). The CAN receiver accepts all possible combinations of the reserved bits (RB1, RB0). The transmitter must be configured to send only zeros. 1000001111101 . . . 0111110000010 . . . www.national.com 84 CP3CN23 Data Length Code (DLC) The DLC field indicates the number of bytes in the data field. It consists of four bits. The data field can be of length zero. The admissible number of data bytes for a data frame ranges from 0 to 8. Data Field The remainder of this division is the CRC sequence transmitted over the bus. On the receiver side, the module divides all bit fields up to the CRC delimiter excluding stuff bits, and checks if the result is zero. This will then be interpreted as a valid CRC. After the CRC sequence a single “recessive” bit is transmitted as the CRC delimiter. ACK Field The Data field consists of the data to be transferred within a data frame. It can contain 0 to 8 bytes. A remote frame has The ACK field is two bits long and contains the ACK slot and the ACK delimiter. The ACK slot is filled with a “recessive” no data field. bit by the transmitter. This bit is overwritten with a “domiCyclic Redundancy Check (CRC) nant” bit by every receiver that has received a correct CRC The CRC field consists of the CRC sequence followed by sequence. The second bit of the ACK field is a “recessive” the CRC delimiter. The CRC sequence is derived by the bit called the acknowledge delimiter. transmitter from the modulo 2 division of the preceding bit fields, starting with the SOF up to the end of the data field, excluding stuff-bits, by the generator polynomial: x15 + x14 + x10 + x8 + x7 + x4 + x3 + 1 The End of Frame field closes a data and a remote frame. It consists of seven “recessive” bits. 17.2.3 CAN Frame Formats Data Frame The structure of a standard data frame is shown in Figure 18. The structure of an extended data frame is shown in Figure 19. STANDARD DATA FRAME (number of bits = 44 + 8N) 8N (0 < N < 8) START OF FRAME ID 10 16 CRC Field 8 15 CRC Arbitration Field 11 Control Field 4 ID0 RTR IDE RB0 DLC3 DLC Data Field 8 CRC DEL ACKNOWLEDGEMENT ACK DEL END OF FRAME d IDENTIFIER 10 ... 0 ddd r rrrrrrrr DATA LENGTH CODE Bit Stuffing Note: d = dominant r = recessive DS020 Figure 18. Standard Data Frame EXTENDED DATA FRAME (number of bits = 64 + 8N) 8N (0 < N < 0) START OF FRAME ID 28 16 CRC Field CRC DEL SCK ACK DEL Arbitration Field 11 ID18 SRR IDE ID17 Control Field 18 ID0 RTR RB1 RB0 DLC3 Data Field 8 8 END OF FRAME 4 DLC 15 CRC d IDENTIFIER 28 ... 18 rr ddd r rrrrrrrr IDENTIFIER 17 ... 0 DATA LENGTH CODE Bit Stuffing Note: d = dominant r = recessive DS021 Figure 19. Extended Data Frame 85 www.national.com CP3CN23 A CAN data frame consists of the following fields: Start of Frame (SOF) Arbitration Field + Extended Arbitration Control Field Data Field Cyclic Redundancy Check Field (CRC) Acknowledgment Field (ACK) End of Frame (EOF) Remote Frame Figure 20 shows the structure of a standard remote frame. Figure 21 shows the structure of an extended remote frame. STANDARD REMOTE FRAME (number of bits = 44) 16 START OF FRAME ID 10 Arbitration Field 11 ID0 RTR IDE RB0 DLC3 Control Field 4 DLC0 CRC Field 15 CRC CRC DEL ACKNOWLEDGEMENT ACK DEL r END OF FRAME d IDENTIFIER 10 ... 0 Note: d = dominant r = recessive ID3 ddd rrrrrrrr DATA LENGTH CODE DS022 Figure 20. Standard Remote Frame EXTENDED REMOTE FRAME (number of bits = 64) 16 START OF FRAME ID 28 Arbitration Field 11 ID18 SRR IDE ID17 18 ID0 RTR RB1 RB0 DLC3 Control Field 4 DLC0 CRC Field CRC DEL SCK ACK DEL r rrrrrrrr 15 CRC END OF FRAME d IDENTIFIER 28 ... 18 Note: d = dominant r = recessive rr rdd IDENTIFIER 17 ... 0 DATA LENGTH CODE DS023 Figure 21. Extended Remote Frame A remote frame is comprised of the following fields, which is the same as a data frame (see CAN Frame Fields on page 84) except for the data field, which is not present. Start of Frame (SOF) Arbitration Field + Extended Arbitration Control Field Cyclic Redundancy Check Field (CRC) Acknowledgment field (ACK) End of Frame (EOF) Note that the DLC must have the same value as the corresponding data frame to prevent contention on the bus. The RTR bit is “recessive”. www.national.com 86 CP3CN23 Error Frame at the bit following the acknowledge delimiter, unless an erAs shown in Figure 22, the Error Frame consists of the error ror flag for a previous error condition has already been startflag and the error delimiter bit fields. The error flag field is ed. built up from the various error flags of the different nodes. If a device is in the error active state, it can send a “domiTherefore, its length may vary from a minimum of six bits up nant” error flag, while a error passive device is only allowed to a maximum of twelve bits depending on when a module to transmit “recessive” error flags. This is done to prevent has detected the error. Whenever a bit error, stuff error, form the CAN bus from getting stuck due to a local defect. For the error, or acknowledgment error is detected by a node, the various CAN device states, please refer to Error Types on node starts transmission of an error flag at the next bit. If a page 88. CRC error is detected, transmission of the error flag starts ERROR FRAME 6 ERROR FLAG