CR16HCT9VJEX

CR16MCT9/CR16MCT5/CR16HCT9/CR16HCT5 16-Bit Reprogrammable/ROM Microcontroller February 2002 CR16MCT9/CR16MCT5/CR16HCT9/CR16HCT5 16-Bit Reprogrammable/ROM Microcontroller 1.0 General Description taining the advantages of a traditional Complex Instruction Set Computer (CISC): compact code, on-chip memory and I/O, and reduced cost. The CPU uses a three-stage instruction pipeline that allows execution of up to one instruction per clock cycle, or up to 24 million instructions per second (MIPS) at a clock rate of 24 MHz. The CR16MCT9/CR16MCT5/CR16HCT9/CR16HCT5 devices contain a FullCAN class, CAN serial interface for low/ high speed applications with 15 orthogonal message buffers, each supporting standard as well as extended message identifiers. The CR16MCT9/CR16MCT5/CR16HCT9/CR16HCT5 CompactRISC™ microcontroller are general-purpose 16bit microcontrollers based on a Reduced Instruction Set Computer (RISC) architecture. The device operates as a complete microcomputer with all system timing, interrupt logic, flash program memory or ROM memory, RAM, EEPROM data memory, and I/O ports included on-chip. It is ideally suited to a wide range of embedded controller applications because of its high performance, on-chip integrated features and low power consumption resulting in decreased system cost. The CR16MCT9/CR16MCT5/CR16HCT9/CR16HCT5 offer the high performance of a RISC architecture while re- Block Diagram CR16B RISC Core Fast Clk Slow Clk CR16CAN FullCAN 2.0B Processing Unit Clock Generator Power-on-Reset Core Bus Bus Interface Unit Peripheral Bus Controller 96k-Byte Flash Program Memory 4k-Byte RAM 2176-Byte 1.5k-Byte ISP EEPROM Memory Data Memory Interrupt Control Power Management Timing and Watchdog Peripheral Bus I/O µWire/SPI 2x USART ACCESS bus 4x VTU 2x MFT 12-ch 8-bit A/D MIWU 2 Analog Comparators Note: Not all peripherals shown above will be contained in any device. ©2002 National Semiconductor Corporation www.national.com Table of Contents 1.0 2.0 3.0 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.1 CR16B CPU Core . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.3 Input/Output Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.4 Bus Interface Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.6 Multi-Input Wake-up . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.7 Dual Clock and Reset . . . . . . . . . . . . . . . . . . . . . . . . 6 3.8 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.9 Multi-Function Timer . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.10 Versatile timer unit . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.11 Real-Time TIMER and Watchdog . . . . . . . . . . . . . . . 6 3.12 USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.13 MICROWIRE/SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.14 CR16CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.15 ACCESS.bus Interface . . . . . . . . . . . . . . . . . . . . . . . 7 3.16 A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.17 Analog Comparators . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.18 Development Support . . . . . . . . . . . . . . . . . . . . . . . . 7 Device Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.1 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 System Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.1 ENV0 and ENV1 Pins . . . . . . . . . . . . . . . . . . . . . . . 12 5.2 Module Configuration (MCFG) Register . . . . . . . . . 12 5.3 Module Status (MSTAT) Register . . . . . . . . . . . . . . 12 Input/Output Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.1 Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.2 Open-Drain Operation . . . . . . . . . . . . . . . . . . . . . . . 14 CPU and Core Registers. . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.1 General-Purpose Registers. . . . . . . . . . . . . . . . . . . 15 7.2 Dedicated Address Registers . . . . . . . . . . . . . . . . . 15 7.3 Processor Status Register . . . . . . . . . . . . . . . . . . . 15 7.4 Configuration Register . . . . . . . . . . . . . . . . . . . . . . 16 7.5 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.6 Stacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.7 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Bus Interface Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.1 Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.2 BIU Control Registers . . . . . . . . . . . . . . . . . . . . . . . 18 8.3 Wait and Hold States Used . . . . . . . . . . . . . . . . . . . 20 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9.1 Flash EEPROM Program Memory . . . . . . . . . . . . . 22 9.2 RAM Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9.3 Flash EEPROM Data Memory . . . . . . . . . . . . . . . . 25 9.4 ISP Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 10.1 Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . 31 10.2 Non-Maskable Interrupt. . . . . . . . . . . . . . . . . . . . . . 32 10.3 Maskable Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . 33 10.4 Interrupt Registers. . . . . . . . . . . . . . . . . . . . . . . . . . 33 10.5 Interrupt Programming Procedures . . . . . . . . . . . . . 34 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 11.1 Active Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 11.2 Power Save Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 36 11.3 Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 11.4 Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 11.5 Clock Inputs and Reset Configuration. . . . . . . . . . . 36 11.6 Switching Between Power Modes . . . . . . . . . . . . . . 36 Dual Clock and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 12.1 External Crystal Network. . . . . . . . . . . . . . . . . . . . . 39 12.2 Main System Clock . . . . . . . . . . . . . . . . . . . . . . . . . 40 12.3 Slow System Clock . . . . . . . . . . . . . . . . . . . . . . . . . 40 12.4 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 12.5 External Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 12.6 Dual Clock and Reset Registers . . . . . . . . . . . . . . . 41 12.7 Slow Clock Prescaler Register (PRSSC) . . . . . . . . 41 13.0 12.8 Slow Clock Prescaler 1 Register (PRSSC1) . . . . . 41 Multi-Input Wake-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 13.1 Wake-Up Edge Detection Register (WKEDG) . . . . 42 13.2 Wake-Up Enable Register (WKENA) . . . . . . . . . . . 42 13.3 Wake-Up Interrupt Control Register 1 (WKCTL1) . 43 13.4 Wake-Up Interrupt Control Register 1 (WKCTL2) . 43 13.5 Wake-Up Pending Register (WKPND). . . . . . . . . . 43 13.6 Wake-Up Pending Clear Register (WKPCL) . . . . . 43 13.7 Programming Procedures . . . . . . . . . . . . . . . . . . . 44 Real-Time Timer and WATCHDOG . . . . . . . . . . . . . . . . . 45 14.1 TWM Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 14.2 Timer T0 Operation . . . . . . . . . . . . . . . . . . . . . . . . 45 14.3 WATCHDOG Operation . . . . . . . . . . . . . . . . . . . . . 46 14.4 TWM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 14.5 WATCHDOG Programming Procedure . . . . . . . . . 48 Multi-Function Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 15.1 Timer Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 15.2 Timer Operating Modes . . . . . . . . . . . . . . . . . . . . . 51 15.3 Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 15.4 Timer I/O Functions . . . . . . . . . . . . . . . . . . . . . . . . 54 15.5 Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Versatile-Timer-Unit (VTU) . . . . . . . . . . . . . . . . . . . . . . . 58 16.1 VTU Functional Description . . . . . . . . . . . . . . . . . . 58 16.2 VTU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 MICROWIRE/SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 17.1 MICROWIRE Operation . . . . . . . . . . . . . . . . . . . . . 65 17.2 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 17.3 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 17.4 Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . 68 17.5 MICROWIRE Interface Registers. . . . . . . . . . . . . . 68 USART. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 18.1 Functional Overview. . . . . . . . . . . . . . . . . . . . . . . . 71 18.2 USART Operation . . . . . . . . . . . . . . . . . . . . . . . . . 71 18.3 USART Registers. . . . . . . . . . . . . . . . . . . . . . . . . . 75 18.4 Baud Rate Calculations . . . . . . . . . . . . . . . . . . . . . 77 ACCESS.bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . 78 19.1 ACB Protocol Overview . . . . . . . . . . . . . . . . . . . . . 78 19.2 ACB Functional Description . . . . . . . . . . . . . . . . . . 79 19.3 ACB Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 19.4 Usage Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 CR16CAN Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 20.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . 85 20.2 Basic CAN Concepts . . . . . . . . . . . . . . . . . . . . . . . 86 20.3 Message Transfer . . . . . . . . . . . . . . . . . . . . . . . . . 95 20.4 Acceptance Filtering. . . . . . . . . . . . . . . . . . . . . . . . 95 20.5 Receive Structure. . . . . . . . . . . . . . . . . . . . . . . . . . 96 20.6 Transmit Structure . . . . . . . . . . . . . . . . . . . . . . . . . 99 20.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 20.8 Time Stamp Counter . . . . . . . . . . . . . . . . . . . . . . 103 20.9 Memory Organization. . . . . . . . . . . . . . . . . . . . . . 103 20.10 System Start-Up and Multi-Input Wake-Up . . . . . 113 Analog Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 21.1 Analog Comparator Control/Status Register (CMPCTRL)116 21.2 Analog Comparator Usage. . . . . . . . . . . . . . . . . . 116 A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 22.1 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . 118 22.2 A/D Converter Registers . . . . . . . . . . . . . . . . . . . 119 22.3 A/D Converter Programming . . . . . . . . . . . . . . . . 121 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Register Layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 24.1 Register layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 ELECTRICAL AND THERMAL CHARACTERISTICS . . 135 Appendix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 26.1 8/16-bit microwire/spi (MWSPI16) . . . . . . . . . . . . 150 26.2 Timing and watchdog module . . . . . . . . . . . . . . . 150 Device Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Physical Dimensions inches. . . . . . . . . . . . . . . . . . . . . 153 14.0 15.0 4.0 5.0 16.0 17.0 6.0 7.0 18.0 19.0 8.0 20.0 9.0 10.0 21.0 11.0 22.0 12.0 23.0 24.0 25.0 26.0 27.0 28.0 www.national.com 2 1.0 General Description (Continued) • The device has up to 96K bytes of reprogrammable flash EEPROM program memory or ROM memory, 1.5K bytes of flash EEPROM In-System-Programming memory, 4K bytes of static RAM, 2K bytes of non-volatile EEPROM data memory and 128 bytes with high endurance, two USARTs, two 16bit multi-function timers, one SPI/MICROWIRE-PLUS™ serial interface, a 12-channel A/D converter, two analog comparators, WATCHDOG™ protection mechanism, and up to 56 general-purpose I/O pins. The device operates with a high-frequency crystal as the main clock source and either the prescaled main clock source or with a low frequency (32.768 kHz) oscillator in Power Save mode. The device supports several Power Save modes which are combined with multi-source interrupt and wake-up capabilities. This device also has a Versatile Timer Unit (VTU) with four timer sub-systems, a CAN interface, and ACCESS.bus synchronous serial bus interface. Powerful cross-development tools are available from National Semiconductor and third party suppliers to support the development and debugging of application software for the device. These tools let you program the application software in C and are designed to take full advantage of the CompactRISC architecture. In the following text, device is always referred to the family of 16-bit CAN-enabled CompactRISC Microtroller. • • • — Versatile Timer Unit with four subsystems (VTU) — Two analog comparators — Integrated WATCHDOG logic I/O Features — Up to 56 general-purpose I/O pins (shared with on-chip peripheral I/O pins) — Programmable I/O pin characteristics: TRI-STATE output, push-pull output, weak pull-up input, high-impedance input — Schmitt triggers on general purpose inputs Power Supply — 4.5V to 5.5V single-supply operation Temperature Range — –40°C to +125°C — –40°C to +85°C — 0°C to +70°C Development Support — Real-time emulation and full program debug capabilities available — CompactRISC tools provide C programming and debugging support 2.0 • Features • • • CPU Features — Fully static core, capable of operating at any rate from 0 to 24 MHz (4 MHz minimum in active mode) — 41.67 ns instruction cycle time with a 24 MHz external clock frequency — Multi-source vectored interrupts (internal, external, and on-chip peripheral) — Dual clock and reset On-chip power-on reset On-Chip Memory — 96K bytes flash EEPROM program memory or ROM memory — 4K bytes of static RAM data memory — For flash program memory, 1.5k bytes flash EEPROM memory is used to store boot loader code — 2K bytes of non-volatile EEPROM data memory with low endurance (25K cycles) and 128 bytes with high endurance (100K cycles) On-Chip Peripherals — Two Universal Synchronous/Asynchronous Receiver/ Transmitter (USART) devices — Two dual 16-bit multi-function timers (MFT1 and MFT2) — 8/16-bit SPI/MICROWIRE-PLUS serial interface — 12-channel, 8-bit Analog-to-Digital (A/D) converter with external voltage reference, programmable sample-and-hold delay, and programmable conversion frequency — ACCESS.bus synchronous serial bus — FullCAN interface with 15 message buffers complaint to CAN specification 2.0B active 3 www.national.com CR16 CompactRISC Microcontroller with CAN Interface Family Selection Guide Programmable devices EEPROM Data Memory (Bytes) 2176 2176 NSID Speed (MHz) Flash (kByte) SRAM (kBytes) USART Timer I/Os Temp. Range Peripherals Package Type CR16MCT9VJEx CR16HCT9VJEx 16 24 96 96 4 4 2 2 2MFT VTU 2MFT VTU 56 56 E, I, C E, I, C ADC, CAN, Comparators ADC, CAN, Comparators 80PQFP 80PQFP Reprogrammable ROMa EEPROM Data Memory (Bytes) 2176 2176 NSID Speed Flash (MHz) (KByte) SRAM (kBytes) USART Timer I/Os Temp. Range Peripherals Package Type CR16MCT9VJExy CR16HCT9VJExy ROM devices 16 24 96 96 4 4 2 2 2MFT VTU 2MFT VTU 56 56 E, I, C E, I, C ADC, CAN, Comparators ADC, CAN, Comparators 80PQFP 80PQFP NSID Speed (MHz) ROM (KByte) EEPROM Data Memory (Bytes) 2176 2176 SRAM (kBytes) USART Timer I/Os Temp. Range Peripherals Package Type CR16MCT5VJExy CR16HCT5VJExy 16 24 96 96 4 4 2 2 2MFT VTU 2MFT VTU 56 56 E, I, C E, I, C ADC, CAN, Comparators ADC, CAN, Comparators 80PQFP 80PQFP Note: a. National offers Reprogrammable ROM that allow devices to be programmed in factory and reprogrammed by the customer. • Suffix x in the NSID is defined below: Temperature Ranges: I = Industrial E = Extended C= Commerial • Suffix y in the NSID defines the ROM code. -40°C to +125°C is represented when x is 7 -40°C to +85°C is represented when x is 8 0°C to +70°C is represented when x is 9 Note: All devices contains Access.bus (ACB), Clock and Reset, MICROWIRE/API, Multi-Input Wake-Up (MIWU), Power Management (PMM), and the Real-Time Timer and Watchdog (TWM) modules. Access.bus is compatible with I2C bus offered by Philips Semiconductor. CR16 CompactRISC Microcontroller with CAN Interface Family Devices National Semiconductor currently offers a variety of the CR16 CompactRISC Microcontrollers with CAN interface. The CR16MCS offer complete functionality in an 80-pin PQFP package. www.national.com 4 3.0 Device Overview The 4K bytes of static RAM are used for temporary storage of data and for the program stack and interrupt stack. Read and write operations can be byte-wide or word-wide, depending on the instruction executed by the CPU. Each memory access requires one clock cycle; no wait cycles or hold cycles are required. There are two types of flash EEPROM data memory storage. The 2K bytes of EEPROM data memory with low endurance (25K cycles) and 128 bytes of flash EEPROM data memory with high endurance (100K cycles) are used for non-volatile storage of data, such as configuration settings entered by the end-user. The 96K bytes of flash EEPROM program memory are used to store the application program. It has security features to prevent unintentional programming and to prevent unauthorized access to the program code. This memory can be programmed with a device external programming unit or with the device installed in the application system (in-system programming). There is a factory programmed boot memory used to store In-System-Programming (ISP) code. (This code allows programming of the program memory via one of the USART interfaces in the final application.) For flash EEPROM program and data memory, the device internally generates the necessary voltages for programming. No additional power supply is required. The CR16MCT9/CR16MCT5/CR16HCT9/CR16HCT5 CompactRISC microcontrollers are complete microcomputers with all system timing, interrupt logic, program memory, data memory, and I/O ports included on-chip, making it well-suited to a wide range of embedded controller applications. The block diagram on page 1 of the data sheet shows the major on-chip components of the CR16MCT9/CR16MCT5/ CRHCT9/CR16HCT5. 3.1 CR16B CPU CORE The CR16MCT9/CR16MCT5/CR16HCT9/CR16HCT5 use the CR16B CPU core module. This is the same core used in other CompactRISC family member designs, like DECT or GSM chipsets. The high performance of the CPU core results from the implementation of a pipelined architecture with a two-bytes-percycle pipelined system bus. As a result, the CPU can support a peak execution rate of one instruction per clock cycle. Compared with conventional RISC processors, the CR16MCT9/CR16MCT5/CR16HCT9/CR16HCT5 differ in the following ways: — The CPU core can use on-chip rather than external memory. This eliminates the need for large and complex bus interface units. — Most instructions are 16 bits, so all basic instructions are just two bytes long. Additional bytes are sometimes required for immediate values, so instructions can be two or four bytes long. — Non-aligned word access is allowed. Each instruction can operate on 8-bit or 16-bit data. — The device is designed to operate with a clock rate in the 10 to 24 MHz range rather than 100 MHz or more. Most embedded systems face EMI and noise constraints that limit clock speed to these lower ranges. A lower clock speed means a simpler, less costly silicon implementation. — The instruction pipeline uses three stages. A smaller pipeline eliminates the need for costly branch prediction mechanisms and bypass registers, while maintaining adequate performance for typical embedded controller applications. For more information, please refer to the CR16B Programmer’s Reference Manual, Literature #: 633150. 3.3 INPUT/OUTPUT PORTS The device has 56 software-configurable I/O pins, organized into seven 8-pin ports called Port B, Port C, Port F, Port G, Port H, Port I, and Port L. Each pin can be configured to operate as a general-purpose input or general-purpose output. In addition, many I/O pins can be configured to operate as a designated input or output for an on-chip peripheral module such as the USART, timer, A/D converter, or MICROWIRE/ SPI interface. The I/O pin characteristics are fully programmable. Each pin can be configured to operate as a TRI-STATE output, pushpull output, weak pull-up input, or high-impedance input. 3.4 BUS INTERFACE UNIT 3.2 MEMORY The CompactRISC architecture supports a uniform linear address space of 2 megabytes. The device implementation of this architecture uses only the lowest 128K bytes of address space. Four types of on-chip memory occupy specific intervals within this address space: • • • • • 96K bytes of flash EEPROM program memory (100K cycles) 4K bytes of static RAM 2K bytes of EEPROM data memory with low endurance (25K cycles) 128 bytes EEPROM data memory with high endurance (100K cycles) 1.5K bytes flash EEPROM memory for ISP code The Bus Interface Unit (BIU) controls the interface between the on-chip modules to the internal core bus. It determines the configured parameters for bus access (such as the number of wait states for memory access) and issues the appropriate bus signals for each requested access. The BIU uses a set of control registers to determine how many wait states and hold states are to be used when accessing flash EEPROM program memory, ISP memory and the I/O area (Port B and Port C). Upon start-up the configuration registers are set for slowest possible memory access. To achieve fastest possible program execution, appropriate values should be programmed. These settings vary with the clock frequency and the type of on-chip device being accessed. 5 www.national.com 3.5 INTERRUPTS 3.9 MULTI-FUNCTION TIMER The Interrupt Control Unit (ICU31L) receives interrupt requests from internal and external sources and generates interrupts to the CPU. An interrupt is an event that temporarily stops the normal flow of program execution and causes a separate interrupt service routine to be executed. After the interrupt is serviced, CPU execution continues with the next instruction in the program following the point of interruption. Interrupts from the timers, USARTs, MICROWIRE/SPI interface, multi-input wake-up, and A/D converter are all maskable interrupts; they can be enabled or disabled by the software. There are 32 of these maskable interrupts, organized into 32 predetermined levels of priority. The highest-priority interrupt is the Non-Maskable Interrupt (NMI), which is generated by a signal received on the NMI input pin. The Multi-Function Timer (MFT16) module contains two independent timer/counter units called MFT1 and MFT2, each containing a pair of 16-bit timer/counter registers. Each timer/ counter unit can be configured to operate in any of the following modes: — Processor-Independent Pulse Width Modulation (PWM) mode, which generates pulses of a specified width and duty cycle, and which also provides a general-purpose timer/counter. — Dual Input Capture mode, which measures the elapsed time between occurrences of external events, and which also provides a general-purpose timer/ counter. — Dual Independent Timer mode, which generates system timing signals or counts occurrences of external events. — Single Input Capture and Single Timer mode, which provides one external event counter and one system timer. 3.6 MULTI-INPUT WAKE-UP The Multi-Input Wake-Up (MIWU16) module can be used for either of two purposes: to provide inputs for waking up (exiting) from the HALT, IDLE, or Power Save mode; or to provide general-purpose edge-triggered maskable interrupts from external sources. This 16-channel module generates four programmable interrupts to the CPU based on the signals received on its 16 input channels. Channels can be individually enabled or disabled, and programmed to respond to positive or negative edges. 3.10 VERSATILE TIMER UNIT The Versatile Timer Unit (VTU) module contains four independent timer subsystems, each operating in either dual 8-bit PWM configuration, as a single 16-bit PWM timer, or a 16-bit counter with two input capture channels. Each of the four timer subsystems offer an 8-bit clock prescaler to accommodate a wide range of frequencies. 3.7 DUAL CLOCK AND RESET 3.11 REAL-TIME TIMER AND WATCHDOG The Dual Clock and Reset (CLK2RES) module generates a high-speed main system clock from an external crystal network. It also provides the main system reset signal and a power-on reset function. This module also generates a slow system clock (32.768 kHz) from another external crystal network. The slow clock is used for operating the device in power-save mode. Without a 32.768kHz external crystal network, the low speed system clock can be derived from the high speed clock by a prescaler. Also, two independent clocks divided down from the high speed clock are available on output pins. The Timing and Watchdog Module (TWM) generates the clocks and interrupts used for timing periodic functions in the system. It also provides Watchdog protection against software errors. The module operates on the slow system clock. The real-time timer can generate a periodic interrupt to the CPU at a software-programmed interval. This can be used for real-time functions such as a time-of-day clock. The realtime timer can trigger a wake-up condition from power-save mode via the Multi-Input Wake-Up module. The Watchdog is designed to detect program execution errors such as an infinite loop or a “runaway” program. Once Watchdog operation is initiated, the application program must periodically write a specific value to a Watchdog register, within specific time intervals. If the software fails to do so, a Watchdog error is triggered, which resets the device. 3.8 POWER MANAGEMENT The Power Management Module (PMM) improves the efficiency of the device by changing the operating mode and therefore the power consumption according to the required level of activity. The device can operate in any of four power modes: — Active: The device operates at full speed using the high-frequency clock. All device functions are fully operational. — Power Save: The device operates at reduced speed using the slow clock. The CPU and some modules can continue to operate at this low speed. — IDLE: The device is inactive except for the Power Management Module and Timing and Watchdog Module, which continue to operate using the slow clock. — HALT: The device is inactive but still retains its internal state (RAM and register contents). 3.12 USART The USART supports a wide range of programmable baud rates and data formats, and handles parity generation and several error detection schemes. The baud rate is generated on-chip, under software control. There are two independent USARTs in the device and they offer a wake-up condition from the power-save mode via the Multi-Input Wake-Up module. 3.13 MICROWIRE/SPI The MICROWIRE/SPI (MWSPI) interface module supports synchronous serial communications with other devices that conform to MICROWIRE or Serial Peripheral Interface (SPI) specifications. It supports 8-bit and 16-bit data transfers. www.national.com 6 The MICROWIRE interface allows several devices to communicate over a single system consisting of four wires: serial in, serial out, shift clock, and slave enable. At any given time, the MICROWIRE interface operates as the master or a slave. The support supports the full set of slave select for multislave implementation. In master mode, the shift clock is generated on chip under software control. In slave mode, a wake-up out of powersave mode is triggered via the Multi-Input Wake-Up module. 3.17 ANALOG COMPARATORS The Dual Analog Comparator (ACMP2) module contains two independent analog comparators with all necessary control logic. Each comparator unit compares the analog input voltages applied to two input pins and determines which voltage is higher. The CPU uses a memory-mapped register to control the comparator and to obtain the comparison results. The comparison result can also be applied to comparator output pins. 3.14 CR16CAN 3.18 DEVELOPMENT SUPPORT The CR16CAN device contains a FullCAN class, CAN serial bus interface for applications that require a high speed (up to 1MBits per second) or a low speed interface with CAN bus master capability. The data transfer between CAN and the CPU is established by 15 memory mapped message buffers, which can be individually configured as receive or transmit buffers. An incoming message is filtered by two masks, one for the first 14 message buffers and another one for the 15th message buffer to provide a basic CAN path. A priority decoder allows any buffer to have the highest or lowest transmit priority. Remote transmission requests can be processed automatically by automatic reconfiguration to a receiver after transmission or by automated transmit scheduling upon reception. In addition, a time stamp counter (16-bits wide) is provided to support real time applications. The CR16CAN device is a fast core bus peripheral, which allows single cycle byte or word read/write access. A set of diagnostic features (such as loopback, listen only, and error identification) support the development with the CR16CAN module and provide a sophisticated error management tool. The CR16CAN receiver can trigger a wake-up condition out of the power-save modes via the Multi-Input Wake-Up module. A powerful cross-development tool set is available from National Semiconductor and third parties to support the development and debugging of application software for the CR16MCT9/CR16MCT5/CR16HCT9/CR16HCT5. The tool set lets you program the application software in C and is designed to take full advantage of the CompactRISC architecture. There are In-System Emulation (ISE) devices available for the device from iSYSTEM™, as well as lower-cost evaluation boards. See your National Semiconductor sales representative for current information on availability and features of emulation equipment and evaluation boards. 3.15 ACCESS.BUS INTERFACE The ACCESS.bus interface module (ACB) is a two-wire serial interface with the ACCESS.bus physical layer. It is also compatible with Intel’s System Management Bus (SMBus) and Philips’ I2C bus. The ACB module can be configured as a bus master or slave, and can maintain bi-directional communications with both multiple master and slave devices. The ACCESS.bus receiver can trigger a wake-up condition out of the power-save modes via the Multi-Input Wake-Up module. 3.16 A/D CONVERTER The A/D Converter (ADC) module is a 12-channel multiplexed-input analog-to-digital converter. The A/D Converter receives an analog voltage signal on an input pin and converts the analog signal into an 8-bit digital value using successive approximation. The CPU can then read the result from a memory-mapped register. The module supports four automated operating modes, providing single-channel or 4channel operation in single or continuous mode. The device has a separate pin, Vref, for the A/D reference voltage. 7 www.national.com 4.0 Device Pinouts Table 1 Pin Name PH4 PH5 PH6 PH7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 ENV0/CLKOUT1 SDA SCL GND Vcc GND CANTx CANRx PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PG7 PG6 PG5 PG4 PG3 PG2 PG1 PG0 CLKOUT2 ENV1/CLK PF7 PF6 PF5 PF4 PF3 PF2 PF1 1 Package Pin Assignments Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 D8 D9 D10 D11 D12 D13 D14 D15 CKX1 TDX1 RDX1 TIO6 TIO5 CKX2 TDX2 RDX2 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 37 TIO4 TIO3 T2B T2A TIO2 TIO1 TIB 38 39 40 41 42 43 44 Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PWR PWR PWR O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O I/O I/O I/O I/O I/O I/O I/O I/O Alternate Function(s) MWCS MD1D0 MD0D1 MSK D0 D1 D2 D3 D4 D5 D6 D7 www.national.com 8 Table 1 Pin Name PF0 NMI X1CKO X1CKI GND Vcc GND X2CKO X2CKI RESET PI0 PI1 PI2 PI3 PI4 PI5 PI6 PI7 Vref AGND AVcc PH0 PH1 PH2 PH3 GND Vcc GND PL0 PL1 PL2 PL3 PL4 PL5 PL6 PL7 2 Package Pin Assignments Pin Number 45 46 47 48 49 50 51 52 53 54 ACH03 ACH13 ACN23 ACH3 ACH5 ACH7 3 Alternate Function(s) TIA Type I/O I O I PWR PWR PWR O I I I/O I/O I/O I/O I/O I/O I/O I/O PWR PWR PWR I/O I/O I/O I/O PWR PWR PWR I/O I/O I/O I/O I/O I/O I/O I/O 55 56 57 58 59 60 61 62 63 64 65 ACH43 3 ACH63 3 ACH8 , WUI4 ACH93, WUI5 ACH10 , WUI6 ACH113, WUI7 3 3 66 67 68 69 70 71 72 COMP1N3, WUI0 COMP1P , WUI1 COMP1O, WUI2 COMP2O, WUI3 COMP2P3 COMP2N3 TIO7 TIO8 3 73 74 75 76 77 78 79 80 Note 1: The ENV0 a nd ENV1 pins each have a weak pull-up to keep the input from floating. Note 2: The RESET input has a weak pulldown. Note 3: These functions are always enabled, due to the direct low-impedance path to these pins. 9 www.national.com 4.1 PIN DESCRIPTION The following is a brief description of all device pins. Some pins have alternate functions which may be enabled. These pins can be individually configured as general purpose pins, even when the module they belong to is enabled. Table 2 Signal X1CKI X2CKI Type OSC OSC Active High High Low Low Prog. Prog. High High * * * * * * * * * * * * * * * * Low Low Low Low Low High * * * Pin (* for a shared pin) Main oscillator clock input. 32kHz oscillator clock input. Chip general reset pin. Schmitt trigger input, asynchronous. Interrupt input for development system. Timer 1 input B. Shares pin with I/O port pin PF1. Timer 2 input B. Shares pin with I/O port pin PF5. USART 1 receive data input. Shares pin with I/O port pin PG5. USART 2 receive data input. Shares pin with I/O port pin PG0. A2D converter channel 0. Shares pin with I/O port pin PI0 A2D converter channel 1. Shares pin with I/O port pin PI1 A2D converter channel 2. Shares pin with I/O port pin PI2 A2D converter channel 3. Shares pin with I/O port pin PI3 A2D converter channel 4. Shares pin with I/O port pin PI4 A2D converter channel 5. Shares pin with I/O port pin PI5 A2D converter channel 6. Shares pin with I/O port pin PI6 A2D converter channel 7. Shares pin with I/O port pin PI7 A2D converter channel 8. Shares pin with I/O port pin PH0 A2D converter channel 9. Shares pin with I/O port pin PH1 A2D converter channel 10. Shares pin with I/O port pin PH2 A2D converter channel 11. Shares pin with I/O port pin PH3 SPI/MICROWIRE slave select. Shares pin with I/O port pin PH4. External non-maskable interrupt. Strap to select operating environment. Strap pin to select operating environment. Strap pin to select operating environment. CAN receive data input. Table 3 Signal X1CKO X2CKO CLK Type OSC OSC Active High High * * * * * Pin (* for a shared pin) Main oscillator clock output. 32kHz oscillator clock output. External reference clock for development environment (shared with ENV1). Clock output generated through prescaler (shared with ENV0). Clock output generated through prescaler (shared with ENV1). USART 1 transmit data output (shared with PG6). USART 2 transmit data output (shared with PG1). CAN output. Output Pins Function Input Pins Function RESET CMOS ISE T1B T2B RDX1 RDX2 ACH0 ACH1 ACH2 ACH3 ACH4 ACH5 ACH6 ACH7 ACH8 ACH9 ACH10 ACH11 MWCS NMI ENV0 ENV1 ENV2 CMOS CMOS CMOS CMOS CMOS Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog CMOS CMOS CMOS CMOS CMOS CANRx CMOS CMOS High CLKOUT1 CMOS High CLKOUT2 CMOS High TDX1 TDX2 CANTx CMOS High CMOS High CMOS High www.national.com 10 Table 4 Signal PF[0:7] PG[0:7] PB[0:7] PC[0:7] PL[0:7] PH[0:7] PI[0:7] T1A T2A TIO[0:7] MDIDO MDODI MSK CKX1 CKX2 SCL SDA Type Active * * * * * * * * * * * * * * * Pin (* for a shared pin) Input/Output Pins Function CMOS High CMOS High CMOS High CMOS High CMOS High CMOS High CMOS High CMOS Prog CMOS Prog CMOS Prog CMOS High CMOS High CMOS Prog CMOS High CMOS High CMOS High CMOS High Generic I/O port. Shared with T1A, T1B, TIO1, TIO2, T2A, T2B, TIO3, TIO4. Generic I/O port. Shared with RDX2, TDX2, CKX2, TIO5, TIO6, RDX1, TDX1, CKX1. Generic I/O port. Generic I/O port. Generic I/O port. Shared with 6 comparator pins, MIWU16 on PL0:3. Generic I/O port. Shared with ADC input channels 8-11, MWCS, MDIDO, MDODI, MSK; MIWU16 on PH4:7. Generic I/O port. Shared with ADC input channels 0-7. Timer 1 input A. Shared with I/O port pin PF0. Timer 2 input A. Shared with I/O port pin PF4. Versatile timer unit I/Os. Shared with PF2:3, PF6:7, PG3:4, PL6:7. Master In/Slave Out port: SPI/Microwire. Shared with I/O pin PH5, Master Out/Slave In port: SPI/Microwire. Shared with I/O pin PH6. SPI/Microwire clock. Shared with I/O pin PH7. USART 1 clock. Shared with I/O pin PG7. USART 2 clock. Shared with I/O pin PG2 ACCESS.bus clock I/O. ACCESS.bus data I/O. Table 5 Power Supply Function Main digital power supply (4 total). Voltage reference supply for analog to digital converter. Analog power supply for analog/digital converter. Signal Vcc Vref AVcc AGND Analog reference ground supply. GND Main digital reference ground (8 total). 11 www.national.com 5.0 System Configuration The MCFG register format is shown below. 7 6 5 4 3 2 CLK1OE 1 0 Reserved CLK2OE Reserved CLKOE Reserved The device has two input pins, ENV0 and ENV1, which are used to specify the operating environment of the device upon reset. There are also two system configuration registers, called the Module Configuration (MCFG) register and the Module Status (MSTAT) register. CLKOE 5.1 ENV0 AND ENV1 PINS Upon reset, the operating mode of the device is determined by the state of the ENV0 and ENV1 input pins, as indicated in Table 6. Table 6 ENV1 0 0 1 1 ENV0 0 1 0 1 Operating Environment Selection Operating Environment Test Mode Flash Memory Test Mode In-System-Programming mode (ISP) Internal ROM enabled Mode (IRE), if program memory is not empty; or ISPMode, if program memory is empty CLK1OE CLK2OE CPU Clock Output Enable. When this bit is cleared (0), the CLK pin (ENV1) remains in the high-impedance state. When this bit is set (1) in normal operating mode, the CLK pin operates as a CPU clock output. Generated Clock Output 1 Enable. When cleared (0), the CLKOUT1 pin (ENV0) stays in high impedance state. When set (1), the pin outputs the clock from the prescaler controlled by PRSSC1.SCDIV1. Generated Clock Output 2 Enable. When this bit is set (1) and CLKOE is cleared, the CLKOUT2 pin (ENV1) outputs the clock from the prescaler controlled by PRSSC1.SCDIV2. Otherwise, the CLKOUT2 pin is in high impedance state. 5.3 MODULE STATUS (MSTAT) REGISTER In the case where the ENV1 and ENV0 pins are both high, the reset algorithm looks at the FLCTRL2.EMPTY bit to determine whether the program memory is empty, and sets the operating mode accordingly. The ENV0 and ENV1 pins have on-chip pull-up devices that are enabled during reset while the pins are being sampled. Therefore, if they are left unconnected, the inputs are considered high and the normal operating mode (IRE-Mode) is selected and the CPU starts to execute code at address 0. To enter any other operating mode, the external hardware must drive the appropriate input low. In the case where the ISP-Mode is selected, the chip starts executing the ISP code residing in the on-chip ISP-Memory area. The test modes are Reserved for factory testing and for external programming of the flash EEPROM program memory. They should not be invoked otherwise. The MSTAT register is a byte-wide, read-only register that indicates the general status of the device. The MCFG register format is shown below. 7 4 Reserved OENV(1:0) 3 PGMBUSY 2 Reserved 1 OENV1 0 OENV0 PGMBUSY 5.2 MODULE CONFIGURATION (MCFG) REGISTER Operating Environment. These two bits contain the values applied to the ENV1 and ENV0 pins upon reset. These bit values are controlled by the external hardware upon reset and are held constant in the register until the next reset. Flash EEPROM Programming Busy. This bit is automatically set to 1 when either the program memory or the data memory is busy being programmed or erased. It is cleared to 0 when neither of the two flash EEPROM memories is busy being programmed or erased. When this bit is set, the software should not attempt any write access to either of these two memories. The MCFG register is a byte-wide, read/write register that sets the clock output features of the device. Upon reset, the non-reserved bits of this register are cleared to zero. The start-up software must write a specific value to this register in order to configure the CLK output pin function. When the software writes to this register, it must write a zero to each reserved bit for the device to operate properly. The register should be written in active mode only, not in power save, HALT, or IDLE mode. However, the register contents are preserved during all power modes. www.national.com 12 6.0 Input/Output Ports on-chip module where it is latched. A Schmitt-Trigger minimizes the effects of electrical noise. The electrical characteristics and drive capabilities of the input and output buffers are described in Section 25.0. For some pins, a direct low-impedance path is provided between the pin and an internal analog function. These are the input pins to the A/D converter and the analog comparators. Each device has up to 56 software-configurable I/O pins, organized into seven ports of up to eight pins per port. The ports are named Port B, Port C, Port F, Port G, Port H, Port I, and Port L. Each pin can be configured to operate as a general-purpose input or general-purpose output. In addition, many I/O pins can be configured to operate as a designated input or output for an on-chip peripheral module such as the USART or the Multi-Input Wakeup. This is called the pin's “alternate function.” The alternate functions of all I/O pins are shown in the pinout diagrams in Table 1. The I/O pin characteristics are fully programmable. Each pin can be configured to operate as a TRI-STATE output, pushpull output, weak pull-up input, or high-impedance input. Different pins within the same port can be individually configured to operate in different modes. Figure 1 is a diagram showing the functional features of an I/ O port pin. The register bits, multiplexers, and buffers allow the port pin to be configured into the various operating modes.The output buffer is a TRI-STATE buffer with weak pull-up capability. The weak pull-up, if used, prevents the port pin from going to an undefined state when it operates as an input. The input buffer is disabled when it is not needed to prevent leakage current caused by an input signal’s level between Vcc-0.2 and Vss+0.2 [Volts]. When enabled, it buffers the input signal and sends the pin's logic level to the appropriate 6.1 PORT REGISTERS Each port has an associated set of memory-mapped registers used for controlling the port and for holding the port data. In general, there are five such registers: — — — — — PxALT: Port alternate function register PxDIR: Port direction register PxDIN: Port data input register PxDOUT: Port data output register PxWKPU: Port weak pull-up register In the descriptions of the ports and port registers, the lowercase letter “x” represents the port designation, either B, C, F, G, H, I, or L. For example, “PxDIR register” means any one of the port direction registers: PBDIR, PCDIR, PFDIR, and so on. All of the port registers are byte-wide read/write registers, except for the port data input registers, which are read-only registers. Each register bit controls the function of the corresponding port pin. For example, PFDIR.2 (bit 2 of the PFDIR register) controls the operation of port pin PF2. Alternate Function enable Weak pull-up Register Alt Device Direction Direction Register { { { Weak pull-up Direction Alt MUX2 Alt Device Data Output Data Out Register Data Input Alternate Data Input Alt Data In Read Strobe Data Out MUX1 PIN Alt * Figure 1. I/O Pin Functional Diagram 13 MUX3 Alt 1 www.national.com 6.1.1 Port Alternate Function Register 6.2 OPEN-DRAIN OPERATION Each port that supports an alternate function (any port other than Port B or Port C) has an alternate function register (PxALT). This register determines whether the port pins are used for general-purpose I/O or for the predetermined alternate function. Each port pin can be controlled independently. A bit cleared to 0 in the alternate function register causes the corresponding pin to be used for general-purpose I/O. In this configuration, the output buffer is controlled by the direction register and the data output register. The input buffer is routed to the data input register. The input buffer is blocked except when the buffer is actually being read. A bit set to 1 in the alternate function register causes the corresponding pin to be used for its predetermined peripheral I/ O function. The output buffer data and TRI-STATE configuration are controlled by signals coming from the on-chip peripheral device. The input buffer is enabled continuously in this case. To minimize power consumption, the input signal should be held within 0.2 volts of the VCC or GND voltage. A reset operation clears the port alternate function registers to 0, which programs the pins to operate as general-purpose I/O ports. This register must be enabled before the corresponding alternate function is enabled. 6.1.2 Port Direction Register A port pin can be configured to operate as an inverting opendrain output buffer. To do this, the CPU should clear the bit in the data output register (PxDOUT) and then use the port direction register (PxDIR) to set the value of the port pin. With the direction register bit set to 1 (direction=out), the value zero is forced on the pin. With the direction register bit cleared to 0 (direction=in), the pin is placed in the TRI-STATE mode. If desired, the internal weak pull-up can be enabled to pull the signal high when the output buffer is in the TRISTATE mode. The port direction register (PxDIR) determines whether each port pin is used for input or for output. A bit cleared to 0 causes the pin to operate as an input, which puts the output buffer in the high-impedance state. A bit set to 1 causes the pin to operate as an output, which enables the output buffer. A reset operation clears the port direction registers to 0, which programs the pins to operate as inputs. 6.1.3 Port Data Input Register The data input register (PxDIN) is a read-only register that returns the current state of each port pin. The CPU can read this register at any time even when the pin is configured as an output. 6.1.4 Port Data Output Register The data output register (PxDOUT) holds the data to be driven onto each port pin configured to operate as a general-purpose output. In this configuration, writing to the register changes the output value. Reading the register returns the last value written to the register. A reset operation leaves the register contents unchanged. Upon power-up, the registers contain unknown values. 6.1.5 Port Weak Pull-Up Register The weak pull-up register (PxWKPU) determines whether each port pin uses a weak pull-up on the output buffer. A bit set to 1 causes the weak pull-up to be used, while a bit cleared to 0 causes the causes the weak pull-up not to be used. The pull-up device, if enabled by the register bit, operates in the general-purpose I/O mode whenever the port output buffer is in the TRI-STATE mode. In the alternate function mode, the pull-ups are always disabled. A reset operation clears the port weak pull-up registers to 0, which disables all pull-ups. www.national.com 14 7.0 CPU and Core Registers 7.2.3 Interrupt Base Register The INTBASE register holds the address of the Dispatch Table for interrupts and traps. The least significant bit of the register is always zero. Thus, the Dispatch Table starts at an even address in the range of 0000 to FFFE. The device uses the same CR16B CPU core as other CompactRISC family members. The core's Reduced Instruction Set Computer (RISC) architecture allows a processing rate of up to one instruction per clock cycle. The CPU core uses a set of internal registers: — — — — General-purpose registers (R0-R13, RA, and SP) Dedicated address registers (PC, ISP and INTBASE) , Processor Status Register (PSR) Configuration Register (CFG) 7.3 PROCESSOR STATUS REGISTER All of these registers are 16 bits wide except for the three address registers, which are 21 bits wide. Some register bits are designated as “reserved.” The CPU must write a zero to each of these bit locations when it writes to the register. Read operations from reserved bit locations return undefined values. The Processor Status Register (PSR) holds status information and selects the operating modes for the CPU core. The format of the register is shown below. 15 14 13 12 11 10 9 Reserved IPE C bit 8 0 7 N 6 Z 5 F 4 0 3 0 2 L 1 T 0 C 7.1 GENERAL-PURPOSE REGISTERS There are 16 general-purpose registers, designated R0 through R13, RA, and SP Registers R0 through R13 can be . used for any purpose such as holding variables, addresses, or index values. The RA register is usually used to store the return address upon entry into a subroutine. The SP register is usually used as the pointer to the program run-time stack. If a general-purpose register is used for a byte-wide operation, only the low-order byte is referenced or modified. The high-order byte is not used or affected by a byte-wide operation. T bit L bit F bit 7.2 DEDICATED ADDRESS REGISTERS There are three dedicated address registers: the Program Counter (PC), the Interrupt Stack Pointer (ISP), and the Interrupt Base Register (INTBASE). Each of these registers is 21 bits wide. 7.2.1 Program Counter Z bit The PC register contains the address of the least significant word currently being fetched. It is automatically incremented or changed by the appropriate amount each time an instruction is executed. The least significant bit of the PC is always zero, thus instructions must always be aligned to an even address in the range of 0000 to 1FFFE hex. Upon reset, the PC register is initialized to zero and program execution starts at that address (if in IRE-Mode). When a reset signal is received, bits 1 through 16 of the PC register (prior to initialization) are stored in register R0. This allows the software to determine the point in the program at which the reset occurred. 7.2.2 Interrupt Stack Pointer N bit E bit The ISP register points to the lowest address of the last item stored on the interrupt stack. This stack is used by the hardware when an interrupt or trap service procedure is invoked. P bit The Carry (C) bit indicates whether a carry or borrow occurred after addition or subtraction. It is set to 1 if a carry or borrow occurred, or cleared to 0 otherwise. The Trace (T) bit, when set, causes a Trace (TRC) trap to be executed after every instruction. This bit is automatically cleared to 0 when a trap or interrupt occurs. The Low (L) bit is set by comparison operations. In a comparison of unsigned integers, the bit is set to 1 if the second operand (Rdest) is less than the first operand (Rsrc). Otherwise, it is cleared to 0. The Flag (F) bit is a general condition flag that is set by various instructions. It may be used to signal exception conditions or to distinguish the results of an instruction. For example, integer arithmetic instructions use this bit to indicate an overflow condition after an addition or subtraction operation. The Zero (Z) bit is set by comparison operations. In a comparison of integers, the bit is set to 1 if the two operands are equal. Otherwise, it is cleared to 0. The Negative (N) bit is set by comparison operations. In a comparison of signed integers, the bit is set to 1 if the second operand (Rdest) is less than the first operand (Rsrc). Otherwise, it is cleared to 0. The Local Maskable Interrupt Enable (E) bit is used to enable or disable maskable interrupts. If this bit and the Global Maskable Interrupt Enable (I) bit are both set to 1, all maskable interrupts are accepted. Otherwise, only the nonmaskable interrupt is accepted. The E bit is set to 1 by the Enable Interrupts (EI) instruction and cleared to 0 by the Disable Interrupts (DI) instruction. The Trace Trap Pending (P) bit is used together with the Trace (T) bit to prevent a Trace (TRC) trap from occurring more than once for any instruction. The P bit may be cleared to 0 (no TRC trap pending) or set to 1 (TRC trap pending). 15 www.national.com I bit The Global Maskable Interrupt Enable (I) bit is used to enable or disable maskable interrupts. If this bit and the Local Maskable Interrupt Enable (E) bit are both set to 1, all maskable interrupts are accepted. Otherwise, only the nonmaskable interrupt is accepted. This bit is automatically cleared to 0 when an interrupt occurs and automatically set to 1 upon completion of an interrupt service routine. Absolute Mode The operand is located in memory. Its address is specified within the instruction. For example: LOADB 4000, R6 For additional information on the instruction set and instruction encoding, see the CompactRISC CR16B Programmer's Reference manual. 7.6 STACKS Upon reset, all non-reserved bits of the register are cleared to 0 except for the E bit (bit 9), which is set to 1. When a device reset occurs, the PSR contents prior to the reset are stored into register R1, allowing the initialization software to determine the state of the device prior to the reset operation. 7.4 CONFIGURATION REGISTER The Configuration (CFG) register is a 16-bit core register that determines the size of the INTBASE register. For the device, the CFG register should always be left in its default state (cleared to zero), resulting in a 16-bit INTBASE register. A stack is a one-dimensional data buffer in which values are entered and removed one at a time. The last valued entered is the first one removed. A register called the stack pointer contains the current address of the last item entered on the stack. In the device, when an item is entered or “pushed” onto the stack, the stack expands downward in memory (the stack pointer is decremented). When an item is removed or “popped” from the stack, the stack shrinks upward in memory (the stack pointer is incremented). The device uses two type of stacks: the program stack and the interrupt stack. The program stack is used by the software to save and restore register values upon entry into and exit from a subroutine. The software can also use the program stack to store local and temporary variables. The stack pointer for this stack is the SP register. The interrupt stack is used to save and restore the program state when an exception occurs (an interrupt or software trap). The on-chip hardware automatically pushes the program state information onto the stack before the exception service procedure is executed. Upon exit from the exception service procedure, the hardware pops this information from the stack and restores the program state. The stack pointer for this stack is the ISP register. 7.5 ADDRESSING MODES Each instruction operates on one or more operands. An operand can be a register or a memory location. Most instructions use one, two, or three device registers as operands. The instruction opcode specifies the registers to be operated on. Some instructions may use an immediate value (a value provided in the instruction itself) instead of a register. Memory locations are accessed only by the Load and Store commands. The memory location to use for a particular instruction can be specified as an absolute, relative, or far-relative address. The instruction set supports the following addressing modes: Register Mode The operand is a general-purpose register: R0 through R13, RA, or SP For exam. ple: ADDB R1, R2 Immediate A constant operand value is specified withMode in the instruction. In a branch instruction, the immediate operand is a displacement from the program counter (PC). In the assembly language syntax, a dollar sign indicates an immediate value. For example: MULW $4, R4 Relative Mode The operand is located in memory. Its address is obtained by adding the contents of a general purpose register to the constant value encoded into the displacement field of the instruction. For example: LOADW 12(R5), R6 Far-Relative The operand is located in memory. Its adMode dress is obtained by concatenating a pair of adjacent general-purpose registers to form a 21-bit value, and adding this value to the constant value encoded into the displacement field of the instruction. 7.7 INSTRUCTION SET Table 7 is a summary list of all instructions in the device instruction set. For each instruction, the table shows the mnemonic and a brief description of the operation performed. In the Mnemonic column, the lower-case letter “i” is used to indicate the type of integer that the instruction operates on, either “B” for byte or “W” for word. For example, the notation ADDi for the “add” instruction means that there are two forms of this instruction, ADDB and ADDW, which operate on bytes and words, respectively. Similarly, the lower-case string “cond” is used to indicate the type of condition tested by the instruction. For example, the notation Jcond represents a class of conditional jump instructions: JEQ for Jump on Equal, JNE for Jump on Not Equal, and so on. www.national.com 16 For detailed information on all instructions, see the CompactRISC CR16B Programmer's Reference manual. Table 7 Mnemonic ADDi ADDUi ADDCi ANDi ASHUi Bcond Bcond0i Bcond1i BAL BR CBITi CMPi DI EI EIWAIT EXCP Jcond JAL JUMP LOADi LOADM LPR LSHi MOVi MOVXB MOVZB MULi MULSi MULUW NOP ORi POP POPRET PUSH RETX Scond MULi SBITi STORi STORM SUBi Add Integer Add Unsigned Integer Add Integer with Carry Bitwise Logical AND Arithmetic Shift Unsigned Conditional Branch Compare Register to 0 and Branch Compare Register to 1and Branch Branch and Link Unconditional Branch Clear Bit in Integer Compare Integer Disable Maskable Interrupts Enable Maskable Interrupts Enable Interrupts and Wait for Interrupt Exception Conditional Jump Jump and Link Jump Load Integer Load Multiple Registers Load Processor Register Logical Shift Integer Move Integer Move with Sign-Extension Move with Zero-Extension Multiply Integer Multiply Signed Multiply Unsigned No Operation Bitwise Logical OR Pop Registers from Stack Pop and jump RA Push Registers on Stack Return from Exception Save Condition as Boolean Multiply Integer Set Bit in Integer Store Integer Store Registers to Memory Subtract Integer Device Instruction Set Summary Description Table 7 Mnemonic SUBCi TBIT WAIT XORi Device Instruction Set Summary Description Subtract Integer with Carry Test Bit Wait for Interrupt Bitwise Logical Exclusive OR 17 www.national.com 8.0 Bus Interface Unit 8.2 BIU CONTROL REGISTERS The BIU has a set of control registers that determine how many wait cycles and hold cycles are to be used for accessing memory. Upon start-up of the device, these registers should be programmed with appropriate values so that the minimum allowable number of cycles is used. This number varies with the clock frequency used. There are four applicable BIU registers: the BIU Configuration (BCFG) register, the I/O Configuration (IOCFG) register, the Static Zone 0 Configuration (SZCFG0) register and the Static Zone 1Configuration (SZCFG1) register. These registers control the bus cycle configuration used for accessing the various on-chip memory types. Note: A system configuration register called the Module Configuration (MCFG) register controls the number of wait cycles used for accessing the EEPROM data memory. This register is described in Section 5.1. 8.2.1 BIU Configuration (BCFG) Register The Bus Interface Unit (BIU) controls the interface between the internal core bus and those on-chip modules which are mapped into BIU zones. These on-chip modules are the flash EEPROM program memory, the ISP-memory and the I/Ozone. It determines the configured parameters for bus access (such as the number of wait states for memory access) and issues the appropriate bus signals for the requested access. Note: The device is manufactured in a 224-pin version which is used in emulation equipment. In the 224-pin device, the BIU controls access to both on-chip and off-chip memory and peripherals. Operation of the 224-pin device and the use of chip-external memory is beyond the scope of this data sheet. 8.1 — — — — BUS CYCLES Normal read Fast read Early write Late write There are four types of data transfer bus cycles: The type of data cycle used in a particular transaction depends on the type of CPU operation (a write or a read), the type of memory or I/O being accessed, and the access type programmed into the BIU control registers (early/late write or normal/fast read). For read operations, a basic normal read takes two clock cycles, whereas a fast read bus cycle takes one clock cycle. Upon reset of the device, normal read bus cycles are enabled by default. For write operations, a basic late write bus cycle takes two clock cycles, whereas a basic early write bus cycle takes three clock cycles. Upon reset of the device, early write bus cycles are enabled by default. However, late write bus cycles are needed for ordinary write operations, so this configuration should be changed by the application software (see Section 8.2.1). In certain cases, one or more additional clock cycles are added to a bus access cycle. There are two types of additional clock cycles for ordinary memory accesses, called internal wait cycles (TIW) and hold (Thold) cycles. A wait cycle is inserted in a bus cycle just after the memory address has been placed on the address bus. This gives the accessed memory more time to respond to the transaction request. A hold cycle is inserted at the end of a bus cycle. This holds the data on the data bus for an extended number of clock cycles. The BIU Configuration (BCFG) Register is a byte-wide, read/ write register that selects either early write or late write bus cycles. The register address is F900 hex. Upon reset, the register is initialized to 07 hex. The register format is shown below. 7 654 Reserved 3 2 Note 1 1 Note 1 0 EWR EWR Early Write. This bit is cleared to 0 for late write operation (two clock cycles to write) or set to 1 for early write operation. Note 1: These bits (bit 1 or bit 2) control the configuration of the 224-pin device used in emulation equipment. The CPU should set this bit to 1 when it writes to the register. Upon reset, the BCFG register is initialized to 07 hex, which selects early write operation. However, late write operation is required for normal device operation, so the software should change the register value to 06 hex. 8.2.2 I/O Zone Configuration (IOCFG) Register The I/O Zone Configuration (IOCFG) register is a word-wide, read/write register that sets the timing and bus characteristics of I/O Zone memory accesses. In the device implementation, the registers associated to Port B and Port C reside in the I/O memory array. (These ports are used as a 16-bit data port, if the device operates in development mode.) www.national.com 18 The IOCFG register address is F902 hex. Upon reset, the register is initialized to 069F hex. The register format is shown below. 15 14 13 12 11 Reserved 10 9 IPST 2 8 Reserved 1 WAIT 0 HOLD 7 BW WAIT 6 5 Reserved 4 3 HOLD BW HOLD BW IPST Memory Wait cycles This field specifies the number of TIW (internal wait state) clock cycles added for each memory access, ranging from 000 binary for no additional TIW wait cycles to 111 binary for seven additional TIW wait cycles. Memory Hold cycles This field specifies the number of Thold clock cycles used for each memory access, ranging from 00 binary for no Thold cycles to 11 binary for three Thold clock cycles. Bus Width. This bit defines the bus width of the zone. If cleared to 0, a bus width of 8-bit is used. if set to 1, a bus width of 16-bit is used. For the device, a bus width of 16-bit needs to be set. Post Idle. An idle cycle follows the current bus cycle, when the next bus cycle accesses a different zone. If cleared to 0, no idle cycle is inserted. If set to 1, one idle cycle is inserted. The IPST bit can be cleared to 0, as no idle cycles are required for on-chip accesses. FRE IPST IPRE Memory Hold cycles This field specifies the number of Thold clock cycles used for each memory access, ranging from 00 binary for no Thold cycles to 11 binary for three Thold clock cycles. These bits are ignored if the SZCFG0.FRE bit is set to 1. Bus Width. This bit defines the bus width of the zone. If cleared to 0, a bus width of 8-bit is used. if set to 1, a bus width of 16-bit is used. For the devicedevice a bus width of 16-bit needs to be set. Fast Read Enable This bit enables (1) or disables (0) fast read bus cycles. A fast read operation takes one clock cycle. A normal read operation takes at least two clock cycles. Post Idle. An idle cycle follows the current bus cycle, when the next bus cycle accesses a different zone. If cleared to 0, no idle cycle is inserted. If set to 1, one idle cycle is inserted. The IPST bit can be cleared to 0, as no idle cycles are required for on-chip accesses. Preliminary Idle. An idle cycle is inserted prior to the current bus cycle, when the new bus cycle accesses a different zone. If cleared to 0, no idle cycle is inserted. If set to 1, one idle cycle is inserted. The IPRE bit can be cleared to 0, as no idle cycles are required for on-chip accesses. Note: Reserved bits must be cleared to 0 when the CPU writes to the register. 8.2.3 Static Zone 0 Configuration (SZCFG0) Register Note: Reserved bits must be cleared to 0 when the CPU writes to the register. 8.2.4 Static Zone 1 Configuration (SZCFG1) Register The Static Zone 0 Configuration (SZCFG0) register is a word-wide, read/write register that sets the timing and bus characteristics of Zone 0 memory accesses. In the device implementation of the CompactRISC architecture, Zone 0 is occupied by the flash EEPROM program memory. The SCCFG0 register address is F904 hex. Upon reset, the register is initialized to 069F hex. The register format is shown below. 15 14 13 12 Reserved 11 FRE 10 IPRE 4 3 HOLD 9 IPST 2 8 Reserved 1 WAIT 0 The Static Zone 1 Configuration (SZCFG1) register is a word-wide, read/write register that sets the timing and bus characteristics of Zone 1 memory accesses. In the device implementation of the CompactRISC architecture, Zone 1 is occupied by the boot ROM memory (ISP-Memory). The SCCFG1 register address is F906 hex. Upon reset, the register is initialized to 069F hex. The register format is shown below. 15 14 13 12 Reserved 11 FRE 10 IPRE 4 3 HOLD 9 IPST 2 8 Reserved 1 WAIT 0 7 BW WAIT 6 5 Reserved 7 BW WAIT 6 5 Reserved Memory Wait cycles This field specifies the number of TIW (internal wait state) clock cycles added for each memory access, ranging from 000 binary for no additional TIW wait cycles to 111 binary for seven additional TIW wait cycles. These bits are ignored if the SZCFG0.FRE bit is set to 1. Memory Wait cycles This field specifies the number of TIW (internal wait state) clock cycles added for each memory access, ranging from 000 binary for no additional TIW wait cycles to 111 binary for seven additional TIW wait cycles. These bits are ignored if the SZCFG0.FRE bit is set to 1. 19 www.national.com HOLD BW FRE IPST IPRE Memory Hold cycles This field specifies the number of Thold clock cycles used for each memory access, ranging from 00 binary for no Thold cycles to 11 binary for three Thold clock cycles. These bits are ignored if the SZCFG0.FRE bit is set to 1. Bus Width. This bit defines the bus width of the zone. If cleared to 0, a bus width of 8-bit is used. if set to 1, a bus width of 16-bit is used. For the device a bus width of 16-bit needs to be set. Fast Read Enable This bit enables (1) or disables (0) fast read bus cycles. A fast read operation takes one clock cycle. A normal read operation takes at least two clock cycles. Post Idle. An idle cycle follows the current bus cycle, when the next bus cycle accesses a different zone. If cleared to 0, no idle cycle is inserted. If set to 1, one idle cycle is inserted. The IPST bit can be cleared to 0, as no idle cycles are required for on-chip accesses. Preliminary Idle. An idle cycle is inserted prior to the current bus cycle, when the new bus cycle accesses a different zone. If cleared to 0, no idle cycle is inserted. If set to 1, one idle cycle is inserted. The IPRE bit can be cleared to 0, as no idle cycles are required for on-chip accesses. For a write operation normal read mode (SZCFG0.FRE=0), the number of wait cycles is equal to the value written to the SZCFG0. WAIT field plus one (in the late write mode) or two (in the early write mode). The number of inserted hold cycles is equal to the value written to the SCCFG0.HOLD field, which can range from zero to three. Writing to the flash EEPROM program memory is a Flash programming operation that requires some additional steps, as explained in Section 9.3. 8.3.2 RAM Memory Read and write accesses to on-chip RAM is performed within a single cycle, regardless of the BIU settings. 8.3.3 EEPROM Data Memory There is either no wait state or one wait state used when the CPU accesses the EEPROM data memory (address F000F27F hex). The number of required wait states (zero or one) depends on the CPU clock frequency and operating mode, and is controlled by programming of the DMCSR.ZEROWS bit in the MCFG register, as explained in Section 9.3. No hold cycles are used. 8.3.4 Accesses to Peripheral When the CPU accesses on-chip peripherals in the range of F800-FAFF hex and FC00-FFFF hex, one wait cycle and one preliminary idle cycle is used. No hold cycles are used. The IOCFG register determines the access timing for the address range FB00-FB16 hex (Ports B and Port C). 8.3.5 Access Timing Summary Table Table 8 is a summary showing the number of access cycles used for various address ranges. 8.3.6 Recommended Register Settings Note: Reserved bits must be cleared to 0 when the CPU writes to the register. 8.3 WAIT AND HOLD STATES USED The number of wait cycles and hold cycles inserted into a bus cycle depends on whether it is a read or write operation, the type of memory or I/O being accessed, and the control register settings. 8.3.1 Flash EEPROM Program Memory Table 9 shows the recommended register settings for various clock rates. Different clock rates require different register settings because the flash EEPROM program memories have specific setup and hold requirements that can be met only by using enough wait cycles and hold cycles. When the CPU accesses the flash EEPROM program memory (address ranges 0000-BFFF and 10000-1BFFF), the number of added wait and hold cycles depends on the type of access and the BIU register settings. In fast read mode (SZCFG0.FRE=1), a read operation is a single cycle access. This limits the maximum CPU operating frequency to either 10 MHz or 24 MHz (see Section 9.1.1). For a read operation in normal read mode (SZCFG0.FRE=0), the number of inserted wait cycles is one plus the value written to the SZCFG0.WAIT field. The number in this field can range from zero to seven, so the total number of wait cycles can range from one to eight. The number of inserted hold cycles is equal to the value written to the SCCFG0.HOLD field, which can range from zero to three. For a write operation in fast read mode (SZCFG0.FRE=1), the number of inserted wait cycles is one. No hold cycles are used. www.national.com 20 Table 8 Address Range (hex) 0000-BFFF Memory or I/O Type Flash EEPROM Program Memory Access Timing Table Access Cycles read SZCFG0.FRE=1: 1 cycle write SZCFG0.FRE=1: 1 cycle + BCFG.EWR (+ programming time) SZCFG0.FRE=0: 2 cycles + BCFG.EWR + SZCFG0.WAIT + SZCFG0.HOLD (+ programming time) 1 cycle MCFG.ZEROWS=1: 1 cycle (+ programming time) MCFG.ZEROWS=0: 2 cycles (+ programming time) 2 cycles SZCFG0.FRE=0: 2 cycles + SZCFG0.WAIT + SZCFG0.HOLD C000-CFFF F000-F27F Static RAM Memory EEPROM Data Memory 1 cycle MCFG.ZEROWS=1: 1 cycle MCFG.ZEROWS=0: 2 cycles F900-FFFF F800-F9FF FC00-FFFF FB00-FBFF On-Chip Peripherals 2 cycles Ports B and C 3 cycle + IOCFG.WAIT + IOCFG.HOLD SZCFG0.FRE=1: 1 cycle 10000-1BFFF Flash EEPROM Program Memory SZCFG0.FRE=0: 2 cycles + SZCFG0.WAIT + SZCFG0.HOLD 3 cycle + BCFG.EW + IOCFG.WAIT + IOCFG.HOLD SZCFG0.FRE=1: 1 cycle + BCFG.EWR (+ programming time) SZCFG0.FRE=0: 2 cycles + BCFG.EWR + SZCFG0.WAIT + SZCFG0.HOLD (+ programming time) Table 9 Clock Rate < 16 MHz, 0 wait state for both CR16MCT and CR16HCT 16 to 24MHz, 0 wait state for CR16HCT 16 to 24MHz, 1wait state for CR16MCT Recommended Register Settings SZCFG1 0880 hex IOCFG 0080 hex SZCFG0 0880 hex 0880 hex 0080 hex 0880 hex 0080 hex 0080 hex 0080 hex 21 www.national.com 9.0 Memory 9.1.1 Reading Program memory read accesses can operate without wait cycles with a CPU clock rate of up to 24MHz in the normal mode. At higher clock rates, memory read accesses can operate with one wait state. The programmed number of wait cycles used (either zero or one) is controlled by the BIU Configuration (BCFG) register and the Static Zone 0 Configuration (SZCFG0) register. These registers are described in Section 8.0. 9.1.2 Conventional Programming Modes The CompactRISC architecture supports a uniform linear address space of 2 megabytes, addressed by 21 bits. The device implementation of this architecture uses only the lowest 128K bytes of address space. Each memory location contains a byte consisting of eight bits. Various types of on-chip memory occupy specific intervals within the address space: 96K bytes of flash EEPROM program memory, 4K bytes of static RAM, 2K bytes of low endurance EEPROM data memory, 128 bytes of high endurance EEPROM data memory, and 1.5K bytes of ISP memory. All of these memories are 16 bits wide, and their contents can be accessed either as bytes (eight bits wide) or words (16 bits wide except for the program memory which only supports word access). The CPU core uses the Load and Store instructions to access memory. These instructions can operate on bytes or words. For a byte access, the CPU operates on a single byte occupying a specified memory address. For a word access, the CPU operates on two consecutive bytes. In that case, the specified address refers to the least significant byte of the data value; the most significant byte is located at the next higher address. Thus, the ordering of bytes in memory is from least to most significant byte, known as “little-endian” ordering. For more efficient data access operations, 16-bit variables should be stored starting at word boundaries (at even address). The flash EEPROM program memory can be programmed either with the device plugged into a flash EEPROM programmer unit (External Programming) or with the device already installed in the application system (In-SystemProgramming). If the device is programmed using a flash EEPROM programmer, the device is set into an external programming mode. In this mode the device operates as if it were a pure flash memory device. The flash memory is programmed without involving any CPU activity. If the device is to be programmed within the user application, it can either be done by an user written boot loader or by utilizing a pre-programmed in-system-programming code (ISPCode) residing in the boot ROM array of the device. The device executes the pre-programmed in-system-programming code if it operates in the In-System-Programming Mode (ISP-Mode). To enter the ISP-Mode the device must be reset (or powered-up) with the ENV0-pin set to low level and the ENV1-pin set to high level (or left open). Also if the flash program memory is not programmed yet (FLCTRL2.EMPTY bit is still set) the device automatically enters the ISP-Mode after reset, even though both pins ENV0 and ENV1are at high level (or left open). If the device enters the ISP-Mode it starts execution at address E000 hex. In ISP-Mode the program code can be downloaded into the device using one of the on-chip USARTs and written into the flash program memory. For more detailed information on the In-System-Programming features of the pre-programmed ISP-Code please refer to the ISP-Monitor manual. 9.1.3 User-Coded Programming Routines 9.1 FLASH EEPROM PROGRAM MEMORY The flash EEPROM program memory is used to store the application program. The 96K bytes of this memory reside in the address range of 0000-BFFF hex and 10000-1BFFF in Zone 0 of the CR16B address space. A normal CPU write operation to this memory has no effect. The flash EEPROM Program Memory module has the following features: — 96K bytes arranged in 2 blocks each organized as 24K by 16 bits — Page size of 64 words — 30 µs programming pulse per word — Page mode erase with a 1 ms pulse, mass erase with 4ms pulse — All erased flash EEPROM program memory bits read 1 — Fast single cycle read access — Flexible software controlled In-System-Programming (ISP) capability — Pipelined programming cycles through double-buffered data register, with write access disabled when the register is full — Programming high voltage and timing generated onchip — Memory disabled when address is out of range — Requires valid key for program and erase to proceed — Provide busy status during programming and erase — Read accesses disabled during programming and erase — Security features to limit read/write access Instead of using a flash EEPROM programmer unit or the conventional in-system programming mode, you can write your own processor code to program and erase the flash EEPROM program memory. User-written code is more flexible than using the other programming methods. Like the conventional in-system programming mode, the device is programmed while it is installed in the system. It is not necessary to reset the device or use the ENV0/ENV1 pins to configure the device. User-written flash programming code must reside outside of the flash program memory. This is because the entire program memory becomes unavailable while programming or erasing any part of this memory. www.national.com 22 9.1.4 Flash EEPROM Programming and Verify The flash EEPROM program memory programming and erase can be performed using different methods. It can be done through user code that is stored in system RAM, or through In-System-Programming mode, but should not be programmed through the flash EEPROM program memory itself as no instruction or data can be fetched from it while it is being programmed. All program and erase operations must be preceded immediately by writing the proper key to the program memory key register PGMKEY. The flash EEPROM program memory is divided into 768 pages, each page containing 64 words (each 16 bits wide). Each page is further divided into two adjacent rows. A page erase will erase one page. Programming is done by writing to all the words within a row, one word following another sequentially within one single high voltage pulse. This is supported through a double-buffered write-data buffer scheme. Byte programming is not supported. Programming should be done on erased rows. A mass erase requires the following code sequence (assuming that this sequence will not be interrupted to do another flash erase or programming): 1. Check for MSTAT.PGMBUSY not set. 2. Set up flash timing reload registers for mass erase operation. 3. Set FLCSR.MERASE = 1. 4. If interrupt was enabled, disable interrupt. 5. Write proper key value to PGMKEY. 6. Write to any valid location within the flash EEPROM program memory. 7. If interrupt was disabled in step 4, re-enable interrupt. 8. Wait for MSTAT.PGMBUSY to clear. 9. Set FLCSR.MERASE = 0. 10. Restore flash timing reload registers for normal operation. A page erase requires the following code sequence (assuming that this sequence will not be interrupted to do another flash erase or programming): 1. 2. 3. 4. 5. 6. 7. Check for MSTAT.PGMBUSY not set. Set FLCSR.ERASE = 1. If interrupt was enabled, disable interrupt. Write proper key value to PGMKEY. Write to any valid location within the page to be erased. If interrupt was disabled in step 3, re-enable interrupt. Set FLCSR.ERASE = 0. If the programming sequence exceeds a row, the flash programming interface will automatically initiate a programming pulse for the next row. The FLCSR.PMLFULL bit is also cleared when programming of the last word of the current row is completed, e.g. programming of the entire row is completed and MSTAT.PGMBUSY is cleared. This means, the separation of the program memory into rows is transparent to the user, as the transition is handled by the flash program memory interface. Figure 3 shows a flowchart for a programming sequence. start MSTAT.PGMBUSY =1? No Yes disable interrupt if necessary write PGMKEY write memory re-enable interrupt if necessary last word? No Yes done When programming, the data to be written into the flash EEPROM program memory is first written into a double-buffered write-data buffer. When a piece of data is written to the page while the flash EEPROM program memory is idle, the write cycle will start. Due to the double-buffered nature of the writedata buffer, a second word can be written to the flash EEPROM program memory. This will then set FLCSR.PMLFULL flag indicating the buffer is now full. When the first write is done, the memory address would be incremented, and the second word would be written to that address while keeping the high voltage pulse active; the FLCSR.PMLFULL flag is cleared. Another word can then be written to the buffer, and this programming will repeat until there are no more words to be programmed. This allows pipelined writes to different words on the same row within the same high voltage pulse. Yes FLCSR.PMLFULL =0? No Figure 2. Programming Sequence for the Program Memory 9.1.5 Erase and Programming Timing The internal hardware of the device handles the timing of erase and programming operations. To drive the timing control circuits, the device divides the system clock by a pro- 23 www.national.com grammable prescaler factor. You should select a prescaler value to produce a program/erase clock of 200 kHz (or as close as possible to 200 kHz without exceeding 200 kHz). For the timing control circuit to operate correctly, you must program the prescaler value in advance and leave it unchanged while a program or erase operation is in progress. A similar (but separate) prescaler factor is applied to the EEPROM data memory. See Section 9.1.7 and Section 9.3.4 for details. 9.1.6 Flash EEPROM Program Memory Control and Status Register (FLCSR) You should choose a value of FTDIV to produce a clock of the highest possible frequency that is equal to or just less than 200 kHz. For example, if the system clock frequency is 12.5 MHz, use the value 3E hex (62 decimal) for FTDIV, because 12.5 MHz / (62+1) = 198.4 kHz. Do not modify this register while a flash EEPROM program or erase operation is in progress. Upon reset, this register is programmed by default with the value 63 hex (99 decimal), which is an appropriate setting for a 20 MHz system clock. 9.1.8 Program Memory Start Time Reload (FLSTART) The Flash EEPROM Program Memory Control and Status (FLCSR) register is a byte-wide, read/write register that contains several status and control bits related to the program memory. All reserved bits must be written with 0 for the memory to operate properly when writing to this register. Upon reset, this register is cleared to zero when the flash memory on the chip is in the idle state. The register format is shown below. 7 MERASE 6 Reserved 4 3 PMLFULL 2 PMBUSY 1 PMER 0 Reserved The FLSTART register is a byte-wide read/write register that controls the program and erase start delay time. This value is loaded into the lower 8 bits of the flash timing counter, and at the same time, 002 is loaded into the upper 2 bits. Before you program or erase the program memory for the first time, program the FLSTART register with the proper prescaler value, FTSTART. The flash timing counter generates a delay of (FTSTART + 1) prescaler output clocks. The default value provides a delay time of 10µs when the prescaler output clock is 200kHz. Do not modify this register while a program or erase operation is in progress. Upon reset, this register resets to 0116 when the flash memory on the chip is in an idle state. 9.1.9 Program Memory Transition Time Reload Register (FLTRAN) PMER PMBUSY PMLFULL MERASE Flash EEPROM Program Memory page erase. When set (1) with MERASE bit cleared, a valid write to the flash EEPROM program memory erases the entire flash EEPROM program memory page pointed to by the write address rather than performing a write to the addressed memory location. Program Memory Busy. This bit is automatically set to 1 when the flash EEPROM program memory is busy being programmed, and cleared to 0 at all other times. (The MSTAT.PGMBUSY is also set to 1 whenever the PMBUSY bit is set to 1.) Program Memory Write-Latch Buffer Full. When set (1), the double-buffered data register for program memory write operations is full. When cleared (0), the double-buffered data register is not full. Mass Erase Flash EEPROM Program Memory Array. When set (1) in ISP or test mode, a valid write to the flash EEPROM program memory performs an erase to the whole flash EEPROM program memory rather than perform a write to the addressed memory location. However, it is necessary to enter new values into the FLERASE and FLEND registers to adjust the mass erase timing before starting the mass erase. The FLTRAN register is a byte-wide read/write register that controls some program/erase transition times. This value is loaded into the lower 8 bits of the flash timing counter, and at the same time, 002 is loaded into the upper 2 bits. Before you program or erase the program memory for the first time, you should program the FLTRAM register with the proper prescaler value, FTTRAN. The flash timing counter generates a delay of (FTTRAN + 1) prescaler output clocks. The default value provides a delay time of 5µs when the prescaler output clock is 200kHz. Do not modify this register while a program or erase operation is in progress. Upon reset, this register resets to 0016 when the flash memory on the chip is in an idle state. 9.1.10 Program Memory Programming Time Reload Register (FLPROG) 9.1.7 Program Memory Timing Prescaler Register (FLPSLR) The FLPSLR register is a byte-wide, read/write register that selects the prescaler divider ratio for the flash EEPROM program memory programming clock. Before you program or erase the program memory for the first time, you should program the FLPSLR register with the proper prescaler value, an 8-bit value called FTDIV. The device divides the system clock by (FTDIV+1) to produce the program memory programming clock. www.national.com The FLPROG register is a byte-wide read/write register that controls the programming pulse width. This value is loaded into the lower 8 bits of the flash timing counter, and at the same time, 002 is loaded into the upper 2 bits. Before you program or erase the program memory for the first time, program the FLPROG register with the proper prescaler value, FTPROG. The flash timing counter generates a programming pulse width of (FTPROG + 1) prescaler output clocks. The default value provides a delay time of 30µs when the prescaler output clock is 200kHz. Do not modify this register while program/erase operation is in progress. Upon reset, this register resets to 0516 when the flash memory on the chip is in idle state. 24 9.1.11 Program Memory Erase Time Reload Register (FLERASE) 9.1.16 Program Memory Write Key Register (PGMKEY) The FLERASE register is a byte-wide read/write register that controls the erase pulse width. This value is loaded into the upper 8 bits of the flash timing counter, and at the same time, 112 is loaded into the lower 2 bits. Before you program or erase the program memory for the first time, program the FLERASE register with the proper prescaler value, FTER. The flash timing counter generates a erase pulse width of 4×(FTER + 1) prescaler output clocks. The default value provides a delay time of 1ms when the prescaler output clock is 200kHz. Do not modify this register while a program or erase operation is in progress. Upon reset, this register resets to 3116 when the flash memory on the chip is in idle state. For mass erase, this value should be changed to C716 to generate a pulse width that is four times as long as the page erase. 9.1.12 Program Memory End Time Reload Register (FLEND) The PGMKEY register is a byte-wide, write-only register that must be written with a key value (A316) immediately prior to each write to the flash EEPROM program memory. Otherwise, the write operation to the program memory will fail. This feature is intended to prevent unintentional programming of the program memory. Reading this register always returns FF hex. Upon reset, the write enable status that is generated as a result of writing to this key register is cleared. 9.2 RAM MEMORY The static RAM memory is used for temporary storage of data and for the program and interrupt stacks. The 4K bytes of this memory reside in the address range of C000-CFFF hex. Each memory access requires one clock cycle, for a byte or word access. No wait cycles or hold cycles are required. For non-aligned word access, each memory access requires multiple clock cycles. 9.3 FLASH EEPROM DATA MEMORY The FLEND register is a byte-wide read/write register that controls the delay time after a program/erase operation. This value is loaded into the lower 8 bits of the flash timing counter, and at the same time, 002 is loaded into the upper 2 bits. Before you program or erase the program memory for the first time, program the FLEND register with the proper prescaler value, FTEND. The flash timing counter generates a delay of (FTEND + 1) prescaler output clocks. The default value provides a delay time of 5µs when the prescaler output clock is 200kHz. Do not modify this register while program/ erase operation is in progress. Upon reset, this register resets to 0016 when the flash memory on the chip is in idle state. For mass erase, this value should be changed to 1316 to provide for a delay time twenty times that of the standard delay. 9.1.13 Program Memory Prescaler Count Register (FLPCNT) The flash EEPROM data memory is used for non-volatile storage of data. The 2K bytes of low endurance memory reside in the address range of E800-EFFF hex and the 128 bytes of high endurance memory reside in the address range of F000-F07F hex. The CPU reads or writes this memory by using ordinary byte-wide or word-wide memory access commands. This memory shares the same array as the ISP flash program memory. This memory also support flash memory test mode and there is no read protection or permanent write protection for this memory. 9.3.1 Reading The flash EEPROM data memory read accesses can operate without wait cycles with a CPU clock rate of up to 20MHz in the normal mode. At higher clock rates, read accesses can operate with one wait state. The programmed number of wait cycles used (either zero or one) is controlled by a bit in the Data Memory Control Status register (DMCSR.ZEROWS). This register is described in Section 9.3.3. 9.3.2 Programming The FLPCNT register is a byte-wide read-only register that returns the value of the program memory prescaler counter. FPCNT contains the flash timing prescaler present count value. 9.1.14 Program Memory Timer Count Register 1 (FLCNT1) The FLCNT1 register is a byte-wide read-only register that returns the lower 8 bits of the program memory timing counter value. FLCNTL is the lower 8 bits of the flash timer present count value. 9.1.15 Program Memory Timer Count Register 2 (FLCNT2) Before you begin programming the flash EEPROM data memory, you should set the value in the EEPROM Data Memory Prescaler register. This register sets the prescaler used to generate the data memory programming clock from the system clock, as described in Section 9.3.4. A code fetch from ISP flash EEPROM program memory is not possible while flash EEPROM data memory is being programmed because they share the same memory array. After the CPU performs a write to the flash EEPROM data memory, the on-chip hardware completes the EEPROM programming in the background. When programming begins, the on-chip hardware sets the DMCSR.DMBUSY bit to 1, and also sets the MSTAT.PGMBUSY bit to 1. When programming is completed, it resets these status bits back to 0. Once the software writes to the flash EEPROM data memory, it should not attempt to access the EEPROM data memory The FLCNT2 register is a byte-wide read-only register that returns the upper 2 bits of the program memory timing counter value and also the state of the key flash memory interface timing signals. The interface timing signals are only used in special test modes. Their function is beyond the scope of this document. 25 www.national.com again until programming is completed and the status bit is reset to 0. The device hardware internally generates the voltages and timing signals necessary for programming. No additional power supply is required, nor any software required except to check the status bit for completion of programming. The minimum time required to erase and reprogram a byte or word is 1.1 ms. The programmed values can be verified by using normal memory read operations. The prescaler output drives a 10-bit counter to generate timing pulses and there are five reload registers to produce various pulse widths. If a reset occurs during a programming or erase operation, the operation is terminated. The reset is extended until the flash memory returns to the idle state. Therefore, the timing logic and program or erase state machine is not cleared on reset; they are cleared on power-up with the clear signal active until the bus signals are in a known state. The flash EEPROM data memory does not have permanent read-protection or write-protection features like those available for the EEPROM program memory. However, the Data Memory Write Key Register provides a way to “lock” the data written to the data memory. 9.3.3 Data Memory Control and Status Register (DMCSR) FTDIV. The device divides the system clock by (FTDIV+1) to produce the data memory programming clock. You should choose a value of FTDIV to produce a clock of the highest possible frequency that is equal to or just less than 200 kHz. Upon reset, this register is programmed by default with the value 63 hex (99 decimal), which is an appropriate setting for a 20 MHz system clock. 9.3.5 Data Memory Start Time Reload Register (DMSTART) The DMSTART register is a byte-wide read/write register that controls the program/erase start delay time. This value is loaded into the lower 8 bits of the flash timing counter, and at the same time, 002 is loaded into the upper 2 bits. Before you write to the data memory for the first time, you should program the DMSTART register with the proper prescaler value, an 8-bit value called FTSTART. The flash timing counter generates a delay of (FTSTART + 1) prescaler output clocks. The default value provides a delay time of 10µs when the prescaler output clock is 200kHz. Do not modify this register while program/erase operation is in progress. Upon reset, this register resets to 0116 when the flash memory on the chip is in idle state. 9.3.6 Data Memory Transition Time Reload Register (DMTRAN) The DMCSR register is a byte-wide, read/write register used with the flash EEPROM data memory or ISP flash EEPROM program memory. When writing to this register, all reserved bits must be written with 0 for the memory to operate properly. There are two status/control bits, as shown in the register format below. 7 6 5 4 3 ERASE 2 DMBUSY 1 ZEROWS 0 Reserved Reserved ZEROWS DMBUSY ERASE Zero Wait-State Access. When cleared (0), the flash EEPROM data memory will be read in two cycles. When set (1), the flash EEPROM data memory will be read in one cycle. Data Memory Busy. This bit is automatically set to 1 when the flash EEPROM data memory or the ISP flash EEPROM program memory is busy being programmed, and cleared to 0 at all other times. (The MSTAT.PGMBUSY is also set to 1 whenever the DMBUSY bit is set to 1.) Erase ISP Flash Program Memory Page. When set (1) a valid write to the ISP flash EEPROM program memory will erase the entire ISP flash EEPROM program memory page pointed to by the write address rather than performing a write to the addressed memory location. This bit should be cleared to 0 and remain cleared after the write operation. The DMTRAN register is a byte-wide read/write register that controls some program/erase transition times. This value is loaded into the lower 8 bits of the flash timing counter, and at the same time, 002 is loaded into the upper 2 bits. Before you write to the data memory for the first time, you should program the DMTRAN register with the proper prescaler value, an 8-bit value called FTTRAN. The flash timing counter generates a delay of (FTTRAN + 1) prescaler output clocks. The default value provides a delay time of 5µs when the prescaler output clock is 200kHz. Do not modify this register while program/erase operation is in progress. Upon reset, this register resets to 0016 when the flash memory on the chip is in idle state. 9.3.7 Data Memory Programming Time Reload Register (DMPROG) The DMPROG register is a byte-wide read/write register that controls the programming pulse width. This value is loaded into the lower 8 bits of the flash timing counter, and at the same time, 002 is loaded into the upper 2 bits. Before you write to the data memory for the first time, you should program the DMPROG register with the proper prescaler value, an 8-bit value called FTPROG. The flash timing counter generates a programming pulse width of (FTPROG + 1) prescaler output clocks. The default value provides a delay time of 30µs when the prescaler output clock is 200kHz. Do not modify this register while program/erase operation is in progress. Upon reset, this register resets to 0516 when the flash memory on the chip is in idle state. 9.3.8 Data Memory Erase Time Reload Register (DMERASE) Upon reset, the DMCSR register is cleared to zero when the flash memory on the chip is in the idle state. 9.3.4 Data Memory Prescaler Register (DMPSLR) The DMPSLR register is a byte-wide, read/write register that selects the prescaler divider ratio for the EEPROM data memory programming clock. Before you write to the data memory for the first time, you should program the DMPSLR register with the proper prescaler value, an 8-bit value called www.national.com The DMERASE register is a byte-wide read/write register that controls the erase pulse width. This value is loaded into the upper 8 bits of the flash timing counter, and at the same 26 time, 112 is loaded into the lower 2 bits. Before you write to the data memory for the first time, you should program the DMERASE register with the proper prescaler value, an 8-bit value called FTER. The flash timing counter generates a erase pulse width of 4×(FTER + 1) prescaler output clocks. The default value provides a delay time of 1ms when the prescaler output clock is 200kHz. Do not modify this register while program/erase operation is in progress. Upon reset, this register resets to 3116 when the flash memory on the chip is in idle state. For mass erase, this value should be changed to C716 when the flash EEPROM data memory goes to idle mode. 9.3.9 Data Memory End Time Reload Register (DMEND) 9.4 ISP MEMORY The In-System Program memory is part of the flash memory array that contains the flash EEPROM data memory. It is not possible to access the ISP memory while programming the flash EEPROM data memory or access the flash EEPROM data memory while programming the ISP memory. The 1.5K bytes of ISP memory resides in the address range of E000E5FF and is used for storing the boot ROM. The ROM contains the code that performs in-system programming, and is programmed at the factory. In ISP mode, code execution starts at address E000. The ISP program memory and flash EEPROM data memory share the same memory array, which makes it impossible to access one type of memory while the other is being programmed. The ISP memory has the following features: — 1.5K bytes flash EEPROM program memory — Page size of 4 words, divided into two rows of 2 words each — Odd and even bytes within a page can be erased separately — 30µs programming pulse width per word — Page mode erase with 1ms pulse, mass erase with 4ms pulse — All erased memory bits read 1 — Fast read access time — Requires valid key for program and erase to proceed — Provide memory protection and security features for flash EEPROM program memory — Security features may limit accesses to ISP memory — Disable memory when address is out of range to prevent accessing data memory — Mass erase only allowed in test modes — Provide busy status during programming and erase — Read/write accesses disabled during programming/ erase — Programming high voltage and timing generated onchip 9.4.1 Reading The DMEND register is a byte-wide read/write register that controls the delay time after a program/erase operation. This value is loaded into the lower 8 bits of the flash timing counter, and at the same time, 002 is loaded into the upper 2 bits. Before you write to the data memory for the first time, you should program the DMEND register with the proper prescaler value, an 8-bit value called FTEND. The flash timing counter generates a delay of (FTEND + 1) prescaler output clocks. The default value provides a delay time of 5µs when the prescaler output clock is 200kHz. Do not modify this register while program/erase operation is in progress. Upon reset, this register resets to 0016 when the flash memory on the chip is in idle state. For mass erase, this value should be changed to 1316. 9.3.10 Data Memory Prescaler Count Register (DMPCNT) The DMPCNT register is a byte-wide read-only register that returns the value of the data memory prescaler counter. FPCNT is the flash timing prescaler present count value. 9.3.11 Data Memory Timer Count Register (DMCNT) The DMCNT register is a word-wide read-only register that returns the data memory timing counter value. The reserved bits return 0000002. FTCNT[0:9] is the flash timer present count value. 9.3.12 Data Memory Write Key Register (DMKEY) The DMKEY register is a byte-wide, read/write register that provides a way to “lock” the data contained in the EEPROM data memory. Upon reset, the register is automatically set to C9 hex, which is the key value. Writing to the EEPROM data memory is allowed as long as the DMKEY register contains this value. When the register contains any value other than C9 hex, writing the EEPROM data memory is disallowed. To “lock” the current data stored in the data memory, write another value (such as 00 hex) to the DMKEY register. To “unlock” the data memory, write the value C9 hex to the DMKEY register. Note: Operation of this register is different in from the PGMKEY register used with the program memory. It is not necessary to write the key value to DMKEY every time you write to the data memory. The ISP flash EEPROM program memory read accesses can operate without wait cycles with a CPU clock rate of up to 20MHz in the normal mode. At higher clock rates, read accesses can operate with one wait state. The programmed number of wait cycles used (either zero or one) is controlled by BIU Configuration (BCFG) register and the Static Zone 1 Configuration (SZCFG1) register. These registers are described in Section 8.0. 9.4.2 User-Coded Programming Routines All program and erase operations must be preceded by writing the proper key to the program memory key register ISPKEY. The programming code can be in-system RAM, but cannot be from ISP flash EEPROM program memory or flash EEPROM data memory as accesses within these ranges are not permitted while ISP flash EEPROM program memory is being programmed. The ISP flash memory is divided into 192 pages, each page containing 4 words (each 16 bits wide). Each page is further divided into two rows. Erase is carried out one page at a time, 27 www.national.com whereas programming is carried out one row (or one partial row) at a time. Once an erase or programming operation is started, the PGMBUSY bit in the MSTAT register is automatically set, and then cleared when the operation is complete. All high-voltage pulses and timing needed for programming and erasing are provided internally. The program memory cannot be accessed while the PGMBUSY bit is set. Erase Procedure Erasing a page requires the following code sequence: 1. 2. 3. 4. 5. 6. 7. Verify that the MSTAT.PGMBUSY bit is cleared. Set the DMCSR.ERASE bit to 1. Locally disable interrupts. Write proper key value to the ISPKEY register. Write to any valid page to be erased. Re-enable interrupts disabled in Step 3. Set the DMCSR.ERASE bit to 0. Programming Procedure programming, the other words in the same page must first be saved, and then re-programmed. 7 EMPTY 5 4 2 1 0 Reserved CODEAREA[9:8] 9.4.3 Programming is done by writing one byte or word at a time and should be done on already erased memory. Programming the ISP flash EEPROM program memory requires the following code sequence: 1. 2. 3. 4. 5. Verify that the MSTAT.PGMBUSY bit is cleared. Locally disable interrupts. Write proper key value to the ISPKEY register. Write a byte or word to the addressed location. Re-enable interrupts disabled in Step 2. CODEAREA[9:8] The 2 least significant bits in address E5FE contains the two most significant bits of the 10bit CODEAREA field. The description of CODEAREA is shown in the E5FC section. EMPTY The EMPTY status indicates if the flash EEPROM program memory array is empty or not. It is located in the 3 most significant bits in address E5FE. When two or more bits in the EMPTY field are set, the flash EEPROM program memory is empty. Upon reset of the device and the environment select pins are all high, the device operates in ISP environment rather than IRE environment. After the program memory has been filled with user code, this field should be cleared to 0002. 000, 001, 010, 100: Program memory contains user code 011, 101, 11x: Program memory is empty, do not start up in IRE E5FF Byte Upon reset, the byte located in the E5FF address is read into the FLSEC register. This byte cannot be written to in the IRE environment. The format of the E5FF byte is shown below: 7 FROMWR 4 3 FROMRD 0 Programmed values can be verified through normal read operations. If a reset occurs in the middle of an erase or programming operation, the operation is terminated. The reset is extended until the flash EEPROM memory returns to the idle state. 9.4.4 Erase and Programming Timing The FROMRD and FROMWR fields in address location E5FF respectively provide read and write security to the flash EEPROM program memory array while executing instructions in all environments except IRE. The user should always write 00002 to enable security feature. 0000, 0001, 0010, 0100, 1000: Security feature enabled 0011, 0101, 011x, 1001, 101x, 11xx: Security feature disabled The program and erase timing are controlled by the flash EEPROM data memory logic. 9.4.5 Memory Control and Protection Features FROMRD The last 8 bytes of the ISP memory are reserved for special functions and some of these bytes provide memory protection and security for the flash EEPROM program memory. Read and various types of write protection are provided. During the reset stretch period, bytes located at E5FE and E5FF are read out to the FLCTRL2 and FLSEC registers respectively. Upon reset and before an instruction fetch, bytes located at E5FC and E5FD are read out to the FLCTRL2 and FLCTRL1 registers respectively. Parts of FLCTRL2 register are loaded at different times. E5FE Byte Upon reset of the chip, the byte located at E5FE is read into the FLCTRL2 register. It can be written in the ISP or test environments. It can also be written in the IRE environment through a byte write instruction when the write instruction is anywhere within the user boot ROM area (defined above) except for the last two words. When the user boot ROM area has been disabled, this word cannot be programmed in the IRE environment. Note that when this word is erased for re- FROMWR Upon reset of the chip, read security is enabled and 0000 is returned in all environments except IRE. The internal program code can only be executed in the IRE environment when read security is activated. Upon reset of the chip, write security is enabled and program and erase operations to the flash EEPROM program memory in either programming modes are prevented. Once read/write security is enabled, the odd numbered bytes from address E5F9 to E5FF cannot be erased. Once a security feature has been enabled, it cannot be undone. To prevent the security status from being erased, the ISP and data memory array cannot be mass erased. Note: In flash memory test mode, this condition also prevents the odd numbered bytes of the high endurance flash EEPROM data memory (F001 to F07F) from being erased; however, the even numbered bytes of the high endurance flash EEPROM data memory (F000 to F07E) and the ISP flash EEPROM program memory (E000 to E5FE) can be erased. Read/write is overridden through PADX. www.national.com 28 E5FC Byte Upon reset of the chip, E5FC is read into the FLCTRL2 register. The byte at E5FC is written in the ISP or test environments, or in the IRE environment through a byte-write instruction when the write instruction is anywhere within the user boot ROM area except for the last two words. When the user boot ROM area has been disabled by having a value of 7F16 in BOOTAREA, this word cannot be programmed in the IRE environment. Note that when this word is erased for reprogramming, the other words in the same page must first be saved, and then re-programmed also. The E5FC register format is shown below: 7 CODEAREA[7:0] This byte contains the lowest 8 bits of the CODEAREA field. When appended to the left with the lowest 2 bits in the address E5FE, it forms the complete CODEAREA field, which provides write protection to all or part of the program memory, see Figure 3. When write security is not enabled and CODEAREA does not contain the value 3FF16, the program memory range from (CODEAREA×128) to 1FFFF is considered as protected user code area and cannot be written. The minimum protected memory range is therefore 256 bytes when CODEAREA contains the value 3FE. Note that the C000-FFFF memory range is not considered as program memory and is not protected by CODEAREA. 1FFFFh protected code area 10000h non-code area, not protected C000h protected code area user CODEAREA×128 user user must first save the other bytes in the same page, and then re-program those bytes. The format of the E5FD byte is shown below: 7 Reserved 6 BOOTAREA 0 0 BOOTAREA provides write protection to part of the program memory, see Figure 4. When the write security feature is not enabled and BOOTAREA does not contain the value 7F 16, then the program memory range from 0 to (BOOTAREA*128)+127 is considered as user boot ROM area and cannot be written to. The maximum protected memory range is therefore 16K-127 bytes when BOOTAREA contains the value 7E16. 1FFFFh boot area maximum limit 3F80h (BOOTAREA×128)+127 protected user boot area 0000h CR16MHR6 Address Map Figure 4. Memory Protection through BOOTAREA When BOOTAREA contains the value 7F16, write protection is disabled. When write security has been enabled, the entire program memory area is already write protected in all environments. Note that when a new value is written into BOOTAREA, write protection controlled by BOOTAREA is updated after the next device reset. 9.4.6 Test Mode 0000h CR16MHR6 Address Map Figure 3. Memory Protection through CODEAREA The ISP flash EEPROM program memory test mode allows direct access to the flash memory from the device pins, and bypasses the CR16B core. This test mode also accesses the flash memory cells that are not used in data memory (three out of four bytes in each page). 9.4.7 Flash Program Memory Control Register 1 (FLCTRL1) When CODEAREA contains the value 3FF16, write protection is disabled. When the user code area overlaps into the user boot ROM area, the overlap area is governed by a more restrictive write protection feature, which is the user boot ROM area. When write security has been enabled, the entire program memory area is already write protected in all environments. Note that when a new value is written into CODEAREA, write protection controlled by CODEAREA is updated after the next device reset. E5FD Byte Upon the reset of the chip, the byte located at the E5FD address is read into the FLCTRL1 register. This byte can only be written in the ISP or test environments but not in the IRE environment. If this byte is erased for re-programming, the The FLCTRL1 register is a read-only byte-wide register. The value of this register is loaded from memory address E5FD16 when the chip comes out of reset. The BOOTAREA field defines a user boot ROM area to be write protected. The Flash EEPROM Program Memory Control Register 1 format is shown below: 7 Reserved 6 BOOTAREA 0 When BOOTAREA has any value other than 7F16, then the memory at 0 to (BOOTAREA×128)+15 is considered as user boot ROM area and is write protected. When it has a value of 7F16, then there is no user boot ROM area to be write protected. 29 www.national.com 9.4.8 Flash Program Memory Control Register 2 (FLCTRL2) The FLCTRL2 register is a read-only word-wide register. The value of this register is loaded from memory addresses E5FC16 and E5FE16 when the chip comes out of reset. When the device starts execution, the EMPTY bit indicates whether the flash EEPROM program memory is empty of not, and selects the chip to be in IRE or ISP environment if the external environment pins are all high. The CODEAREA field defines a user code area to be write protected. The Flash EEPROM Program Memory Control Register 2 format is shown below: 15 EMPTY 13 12 Reserved 10 9 CODEAREA 0 program memory for the flash write operation to proceed, otherwise any other write operation will clear the key (the only exception is that the subsequent write is another write to this key register with the proper key, in which case the key is still set). A read always returns FF16. Engineering note: on reset, the write enable status that is generated as a result of a write to this key register is cleared. The ISP Memory Write Key register format is shown below: 7 ISPKYVAL 0 When the bits are either 0112, 1012, 1102, or 1112, and if the device’s environment select pins are all high, the device will come out of reset in ISP environment instead of IRE environment. CODEAREA When it has any value other than 3FF16, then the memory (CODEAREA ×128) to 1FFFF16 is considered as user code area and is write protected. When it has a value of 3FF16, then there is no code protection area to be write protected. 9.4.9 Flash Program Memory Security Register (FLSEC) EMPTY ISPKYVAL is the ISP Flash Program Memory Write Enable Key Value. The FLSEC register is a read-only byte-wide register. When the chip comes out of reset, the value of this register is loaded from memory address E5FF16. The FROMRD and FROMWR field control the read and write security of the flash EEPROM program memory respectively. The Flash EEPROM Program Memory Security register format is shown below: 7 FROMWR 43 FROMRD 0 0000, 0001, 0010, 0100, 1000: Security feature enabled 0011, 0101, 011x, 1001, 101x, 11xx: Security feature disabled FROMRD FROMWR When read security feature is enabled, the flash EEPROM program memory can only be read in IRE environment, but will return 000016 in other environments; also, erase to odd numbered bytes from address E5F916 to E5FF16 and mass erase to ISP and flash EEPROM data memory array are ignored unless PADX is activated (see security override below). Unless PADX is activated (see override below), when write security feature is enabled, all further writes and erases to flash EEPROM program memory, erase to odd numbered bytes from address E5F916 to E5FF16, and mass erase to ISP and flash EEPROM data memory array are ignored. 9.4.10 ISP Memory Write Key Register (ISPKEY) The In-System-Programming Memory Write Key (ISPKEY) register is a byte-wide, write-only register. It contains the enable key to enable writes to ISP flash EEPROM program memory. A value of 6A16 must be written to this register immediately preceding every write to the ISP flash EEPROM www.national.com 30 10.0 Interrupts The Interrupt Control Unit (ICU31L) receives interrupt requests from internal and external sources and generates interrupts to the CPU. Interrupts from the timers, USARTs, MICROWIRE/SPI interface, Multi-Input Wake-Up, and A/D converter are all maskable interrupts. The highest-priority interrupt is the Non-Maskable Interrupt (NMI), which is triggered by a falling edge received on the NMI input pin. Table 10 0: Reserved 1: NMI 2: Reserved 3: Reserved 4: Reserved 5: SVC (Supervisor Call Trap) 6: DVC (Divided by Zero Trap) 7: FLG (Flag Trap) 8: BPT (Breakpoint Trap) 9: TRC (Trace Trap) 10: UND (Undefined Instruction Trap) 11: Reserved 12: Reserved 13: Reserved 14: Reserved 15: Reserved 16: INT0 (Reserved) 17: INT1 (Flash EEPROM Program Memory) 18: INT2 (Reserved) 19: INT3 (Reserved) 20: INT4 (Reserved) 21: INT5 (ADC) 22: INT6 (MIWU Interrupt 3) 23: INT7 (MIWU Interrupt 2) 24: INT8 (MIWU Interrupt 1) 25: INT9 (MIWU Interrupt 0) 26: INT10 (USART 2 Tx) 27: INT11 (USART 1Tx) 28: INT12 (Reserved) 29: INT13 (MICROWIRE/SPI Rx/TX) 30: INT14 (ACCESS.bus) 31: INT15 (USART 2 Rx) 32: INT16 (USART 1 Rx) 33: INT17 (Reserved) 34: INT18 (CAN) 35: INT19 (Reserved) 36: INT20 (Reserved) 37: INT21 (Reserved) Dispatch Table Entries 10.1 INTERRUPT OPERATION An exception is an event that temporarily stops the normal flow of program execution and causes execution of a separate service routine. Upon completion of the service routine, execution of the interrupted program continues from the point at which it was stopped. There are two kinds of exceptions, called traps and interrupts. A trap is the result of some action or condition in the program itself, such as execution of an Exception (EXCP) instruction. An interrupt is a CPU-external event, such as a signal received on a Multi-Input Wake-Up input or a request from an on-chip peripheral module for service. The operation of traps is beyond the scope of this data sheet. For information on traps, and for additional detailed information on interrupts not provided in this data sheet, please refer to the CompactRISC CR16B Programmer's Reference Manual. 10.1.1 Interrupt Operation Summary When an interrupt occurs, the on-chip hardware performs the following steps: 1. Decrements the Interrupt Stack Point (ISP) by four. 2. Saves the contents of the Program Counter (PC) and Processor Status Register (PSR) on the interrupt stack. 3. Clears the I, P and T bits in the Processor Status Regis, ter (PSR). These are the Global Maskable Interrupt Enable bit, Trace Trap Pending bit, and Trace bit, respectively. 4. Reads the interrupt vector from the Interrupt Vector Register (IVCT). 5. Combines the interrupt vector with the value in the Interrupt Base (INTBASE) register to obtain an address in the Interrupt Dispatch Table, and loads the dispatch table entry into the Program Counter (PC). From this point onward, the CPU executes the interrupt service routine. The service routine ends with a Return from Exception (RETX) instruction. This returns the CPU to the interrupted program. The CPU restores the contents of the PC and PSR registers from the stack and increments the Interrupt Stack Pointer by four. 10.1.2 Service Routine Addresses When an interrupt or trap occurs, the CPU executes a service routine. There are different service routines for different interrupts and traps. Each service routine may reside anywhere in program memory. The starting addresses of the service routines are contained in a table called the Dispatch Table. Entries in the table are organized in the order shown in Table 10. Each entry in the Dispatch Table consists of two bytes that provide bits 1 through 16 of the starting address of the corre- 31 www.national.com Table 10 38: INT22 (Reserved) Dispatch Table Entries the registers. A high-level language typically allocates the local (non-static) variables on the stack. The pointer to the program stack is the SP register, which must be initialized prior to any register save/restore operations or data transfer operations. Using the program stack, an interrupt routine needs to initially save the contests of all registers that it uses, and restore those register contents before returning to the interrupted program. 39: INT23 (VTUD Interrupt Request 4) 40: INT24 (VTUD Interrupt Request 3) 41: INT25 (VTUD Interrupt Request 3) 42: INT26 (VTUD Interrupt Request 1) 43: INT27 (T2B Timer 2 Interrupt B) 44: INT28 (T2A Timer 2 Interrupt A) 45: INT29 (T1B Timer 1Interrupt B) 46: INT30 (T1A Timer 1Interrupt A) 47: INT31 (RTI Timer 0) sponding service routine. The full 21-bit address of a service routine is reconstructed by adding a leading 0 and a trailing 0 to the 16-bit table entry. The INTBASE register is a pointer to the Dispatch Table. Upon reset, the initialization software must write the starting address of the Dispatch Table to the INTBASE register, a 21bit register with the five most significant bits and the least significant bit always equal to 0. It is typically kept in the flash EEPROM program memory. The Dispatch Table is 48 words long. Each interrupt or trap source has an associated vector number ranging from 0 to 31, as indicated in Table 10. When an interrupt occurs, the hardware multiplies the vector by 2, adds the result to the contents of the INTBASE register, and uses the resulting address to obtain the service routine starting address from the corresponding entry in the Dispatch Table. This address is placed in the Program Counter so that the CPU begins executing the interrupt service routine. Figure 5 summarizes the method used by the device to generate the starting address of a service routine. 10.1.3 Stack Usage ~ INTBASE 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 to 127 ~ Reserved NMI Reserved Reserved Reserved SVC DVZ FLG BPT TRC UND Reserved Reserved Reserved DBG ISE INTn ~ 0 Non-maskable Interrupt Supervisor Call Trap Divide By Zero Trap Flag Trap Breakpoint Trap Trace Trap Undefined Instruction Trap Debug Trap In-System Emulator Interrupt Maskable Interrupts When an interrupt occurs, the CPU automatically preserves the contents of the Program Counter (PC) and Processor Status Register (PSR) by pushing them on the interrupt stack and decrementing the Interrupt Stack Pointer by four. The service routine ends with a Return from Exception (RETX) instruction, which returns control to the interrupted program by restoring the PC and PSR values and incrementing the Interrupt Stack Pointer (ISP) by four. Prior to using any interrupts, the Interrupt Stack Pointer (ISP) must be initialized so that it points to a space in RAM where the interrupt stack will be kept. The stack grows downward in memory (toward address zero) when an interrupt occurs and items are pushed onto the stack. The stack shrinks upward in memory when an interrupt service routine ends and items are popped from the stack. Many routines need to use the general-purpose registers R0 through R13. To preserve the existing register contents, a routine can save register contents on the program stack upon start of the routine and restore the register contents prior to completion of the routine. The software can also use the program stack to transfer data parameters from one routine to another when the parameters are too large to easily fit into ~ Figure 5. 10.2 NON-MASKABLE INTERRUPT A non-maskable interrupt is triggered by a falling edge on the NMI input pin, which generates a software trap. The NMI pin is an asynchronous input with Schmitt trigger characteristics and an internal synchronization circuit. Therefore, no external synchronizing is needed. Upon reset, the non-maskable interrupt is disabled and should remain disabled until the software initializes the interrupt table, interrupt base, and interrupt stack pointer. It can be enabled by setting either of two control bits in the External NMI Control/Status (EXNMI) register. The two bits are called the EN (Enable) bit and the ENLCK (Enable and Lock) bit. The EN bit enables the NMI trap until an NMI trap event or a reset occurs. An NMI trap automatically resets the EN bit. Using this bit to enable the NMI trap is intended for applications where the NMI pin is toggled frequently but nested NMI traps are not needed. The trap service routine should re-enable the NMI trap by setting the EN bit before returning to the main program. www.national.com 32 The ENLCK bit enables the NMI trap and locks it in the enabled state. In other words, it leaves the NMI trap enabled even after the trap occurs. It can be cleared only by a reset operation. After the bit is set, an NMI trap is triggered by each falling edge on the NMI pin, allowing nested NMI traps. To use the EN bit, the ENLCK must remain cleared to 0. Otherwise, the EN bit is ignored. 10.3 MASKABLE INTERRUPTS To enable a maskable interrupt, the enable bit must be set in the applicable peripheral module and also in the appropriate Interrupt and Enable Mask register, IENAM0 or IENAM1. In addition, both the Global Maskable Interrupt Enable bit (I) and the Local Maskable Interrupt Enable bit (E) must be set to 1 in the PSR register. If either one of these bits is 0, then all maskable interrupts are disabled. The CR16B core supports IRQ0, but ICU31L reserves IRQ0 so that it is not connected to any interrupt source. Both the E bit and I bit can be controlled with the Load Processor Register (LPR) instruction. In addition, the E bit is easily changed by executing the Enable Interrupts (EI) or Disable Interrupts (DI) instruction. Using the EI and DI instructions avoids the possibility of an interrupt occurring within a read-modify-write operation on the PSR register. Maskable interrupts can be enabled or disabled under software control. There are 31 level-triggered maskable interrupt sources (including some reserved for future expansion), organized into levels of priority. If more than one interrupt event occurs at any given time, the interrupt source with the highest priority is serviced first. The others must wait until the highest-priority interrupt is serviced and is no longer pending. Figure 11 lists the maskable interrupt sources of the device in order of priority, from the highest-priority interrupt (IRQ31) to the lowest (IRQ0). Table 11 Maskable Interrupt Priority List Source RTI (Timer 0), highest priority T1A (Timer 1 input A) T1B (Timer 1 input B) T2A (Timer 2 input A) T2B (Timer 2 input B) VTUA (VTU Interrupt Request 1) VTUB (VTU Interrupt Request 2) VTUC (VTU Interrupt Request 3) VTUD (VTU Interrupt Request 4) Reserved CAN Reserved USART1 Rx USART2 Rx ACCESS.bus MICROWIRE/SPI Rx/Tx Reserved USART1 Tx USART2 Tx MIWU16 Interrupt 0 MIWU16 Interrupt 1 MIWU16 Interrupt 2 MIWU16 Interrupt 3 ADC Reserved Flash Program Memory Reserved, lowest priority 10.4 INTERRUPT REGISTERS The Interrupt Control Unit uses the following interrupt control and status registers: — Non-Maskable Interrupt Status Register (NMISTAT) — Non-Maskable Interrupt Status Monitor Reg. (NMIMNTR) — External NMI Control/Status Register (EXNMI) — Interrupt Enable and Mask Register 0 (IENAM0) — Interrupt Enable and Mask Register 1 (IENAM1) — Interrupt Vector Register (IVCT) — Interrupt Status Register 0 (ISTAT0) — Interrupt Status Register 1 (ISTAT1) — Interrupt Debug Register (IDBG) The following CPU core registers are also used in processing interrupts: — Interrupt Stack Pointer (ISP) — Interrupt Base Register (INTBASE) 10.4.1 Non-Maskable Interrupt Status Register (NMISTAT) Interrupt Request IRQ31 IRQ30 IRQ29 IRQ28 IRQ27 IRQ26 IRQ25 IRQ24 IRQ23 IRQ22-IRQ19 IRQ18 IRQ17 IRQ16 IRQ15 IRQ14 IRQ13 IRQ12 IRQ11 IRQ10 IRQ9 IRQ8 IRQ7 IRQ6 IRQ5 IRQ4-IRQ2 IRQ1 IRQ0 The NMISTAT register is a byte-wide, read-only register that holds the current pending status of the Non-Maskable Interrupt (NMI). This register is cleared upon reset. It is also cleared each time it is read. The register format is shown below. 7 6 5 4 3 Reserved 2 1 0 EXT EXT External Non-Maskable Interrupt Request. When set to 1 by the hardware, it indicates an external Non-Maskable Interrupt request has occurred. See the description of the EXNMI register below for more information. External NMI Control/Status Register (EXNMI) 10.4.2 The EXNMI register is a byte-wide, read/write register that shows the current state of the NMI pin and also allows the NMI trap to be enabled by setting either the EN bit or the ENLCK bit. Both of these bits are cleared upon reset. When the software writes to this register, it must write 0 to all reserved bit positions for the device to function properly. EN, ENLCK, and TST are cleared upon reset. The register format is shown below. 33 www.national.com 10.4.5 7 6 5 4 Reserved 3 2 ENLCK 1 PIN 0 EN Interrupt Enable and Mask Register 1 (IENAM1) The IENAM0 register is a word-wide, read/write register that enables or disables the individual interrupts IRQ16 through IRQ31. The register format is shown below. 15 IENA(31:16) A bit set to 1 enables the corresponding interrupt. A bit cleared to 0 disables the corresponding interrupt. Upon reset, this register is initialized to FFFF hex. 10.4.6 Interrupt Status Register 0 (ISTAT0) 0 EN PIN ENLCK Enable NMI Trap. When set to 1, NMI traps are enabled and falling edge on the NMI pin generates a NMI trap. Each occurrence of an NMI trap automatically clears the EN bit. The trap service routine should set the EN bit to 1 before returning control to the interrupted program. When EN is cleared to 0, NMI traps are disabled unless they are enabled with the ENLCK bit. When the ENLCK bit is set to 1, the EN bit is ignored. NMI Pin. This bit shows the current state of the NMI input pin (without logical inversion). A 1 indicates a high level and a 0 indicates a low level on the pin. This is a read-only bit. In a write operation, the value written to this bit position is ignored. Enable and Lock NMI Trap. When set to 1, NMI traps are enabled and locked in the enabled state. Each falling edge on the NMI pin generates a NMI trap, even if a previous NMI trap has occurred and is still being processed. When ENLCK is cleared to 0, NMI traps are disabled unless they are enabled with the EN bit. Interrupt Vector Register (IVCT) The ISTAT0 register is a word-wide, read-only register that indicates which maskable interrupt inputs to the ICU31L (IRQ0 through IRQ15) are currently active. The register format is shown below. 15 IST(15:0) IST(15:0) Interrupt Status bits. Each bit indicates the current status of an interrupt input to the ICU31L, corresponding to interrupts IRQ0 through IRQ15. A bit set to 1 indicates an active interrupt input, even when the interrupt is masked out by the IENAM0 register. A bit cleared to 0 indicates an inactive interrupt input. 0 10.4.3 10.4.7 Interrupt Status Register 1 (ISTAT1) The IVCT register is a byte-wide, read-only register that contains the encoded value of the enabled and pending maskable interrupt with the highest priority. The on-chip hardware automatically updates this field whenever there is a change in the highest-priority enabled and pending maskable interrupt. The CPU reads this register during an interrupt acknowledge core bus cycle to determine where to begin executing the interrupt service routine. The register contents are guaranteed to be valid at that time. The register is not guaranteed to contain valid data during a hardware update operation. The register format is shown below. 7 0 INTVECT 6 0 5 4 3 2 INTVECT 1 0 The ISTAT1 register is a word-wide, read-only register that indicates which maskable interrupt inputs to the ICU31L (IRQ16 through IRQ31) are currently active. The register format is shown below. 15 IST(31:16) IST(31:16) Interrupt Status bits. Each bit indicates the current status of an interrupt input to the ICU31L, corresponding to interrupts IRQ16 through IRQ31. A bit set to 1 indicates an active interrupt input, even when the interrupt is masked out by the IENAM0 register. A bit cleared to 0 indicates an inactive interrupt input. 0 Interrupt Vector. This 6-bit field contains the encoded value of the enabled and pending maskable interrupt with the highest priority. For example, if interrupts IRQ1 and IRQ6 are both enabled and pending, the higher-priority interrupt is IRQ6. As a result the 6 bit interrupt vector is 010110. 10.4.8 Interrupt Debug Register The IDBG register is a word-wide read-only register, which contains various status information of the ICU31L. The lowest 6 bits contain the INTVECT value during the last read from address FE00. The next 6 bits contain the INTVECT value when a maskable interrupt request is sent to the CR16B core. Upon reset, this register is set to 0000 hex. 10.4.4 Interrupt Enable and Mask Register 0 (IENAM0) The IENAM0 register is a word-wide, read/write register that enables or disables the individual interrupts IRQ0 through IRQ15. The register format is shown below. 15 IENA(15:0) A bit set to 1 enables the corresponding interrupt. A bit cleared to 0 disables the corresponding interrupt. Upon reset, this register is initialized to FFFF hex. 0 10.5 INTERRUPT PROGRAMMING PROCEDURES The following subsections provide information on initializing the device for interrupts, clearing interrupts, and nesting interrupts. 10.5.1 Initialization Upon reset, all interrupts are disabled. To program the device for interrupt operation and to enable interrupts, use the following procedure in the application software: www.national.com 34 1. Set the Interrupt Stack Pointer (ISP) 2. Load the INTBASE register so that it points to the base of the Interrupt Dispatch Table. 3. Perform any required preparation steps for the interrupt service routines. 4. Initialize the peripheral devices that can generate interrupts and set their respective interrupt enable bits. 5. Set the relevant bits in the interrupt mask registers (IENAM0 and IENAM1) Note: The MIWU16 interrupts have no local interrupt enable bits, which means you can only disable the MIWU16 interrupts if you clear the specific bits in the IENAM register. 6. Use the Load Processor Register (LPR) instruction to set I bit in the PSR register. 7. When the device is ready to execute interrupts, set the E bit in the PSR register by executing the Enable Interrupts (EI) instruction. Once maskable interrupts are enabled by setting the E and I bits, you can disable and re-enable all maskable interrupts locally by using the Enable Interrupts (EI) and Disable Interrupts (DI) instructions, which set and clear the E bit. 10.5.2 Clearing Interrupts the software after clearing the interrupt pending bit and before another interrupt. Placing a NOP instruction will perform this instruction. This is because the instruction which resets the pending bit may not yet be finished when the interrupts are already enabled again by setting the I bit in the PSR register. To avoid this situation the user has to make sure that prior to enabling the interrupt an additional instruction is inserted. This could look like the example below: SBITi $0, T1ICRL # clear pending bit NOP LPR r0, psr # NOP instruction MOVW $0x0a00, r0 # enable further interrupts A CBITi or SBITi instruction may be used to clear the interrupt pending bit. In such cases, a spurious interrupt may occur. Clearing an interrupt request before it is serviced may cause a spurious interrupt because the CPU may detect an interrupt not reflected in the Interrupt Vector (IVCT) register. To ensure reliable operation, clear interrupt requests only while interrupts are disabled. Changing the polarity of an interrupt input (for example, in the Multi-Input Wake-Up module) can cause a spurious interrupt, and therefore should be done only while interrupts are disabled. For the same reason, clearing an enable bit in a peripheral module should be carried out only while the interrupt is disabled. 10.5.3 Nesting Interrupts Interrupts may be nested, or in other words, an interrupt service routine can itself be interrupted by a different interrupt source. There is no hardware limitation on the number of interrupt nesting levels. However, the interrupt stack must not be allowed to overflow its allocated memory space. Unless specifically enabled by the software, nested interrupts will not occur. When the CPU acknowledges an interrupt, the I bit in the PSR register is automatically cleared to 0 for the duration of the service routine, disabling any further maskable interrupts. To allow nested interrupts, an interrupt service routine should first set or clear the respective interrupt enable bits to specify which peripherals will be allowed to interrupt the current service routine. The present interrupt routine should be disabled (or interrupt pending bit cleared). The service routine should then set the PSR.I bit to 1, thus enabling maskable interrupts. This bit can be controlled with the Store Processor Register (SPR) and Load Processor Register (LPR) instructions. Note: Clearing the pending bit of the current interrupt should not be immediately followed by enabling further interrupts by setting the I bit in the PSR register. Wait states must be inserted into 35 www.national.com 11.0 Power Management The Power Management Module (PMM) improves the efficiency of the device by changing the operating mode (and therefore the power consumption) according to the required level of device activity. The device can operate in any of four power modes: — — — — Active Power Save Idle Halt by the slow clock rather than the normal high-speed clock. In order to work properly in Power Save mode, modules that perform real-time operations (such as a USART baud rate generator) must be reprogrammed to use the slower clock. To reduce power consumption as much as possible, the program should execute a WAIT instruction during periods of CPU inactivity. 11.3 IDLE MODE Table 12 summarizes the main properties of the four operating modes: the state of the high-frequency oscillator (on or off), the type of clock used by most modules, and the clock used by the Timing and Watchdog Module (TWM). Table 12 Mode Active Idle Halt Power Mode Operating Summary In the Idle mode, the clock is stopped for most of the device. Only the Power Management Module and Timing and Watchdog Module continue to operate. Both of these modules use the slow clock in this mode. 11.4 HALT MODE High-Frequency Clock Used TWM Clock Oscillator On On or Off Off Main Clock Slow Clock None None Slow Clock Slow Clock Slow Clock None Power Save On or Off In the Halt mode, all device clocks are disabled and the highfrequency oscillator is shut off. In this mode, the device consumes the least possible power while maintaining the device memory and register contents. The low-frequency oscillator continues to operate in this mode, but with very low power consumption due to its power-optimized design. 11.5 CLOCK INPUTS AND RESET CONFIGURATION The low-frequency oscillator continues to operate in all four modes and power must be provided continuously to the device power supply pins. In the Halt mode, however, the internal SLCLK does not toggle, and as a result, the TWM timer and Watchdog Module do not operate. For the Power Save and Idle modes, the high-frequency oscillator can be turned on or off under software control, as long as the low-frequency oscillator is used. The system uses a high frequency clock Active mode. The source of this clock in the device is a high frequency crystal oscillator. The Oscillating High Frequency Clock (OHFC) input indicates to the Power Management Module (PMM) when this clock is stable and therefore usable. The clock can be used when OHFC is set to 1. The PMM does not use the high frequency clock when OHFC is set to 0. OHFC can be the output of a clock monitor or a strapped input signal to this module. The low frequency clock is used in Power Save mode as the system clock source. In Idle mode, it is used as the clock source for the PMM and the TWM, both of which remain clocked. The clock source may be a low frequency clock oscillator or the prescaler from the high frequency clock. The Oscillating Low Frequency Clock (OLFC) input indicates to the PMM when the clock is stable and therefore usable. When OLFC is set to 1, it indicates that the clock can be used. When OLFC is set to 0, the PMM does not use the low frequency clock. OLFC is generated by the “slow clock good” output of the Dual Clock and Reset module (CLK2RES). While in reset (i.e., the reset signal is active), the PMM outputs the clock as long as the clock selected for use upon reset is stable (OHFC or OLFC are 1). If the clock selected is not stable, the PMM clock output remains low. 11.1 ACTIVE MODE In the Active mode, all device modules are fully operational. This is the operating mode upon reset. Most device modules use the clock generated by the high-frequency clock oscillator. The clock rate is determined by the external crystal network. Power consumption in the Active mode can be reduced by selectively disabling unused modules and/or by executing the WAIT instruction. When WAIT is executed, the core stops executing new instructions and waits for an interrupt. 11.2 POWER SAVE MODE In the Power Save mode, all device modules operate off the low-frequency clock. If the low-frequency clock is generated from an external crystal network, the high-frequency clock oscillator can be turned off to further reduce power consumption. All on-chip modules continue to operate in the Power Save mode, with the SLCLK acting as their system clock. If this mode is entered by using the WAIT command, the CPU is inactive and waits for an interrupt to wake up. Otherwise, CPU continues to function normally at the lower frequency of the slow clock. The low frequency of the clock in Power Save mode limits the operation of modules such as the USARTs, MICROWIRE interface, A/D Converter, and timers because they are driven www.national.com 11.6 SWITCHING BETWEEN POWER MODES Switching from a higher to a lower power consumption mode is accomplished by writing an appropriate value to the Power Management Control/Status Register (PMCSR). Switching from a lower power consumption mode to the Active mode is usually triggered by a hardware interrupt. Figure 6 shows the four power consumption modes and the events that trigger a transition from one mode to another. Some of the power-up transitions are based on the occurrence of a wake-up event. An event of this type can be either 36 Reset Active PSM =1 Power Save IDLE =1 and WAIT HW event or PSM =0 HALT Idle HW event HALT =1 and WAIT Halt HW event Figure 6. Power Modes and Transitions WBPSM a maskable interrupt or a non-maskable interrupt (NMI). All of the maskable hardware wake-up events are gathered and processed by the Multi-Input Wake-Up Module, which is active in all modes. Once a wake-up event is detected, it is latched until an interrupt acknowledge cycle occurs or a reset is applied. A wake-up event causes a transition to the Active mode and restores normal clock operation, but does not start execution of the program. It is the interrupt service routine associated with the wake-up source (MIWU16 or NMI) that causes actual program execution to resume. 11.6.1 Power Management Control/Status Register (PMCSR) The Power Management Control/Status Register (PMCSR) is a byte-wide, read/write register that controls the operating power mode (Active, Power Save, Idle, or Halt) and enables or disables the high-frequency oscillator in the Power Save and Idle modes. The two most significant bits, OLFC and OHFC, are read-only status bits controlled by the hardware. Upon reset, the non-reserved bits of this register are cleared. The format of the register is shown below. 7 6 5 4 3 2 1 0 OLFC OHFC WBPSM Reserved HALT IDLE DHF PSM PSM Power Save Mode. When this bit is 0, the device operates in the Active mode. Writing a 1 to this bit position puts the device into the Power Save mode, either immediately or upon execution of the next WAIT instruction, depending on the WBPSM bit. The PSM bit can be set and cleared by the software. It is also cleared by the hardware when a hardware wake-up event is detected. Disable High-Frequency Oscillator. This bit enables (0) or disables (1) the high-frequency oscillator in the Power Save or Idle mode. (The high-frequency oscillator is always enabled in Active mode and always disabled in Halt mode, regardless of this bit settings.) The DHF bit is cleared automatically when a hardware wakeup event is detected. Idle Mode. When this bit is set and the device is in Power Save mode, the device enters the OHFC OLFC DHF Idle mode upon execution of a WAIT instruction. In order to enter the Idle mode directly from the Active mode, the WBPSM bit must be set before the WAIT instruction is executed. The IDLE bit can be set and cleared by the software. When a hardware wake-up event is detected, this bit is cleared automatically and the device returns to the Active mode. Halt Mode. When this bit is set and the device is in Idle mode, the device enters the Halt mode upon execution of a WAIT instruction. In order to enter the Halt mode directly from the Active mode, the WBPSM bit must be set before the WAIT instruction is executed. The Halt bit can be set and cleared by the software. When a hardware wake-up event is detected, this bit is cleared automatically and the device returns to the Active mode. Wait Before Entering Power Save Mode. When the CPU writes a 1 to the PSM bit, the WBPSM determines when the transition from Active to Power Save mode is done. If the WBPSM bit is 0, the switch to Power Save mode is initiated immediately; the PSM bit in the register is set to 1 upon completion of the switch to Power Save mode. If the WBPSM bit is 1, the device continues to operate in Active mode until the next WAIT instruction, and then enters the Power Save mode. In this case, the PSM bit is set to 1 immediately, even if a WAIT instruction has not yet been executed. In the Active mode, the WBPSM bit must be set in order to enter the Idle or Halt mode. Oscillating High-Frequency Clock. This readonly bit indicates the status of the high-frequency clock. If this bit is 1, the high-frequency clock is available and stable. If this bit is 0, the highfrequency clock is either disabled, not available to the Power Management Module, or operating but not yet stable. The device can switch to the Active mode only when this bit is 1. Oscillating Low-Frequency Clock. This readonly bit indicates the status of the low-frequency (slow) clock. If this bit is 1, it indicates that the slow clock is running and stable. The slow clock can be either the prescaled fast clock (the default) or the external oscillator (if selected). The Dual Clock module will not allow a transition to the slow crystal mode unless the slow crystal is operating, so this bit should be 1 under normal circumstances. The device can switch from the Active mode to the Power Save or Idle mode only if the OLFC bit is 1. There is no such restriction on switching to the Halt mode. Active to Power Save Mode 11.6.2 IDLE A transition from the Active mode to the Power Save mode is accomplished by writing a 1 to the PMCSR.PSM bit. The transition to Power Save mode is either initiated immediately or upon execution of the next WAIT instruction, depending on the PMCSR.WBPSM bit. 37 www.national.com For an immediate transition to Power Save mode (PMCSR.WBPSM=0), the CPU continues to operate using the lowfrequency clock. The PMCSR.PSM bit is set to 1 when the transition to the Power Save mode is completed. For a transition upon the next WAIT instruction (PMCSR.WBPSM=1), the CPU continues to operate in the Active mode until it executes a WAIT instruction. Upon execution of the WAIT instruction, the device enters the Power Save mode and the CPU waits for the next interrupt event. In this case, the PMCSR.PSM bit is set to 1 when it is written, even before the WAIT instruction is executed. 11.6.3 Entering the Idle Mode SR.DHF bit. Before writing a 0 to the PMCSR.PSM bit, the software should first monitor the PMCSR.OHFC bit to determine whether the oscillator has stabilized. 11.6.7 Wake-Up Transition to Active Mode A hardware wake-up event switches the device directly from Power Save, Idle, or Halt mode to the Active mode. Hardware wake-up events are: • • a Non-Maskable Interrupt (NMI) a valid wake-up event on a Multi-Input Wake-Up channel When a wake-up event occurs, the on-chip hardware performs the following steps: 1. Clears the PMCSR.DHF bit, thus enabling the high-frequency clock (if it was disabled). 2. Waits for the PMCSR.OHFC bit to be set, which indicates that the high-frequency clock is operating and is stable. 3. Switches the device into the Active mode. 11.6.8 Power Mode Switching Protection Entry into the Idle mode is accomplished by writing a 1 to the PMCSR.IDLE bit and then executing a WAIT instruction. The Idle mode can be entered only from the Active or Power Save mode. For entry from the Active mode, the PMCSR.WBPSM bit must be set before the WAIT instruction is executed. 11.6.4 Disabling the High-Frequency Clock In systems where the low-frequency crystal is available and is used to generate the Slow Clock (SLCLK), power consumption can be reduced further in the Power Save or Idle mode by disabling the high-frequency clock. This is accomplished by writing a 1 to the PMCSR.DHF bit before executing the WAIT instruction that puts the device in the Power Save or Idle mode. The high-frequency clock is turned off only after the device enters the Power Save or Idle mode. The CPU operates on the low-frequency clock in Power Save mode. It can turn off the high-frequency clock at any time by writing a 1 to the PMCSR.DHF bit. The high-frequency oscillator is always enabled in Active mode and always disabled in Halt mode, regardless of the PMCSR.DHF bit setting. Immediately following power-up and entry into the Active mode, the software must wait for the low-frequency clock to become stable before it can put the device in the Power Save mode. It should monitor the PMCSR.OLFC bit for this purpose. Once this bit is set to 1, the slow clock is stable and the Power Save mode can be entered. 11.6.5 Entering the Halt Mode The Power Management Module has several mechanisms to protect the device from malfunctions caused by missing or unstable clock signals. The PMCSR.OHFC and PMCSR.OLFC bits indicate the current status of the high-frequency and low-frequency clock oscillators, respectively. The software can check the appropriate bit before it changes to an operating mode that requires the clock. A status bit set to 1 indicates an operating, stable clock. A status bit cleared to 0 indicates a clock that is disabled, not available, or not yet stable. During a power mode transition, if there is a request to switch to a mode that uses clock with its status bit cleared to 0, the switch is delayed until that bit is set to 1 by the hardware. When the system is built without an external crystal network for the low-frequency clock, the high-frequency clock is divided by a prescaler factor to produce the low-frequency clock. In this situation, the high-frequency clock is disabled only in the Halt mode, and cannot be disabled for the Power Save or Idle mode, regardless of the software command issued. Without an external crystal network for the low-frequency clock, the device comes out of the Halt or Idle mode and enters the Active mode with the high-speed oscillator used as the clock. The device can still enter the Power Save from the Active mode by using the high-frequency-clock divider to generate the slow clock (PMCSR.DHF=0). Note: For correct operation in the absence of a low-frequency crystal, the X2CKI pin must be tied low (not left floating) so that the hardware can detect the absence of the crystal. Entry into the Halt mode is accomplished by writing a 1 to the PMCSR.HALT bit and then executing a WAIT instruction. The Halt mode can be entered only from the Active or Power Save mode. For entry from the Active mode, the PMCSR.WBPSM bit must be set before the WAIT instruction is executed. 11.6.6 Software-Controlled Transition to Active Mode A transition from the Power Save mode to the Active mode can be accomplished by either a software command or a hardware wake-up event. The software method is to write a 0 to the PMCSR.PSM bit. The value of the register bit changes only after the transition to the Active mode is completed. If the high-frequency oscillator is disabled for Power Save operation, the oscillator must be enabled and allowed to stabilize before the transition to Active mode. To enable the highfrequency oscillator, the software writes a 0 to the PMC- www.national.com 38 12.0 Dual Clock and Reset The Dual Clock and Reset module (CLK2RES) generates a high-speed main system clock from an external crystal network and a slow clock (32.768 kHz or other rate) for operating the device in Power Save mode. It also provides the main system reset signal, a power-on reset function, a main clock prescaler to generate two additional low speed clocks, and an 32kHz oscillator start-up delay. Figure 7 is block diagram of the Dual Clock and Reset module. Reset Power-On-Reset System Reset Stop Main Osc. Preset X1CKI Start-Up-Delay 14-Bit Timer X1CKO Main Osc. Stop Main Osc In Time-out Good Main Clk Main Clk 4-Bit Prescaler 4-Bit Prescaler Div. by-2 8-Bit Prescaler 2 Low Speed Clk Outputs X2CKI 32kHz Osc. Low Speed Clk Mux Start-Up-Delay 6-Bit Timer X2CKO Preset Time-out Good Low Speed Clk Stop 32kHz Osc. Figure 7. Dual Clock and Reset Module Block Diagram Stop Low Speed Clk 12.1 EXTERNAL CRYSTAL NETWORK An external crystal network is required at pins X1CKI and X1CKO for the main clock. A similar external crystal network may be used at pins X2CKI and X2CKO for the slow clock in packages that have these pins. If an external crystal network is not used for the slow clock, the clock is generated by dividing the fast main clock. The crystal oscillator you choose may require external components different from the ones specified above. In that case, consult with National’s engineer for the component specifications The crystals and other oscillator components should be placed close to the X1CKI/X1CKO and X2CKI/X2CKO device input pins to keep the printed trace lengths to an absolute minimum. Figure 8 shows the required crystal network at X1CKI/ X1CKO and optional crystal network at X2CKI/X2CKO. Table 13 shows the component specifications for the main crystal network and Table 14 shows the component specifications for the 32.768 kHz crystal network. 39 www.national.com X1CKI / X2CKI XTAL C1 R1 X1CKO / X2CKO C2 R2 Figure 8. Table 13 Component Oscillator External Crystal Network Component Values of the High Frequency Crystal Circuit Values 4 MHz AT-Cut 75 Ω 4 pF 12 pF 1 MΩ 0Ω 22 pF Values 12 MHz AT-Cut 35 Ω 4 pF 15 pF 1 MΩ 0Ω 20 pF Values 16 MHz AT-Cut 35 Ω 4 pF 15 pF 1 MΩ 0Ω 20 pF Values 20 MHz AT-Cut 35 Ω 4 pF 20 pF 1 MΩ 0Ω 20 pF Values 24 MHz AT-Cut 35 Ω 4 pF 20 pF 1 MΩ 0Ω 20 pF Tolerance Parameters Resonance Frequency Type Max. Serial Resistance Max. Shunt Capacitance Load Capacitance Resistor R1 Resistor R2 Capacitor C1, C2 N/A Crystal 5% 5% 20% Table 14 Component Oscillator Component Values of the Low Frequency Crystal Circuit Parameters Values 32.768kHz Parallel N-Cut or XY-bar 40 kΩ 2 pF 9-13 pF 10-20 MΩ 4.7 kΩ 20 pF Tolerance Resonance Frequency Type Maximum Serial Resistance Maximum Shunt Capacitance Load Capacitance N/A Crystal Resistor R1 Resistor R2 Capacitor C1, C2 5% 5% 20% Choose capacitor component values in the tables obtain the specified load capacitance for the crystal when combined with the parasitic capacitance of the trace, socket, and package (which can vary from 0 to 8 pF). As a guideline, the load capacitance is: CL = (C1 * C2)/(C1+C2) + Cparasitic C2 > C1 C1 can be trimmed to obtain the desired load capacitance. The start-up time of the 32.768 kHz oscillator can vary from one to six seconds. The long start-up time is due to the high “Q” value and high serial resistance of the crystal necessary to minimize power consumption in Power Save mode. This signal is an indicator that the main clock oscillator is stable. The “Stop Main Osc” signal from the Power Management Module stops and starts the main oscillator. When this signal is asserted, it presets the 14-bit timer to 3FFF hex and stops the main oscillator. When the signal goes inactive, the main oscillator starts and the 14-bit timer counts down from its preset value. When the timer reaches zero, it stops counting and asserts the “Good Main Clk” signal. 12.3 SLOW SYSTEM CLOCK 12.2 MAIN SYSTEM CLOCK The slow (32.768 kHz) clock is necessary for operating the device in Power Save modes and to provide a clock source for modules such as the Timing and Watchdog Module. The slow clock operates in a manner similar to the main clock. The “Stop Slow Osc” signal from the Power Management Module stops and starts the slow oscillator. When this signal is asserted, it presets a 6-bit timer to 3F hex and disables the slow oscillator. When the signal goes inactive, the slow oscillator starts and the 6-bit timer counts down from its preset value. When the timer reaches zero, it stops counting The main system clock is generated by the main oscillator. It can be stopped by the Power Management Module to reduce power consumption during periods of reduced activity. When the main clock is restarted, a 14-bit timer generates a “Good Main Clk” signal after a start-up delay of 32,768 clock cycles. www.national.com 40 and asserts the “Good Low Speed Clk” signal, thus indicating that the slow clock is stable. For systems that do not require a reduced power consumption mode, the external crystal network may be omitted for the slow clock. In that case, the slow clock can be created by dividing the main clock by a prescaler factor. The prescaler circuit consists of a fixed divide-by-2 counter and a programmable 8-bit prescaler register. This allows a choice of clock divisors ranging from 2 to 512. The resulting slow clock frequency must not exceed 100 kHz. A software-programmable multiplexer selects either the prescaled main clock or the 32.768 kHz oscillator as the slow clock. Upon reset, the prescaled main clock is selected, ensuring that the slow clock is always present initially. Selection of the 32.768 kHz oscillator as the slow clock disables the clock prescaler, which allows the CLK1 oscillator to be turned off during power-save operation, thus reducing power consumption and radiated emissions. This can be done only if the module detects a togging low-speed oscillator. If the lowspeed oscillator is not operating, the prescaler remains available as the slow clock source. POR When this bit is cleared to 0, the prescaled main clock is used for the slow clock. Upon reset, this bit is cleared to 0. Power-On Reset. This bit is set to 1 by the hardware when a power-on condition is detected, allowing the CPU to determine whether a power-up has occurred. The CPU can clear this bit to 0 but cannot set it to 1. Any attempt by the CPU to set this bit is ignored. 12.7 SLOW CLOCK PRESCALER REGISTER (PRSSC) The Slow Clock Prescaler (PRSSC) register is a byte-wide read/write register that holds the clock divisor used to generate the slow clock from the main clock. The format of the register is shown below. 7 6 5 4 3 SCDIV 2 1 0 SCDIV 12.4 POWER-ON RESET 12.8 The Power-On Reset circuit generates a system reset signal upon power-up and holds the signal active for a period of time to allow the crystal oscillator to stabilize. The circuit detects a power turn-on condition, which presets the 14-bit timer to 3FFF hex. Once oscillation starts and the clock becomes active, the timer starts counting down. When the count reaches zero, the 14-bit timer stops counting and the internal reset signal is deactivated (unless the RESET pin is held low). The circuit sets a power-on reset flag bit upon detection of a power-on condition. The CPU can read this flag to determine whether a reset was caused by a power-up or by the RESET input. Note: Power-On Reset circuit cannot be used to detect a drop in the supply voltage. Slow Clock Divisor. If the clock divider is enabled (CRCTRL.SCLK=0), the main clock is divided by (SCDIV+1)*2 to produce the slow system clock. Upon reset, PRSSC register is set to FF hex. SLOW CLOCK PRESCALER 1 REGISTER (PRSSC1) The Slow Clock Prescaler 1 (PRSSC1) register is a bytewide read/write register that holds the clock divisor used to generate the two additional slow clocks from the high-speed clock. Upon reset, the register is set to 00. The format of the register is shown below. 7 SCDIV2 SCDIV1 4 3 SCDIV1 0 SCDIV1 12.5 EXTERNAL RESET An active-low reset input pin called RESET allows the device to be reset at any time. When the signal goes low, it generates an internal system reset signal that remains active until the RESET signal goes high again. Slow Clock Divisor 1. The main clock is divided by (SCDIV1+1) to obtain the first slow system clock. Slow Clock Divisor 2. The main clock is divided by (SCDIV2+1) to obtain the second slow system clock. 12.6 DUAL CLOCK AND RESET REGISTERS The Dual Clock and Reset module (CLK2RES) contains two registers: the Clock and Reset Control register (CRCTRL) and the Slow Clock Prescaler register (PRSSC). 12.6.1 Clock and Reset Control Register (CRCTRL) Clock and Reset Control Register (CRCTRL) is a byte-wide read/write register that contains the power-on reset flag and selects the type of slow clock. The register format is shown below. 7 6 5 4 Reserved 3 2 1 POR 0 SCLK SCLK Slow Clock Select. When this bit is set to 1, the 32.728 kHz oscillator is used for the slow clock. 41 www.national.com 13.0 Multi-Input Wake-Up The Multi-Input Wake-Up (MIWU16) module monitors its 16 input channels for a software-selectable trigger condition. Upon detection of a trigger condition, the module generates an interrupt request and if enabled, a wake-up request. A wake-up request can be used by the power management unit to exit the Halt, Idle, or Power Save mode and return to the active mode. An interrupt request generates an interrupt to the CPU (interrupt IRQ2), allowing interrupt processing in response to external events. The wake-up event only activates the clocks and CPU, but does not by itself initiate execution of any code. It is the interrupt request associated with the MIWU16 that gets the CPU to start executing code, by jumping to the proper interrupt routine. Therefore, setting up the MIWU16 interrupt handler is essential for any wake-up operation. There are four interrupt requests that can be routed to the ICU as shown in Figure 9. Each of the 16 MIWU channels can be programmed to activate one of these four interrupt requests. The input pins for the Multi-Input Wake-Up channels are named WUI0 through WUI15. WUI0 WUI1 WUI2 WUI3 WUI4 WUI5 WUI6 WUI7 WUI8 WUI9 WUI10 WUI11 WUI12 WUI13 WUI14 WUI15 PL0 PL1 PL2 PL3 PH0 PH1 PH2 PH3 TWM-T0OUT ACCESS.bus Canards MWCS RDX1 RDX2 Comparator 1 Comparator 2 13.1 WAKE-UP EDGE DETECTION REGISTER (WKEDG) The Wake-Up Edge Detection (WKEDG) register is a wordwide read/write register that controls the edge sensitivity of the Multi-Input Wake-Up pins. Register bits 0 through 15 control input pins WUI0 through WUI15, respectively. A bit cleared to 0 configures the corresponding input to trigger on a rising edge (a low-to-high transition). A bit set to 1 configures the corresponding input to trigger on a falling edge (a high-to-low transition). This register is cleared upon reset, which configures all 16 inputs to be triggered on rising edges. The register format is shown below. 15 WKED15-WKED0 0 13.2 WAKE-UP ENABLE REGISTER (WKENA) The Wake-Up Enable (WKENA) register is a word-wide read/ write register that enables or disables each of the Multi-Input Wake-Up channels. Register bits 0 through 15 control channels WUI0 through WUI15, respectively. A bit cleared to 0 disables the wake-up function and a bit set to 1 enables the function. This register is cleared upon reset, which disables all eight wake-up/interrupt channels. Each input can be configured to trigger on rising or falling edges, as determined by the setting in the WKEDG register. Each trigger event is latched into the WKPND register. If a trigger event is enabled by its respective bit in the WKENA register, an active wake-up/interrupt signal is generated. The software can determine which channel has generated the active signal by reading the WKPND register. The Multi-Input Wake-Up module is active at all times, including the Halt mode. All device clocks are stopped in this mode. Therefore, detecting an external trigger condition and the subsequent setting of the pending flag are not synchronous to the system clock. www.national.com 42 Peripheral Bus 15 .......... WKENA 0 WKICTL1-2 WUI0 0 4 EXINT3:0 to ICU Wake-Up Signal To Power Mgt WUI15 15 WKEDG Figure 9. The register format is shown below. 15 WKEN15-WKEN0 WKPND Multi-Input Wake-Up Module Block Diagram quests outputs to the ICU31L are to be activated for the corresponding channel. 00 01 10 11 enables MIWU Interrupt Request 0 enables MIWU Interrupt Request 1 enables MIWU Interrupt Request 2 enables MIWU Interrupt Request 3 0 13.3 WAKE-UP INTERRUPT CONTROL REGISTER 1 (WKCTL1) The Wake-Up Interrupt Control Register 1 (WKICTL1) register is a word-wide read/write register that selects the interrupt request signal for the associated channels WUI0 to WUI7. Upon reset, WKICTL1 is set to 0, which selects MIWU Interrupt Request 0 for all eight channels. The register format is shown below. 15 14 13 12 11 10 9 8 7 65 43 2 1 0 WKINTR WKINTR WKINTR WKINTR WKINTR WKINTR 7 6 5 4 3 2 WKINTR 1 WKINTR 0 13.5 WAKE-UP PENDING REGISTER (WKPND) WKINTR0:7 Wake-Up Interrupt Request Select. Each field selects which of the following four interrupt requests outputs to the ICU31L are to be activated for the corresponding channel. 00 01 10 11 enables MIWU Interrupt Request 0 enables MIWU Interrupt Request 1 enables MIWU Interrupt Request 2 enables MIWU Interrupt Request 3 The Wake-Up Pending (WKPND) register is a word-wide read/write register in which the Multi-Input Wake-Up module latches any detected trigger conditions. Register bits 0 through 15 serve as latches for channels WUI0 through WUI15, respectively. A bit cleared to 0 indicates that no trigger condition has occurred. A bit set to 1 indicates that a trigger condition has occurred and is pending on the corresponding channel. This register is cleared upon reset. The CPU can only write a 1 to any bit position in this register. If the CPU attempts to write a 0, it has no effect on that bit. To clear a bit in this register, the CPU must use the WKPCL register (described below). This implementation prevents a potential hardware-software conflict during a read-modifywrite operation on the WKPND register. The register format is shown below. 15 WKPD15-WKPD0 0 13.4 WAKE-UP INTERRUPT CONTROL REGISTER 1 (WKCTL2) 13.6 The Wake-Up Interrupt Control Register 2 (WKICTL2) register is a word-wide read/write register that selects the interrupt request signal for the associated channels WUI8 to WUI15. Upon reset, WKICTL2 is set to 0, which selects MIWU Interrupt Request 0 for all eight channels. The register format is shown below. 15 14 13 12 11 10 9 8 7 65 43 2 1 0 WKINTR WKINTR WKINTR WKINTR WKINTR WKINTR 15 14 13 12 11 10 WKINTR 9 WKINTR 8 WAKE-UP PENDING CLEAR REGISTER (WKPCL) The Wake-Up Pending Clear (WKPCL) register is a wordwide write-only register that lets the CPU clear bits in the WKPND register. Writing a 1 to a bit position in the WKPCL register clears the corresponding bit in the WKPND register. Writing a 0 leaves the corresponding bit in the WKPND register unchanged. Reading this register location returns unknown data. Therefore, do not use a read-modify-write sequence to set the individual bits. In other words, do not attempt to read the WKINTR8:5 Wake-Up Interrupt Request Select. Each field selects which of the following four interrupt re- 43 www.national.com register and do a logical OR with the register value. Instead, just write the mask directly to the register address. The register format is shown below. 15 WKCL15-WKCL0 0 13.7 PROGRAMMING PROCEDURES To set up and use the Multi-Input Wake-Up function, use the following procedure. Performing the steps in the order shown will prevent false triggering of a wake-up condition. This same procedure should be used following a reset because the wake-up inputs are left floating, resulting in unknown data on the input pins. 1. Clear the WKENA register to disable the wake-up channels. 2. If the input originates from an I/O port (the usual case), set the corresponding bit in the port direction register to configure the I/O pin to operate as an input. 3. Write the WKEDG register to select the desired type of edge sensitivity (clear to 0 for rising edge, set to 1 for falling edge). 4. Set all bits in the WKPCL register to clear any pending bits in the WKPND register. 5. Set up the WKICTL1 and WKICTL2 registers to define the interrupt request signal used for each channel. 6. Set the bits in the WKENA register corresponding to the wake-up channels to be activated. To change the edge sensitivity of a wake-up channel, use the following procedure. Performing the steps in the order shown will prevent false triggering of a wake-up/interrupt condition. 1. Clear the WKENA bit associated with the input to be reprogrammed. 2. Write the new value to the corresponding bit position in the WKEDG register to reprogram the edge sensitivity of the input. 3. Set the corresponding bit in the WKPCL register to clear the pending bit in the WKPND register. 4. Set the same WKENA bit to re-enable the wake-up function. www.national.com 44 14.0 Real-Time Timer and WATCHDOG The Timing and WATCHDOG Module (TWM) generates the clocks and interrupts used for timing periodic functions in the system, and also provides Watchdog protection against software errors. The module operates off the slow clock either generated by the external 32kHz oscillator or from the prescaled high speed system clock. The maximum operating clock frequency is 100kHz. The WATCHDOG is designed to detect program execution errors. Once WATCHDOG operation is initiated, the software must periodically write a specific value to a WATCHDOG register. If the software fails to do so, a WATCHDOG error is triggered, which resets the device. The TWM is flexible in allowing selection of a variety of clock ratios and clock sources for the WATCHDOG circuit. Once the software configures the TWM, it can lock the configuration for a higher level of protection against erroneous software action. Once locked, the TWM can be released only by a device reset. All counting activities of the module are based on the slow clock (SLCLK). A prescaler counter divides this clock to make a slower clock. The prescaler factor is defined by a 3bit field in the Timer and WATCHDOG Prescaler register, which selects either 1, 2, 4, 8, 16, or 32 and the divide-by factor. Thus, the prescaled clock period can be set to 1, 2, 4, 8, 16, or 32 times the slow clock period. The prescaled clock signal is called T0IN. 14.2 TIMER T0 OPERATION Timer T0 is a programmable 16-bit down counter that can be used as the time base for real-time operations such as a periodic audible tick. It can also be used to drive the WATCHDOG circuit. The timer starts counting from the value loaded into the TWMT0 register and counts down on each rising edge of T0IN. When the timer reaches zero, it is automatically reloaded from the TWMT0 register and continues counting down from that value. Thus, the frequency of the timer is: fSLCLK / [(TWMT0+1) * prescaler] When an external crystal oscillator is used as the SLCLK source or when the fast clock is divided accordingly, fSLCLK is 32.768 kHz. The value stored in TWMT0 can range from 0001 hex to FFFF hex. 14.1 TWM STRUCTURE Figure 10 is a block diagram showing the internal structure of the Timing and WATCHDOG module. There are two main sections: the Real-Time Timer (T0) section at the top and the WATCHDOG section on the bottom. Peripheral Bus REAL TIME TIMER (T0) CLKIN1 slow clock from dual clock and reset module 5-bit pre-scaler counter (TWCP) T0IN TWMT0 register Restart T0CSR Contrl. Reg. T0LINT (to ICU) 16-bit Timer (Timer0) Underflow T0OUT (to Multi-InputWake-Up) WATCHDOG Timer Underflow Restart WDSDM WATCHDOG Service Logic WDCNT WATCHDOG ERROR WDERR WATCHDOG Figure 10. Timing and WATCHDOG Module Block Diagram 45 www.national.com When the counter reaches zero, an internal timer signal called T0OUT is set to 1 for one T0IN clock cycle. This signal sets the TC bit in the TWMT0 Control and Status Register (T0CSR). It also generates an interrupt called RTI (IRQ14) if the interrupt is enabled by the T0CSR.T0INTE bit. If the software loads TWMT0 with a new value, the timer uses that value the next time that it reloads the 16-bit timer register (in other words, after reaching zero). The software can restart the timer at any time (on the very next edge of the T0IN clock) by setting the Restart (RST) bit in the T0CSR register. The T0CSR.RST bit is cleared automatically upon restart of the 16-bit timer. Note: If the user wishes to switch to power save or idle mode after setting T0CSR.RST, the user must wait for reset operation to complete before doing the switch. locking state of the TWCFG, TWCPR, TIMER0, T0CSR, and WDCNT registers. A register that is locked cannot be read or written. A write operation is ignored and a read operation returns unpredictable results. If the TWCFG register is itself locked, it remains locked until the device is reset. Any other locked registers also remain locked until the device is reset. This feature prevents a runaway program from tampering with the programmed WATCHDOG function. 14.3.2 Power Save Mode Operation 14.3 WATCHDOG OPERATION The WATCHDOG is an 8-bit down counter that operates on the rising edge of a specified clock source. Upon reset, the WATCHDOG is disabled; it does not count and no WATCHDOG signal is generated. A write to either the WATCHDOG Count (WDCNT) register or the WATCHDOG Service Data Match (WDSDM) register starts the counter. The WATCHDOG counter counts down from the value programmed in to the WDCNT register. Once started, only a reset can stop the WATCHDOG from operating. The WATCHDOG can be programmed to use either T0OUT or T0IN as its clock source (the output and input of Timer T0, respectively). The TWCFG.WDCT0I bit controls this clock selection. The software must periodically “service” the WATCHDOG. There are two ways to service the WATCHDOG, the choice depending on the programmed value of the WDSDME bit in the Timer and WATCHDOG Configuration (TWCFG) register. If TWCFG.WDSDME bit is cleared to 0, the WATCHDOG is serviced by writing a value to the WDCNT register. The value written to the register is reloaded into the WATCHDOG counter. The counter then continues counting down from that value. If TWCFG.WDSDME bit is set to 1, the WATCHDOG is serviced by writing the value 5C hex to the WATCHDOG Service Data Match (WDSDM) register. This reloads the WATCHDOG counter with the value previously programmed into the WDCNT register. The counter then continues counting down from that value. A WATCHDOG error signal is generated by any of the following events: — The WATCHDOG serviced too late. — The WATCHDOG serviced too often. — The WDSDM register is written with a value other than 5C hex when WDSDM type servicing is enabled (TWCFG.WDSDME=1). A WATCHDOG error condition resets the device. 14.3.1 Register Locking The Timer and WATCHDOG Module is active in both the Power Save and Idle modes. The clocks and counters continue to operate normally in these modes. The WDSDM register is accessible in the Power Save and Idle modes, but the other TWM registers are accessible only in the Active mode. Therefore, WATCHDOG servicing must be carried out using the WDSDM register in the Power Save or Idle mode. In the Halt mode, the entire device is frozen, including the Timer and WATCHDOG Module. Upon return to the Active mode, operation of the module resumes at the point at which it was stopped. Note: After a restart or WATCHDOG service through WDCNT, do not enter Power Save mode for a period equivalent to 5 slow clock cycles. 14.4 TWM REGISTERS The TWM registers controls the operation of the Timing and WATCHDOG Module. There are six such registers: — Timer and WATCHDOG Configuration Register (TWCFG) — Timer and WATCHDOG Clock Prescaler Register (TWCP) — TWM Timer 0 Register (TWMT0) — TWMT0 Control and Status Register (T0CSR) — WATCHDOG Count Register (WDCNT) — WATCHDOG Service Data Match Register (WDSDM) The WDSDM register is accessible in both Active and Power Save mode. The other TWM registers are accessible only in Active mode. 14.4.1 Timer and WATCHDOG Configuration Register (TWCFG) The TWCFG register is a byte-wide, read/write register that selects the WATCHDOG clock input and service method, and also allows the WATCHDOG registers to be selectively locked. Once a bit is set, that bit cannot be cleared until the device resets. Upon reset, the non-reserved bits of the register are all cleared to 0. The register format is shown below. 7 6 5 4 3 2 1 0 Reserved WDSDME WDCT0I LWDCNT LTWMT0 LTWCP LTWCFG LTWCFG The Timer and WATCHDOG Configuration (TWCFG) register is used to set the WATCHDOG configuration. It controls the WATCHDOG clock source (T0IN or T0OUT), the type of WATCHDOG servicing (using WDCNT or WDSDM), and the Lock TWCFG Register. When cleared to 0, access to the TWCFG register is allowed. When set to 1, the TWCFG register is locked. A locked register cannot be read or written; a read operation returns unpredictable values and a write operation is ignored. Locking the TWCFG register remains in effect until the device is reset. www.national.com 46 LTWCP LTWMT0 LWDCNT WDCT0I WDSDME Lock TWCP Register. When cleared to 0, access to the TWCP register is allowed. When set to 1, the TWCP register is locked. Lock TWMT0 Register. When cleared to 0, access to the TWMT0 and T0CSR registers are allowed. When set to 1, the TWMT0 and T0CSR registers are locked. Lock LDWCNT Register. When cleared to 0, access to the LDWCNT register is allowed. When set to 1, the LDWCNT register is locked. WATCHDOG Clock from T0IN. When cleared to 0, the T0OUT signal (the output of Timer T0) is used as the WATCHDOG clock. When set to 1, the T0IN signal (the prescaled slow clock) is used as the WATCHDOG clock. WATCHDOG Service Data Match Enable. When cleared to 0, WATCHDOG servicing is accomplished by writing a count value to the WDCNT register; write operations to the WATCHDOG Service Data Match (WDSDM) register are ignored. When set to 1, WATCHDOG servicing is accomplished by writing the value 5C hex to the WDSDM register. T0IN divided by (PRESET+1). The allowed values of PRESET are 0001 hex through FFFF hex. 14.4.4 TWMT0 Control and Status Register (T0CSR) The T0CSR register is a byte-wide, read/write register that controls Timer T0 and shows its current status. Upon reset, the non-reserved bits of the register are cleared to 0. The register format is shown below. 7 6 5 4 Reserved 3 2 T0INTE 1 TC 0 RST RST TC 14.4.2 Timer and WATCHDOG Clock Prescaler Register (TWCP) T0INTE The TWCP register is a byte-wide, read/write register that defines the prescaler value used for dividing the low frequency clock to generate the T0IN clock. Upon reset, the non-reserved bits of the register are cleared to 0. The register format is shown below. 7 6 5 4 Reserved 3 2 1 MDIV 0 Restart. When this bit is set to 1, it forces the timer to reload the value in the TWMT0 register on the next rising edge of the selected input clock. The RST bit is reset automatically by the hardware on the same rising edge of the selected input clock. Writing a 0 to this bit position has no effect. Upon reset, the non-reserved bits of the register are cleared to 0. Terminal Count. This bit is set to 1 by the hardware when the Timer T0 count reaches zero and is cleared to 0 when the software reads the T0CSR register. It is a read-only bit. Any data written to this bit position is ignored. Timer T0 Interrupt Enable. When this bit is set to 1, it enables an interrupt to the CPU each time the Timer T0 count reaches zero. When this bit is cleared to 0, Timer T0 interrupts are disabled. WATCHDOG Count Register (WDCNT) 14.4.5 MDIV Main Clock Divide. This 3-bit field defines the prescaler factor used for dividing the low speed device clock to create the T0IN clock. The allowed 3-bit values and the corresponding clock divisors and clock rates are listed below. MDIV Clock Divisor TOIN Frequency (fSCLK=32.768 kHz) 000 1 32.768 kHz 001 2 16.384 kHz 010 4 8.192 kHz 011 8 4.096 kHz 100 16 2.056 kHz 101 32 1.024 kHz other Reserved N/A TWM Timer 0 Register (TWMT0) The WDCNT register is a byte-wide, write-only register that holds the value that is loaded into the WATCHDOG counter each time the WATCHDOG is serviced. The WATCHDOG is started by the first write to this register. Each successive write to this register restarts the WATCHDOG count with the written value. Upon reset, this register is initialized to 0F hex. 14.4.6 WATCHDOG Service Data Match Register (WDSDM) 14.4.3 The WSDSM register is a byte-wide, write-only register used for servicing the WATCHDOG. When this type of servicing is enabled (TWCFG.WDSDME=1), the WATCHDOG is serviced by writing the value 5C hex to the WSDSM register. Each such servicing reloads the WATCHDOG counter with the value previously written to the WDCNT register. Writing any data other than 5C hex triggers a WATCHDOG error. Writing to the register more than once in one WATCHDOG clock cycle also triggers a WATCHDOG error signal. If this type of servicing is disabled (TWCFG.WDSDME=0), any write to the WSDSM register is ignored. The TWMT0 register is a word-wide, read/write register that defines the T0OUT interrupt rate. Upon reset, TWMT0 register is initialized to FFFF hex. The register format is shown below. 15 14 13 12 11 10 9 876 PRESET 5 4 3 2 1 0 PRESET Timer T0 Preset. Timer T0 is reloaded with this value on each underflow. Thus, the frequency of the Timer T0 interrupt is the frequency of 47 www.national.com 14.5 WATCHDOG PROGRAMMING PROCEDURE The highest level of protection against software errors is achieved by programming and then locking the WATCHDOG registers and using the WDSDM register for servicing. This is the procedure: 1. Write the desired values into the TWM Clock Prescaler register (TWCP) and the TWM Timer 0 register (TWMT0) to control the T0IN and T0OUT clock rates. The frequency of T0IN can be programmed to any of six frequencies ranging from 1/32*fSLCLK to fSLCLK . The frequency of T0OUT is equal to the frequency of T0IN divided by (1+PRESET), where PRESET is the value written to the TWMT0 register. 2. Configure the WATCHDOG clock to use either T0IN or T0OUT by setting or clearing the TWCFG.WDCT0I bit. 3. Write the initial value into the WDCNT register. This starts operation of the WATCHDOG and specifies the maximum allowed number of WATCHDOG clock cycles between service operations. 4. Lock the WATCHDOG registers and enable the WATCHDOG Service Data Match Enable function by setting bits 0, 1, 2, 3, and 5 in the TWCFG register. 5. Service the WATCHDOG by periodically writing the value 5C hex to the WDSDM register at an appropriate rate. Servicing must occur at least once per period programmed into the WDCNT register, but no more than once in a single WATCHDOG input clock cycle. www.national.com 48 15.0 Multi-Function Timer The Multi-Function Timer (MFT16) module contains two independent timer/counter units called MFT1 and MFT2, each containing a pair of 16-bit timer/counters. Each timer/counter unit offers a choice of clock sources for operation and can be configured to operate in any of the following modes: • Processor-Independent Pulse Width Modulation (PWM) mode, which generates pulses of a specified width and duty cycle, and which also provides a general-purpose timer/counter Dual Input Capture mode, which measures the elapsed time between occurrences of external events, and which also provides a general-purpose timer/counter Dual Independent Timer mode, which generates system timing signals or counts occurrences of external events Single Input Capture and Single Timer mode, which provides one external event counter and one system timer The two timer units, MFT1 and MFT2, are identical in operation and separately programmable. Each timer unit uses two I/O pins, called T1A and T1B (for Timer MFT1) or T2A and T2B (for Timer MFT2). The timer I/O pins are alternate functions of the Port F I/O pins. In the description of the timers, the lower-case letter “n” represents the timer number, either 1 or 2. For example, “TnA” means I/O pin T1A or T2A. • 15.1 TIMER STRUCTURE • • Figure 11 is a block diagram showing the internal structure of each timer. There are two main functional blocks: a Timer/ Counter and Action block and a Clock Source block. The Timer/Counter and Action block contains two separate timer/ counter units, called Timer/Counter I and Timer/Counter II (a total of four timer/counter unit in both MFT1 and MFT2). Clock Source Timer/Counter Reload/Capture A Action Clock Prescaler/Selector Timer/Counter 1 Reload/Capture B Timer/Counter 2 PWM/Capture/Counter Toggle/Capture/Interrupt TnA Interrupt A Interrupt B System Clock TnB External Event Figure 11. 15.1.1 Timer/Counter Block Mode Select + Control Multi-Function Timer Block Diagram Counter Clock Source Select There are two clock source selectors that allow the software to independently select the clock source for each of the two 16-bit counters from any one of the following sources: — — — — — no clock (which stops the counter) prescaled system clock external event count based on TnB pulse accumulate mode based on TnB slow clock (derived from the low-frequency oscillator or divided from the high-speed oscillator) The Timer/Counter block contains the following functional blocks: — two 16-bit counters, Timer/Counter I (TnCNT1) and Timer/Counter II (TnCNT2) — two 16-bit reload/capture registers, TnCRA and TnCRB — control logic necessary to configure the timer to operate in any of the four operating modes — interrupt control and I/O control logic In a power-saving mode that uses the low-frequency (32.768 kHz) clock as the system clock, the synchronization circuit requires that the slow clock operate at no more than onefourth the speed of the 32.768 kHz system clock. 15.1.2 Clock Source Block Prescaler The 5-bit clock prescaler allows the software to run the timer with a prescaled clock signal. The prescaler consists of a 5bit read/write prescaler register (TnPRSC) and a 5-bit down counter. The system clock is divided by the value contained in the prescaler register plus 1. Thus, the timer clock period can be set to any value from 1 to 32 divisions of the system clock period. The prescaler register and down counter are both cleared upon reset. The Clock Source block generates the signals used to clock the two timer/counter registers. The internal structure of the Clock Source block is shown in Figure 12. 49 www.national.com Prescaler Register TnPRSC No Clock Counter I Clock Select Reset System Clock 5-bit Prescaler Counter Prescaled Clock Pulse Accumulate External Event Counter I Clock Counter II Clock Select Counter II Clock TnB Synchr. Figure 12. Clock Source Block Diagram Pulse Accumulate Mode The counter can also be configured to count prescaler output clock pulses when the TnB is high and not count when TnB is low, as illustrated in Figure 13. The resulting count is an indicator of the cumulative time that TnB is high. This is called the “pulse accumulate” mode. In this mode, an AND gate generates a clock signal for the counter whenever a prescaler clock pulse is generated and TnB input is high. (The polarity of the TnB signal is programmable, so the counter can count when TnB is low rather than high.) The pulse accumulate mode is not available in the capture modes (modes 2 and 4) because the TnB pin is used as one of the two capture inputs. External Event Clock The TnB I/O pin can be configured to operate as an external event input clock for either of the two 16-bit counters. This input can be programmed to detect either rising or falling edges. The minimum pulse width of the external signal is one system clock cycle. This means that the maximum frequency at which the counter can run in this mode is one-half of the system clock frequency. This clock source is not available in the capture modes (modes 2 and 4) because the TnB pin is used as one of the two capture inputs. Prescaler Output TnB Counter Clock Figure 13. Slow Clock Pulse Accumulate Mode Operation clock to input clock ratio needed for the synchronization cannot be maintained. However, the External Event Clock and Pulse Accumulate Mode will still work, as long as the external event pulses are at least the size of the whole slow-clock period. Using the prescaled system clock will also work, but at a much slower rate than the original system clock. Some Power Save modes stops the system clock (the highfrequency and/or low-frequency clock) completely. If the system clock is stopped, the timer stops counting until the system clock resumes operation. In the Idle or Halt mode, the system clock stops completely, which stops the operation of the timers. In that case, the timers stop counting until the system clock resumes operation. The slow clock is generated by the Dual Clock and Reset (CLK2RES) module. The clock source is either the divided fast clock or the external 32.768 kHz clock crystal (if available and selected). The slow clock can be used as the clock source for the two 16-bit counters. Because the slow clock can be asynchronous to the system clock, a circuit is provided to synchronize the clock signal to the high-frequency system clock before it is used for clocking the counters. The synchronization circuit requires that the slow clock operate at no more than one-fourth the speed of the system clock. Limitations in Low-Power Modes The Power Save mode uses the low-frequency clock as the system clock. In this mode, the slow clock cannot be used as a clock source for the timers because both CLK and SLCLK are driven then at the same frequency, and the 2:1 systemwww.national.com 50 15.2 TIMER OPERATING MODES 15.2.1 Mode 1: Processor-Independent PWM Each timer/counter unit can be configured to operate in any of the following modes: — Processor-Independent Pulse Width Modulation (PWM) mode — Dual Input Capture mode — Dual Independent Timer mode — Single Input Capture and Single Timer mode Upon reset, the timers are disabled. To configure and start the timers, the software must write a set of values to the registers that control the timers. The registers are described in Section 15.5. Mode 1 is the Processor-Independent Pulse Width Modulation (PWM) mode, which generates pulses of a specified width and duty cycle, and which also provides a separate general-purpose timer/counter. Figure 14 is a block diagram of the Multi-Function Timer configured to operate in Mode 1. Timer/Counter I (TnCNT1) functions as the time base for the PWM timer. It counts down at the clock rate selected for the counter. When an underflow occurs, the timer register is reloaded alternately from the TnCRA and TnCRB register, and counting proceeds downward from the loaded value. Reload A = Time 1 TnCRA Underflow Timer I Clock Timer/Counter I TnCNT1 Underflow Reload B = Time 2 TnCRB TnAPND Timer Interrupt A TnA TnAEN Timer Interrupt B TnAIEN TnBIEN TnBPND Timer II Clock Timer/Counter II TnCNT2 TnDIEN TnDPND Timer Interrupt D Clock Selector Figure 14. Mode 1: Processor-Independent PWM Block Diagram TnB On the first underflow, the timer is loaded from TnCRA, then from TnCRB on the next underflow, then from TnCRA again on the next underflow, and so on. Every time the counter is stopped and restarted, it always obtains its first reload value from TnCRA. This is true whether the timer is restarted upon reset, after entering Mode 1 from another mode, or after stopping and restarting the clock with the Timer/Counter I clock selector. The timer can be configured to toggle the TnA output bit upon each underflow. This generates a clock signal on TnA with the width and duty cycle determined by the values stored in the TnCRA and TnCRB registers. This is a “processor-independent” PWM clock because once the timer is set up, no more action is required from the CPU to generate a continuous PWM signal. The timer can be configured to generate separate interrupts upon reload from TnCRA and TnCRB. The interrupts can be enabled or disabled under software control. The CPU can determine the cause of each interrupt by looking at the TnAPND and TnBPND flags, which are set by the hardware upon each occurrence of a timer reload. In Mode 1, Timer/Counter II (TnCNT2) can be used either as a simple system timer, an external event counter, or a pulse accumulate counter. The clock counts down using the clock selected with the Timer/Counter II clock selector. It generates an interrupt upon each underflow if the interrupt is enabled with the TnDIEN bit. 15.2.2 Mode 2: Dual Input Capture Mode 2 is the Dual Input Capture mode, which measures the elapsed time between occurrences of external events, and which also provides a separate general-purpose timer/ counter. Figure 15 is a block diagram of the Multi-Function Timer configured to operate in Mode 2. The time base of the capture timer depends on Timer/Counter I, which counts down using the clock selected with the Timer/Counter I clock selector. 51 www.national.com The TnA and TnB pins function as capture inputs. A transition received on the TnA pin transfers the timer contents to the TnCRA register. Similarly, a transition received on the TnB pin transfers the timer contents to the TnCRB register. Each input pin can be configured to sense either rising or falling edges. Timer Interrupt I TnAIEN TnAPND Capture A TnCRA Preset TnAEN Timer I Clock Timer/Counter I TnCNT1 Underflow Preset TnBEN Capture B TnCRB TnBPND TnCIEN TnCPND TnA Timer Interrupt I TnB TnBIEN Timer Interrupt I Timer II Clock Timer/Counter II TnCNT2 TnDPND Underflow Timer Interrupt II Figure 15. TnDIEN Mode 2: Dual Input Capture Block Diagram The TnA and TnB inputs can be configured to preset the counter to FFFF hex upon reception of a valid capture event. In this case, the current value of the counter is transferred to the corresponding capture register and then the counter is preset to FFFF hex. Using this approach allows the software to determine the on-time and off-time and period of an external signal with a minimum of CPU overhead. The values captured in the TnCRA register at different times reflect the elapsed time between transitions on the TnA pin. The same is true for the TnCRB register and the TnB pin. The input signal on TnA or TnB must have a pulse width equal to or greater than one system clock cycle. There are three separate interrupts associated with the capture timer, each with its own enable bit and pending flag. The three interrupt events are reception of a transition on TnA, reception of a transition on TnB, and underflow of the TnCNT1 counter. The enable bits for these events are TnAIEN, TnBIEN, and TnCIEN, respectively. In Mode 2, Timer/Counter II (TnCNT2) can be used as a simple system timer. The clock counts down using the clock selected with the Timer/Counter II clock selector. It generates an interrupt upon each underflow if the interrupt is enabled with the TnDIEN bit. Neither Timer/Counter I (TnCNT1) nor Timer/Counter II (TnCNT2) can be configured to operate as an external event counter or to operate in the pulse accumulate mode because the TnB input is used as a capture input. Attempting to select one of these configurations will cause one or both counters to stop. 15.2.3 Mode 3: Dual Independent Timer/Counter Mode 3 is the Dual Independent Timer mode, which generates system timing signals or counts occurrences of external events. Figure 16 is a block diagram of the Multi-Function Timer configured to operate in Mode 3. The timer is configured to operate as a dual independent system timer or dual external event counter. In addition, Timer/Counter I can generate a 50% duty cycle PWM signal on the TnA pin. The TnB pin can be used as an external event input or pulse accumulate input and can be used as the clock source for either Timer/Counter I or Timer/Counter II. Both counters can also be clocked by the prescaled system clock. www.national.com 52 Reload A TnCRA Underflow Timer I Clock Timer/Counter I TnCNT1 TnAPND Timer Interrupt I TnAIEN TnA TnAEN Reload B TnCRB Underflow Timer II Clock Clock Selector Timer/Counter II TnCNT2 Timer Interrupt II TnDIEN TnDPND TnB Figure 16. Mode 3: Dual Independent Timer/Counter Block Diagram ceeds down from the reloaded value. The TnA pin is toggled on each underflow if this function is enabled by the TnAEN bit. When the TnA pin is toggled from low to high, it sets the TnCPND interrupt pending flag and also generates an interrupt if the interrupt is enabled by the TnAIEN bit. A 50% duty cycle PWM signal can be generated on TnA without any further action from the CPU once the pulse train is initiated. Timer/Counter II (TnCNT1) counts down at the rate of the selected clock. The TnB pin functions as the capture input. A transition received on TnB transfers the timer contents to the TnCRB register. The input pin can be configured to sense either rising or falling edges. The TnB input can be configured to preset the counter to FFFF hex upon reception of a valid capture event. In this case, the current value of the counter is transferred to the capture register and then the counter is preset to FFFF hex. The values captured in the TnCRB register at different times reflect the elapsed time between transitions on the TnA pin. The input signal on TnB must have a pulse width equal to or greater than one system clock cycle. There are two separate interrupts associated with the capture timer, each with its own enable bit and pending flag. The two interrupt events are reception of a transition on TnB and underflow of the TnCNT2 counter. The enable bits for these events are TnBIEN and TnDIEN, respectively. Neither Timer/Counter I (TnCNT1) nor Timer/Counter II (TnCNT2) can be configured to operate as an external event counter or to operate in the pulse accumulate mode because the TnB input is used as a capture input. Attempting to select one of these configurations will cause one or both counters to stop. In this mode, Timer/Counter II must be enabled at all times. Timer/Counter I (TnCNT1) counts down at the rate of the selected clock. Upon underflow, it is reloaded from the TnCRA register and counting proceeds down from the reloaded value. In addition, the TnA pin is toggled on each underflow if this function is enabled by the TnAEN bit. The initial state of the TnA pin is software-programmable. When the TnA pin is toggled from low to high, it sets the TnCPND interrupt pending flag and also generates an interrupt if the interrupt is enabled by the TnAIEN bit. Because TnA toggles on every underflow, a 50% duty cycle PWM signal can be generated on TnA without any further action from the CPU once the pulse train is initiated. Timer/Counter II (TnCNT2) counts down at the rate of the selected clock. Upon underflow, it is reloaded from the TnCRB register and counting proceeds down from the reloaded value. In addition, each underflow sets the TnDPND interrupt pending flag and generates an interrupt if the interrupt is enabled by the TnDIEN bit. 15.2.4 Mode 4: Input Capture Plus Timer Mode 4 is the Single Input Capture and Single Timer mode, which provides one external event counter and one system timer. Figure 17 is a block diagram of the Multi-Function Timer configured to operate in Mode 4. This mode offers a combination of Mode 3 and Mode 2 functions. Timer/Counter I is used as a system timer as in Mode 3 and Timer/Counter II is used as a capture timer as in Mode 2, but with a single input rather than two inputs. Timer/Counter I (TnCNT1) operates the same as in Mode 3. It counts down at the rate of the selected clock. Upon underflow, it is reloaded from the TnCRA register and counting pro- 53 www.national.com Reload A TnCRA Underflow Timer I Clock Timer/Counter I TnCNT1 TnAPND Timer Interrupt I TnA TnATEN Timer Interrupt I TnAIEN TnBIEN TnBPND Capture B TnCRB Preset TnBEN TnDPND Timer II Clock Timer/Counter II TnCNT2 TnDIEN Figure 17. Mode 4: Input Capture Plus Timer Block Diagram TnB Timer Interrupt II 15.3 TIMER INTERRUPTS 15.4 TIMER I/O FUNCTIONS Each Multi-Function Timer unit has four interrupt sources, designated A, B, C, and D. Interrupt sources A, B, and C are mapped into a single system interrupt called Timer Interrupt I, while interrupt source D is mapped into a system interrupt called Timer Interrupt II. Each of the four interrupt sources has its own enable bit and pending flag. The enable flags are named TnAIEN, TnBIEN, TnCIEN, and TnDIEN. The pending flags are named TnAPND, TnBPND, TnCPND, and TnDPND. For Multi-Function Timer unit MFT1, Timer Interrupts I and II are system interrupts T1A and T1B (IRQ13 and IRQ12), respectively. For Multi-Function Timer unit MFT2, Timer Interrupts I and II are system interrupts T2A and T2B (IRQ11 and IRQ10), respectively. Table 15 shows the events that trigger interrupts A, B, C, and D in each of the four operating modes. Note that some interrupt sources are not used in some operating modes, as indicated by the notation “N/A” (Not Applicable) in the table. Each Multi-Function Timer unit uses two I/O pins, called T1A and T1B (for Timer MFT1) or T2A and T2B (for Timer MFT2). The function of each pin depends on the timer operating mode and the TnAEN and TnBEN enable bits. Table 16 shows the functions of the pins in each operating mode, and for each combination of enable bit settings. When pin TnA is configured to operate as a PWM output (TnAEN = 1), the state of the pin is toggled on each underflow of the TnCNT1 counter. In this case, the initial value on the pin is determined by the TnAOUT bit. For example, to start with TnA high, the software should set the TnAOUT bit to 1 prior to enabling the timer clock. This option is available only when the timer is configured to operate in Mode 1, 3, or 4 (in other words, when TnCRA is not used in Capture mode). L www.national.com 54 Table 15 Interrupt pending flag Mode 1 PWM + Counter TnCNT1 reload from TnCRA TnCNT1 reload from TnCRB N/A TnCNT2 underflow Timer Interrupts Overview Mode 2 Mode 3 Dual Counter TnCNT1 reload from TnCRA N/A N/A TnCNT2 reload from TnCRB Mode 4 Single Capture + counter TnCNT1 reload from TnCRA Input Capture on TnB transition N/A TnCNT2 underflow Sys. Int. Dual Input Capture + counter Input capture on TnA transition Input Capture on TnB transition TnCNT1 underflow TnCNT2 underflow TnAPND Timer Int. I (TnA Int.) TnBPND TnCPND TnDPND Timer Int. II (TnB Int.) Table 16 Mode 1 I/O TnAEN TnBEN TnAEN=0 TnBEN=X TnAEN=1 TnBEN=X TnB TnAEN=X TnBEN=0 TnAEN=X TnBEN=1 PWM + Counter No Output Timer I/O Functions Mode 2 Mode 3 Dual Counter No Output toggle Toggle Output on underflow of TnCNT1 Ext. Event or Pulse Accumulate Input Ext. Event or Pulse Accumulate Input Mode 4 Single Capture + counter No Output toggle Toggle Output on underflow of TnCNT1 Capture TnCNT2 into TnCRB Capture TnCNT2 into TnCRB and preset TnCNT2 Dual Input Capture + counter Capture TnCNT1 into TnCRA TnA Toggle Output on Capture TnCNT1 into underflow of TnCNT1 TnCRA and preset TnCNT1 Ext. Event or Pulse Accumulate Input Ext. Event or Pulse Accumulate Input Capture TnCNT1 into TnCRB Capture TnCNT1 into TnCRB and preset TnCNT1 55 www.national.com 15.5 TIMER REGISTERS The following CPU-accessible registers are used to control the Multi-Function Timers: — — — — — — — — — Clock Prescaler Register (TnPRSC) Clock Unit Control Register (TnCKC) Timer/Counter I Register (TnCNT1) Timer/Counter II Register (TnCNT2) Reload/Capture A Register (TnCRA) Reload/Capture B Register (TnCRB) Timer Mode Control Register (TnCTRL) Timer Interrupt Control Register (TnICTL) Timer Interrupt Clear Register (TnICLR) Clock Prescaler Register (TnPRSC) * Operation of the slow clock is determined by the CRCTRL.SCLK control bit, as described in Section 12.6.1. 15.5.3 Timer/Counter I Register (TnCNT1) The Timer/Counter I (TnCNT1) register is a word-wide, read/ write register that holds the current count value for Timer/ Counter I. The register contents are not affected by a reset and are unknown upon power-up. 15.5.4 Timer/Counter II Register (TnCNT2) 15.5.1 The Timer/Counter II (TnCNT2) register is a word-wide, read/ write register that holds the current count value for Timer/ Counter II. The register contents are not affected by a reset and are unknown upon power-up. 15.5.5 Reload/Capture A Register (TnCRA) The Clock Prescaler (TnPRSC) register is a byte-wide, read/ write register that holds the current value of the 5-bit clock prescaler (CLKPS). This register is cleared upon reset. The register format is shown below. 7 6 5 Reserved 4 3 2 CLKPS 1 0 The Reload/Capture A (TnCRA) register is a word-wide, read/write register that holds the reload or capture value for Timer/Counter I. The register contents are not affected by a reset and are unknown upon power-up. 15.5.6 Reload/Capture B Register (TnCRB) CLKPS Clock Prescaler. When the timer is configured to use the prescaled clock, the system clock is divided by CLKPS+1 to produce the timer clock. Thus, the system clock divide-by factor can range from 1 to 32. Clock Unit Control Register (TnCKC) The Reload/Capture B (TnCRB) register is a word-wide, read/write register that holds the reload or capture value for Timer/Counter II. The register contents are not affected by a reset and are unknown upon power-up. 15.5.7 Timer Mode Control Register (TnCTRL) 15.5.2 The Clock Unit Control (TnCKC) register is a byte-wide, read/ write register that selects the clock source for each timer/ counter. Selecting the clock source also starts the counter. This register is cleared upon reset, which disables the timer/ counters. The register format is shown below. 7 6 Reserved C1CSEL 5 4 C2CSEL 3 2 1 C1CSEL 0 The Timer Mode Control (TnCTRL) register is a byte-wide, read/write register that sets the operating mode of the timer/ counter and the TnA and TnB pins. This register is cleared upon reset. The register format is shown below. 7 6 5 TnBEN 4 TnAEN 3 TnBEDG 2 TnAEDG 1 MDSEL 0 Reserved TnAOUT MDSEL Mode Select. This 2-bit field sets the operating mode of the timer/counter as follows: 00 = Mode 1: PWM plus system timer 01 = Mode 2: Dual Input Capture plus system timer 10 = Mode 3: Dual Timer/Counter 11 = Mode 4: Single Input Capture and Single Timer TnA Edge Polarity. When cleared (0), input pin TnA is sensitive to falling edges (high to low transitions). When set (1), input pin TnA is sensitive to rising edges (low to high transitions). TnB Edge Polarity. When cleared (0), input pin TnB is sensitive to falling edges (high to low transitions). When set (1), input pin TnB is sensitive to rising edges (low to high transitions). In pulse accumulate mode, when this bit is set (1), the counter is enabled only when TnB is high; when this bit is cleared (0), the counter is enabled only when TnB is low. TnA Enable. When set (1), the TnA pin is enabled to operate as a preset input or as a PWM output, depending on the timer operating mode. In Mode 2 (Dual Input Capture), a transition on the TnA pin presets the TnCNT1 counter to FFFF hex. In the other modes, TnA functions as a PWM output. When this bit is www.national.com Counter I Clock Select. This 3-bit field defines the clock mode for Timer/Counter I as follows: 000 = no clock (timer/counter I stopped) 001 = prescaled system clock 010 = external event on TnB (modes 1 and 3 only) 011 = pulse accumulate mode based on TnB (modes 1 and 3 only) 100 = slow clock * other values = undefined Counter II Clock Select. This 3-bit field defines the clock mode for Timer/Counter II as follows: 000 = no clock (Timer/Counter II stopped modes 1, 2, and 3 only) 001 = prescaled system clock 010 = external event on TnB (modes 1 and 3 only) 011 = pulse accumulate mode based on TnB (modes 1 and 3 only) 100 = slow clock * other values = undefined TnAEDG TnBEDG C2CSEL TnAEN 56 TnBEN TnAOUT cleared (0), operation of the pin for the timer/ counter is disabled. TnB Enable. When set (1), the TnB pin in enabled to operate in Mode 2 (Dual Input Capture) or Mode 4 (Single Input Capture and Single Timer). A transition on the TnB pin presets the corresponding timer/counter to FFFF hex (TnCNT1 in Mode 2 or TnCNT2 in Mode 4). When this bit is cleared (0), operation of the pin for the timer/counter is disabled. This bit setting has no effect in Mode 1 or Mode 3. TnA Output Data. This is a status bit that indicates the current state of the TnA pin when the pin is used as a PWM output. When set (1), the TnA pin is high; when cleared (0), the TnA pin is low. The hardware sets and clears this bit, but the software can also read or write this bit at any time and thus control the state of the output pin. In case of conflict, a software write has precedence over a hardware update. This bit setting has no effect when TnA is used as an input. Timer Interrupt Control Register (TnICTL) TnCIEN TnDIEN 15.5.9 Timer Interrupt C Enable. See the description of TnAIEN. Timer Interrupt D Enable. See the description of TnAIEN. Timer Interrupt Clear Register (TnICLR) The Timer Interrupt Clear (TnICLR) register is a byte-wide, write-only register that allows the software to clear the TnAPND, TnBPND, TnCPND, and TnDPND bits in the Timer Interrupt Control (TnICTRL) register. The register format is shown below. 7654 Reserved TnACLR 3 TnDCLR 2 TnCCLR 1 TnBCLR 0 TnACLR TnBCLR TnCCLR TnDCLR 15.5.8 The Timer Interrupt Control (TnICTL) register is a byte-wide, read/write register that contains the interrupt enable bits and interrupt pending bits for the four timer interrupt sources, designated A, B, C, and D. The condition that causes each type of interrupt depends on the operating mode, as shown in Table 15. This register is cleared upon reset. The register format is shown below. 7 TnDIEN 6 TnCIEN 5 TnBIEN 4 TnAIEN 3 2 1 0 TnAPND TnDPND TnCPND TnBPND Timer Pending A Clear. When written with a 1, the Timer Interrupt Source A Pending bit (TnAPND) is cleared in the Timer Interrupt Control register (TnICTL). Writing a 0 to the TnACLR bit has no effect. Timer Pending B Clear. See the description of TnACLR. Timer Pending C Clear. See the description of TnACLR. Timer Pending D Clear. See the description of TnACLR. TnAPND TnBPND TnCPND TnDPND TnAIEN TnBIEN Timer Interrupt Source A Pending. When this bit is set (1), it indicates that timer interrupt condition “A” has occurred. When this bit is cleared (0), it indicates that the interrupt condition has not occurred. For an explanation of interrupt conditions A, B, C, and D, see Table 15 This bit can be set by the hardware or by the software. To clear this bit, the software must use the Timer Interrupt Clear Register (TnICLR). Any attempt by the software to directly write a 0 to this bit is ignored. Timer Interrupt Source B Pending. See the description of TnAPND. Timer Interrupt Source C Pending. See the description of TnAPND. Timer Interrupt Source D Pending. See the description of TnAPND. Timer Interrupt A Enable. When set (1), this bit enables an interrupt on each occurrence of interrupt condition “A.” When cleared (0), an occurrence of interrupt condition “A” does not generate an interrupt to the CPU, but still sets the associated pending flag (TnAPND). For an explanation of interrupt conditions A, B, C, and D, see Table 15. Timer Interrupt B Enable. See the description of TnAIEN. 57 www.national.com 16.0 Versatile-Timer-Unit (VTU) The Versatile Timer Unit (VTU) contains four fully independent 16-bit timer subsystems. Each timer subsystem can operate either as dual 8-bit PWM timers, as a single 16-bit PWM timer, or as a 16-bit counter with 2 input capture channels. These timer subsystems offers an 8-bit clock prescaler to accommodate a wide range of system frequencies. The Versatile Timer Unit offers the following features: • The Versatile Timer Unit (VTU) can be configured to provide: — Eight fully independent 8-bit PWM channels — Four fully independent 16-bit PWM channels — Eight 16-bit input capture channels The VTU consists of four timer subsystems, each of which contains: — a 16-bit counter — two 16-bit capture / compare registers — an 8-bit fully programmable clock prescaler Each of the four timer subsystems can operate in the following modes: — low power mode, i.e. all clocks are stopped — dual 8-bit PWM mode — 16-bit PWM mode — dual 16-bit input capture mode • The Versatile-Timer-Unit controls a total of eight I/O pins, each of which can function as either: — PWM output with programmable output polarity — Capture input with programmable event detection and timer reset A flexible interrupt scheme with — four separate system level interrupt requests — a total of 16 interrupt sources each with a separate interrupt pending flag and interrupt enable bit • 16.1 VTU FUNCTIONAL DESCRIPTION • • The Versatile-Timer-Unit (VTU) is comprised of four timer subsystems. Each timer subsystem contains an 8-bit clock prescaler, a 16-bit up-counter and two 16-bit registers. Each timer subsystem controls two I/O pins which either function as PWM outputs or capture inputs depending on the mode of operation. There are four system level interrupt requests, one for each timer subsystem. Each system level interrupt request is controlled by four interrupt pending flags with associated enable/disable bits. All four timer subsystems are fully independent and each may operate as a dual 8-bit PWM timer, a 16-bit PWM timer or as a dual 16-bit capture timer. Figure 18 illustrates the main elements of the Versatile-TimerUnit (VTU). 0 15 MODE 15 0 15 0 15 0 IO1CTL 15 INTCTL 0 IO2CTL INTPND Timer Subsystem 1 7 0 7 Timer Subsystem 2 0 7 Timer Subsystem 3 0 7 Timer Subsystem 4 0 C1PRSC == Prescaler Counter 15 0 15 C2PRSC == Prescaler Counter 0 15 C3PRSC == Prescaler Counter 0 15 C4PRSC == Prescaler Counter 0 COUNT1 compare - capture COUNT2 compare - capture COUNT3 compare - capture COUNT4 compare - capture PERCAP1 compare - capture PERCAP2 compare - capture PERCAP3 compare - capture PERCAP4 compare - capture DTYCAP1 DTYCAP2 DTYCAP3 DTYCAP4 I/O control I/O control I/O control I/O control I/O control I/O control I/O control I/O control TIO1 TIO2 TIO3 TIO4 TIO5 TIO6 TIO7 TIO8 Figure 18. VTU Block Diagram www.national.com 58 16.1.1 Dual 8-bit PWM Mode Each timer subsystem may be configured to generate two fully independent PWM waveforms on the respective TIOx pins. In this mode, the counter COUNTx is split and operates as two independent 8-bit counters. Each counter increments at the rate determined by the clock prescaler. Each of the two 8-bit counters may be started and stopped separately via the associated TxRUN bits. Once either of the two 8-bit timers is running the clock prescaler starts counting. Once the clock prescaler counter value matches the value of the associated CxPRSC register field, COUNTx is incremented. The period of the PWM output waveform is determined by the value of the PERCAPx register. The TIOx output starts at the default value as pro-grammed via the IOxCTL.PxPOL bit. Once the counter value reaches the value of the period register PERCAPx, the counter is reset to 0016 upon the next counter increment. Upon the following increment from 0016 to 0116, the TIOx output will change to the opposite of the default value. The duty cycle of the PWM output waveform is controlled by the DTYCAPx register value. Once the counter value reaches the value of the duty cycle register DTYCAPx, the PWM output TIOx changes back to its default value upon the next counter increment. Figure 19 illustrates this concept. COUNTx PERCAPx 09 08 07 06 05 DTYCAPx 03 02 01 00 TxRUN=1 00 01 02 04 03 04 05 06 07 08 0A 09 0A TIOx (PxPOL=0) TIOx (PxPOL=1) Figure 19. The period time is determined by the following formula: PWMperiod = (PERCAPx + 1) * (CxPRSC + 1) * TCLK The duty cycle in percent is calculated as follows: DutyCycle[%] = (DTYCAPx / (PERCAPx+1)) *100 VTU PWM generation register while either of the two PWM channels is enabled, the new value will not take effect until the counter value matches the previous period value or the timer is stopped. Reading the PERCAPx or DTYCAPx register will always return the most recent value written to it. The counter registers can be written if both 8-bit counters are stopped. This allows the user to preset the counters before starting and therefore generate PWM output waveforms with a phase shift relative to one another. If the counter is written with a value other then 0016 it will start incrementing from that value while TIOx remains at its default value until the first 0016 to 0116 transition of the counter value occurs. If the counter is preset to values which are smaller or equal then the value held in the period register (PERCAPx) the counter will count up until a match between the counter value and the PERCAPx register value occurs. The counter will then be reset to 0016 and continue counting up. Alternatively the counter may be written with a value which is greater then the If the duty cycle register (DTYCAPx) holds a value which is greater then the value held in the period register (PERCAPx) the TIOx output will remain at the opposite of its default value which corresponds to a duty cycle of 100%. If the duty cycle register (DTYCAPx) register holds a value of 0016, the TIOx output will remain at the default value which corresponds to a duty cycle of 0%. In that case the value contained in the PERCAPx register is irrelevant. This scheme allows the duty cycle to be programmed in a range from 0% to 100%. In order to allow fully synchronized updates of the period and duty cycle compare values, the PERCAPx and DTYCAPx registers are double buffered when operating in PWM mode. Therefore if the user writes to either the period or duty cycle 59 www.national.com value held in the period register. In that case the counter will count up to FF16 and then roll over to 0016. In any case the TIOx pin always changes its state at the 0016 to 0116 transition of the counter. The user software may only write to the COUNTx register if both TxRUN bits of a timer subsystem are cleared. Any writes to the counter register while either timer is running will be ignored. The two I/O pins associated with a timer subsystem function as independent PWM outputs in the dual 8-bit PWM mode. If a PWM timer is stopped via its associated MODE.TxRUN bit the following actions result: — The associated TIOx pin will return to its default value as defined by the IOxCTL.PxPOL bit. — The counter will stop and will retain its last value. — Any pending updates of the PERCAPx and DTYCAPx register will be completed. — The prescaler counter will be stopped and reset if both MODE.TxRUN bits are cleared. Figure 20 illustrates the configuration of a timer subsystem while operating in dual 8-bit PWM mode. The numbering in Figure 20 refers to timer subsystem 1 but equally applies to the other three timer subsystems. 7 0 The two TIOx outputs associated with a timer subsystem can be used to produce either two identical PWM waveforms or two PWM waveforms of opposite polarities. This can be accomplished by setting the two PxPOL bits of the respective timer subsystem to either identical or opposite values. Figure 21 illustrates the configuration of a timer subsystem while operating in 16-bit PWM mode. The numbering in Figure 21 refers to timer subsystem 1 but equally applies to the other three timer subsystems. 7 0 C1PRSC == Prescaler Counter T1RUN 15 TMOD1=10 0 [15:0] Restart COUNT1[15:0] compare PERCAP1[15:0] compare DTYCAP1[15:0] S R Q S R Q C1PRSC == Prescaler Counter T2RUN 15 8 [15:8] Res 7 TMOD1=01 P2POL TIO2 P1POL TIO1 T1RUN 0 [7:0] Res Figure 21. 16.1.3 VTU 16-bit PWM Mode COUNT1[15:8] compare COUNT1[7:0] compare Dual 16-Bit Capture Mode PERCAP1[15:8] compare PERCAP1[7:0] compare DTYCAP1[15:8] DTYCAP1[7:0] In addition to the two PWM modes, each timer subsystem may be configured to operate in an input capture mode which provides two 16-bit capture channels. The input capture mode can be used to precisely measure the period and duty cycle of external signals. In capture mode the counter COUNTx operates as a 16-bit up-counter while the two TIOx pins associated with a timer subsystem operate as capture inputs. A capture event on the TIOx pins causes the contents of the counter register (COUNTx) to be copied to the PERCAPx or DTYCAPx registers respectively. Starting the counter is identical to the 16-bit PWM mode, i.e. setting the lower of the two MODE.TxRUN bits will start the counter and the clock prescaler. In addition, the capture event inputs are enabled once the MODE.TxRUN bit is set. The TIOx capture inputs can be independently configured to detect a capture event on either a positive transition, a negative transition or both a positive and a negative transition. In addition, any capture event may be used to reset the counter COUNTx and the clock prescaler counter. This avoids the need for the user software to keep track of timer overflow conditions and greatly simplifies the direct frequency and duty cycle measurement of an external signal. Figure 22 illustrates the configuration of a timer subsystem while operating in capture mode. The numbering in Figure 22 S R Q S R Q P2POL TIO2 P1POL TIO1 Figure 20. VTU Dual 8-bit PWM Mode 16.1.2 16-Bit PWM Mode Each of the four timer subsystems may be independently configured to provide a single 16-bit PWM channel. In this case the lower and upper bytes of the counter are concatenated to form a single 16-bit counter. Operation in 16-bit PWM mode is conceptually identical to the dual 8-bit PWM operation as outlined under Dual 8-bit PWM Mode on page 59. The 16-bit timer may be started or stopped with the lower MODE.TxRUN bit, i.e. T1RUN for timer subsystem 1. www.national.com 60 refers to timer subsystem 1 but equally applies to the other three timer subsystems. 7 0 ed with them. All interrupt pending flags are denoted IxAPD through IxDPD where “x” relates to the specific timer subsystem. There is one system level interrupt request for each of the four timer subsystems. Figure 23 illustrates the interrupt structure of the versatile timer module. C1PRSC == Prescaler Counter T1RUN 15 Restart TMOD1=11 I1AEN 0 [15:0] I1BEN I1CEN I1DEN I1APD I1BPD I1CPD System Interrupt Request 1 COUNT1[15:0] capture PERCAP1[15:0] capture DTYCAP1[15:0] cap rst 2 0 cap rst 2 I1DPD 0 C1EDG TIO1 C2EDG TIO2 I4AEN I4BEN Figure 22. 16.1.4 VTU Dual 16-bit Capture Mode I4APD I4BPD I4CPD I4DPD I4CEN I4DEN System Interrupt Request 4 Low Power Mode In case a timer subsystem is not used, the user can place it in a low-power-mode. All clocks to a timer subsystem are stopped and the counter and prescaler contents are frozen once low-power-mode is entered. The user may continue to write to the MODE, INTCTL, IOxCTL and CLKxPS registers. Write operations to the INTPND register are allowed; but if a timer subsystem is in low power mode, its associated interrupt pending bits cannot be cleared. The user cannot write to the COUNTx, PERCAPx and DTYCAPx registers of a timer subsystem while it is in low-power-mode. All registers can be read at any time. 16.1.5 Interrupts Figure 23. VTU Interrupt Request Structure The Versatile-Timer-Unit (VTU) has a total of 16 interrupt sources, four for each of the four timer subsystems. All interrupt sources have a pending flag and an enable bit associat- Each of the timer pending flags - IxAPD through IxDPD - is set by a specific hardware event depending on the mode of operation, i.e., PWM or Capture mode. Table 17 outlines the specific hardware events relative to the operation mode which cause an interrupt pending flag to be set. Table 17 Pending Flag IxAPD IxBPD IxCPD IxDPD 16.1.6 Dual 8-bit PWM Mode Low Byte Duty Cycle match Low Byte Period match High Byte Duty Cycle match High Byte Period match ISE Mode operation VTU Interrupt Sources 16-bit PWM Mode Duty Cycle match Period match N/A N/A Capture Mode Capture to DTYCAPx Capture to PERCAPx Counter Overflow N/A 16.2 VTU REGISTERS The VTU supports breakpoint operation of the In-SystemEmulator (ISE). If FREEZE is asserted, all timer counter clocks will be inhibited and the current value of the timer registers will be frozen; in capture mode, all further capture events are disabled. Once FREEZE becomes inactive, counting will resume from the previous value and the capture input events are re-enabled. The Versatile-Timer-Unit contains a total of 19 user accessible registers. All registers are word-wide and are initialized to a known value upon reset. All software accesses to the VTU registers must be word accesses. 61 www.national.com 16.2.1 Mode Control Register (MODE) The Mode Control (MODE) registries a word-wide read/write register which controls the mode selection of all four timer subsystems. The register is cleared (000016) upon reset. 15 14 13 T8RUN 5 T4RUN 12 T7RUN 4 T3RUN 11 10 9 T6RUN 1 T2RUN 8 T5RUN 0 T1RUN TMOD4 7 6 TMOD3 3 2 value of this three bit field has no effect while operating in PWM mode. CxEDG 000 001 010 011 100 101 110 111 PxPOL Capture rising edge falling edge rising edge falling edge both edges both edges both edges both edges Counter Reset No No Yes Yes No rising edge falling edge both edges TMOD2 TMOD1 TxRUN TMODx Timer start/stop. If set (1), the associated counter and clock prescaler is started depending on the mode of operation. Once set, the clock to the clock prescaler and the counter are enabled and the counter will increment each time the clock prescaler counter value matches the value defined in the associated clock prescaler field (CxPRSC). Timer System Operating Mode. This 2-bit wide field enables or disables the Timer Subsystem and defines it’s operating mode. 00: Low-Power-Mode enabled. All clocks to the counter subsystem are stopped. The counter is stopped regardless of the value of the TxRUN bits. Read operations to the Timer Subsystem will return the last value; the user shall not perform any write operations to the Timer Subsystem while it is disabled since those will be ignored. Dual 8-bit PWM mode enabled. Each 8bit counter may individually be started or stopped via its associated TxRUN bit. The TIOx pins will function as PWM outputs. 16-bit PWM mode enabled. The two 8bit counters are concatenated to form a single 16-bit counter. The counter may be started or stopped with the lower of the two TxRUN bits, i.e. T1RUN, T3RUN, T5RUN and T7RUN. The TIOx pins will function as PWM outputs. Capture Mode enabled. Both 8-bit counters are concatenated and operate as a single 16-bit counter. The counter may be started or stopped with the lower of the two TxRUN bits, i.e., T1RUN, T3RUN, T5RUN and T7RUN. The TIOx pins will function as capture inputs. PWM Polarity. While operating in PWM mode the bit defines the output polarity of the corresponding PWM output (TIOx). 0= The PWM output is set (1) upon the 0016 to 0116 transition of the counter and will be reset (0) once the counter value matches the duty cycle value. The PWM output is reset (0) upon the 0016 to 0116 transition of the counter and will be set (1) once the counter value matches the duty cycle value. 1= 01: Once a counter is stopped, the output will assume the value of PxPOL, i.e., its initial value. The PxPOL bit has no effect while operating in capture mode. 16.2.3 I/O Control Register 2 (IO2CTL) 10: The I/O Control Register 2 (IO2CTL) is a word-wide read/ write register. The register controls the functionality of the I/O pins TIO5 through TIO8 depending on the selected mode of operation. The register is cleared (0000) upon reset. 15 14 12 11 10 8 7 6 4 3 2 0 P8POL C8EDG P7POL C7EDG P6POL C6EDG P5POL C5EDG The functionality of the bit fields of the IO2CTL register is identical to the ones described in the IO1CTL register section. 16.2.4 Interrupt Control Register (INTCTL) 11: 16.2.2 I/O Control Register 1 (IO1CTL) The Interrupt Control (INTCTL) register is a word-wide read/ write register. It contains the interrupt enable bits for all 16 interrupt sources of the Versatile-Timer-Unit. Each interrupt enable bit corresponds to an interrupt pending flag located in the Interrupt Pending Register (INTPND). All INTCTL register bits are solely under software control. The register is cleared (000016) upon reset.. 15 14 13 12 11 10 9 8 I4DEN I4CEN I4BEN I4AEN I3DEN I3CEN I3BEN I3AEN The I/O Control Register 1 (IO1CTL) is a word-wide read/ write register. The register controls the functionality of the I/O pins TIO1 through TIO4 depending on the selected mode of operation. The register is cleared (000016) upon reset. 15 14 12 11 10 8 7 6 4 3 2 0 P4POL C4EDG P3POL C3EDG P2POL C2EDG P1POL C1EDG 7 6 5 4 3 2 1 0 I2DEN I2CEN I2BEN I2AEN I1DEN I1CEN I1BEN I1AEN IxAEN CxEDG Capture Edge Control. Defines the polarity of a capture event and the reset of the counter. The Timer x interrupt A enable. Enable/Disable an interrupt request based on the corresponding IxAPD flag being set. The associated IxAPD www.national.com 62 flag will be updated regardless of the value of the IxAEN bit. 0 1 IxBEN Enable system interrupt request for the IxAPD pending flag Disable system interrupt request for the IxAPD pending flag IxDPD IxCPD Timer x interrupt B enable. Enable/Disable an interrupt request based on the corresponding IxBPD flag being set. The associated IxBPD flag will be updated regardless of the value of the IxBEN bit. 0 1 Enable system interrupt request for the IxBPD pending flag Disable system interrupt request for the IxBPD pending flag lists the hardware condition which causes this bit to be set. Timer x interrupt C pending. If set (1), indicates that an interrupt condition for the related timer subsystem has occurred. Table 17 on page 61 lists the hardware condition which causes this bit to be set. Timer x interrupt D pending. If set (1), indicates that an interrupt condition for the related timer subsystem has occurred. Table 17 on page 61 lists the hardware condition which causes this bit to be set. Clock Prescaler Register 1 (CLK1PS) 16.2.6 IxCEN Timer x interrupt C enable. Enable/Disable an interrupt request based on the corresponding IxCPD flag being set. The associated IxCPD flag will be updated regardless of the value of the IxCEN bit. 0 1 Enable system interrupt request for the IxCPD pending flag Disable system interrupt request for the IxCPD pending flag CLK1PS is a word-wide read/write register. The register is split into two 8-bit wide field called C1PRSC and C2PRSC. Each field holds the 8-bit clock prescaler compare value for timer subsystems 1 and 2 respectively. The register is cleared upon reset. 15 C2PRSC C1PRSC 87 C1PRSC 0 IxDEN Timer x interrupt D enable. Enable/Disable an interrupt request based on the corresponding IxDPD flag being set. The associated IxDPD flag will be updated regardless of the value of the IxDEN bit. 0 1 Enable system interrupt request for the IxDPD pending flag Disable system interrupt request for the IxDPD pending flag C2PRSC Clock Prescaler 1 compare value. Holds the 8bit prescaler value for timer subsystem 1. The counter of timer subsystem is incremented each time when the clock prescaler compare value matches the value of the clock prescaler counter. The divide-by-ratio is equal to C1PRSC+1 i.e. a value of 0016 results in a divide by 1 whereas the maximum divide-by ratio is 256 for a C1PRSC value of FF16. Clock Prescaler 2 compare value. Holds the 8bit prescaler value for timer subsystem 2. The functionality of this field is identical to the one described for C1PRSC in the previous paragraph. Clock Prescaler Register 2 (CLK2PS) 16.2.5 Interrupt Pending Register (INTPND) 16.2.7 The Interrupt Pending (INTPND) register is a word-wide read/write register which contains all 16 interrupt pending flags. There are four interrupt pending flags called IxAPD through IxDPD per timer subsystem. Each interrupt pending flag is set by a hardware event and can be cleared if the user software writes a 1 to the bit position. The value will remain unchanged if a 0 is written to the bit position. All interrupt pending flags are cleared (0) upon reset. 15 14 13 12 11 10 9 8 I4DPD I4CPD I4BPD I4APD I3DPD I3CPD I3BPD I3APD The Clock Prescaler Register 2 (CLK2PS) is a word-wide read/write register. The register is split into two 8-bit wide fields called C3PRSC and C4PRSC. Each field holds the 8bit clock prescaler compare value for timer subsystems 3 and 4 respectively. The register is cleared upon reset. 15 C4PRSC C3PRSC 87 C3PRSC 0 7 6 5 4 3 2 1 0 I2DPD I2CPD I2BPD I2APD I1DPD I1CPD I1BPD I1APD C4PRSC IxAPD IxBPD Timer x interrupt A pending. If set (1), indicates that an interrupt condition for the related timer subsystem has occurred. Table 17 on page 61 lists the hardware condition which causes this bit to be set. Timer x interrupt B pending. If set (1), indicates that an interrupt condition for the related timer subsystem has occurred. Table 17 on page 61 Clock Prescaler 3 compare value. Holds the 8bit prescaler value for timer subsystem 3. The functionality of this field is identical to the one described for C1PRSC on page 63. Clock Prescaler 4 compare value. Holds the 8bit prescaler value for timer subsystem 4. The functionality of this field is identical to the one described for C1PRSC on page 63. Counter Registers (COUNTx) 16.2.8 The Counter (COUNTx) registers are word wide read/write registers. There are a total of four registers called COUNT1 through COUNT4, one for each of the four timer subsystems. The user software may read the registers at any time. Reading the register will return the current value of the counter. 63 www.national.com The register may only be written if the counter is stopped i.e. if both TxRUN bits associated with a timer subsystem are cleared. The registers are cleared upon reset (0000). 15 CNTx 16.2.9 Period/Capture Registers (PERCAPx) 0 The Period/Capture (PERCAPx) registers are word-wide read/write registers. There are a total of four registers called PERCAP1 through PERCAP4, one for each timer subsystem. The register hold the period compare value in PWM mode of the counter value at the time the last associated capture event occurred. In PWM mode the register is double buffered. If a new period compare value is written while the counter is running, the write will not take effect until counter value matches the previous period compare value or until the counter is stopped. Reading may take place at any time and will return the most recent value which was written. The PERCAPx registers are reset to 0000 upon reset. 15 PCAPx 16.2.10 Duty Cycle / Capture Registers (DTYCAPx) The Duty Cycle/Capture (DTYCAPx) registers are word-wide read/write registers. There are a total of four registers called DTYCAP1 through DTYCAP4, one for each timer subsystem. The registers hold the period compare value in PWM mode or the counter value at the time the last associated capture event occurred. In PWM mode the register is double buffered. If a new duty cycle compare value is written while the counter is running, the write will not take effect until the counter value matches the previous period compare value or until the counter is stopped. In other words, the update takes effect on period boundaries only. Reading may take place at any time and will return the most recent value which was written. The DTYCAPx registers are reset to 000016 upon reset. 15 DCAPx 0 0 www.national.com 64 17.0 MICROWIRE/SPI MICROWIRE/PLUS is a synchronous serial communications protocol, originally implemented in National Semiconductor's COPS™ and HPC™ families of microcontrollers to minimize the number of connections, and therefore the cost, of communicating with peripherals. The device has an enhanced MICROWIRE/SPI interface module (MWSPI) that can communicate with all peripherals that conform to MICROWIRE or Serial Peripheral Interface (SPI) specifications. This enhanced MICROWIRE interface is capable of operating as either a master or slave and in 8or 16-bit mode. Figure 24 shows a typical enhanced MICROWIRE interface application. MCS 5 Chip Select Lines MCS CS CS CS CS Master I/O Lines 8-Bit A/D 1K Bit EEPROM LCD Display driver SK DI VF Display Driver SK DI Slave I/O Lines DO SK DI DO SK DI DO MDIDO MDODI MSK MDIDO MDODI MSK Figure 24. MICROWIRE Interface data out signal (MDODI for master mode, MDIDO for slave mode) and the serial clock (MSK). In slave mode, an optional fourth signal (MCS ) may be used to enable the slave transmit. At any given time, only one slave can respond to the master. Each slave device has its own chip select signal (MCS) for this purpose. The MICROWIRE interface allows the device to operate either as a master or slave transferring 8- or 16-bits of data. This is configured via the MMNS bit. Figure 25 shows a block diagram of the enhanced MICROWIRE serial interface in the device. 17.1.1 Shifting The enhanced MICROWIRE interface module includes the following features: — — — — — — — — — — — — Programmable operation as a Master or Slave Programmable shift-clock frequency (master only) Programmable 8- or 16-bit mode of operation 8- or 16-bit serial I/O data shift register Two modes of clocking data Serial clock can be low or high when idle 16-bit read buffer Busy flag, Read Buffer Full flag, and Overrun flag for polling and as interrupt sources Supports multiple masters Maximum bit rate of 10M bits/second (master mode) 5M bits/second (slave mode) at 20MHz system clock Supports very low-end slaves with the Slave Ready output Echo back enable/disable (Slave only) 17.1 MICROWIRE OPERATION The MICROWIRE interface allows several devices to be connected on one three-wire system. At any given time, one of these devices operates as the master while all other devices operate as slaves. The master device supplies the synchronous clock (MSK) for the serial interface and initiates the data transfer. The slave devices respond by sending (or receiving) the requested data. Each slave device uses the master’s clock for serially shifting data out (or in), while the master shifts the data in (or out). The three-wire system includes: the serial data in signal (MDIDO for master mode, MDODI for slave mode), the serial The MICROWIRE interface is a full duplex transmitter/receiver. A 16-bit shifter, which can be split into a low and high byte, is used for both transmitting and receiving. In 8-bit mode, only the lower 8-bits are used to transfer data. The transmitted data is shifted out through MDODI pin (master mode) or MDIDO pin (slave mode), starting with the most significant bit. At the same time, the received data is shifted in through MDIDO pin (master mode) or MDODI pin (slave mode), also starting with the most significant bit first. The shift in and shift out are controlled by the MSK clock. In each clock cycle of MSK, one bit of data is transmitted/received. The 16-bit shifter is accessible via the MWDAT register. Reading the MWDAT register returns the value in the read buffer. Writing to the MWDAT register updates the 16-bit shifter. 17.1.2 Reading The enhanced MICROWIRE interface implements a double buffer on read. As illustrated in Figure 25, the double read 65 www.national.com Interrupt Request Control + Status MCS Read Data 16-bit Read Buffer Write Data 8 8 MWDAT Slave 16-bit Shift Register Data Out Master MDODI Data In Slave Master MDIDO MSK MSK Clock Prescaler + Select System Clock Figure 25. Master MICROWIRE Block Diagram (master mode) or the MDODI pin (slave mode), is sampled on the rising edge of MSK. In the alternate mode, the output data is shifted out on the rising edge of MSK on the MDODI pin (master mode) or MDIDO pin (slave mode). The input data, which is received via MDIDO pin (master mode) or MDODI pin (slave mode), is sampled on the falling edge of MSK. The clocking modes are selected with the MSKM bit. The MIDL bit allows selection of the value of MSK when it is idle (when there is no data being transferred). Various MSK clock frequencies can be programmed via the MCDV bits. Figures 27, 28, 29, and 30 show the data transfer timing for the normal and the alternate modes with the MIDL bit equal to 0 and equal to 1. Note that when data is shifted out on MDODI (master mode) or MDIDO (slave mode) on the leading edge of the MSK clock, bit 14 (16-bit mode) is shifted out on the second leading edge of the MSK clock. When data are shifted out on MDODI (master mode) or MDIDO (slave mode) on the trailing edge of MSK, bit 14 (16-bit mode) is shifted out on the first trailing edge of MSK. buffer consists of the 16-bit shifter and a buffer, called the read buffer. The 16-bit shifter loads the read buffer with new data when the data transfer sequence is completed and previous data in the read buffer has been read. In master mode, an Overrun error occurs when the read buffer is full, the 16-bit shifter is full and a new data transfer sequence starts. When 8-bit mode is selected, the lower byte of the shift register is loaded into the lower byte of the read buffer and the read buffer’s higher byte remains unchanged. The “Receive Buffer Full” (MRBF) bit indicates if the MWDAT register holds valid data. The MOVR bit indicates that an overrun condition has occurred. 17.1.3 Writing The “MICROWIRE Busy” (MBSY) bit indicates whether the MWDAT register can be written. All write operations to the MWDAT register update the shifter while the data contained in the read buffer is not affected. Undefined results will occur if the MWDAT register is written to while the MBSY bit is set to 1. 17.1.4 Clocking Modes Two clocking modes are supported: the normal mode and the alternate mode. In the normal mode, the output data, which is transmitted on the MDODI pin (master mode) or the MDIDO pin (slave mode), is clocked out on the falling edge of the shift clock MSK. The input data, which is received via the MDIDO pin 17.2 MASTER MODE In Master mode, the MSK pin is an output for the shift clock, MSK. When data is written to the (MWnDAT register), eight www.national.com 66 End of Transfer MSK Data Out MSB msb-1 msb-2 5 Bit 1 Bit 0 (lsb) Data In M SB msb-1 msb-2 Bit 1 Bit 0 (lsb) Sample Point Shift Out Figure 26. Normal Mode, MIDL Bit = 0 End of Transfer MSK Data Out msb msb-1 msb-2 Bit 1 Bit 0 (lsb) Data In msb msb-1 msb-2 Bit 1 Shift Out Bit 0 (lsb) Sample Point Figure 27. Normal Mode, MIDL Bit = 1 End of Transfer MSKn Data Out msb msb-1 msb-2 Bit 1 Bit 0 (lsb) Data In msb msb-1 msb-2 Bit 1 Shift Out Bit 0 (lsb) Sample Point Figure 28. Alternate Mode, MIDL Bit = 0 MSK goes idle again. The MSK idle state can be either high or low, depending on the MIDL bit. or sixteen MSK clocks, depending on the mode selected, are generated to shift the eight or sixteen bits of data and then 17.3 SLAVE MODE In Slave mode, the MSK pin is an input for the shift clock MSK. MDIDO is placed in TRI-STATE mode when MCS is inactive. Data transfer is enabled when MCS is active. 67 www.national.com End of Transfer MSKn Data Out msb msb-1 msb-2 Bit 1 Bit 0 (lsb) Data In msb msb-1 msb-2 Bit 1 Bit 0 (lsb) Shift Out Sample Point Figure 29. Alternate Mode, MIDL Bit = 1 The slave starts driving MDIDO when MCS is activated. The most significant bit (lower byte in 8-bit mode or upper byte in 16-bit mode) is output onto the MDIDO pin first. After eight or sixteen clocks (depending on the selected mode), the data transfer is completed. If a new shift process starts before MWDAT was written, i.e., while MWDAT does not contain any valid data, and the “Echo Enable” (MECH) bit is set to 1, the data received from MDODI is transmitted on MDIDO in addition to being shifted to MWDAT. If the MECH bit is cleared to 0, the data transmitted on MDIDO is the data held in the MWDAT register, regardless of its validity. The master may negate the MCS signal to synchronize the bit count between the master and the slave. In the case that the slave is the only slave in the system, MCS can be tied to VSS. MEIO MOVR = 1 MRBF = 1 MEIR MBSY = 0 MEIW Figure 30. MWSPI Interrupts 17.5.1 MICROWIRE Data Register (MWDAT) MWSPI Interrupt 17.4 INTERRUPT GENERATION An interrupt is generated in any of the following cases: — When the read buffer is full (MRBF=1) and the “Enable Interrupt for Read” bit is set (MEIR=1). — Whenever the shifter is not busy, i.e. the MBSY bit is cleared (MBSY=0) and the “Enable Interrupt for Write” bit is set (MEIW=1). — When an overrun condition occurs (MOVR is set to 1) and the “Enable Interrupt on Overrun” bit is set (MEIO=1). This usage is restricted to master mode. Figure 30 illustrates the various interrupt capabilities of this module. The MWDAT register is a word-wide, read/write register used to transmit and receive data through the MDODI and MDIDO pins. Figure 31 shows the hardware structure of the register. . 17.5 MICROWIRE INTERFACE REGISTERS The software interacts with the MICROWIRE interface by accessing the MICROWIRE registers. There are five such registers: — MICROWIRE Data Register (MWDAT) — MICROWIRE Control Register (MWCTL) — MICROWIRE Status Register (MWSTAT) www.national.com 68 write DIN Shift Register Low-Byte High-Byte 1 0 DOUT (store) (store & MWMOD) MWMOD Read Buffer Low-Byte read High-Byte MWDAT Figure 31. MWDAT Register Structure Upon reset, all non-reserved bits are cleared to 0. The register format is shown below. 15 9 8 7 6 5 4 3 2 1 0 MCDV MIDL MSKM MEIW MEIR MEIO MECH MMOD MMNS MEN [6:0] MEN MICROWIRE Enable. This bit enables (1) or disables (0) the MICROWIRE interface module. Clearing this bit disables the module, clears the status bits in the MICROWIRE status register (the MBSY, MRBF, and MOVR flags in MWSTAT), and places the MICROWIRE interface pins in the states described in Table 18. Table 18 MSK MCS MDIDO MDODI Pin Values with MICROWIRE Disabled Master: MnIDL Bit Slave: input Input Master: input Slave: TRI-STATE Master: known Value Slave: input MEIO MEIR MMNS MMOD MECH MICROWIRE Master/Slave Select. When cleared to 0, the device operates as a slave. When set to 1, the device operates as the master. MICROWIRE Mode Select (8- or 16-bit). When set to 0, the device operates in 8-bit mode. When set to 1, the device operates in 16-bit mode. This bit should only be changed when the module is disabled or the MICROWIRE interface is idle (MWSTAT.MBSY=0). MICROWIRE Echo Back. This bit enables (1) or disables (0) the echo back function in slave MEIW MSKM mode. This bit should be written only when the MICROWIRE interface is idle (MWSTAT.MBSY=0). The MECH bit is ignored in master mode. The MWDAT register is valid from the time the register has been written until the end of the transfer. In the echo back mode, MDODI is transmitted (echoed back) on MDIDO if MWDAT does not contain any valid data. With the echo back function disabled, the data held in the MWDAT register is transmitted on MDIDO, whether or not the data is valid. MICROWIRE Enable Interrupt on Overrun. This bit enables or disables the overrun error interrupt. When set to 1, an interrupt is generated when the Receive Overrun Error flag (MWSTAT.MOVR) is set. Otherwise, no interrupt is generated when an overrun error occurs. This bit should only be enabled in master mode. MICROWIRE Enable Interrupt for Read. When set to 1, an interrupt is generated when the Read Buffer Full flag (MWSTAT.MRBF) is set. Otherwise, no interrupt is generated when the read buffer is full. MICROWIRE Enable Interrupt for Write. When set to 1, an interrupt is generated when the Busy bit (MWSTAT.MBSY) is cleared, which indicates that a data transfer sequence has been completed and the read buffer is ready to receive the new data. Otherwise, no interrupt is generated when the Busy bit is cleared. MICROWIRE Clocking Mode. When cleared to 0, the device uses the normal clocking mode. When set to 1, the device uses the alternate clocking mode. In the normal mode, the output data is clocked out on the falling edge of MSK 69 www.national.com MIDL MCDV and the input data is sampled on the rising edge of MSK. In the alternate mode, the output data is clocked out on the rising edge of MSK and the input data is sampled on the falling edge of MSK. MICROWIRE Idle. This bit sets the value of the MSK output when the MICROWIRE interface is idle: 0 for low or 1 for high. This bit should be changed only when the MICROWIRE interface module is disabled (MEN=0) or when no bus transaction is in progress (MWSTAT.MBSY=0). MICROWIRE Clock Divider Value. This 7-bit field specifies the divide-by factor used for generating the MSK shift clock from the system clock. The divide-by factor is 2*(MCDV[6:0]+1). This allows selection of a divide-by ratio from 2 to 256. This field is ignored in slave mode (MWCTL1.MMNS=0). MICROWIRE Status Register (MWSTAT) MOVR diately reloaded with the new data and is ready to be read by the software. MICROWIRE Receive Overrun Error. This bit, when set to 1 in master mode, indicates that a receive overrun error has occurred. This error occurs when the read buffer is full, the 8-bit shifter is full, and a new data transfer sequence starts. This bit is undefined in slave mode. The MOVR bit, once set, remains set until cleared by the software. The software clears this bit by writing a 1 to its bit position. Writing a 0 to this bit position has no effect. No other bits in the MWSTAT register are affected by a write operation to the register. 17.5.2 The MICROWIRE Status Register is a word-wide, read-only register that shows the current status of the MICROWIRE interface module. Upon reset, all non-reserved bits are cleared to 0. The register format is shown below. 15 Reserved MBSY 3 2 MOVR 1 MRBF 0 MBSY MICROWIRE Busy. This bit, when set to 1, indicates that the MICROWIRE shifter is busy. In master mode, MBSY is set to 1 when the MWDAT register is written. In slave mode, this bit is set to 1 on the first leading edge of MSK when MCS is asserted or when the MWDAT register is written, whatever occurs first. In both master and slave modes, this bit is cleared to 0 when the MICROWIRE data transfer sequence is completed and the read buffer is ready to receive the new data; in other words, when the previous data held in the read buffer has already been read. If the previous data in the read buffer has not been read and a new data has been received into the shift register, the MBSY will not be cleared, as the transfer could not be completed. This is because the contents of the shift register could not be copied into the read buffer. MICROWIRE Read Buffer Full. This bit, when set to 1, indicates that the MICROWIRE read buffer is full and ready to be read by the software. It is set to 1 when the shifter loads the read buffer, which occurs upon completion of a transfer sequence if the read buffer is empty. The MRBF bit is updated when the MWDAT register is read. At that time, the MRBF bit is cleared to 0 if the shifter does not contain any new data (in other words, the shifter is not receiving data or has not yet received a full byte of data). The MRBF bit remains set to 1 if the shifter already holds new data at the time that MWDAT is read. In that case, MWDAT is imme- MRBF www.national.com 70 18.0 USART The USART module is a full-duplex Universal Synchronous/ Asynchronous Receiver/Transmitter that supports a wide range of software-programmable baud rates and data formats. It handles automatic parity generation and several error detection schemes. There are one or two independent USART modules in each device, depending on the package type. Each USART module offers the following features: — Full-duplex double-buffered receiver/transmitter — Synchronous or asynchronous operation — programmable baud rate from SYS_CLK/ [2*(1+2^11)*16] up to SYSCLK/2 for USART configured to run in synchronous mode — programmable baud rate from SYS_CLK/ [16*(1+2^11)*16] up to SYSCLK/16 for USART configured to run in asynchronous mode — Programmable framing formats: seven, eight, or nine data bits; one or two stop bits; and odd, even, mark, space, or no parity — Hardware parity generation for data transmission and parity check for data reception — Interrupts on “transmit ready” and “receive ready” conditions, separately enabled — Software-controlled break transmission and detection — Internal diagnostic capability — Automatic detection of parity, framing, and overrun errors the first stage based on the programmed baud rate divisor to create the baud rate clock. The Control and Error Detection block contains the USART control registers, control logic, error detection circuit, parity generator/checker, and interrupt generation logic. The control registers and control logic determine the data format, mode of operation, clock source, and type of parity used. The error detection circuit generates parity bits and checks for parity, framing, and overrun errors. 18.2 USART OPERATION The USART has two basic modes of operation: synchronous and asynchronous. In addition, there are two specialpurpose synchronous and asynchronous modes, called attention and diagnostic. This section describes the operating modes of the USART. 18.2.1 Asynchronous Mode The asynchronous mode of the USART enables the device to communicate with other devices using just two communication signals: transmit and receive. In the asynchronous mode, the transmit shift register (TSFT) and the transmit buffer (UnTBUF) double-buffer the data for transmission. To transmit a character, a data byte is loaded in the UnTBUF register. The data is then transferred to the TSFT register. While the TSFT is shifting out the current character (LSB first) on the TDXn pin, the UnTBUF register is loaded by software with the next byte to be transmitted. When TSFT finishes transmission of the last stop bit of the current frame, the contents of UnTBUF are transferred to the TSFT register and the Transmit Buffer Empty flag (UnTBE) is set. The UnTBE flag is automatically reset by the USART when the software loads a new character into the UnTBUF register. During transmission, the UnXMIP bit is set high by the USART. This bit is reset only after the USART has sent the last stop bit of the current character and the UnTBUF register is empty. The UnTBUF register is a read/write register. The TSFT register is not user accessible. In asynchronous mode, the input frequency to the USART is 16 times the baud rate. In other words, there are 16 clock cycles per bit time. In asynchronous mode the baud rate generator is always the USART clock source. The receive shift register (RSFT) and the receive buffer (UnRBUF) double buffer the data being received. The USART receiver continuously monitors the signal on the RDXn pin for a low level to detect the beginning of a start bit. Upon sensing this low level, the USART waits for seven input clock cycles and samples again three times. If all three samples still indicate a valid low, then the receiver considers this to be a valid start bit, and the remaining bits in the character frame are each sampled three times, around the mid-bit position. For any bit following the start bit, the logic value is found by majority voting, i.e. the two samples with the same value define the value of the data bit. Figure 33 illustrates the process of start bit detection and bit sampling. Serial data input on the RDXn pin is shifted into the RSFT register. Upon receiving the complete character, the contents of the RSFT register are copied into the UnRBUF register and the Receive Buffer Full flag (UnRBF) is set. The UnRBF 18.1 FUNCTIONAL OVERVIEW Figure 32 is a block diagram of the USART module showing the basic functional units in the USART: — Transmitter — Receiver — Baud Rate Generator — Control and Error Detection Note: In the description of the USART, the lower-case letter “n” represents the USART number. For example, TDXn means TDX1 or TDX2. The Transmitter block consists of an 8-bit transmit shift register and an 8-bit transmit buffer. Data bytes are loaded in parallel from the buffer into the shift register and then shifted out serially on the TDXn pin. The Receiver block consists of an 8-bit receive shift register and an 8-bit receive buffer. Data is received serially on the RDXn pin and shifted into the shift register. Once eight bits have been received, the contents of the shift register are transferred in parallel to the receive buffer. The Transmitter and Receiver blocks both contain extensions for 9-bit data transfers, as required by the 9-bit and loopback operating modes. The Baud Rate Generator generates the clock for the synchronous and asynchronous operating modes. It consists of two registers and a two-stage counter. The registers are used to specify a prescaler value and a baud rate divisor. The first stage of the counter divides the USART clock based on the value of the programmed prescaler to create a slower clock. The second stage of the counter divides the output of 71 www.national.com flag is automatically reset when software reads the character from the UnRBUF register. The RSFT register is not user accessible. Transmitter Baud clock Sys_clk TDXn Internal Bus Control and Error Detection Baud Rate Generator CKXn Parity Generator/Checker Baud Clock Receiver Figure 32. USART Block Diagram RDXn 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 Sample STARTBIT Sample DATA (LSB) 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 Sample DATABIT Figure 33. 18.2.2 Synchronous Mode USART Asynchronous Communication Data bytes are transmitted and received least significant bit (LSB) first. In the synchronous mode, the transmit shift register (TSFT) and the transmit buffer (UnTBUF) double-buffer the data for transmission. To transmit a character, a data byte is loaded in the UnTBUF register. The data is then transferred to the TSFT register. The TSFT register shifts out one bit of the current character, LSB first, on each rising edge of the clock. The synchronous mode of the USART enables the device to communicate with other devices using three communication signals: transmit, receive, and clock. In this mode, data bits are transferred synchronously with the USART clock signal. Data bits are transmitted on the rising edges and received on the falling edges of the clock signal, as shown in Figure 34. www.national.com 72 CKX TDX to the receive buffer. The UnRBF flag is set and an interrupt (if enabled) is generated. The UnATN bit is automatically reset to zero, and the USART begins receiving all subsequent characters. The software must examine the contents of the UnRBUF register and respond by accepting the subsequent characters (by leaving the UnATN bit reset) or waiting for the next address character (by setting the UnATN bit again). The operation of the USART transmitter is not affected by the selection of this mode. The value of the ninth bit to be transmitted is programmed by setting or clearing a bit called UnXB9 in the USART Frame Select register. The value of the ninth bit received is read from UnRB9 in the USART Status Register. Sample Input 18.2.4 Diagnostic Mode RDX Figure 34. USART Synchronous Communication While the TSFT is shifting out the current character on the TDXn pin, the UnTBUF register may be loaded by the software with the next byte to be transmitted. When the TSFT finishes transmission of the last stop bit within the current frame, the contents of UnTBUF are transferred to the TSFT register and the Transmit Buffer Empty flag (UnTBE) is set. The UnTBE flag is automatically reset by the USART when the software loads a new character into the UnTBUF register. During transmission, the UnXMIP bit is set high by the USART. This bit is reset only after the USART has sent the last frame bit of the current character and the UnTBUF register is empty. The receive shift register (RSFT) and the receive buffer (UnRBUF) double-buffer the data being received. Serial data received on the RDXn pin is shifted into the RSFT register at the first falling edge of the clock. Each subsequent falling edge of the clock causes an additional bit to be shifted into the RSFT register. The USART assumes a complete character has been received after the correct number of rising edges on CKXn (based on the selected frame format) have been detected. Upon receiving a complete character, the contents of the RSFT register are copied into the UnRBUF register and the Receive Buffer Full flag (UnRBF) is set. The UnRBF flag is automatically reset when the software reads the character from the UnRBUF register. The transmitter and receiver may be clocked from either an external source provided to the CKXn pin or by the internal baud rate generator. In the latter case, the clock signal is placed on the CKXn pin as an output. 18.2.3 Attention Mode The Diagnostic mode is available for testing of the USART. In this mode, the TDXn and RDXn pins are internally connected together, and data that is shifted out of the transmit shift register is immediately transferred to the receive shift register. This mode supports only the 9-bit data format with no parity. The number of start and stop bits is programmable. 18.2.5 Frame Format Selection The format shown in Figure 35 consists of a start bit, seven data bits (excluding parity), and one or two stop bits. If parity bit generation is enabled by setting the UnPEN bit, a parity bit is generated and transmitted following the seven data bits. 1 1a 1b 1c START BIT START BIT START BIT START BIT 7 BIT DATA 7 BIT DATA 7 BIT DATA 7 BIT DATA S 2S PA PA S 2S Figure 35. Seven Data Bit Frame Options The format shown in Figure 36 consists of one start bit, eight data bits (excluding parity), and one or two stop bits. If parity bit generation is enabled by setting the UnPEN bit, a parity bit is generated and transmitted following the eight data bits. 2 2a 2b 2c START BIT START BIT START BIT START BIT 8 BIT DATA 8 BIT DATA 8 BIT DATA 8 BIT DATA S 2S PA PA S 2S The Attention mode is available for networking this device with other processors. This mode requires the 9-bit data format with no parity. The number of start bits and number of stop bits are programmable. In this mode, two types of 9-bit characters are sent on the network: address characters consisting of 8 address bits and a 1 in the ninth bit position and data characters consisting of 8 data bits and a 0 in the ninth bit position. While in Attention mode, the USART receiver monitors the communication flow but ignores all characters until an address character is received. Upon the receipt of an address character, the contents of the receive shift register are copied Figure 36. Eight Data Bit Frame Options The format shown in Figure 37 consists of one start bit, nine data bits, and one or two stop bits. This format also supports the USART attention feature. When operating in this format, all eight bits of UnTBUF and UnRBUF are used for data. The 73 www.national.com ninth data bit is transmitted and received using two bits in the control registers, called UnXB9 and UnRB9. Parity is not generated or verified in this mode. 3 Table 19 Prescaler Select 01100 Prescaler Factors Prescaler Select 11100 11101 11110 11111 Prescaler Factor 14.5 15 15.5 16 Prescaler Factor 6.5 7 7.5 8 START BIT 9 BIT DATA S 01101 2S 3a START BIT 9 BIT DATA 01110 01111 Figure 37. 18.2.6 Nine Data Bit Frame Options Baud Rate Generator The Baud Rate Generator creates the basic baud clock from the system clock. The system clock is passed through a twostage divider chain consisting of a 5-bit baud rate prescaler (UnPSC) and an 11-bit baud rate divisor (UnDIV). The relationship between the 5-bit prescaler select (UnPSC) setting and the prescaler factors is shown in Table 19. Table 19 Prescaler Select 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 Prescaler Factors Prescaler Select 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 Prescaler Factor 8.5 9 9.5 10 10.5 11 11.5 12 12.5 13 13.5 14 A prescaler factor of zero corresponds to “no clock.” The “no clock” condition is the USART power down mode, in which the USART clock is turned off to reduce power consumption. The application program should select the “no clock” condition before entering a new baud rate. Otherwise, it could cause incorrect data to be received or transmitted. The UnPSR register must contain a value other than zero when an external clock is used at CKXn. In asynchronous mode, the baud rate is calculated by: SYS _ CLK BR = -----------------------------( 16 × N × P ) where BR is the baud rate, SYS_CLK is the system clock, N is the value of the baud rate divisor + 1, and P is the prescaler divide factor selected by the value in the UnPSR register. The divide by 16 is performed because in the asynchronous mode, the input frequency to the USART is 16 times the baud rate. In synchronous mode, the input clock to the USART equals the baud rate. 18.2.7 • • • Interrupts Prescaler Factor 1 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 The USART is capable of generating interrupts on: Receive Buffer Full Receive Error Transmit Buffer Empty Figure 38 shows a diagram of the interrupt sources and associated enable bits. UnFE UnEEI UnDOE UnERR UnRBF RX Interrupt UnPE UnERI UnTBE UnETI Figure 38. USART Interrupts TX Interrupt www.national.com 74 The interrupts can be individually enabled or disabled using the Enable Transmit Interrupt (UnETI), Enable Receive Interrupt (UnERI) and Enable Receive Error Interrupt (UnEER) bits in the UnICTRL register. A transmit interrupt is generated when both the UnTBE and UnETI bits are set. To remove this interrupt, software must either disable the interrupt by clearing the UnETI bit or write to the UnTBUF register (thus clearing the UnTBE bit). A receive interrupt is generated on two conditions: 1. Both the UnRBF and UnERI bits are set. To remove this interrupt, software must either disable the interrupt by clearing the UnERI bit or read from the UnRBUF register (thus clearing the UnRBF bit). 2. Both the UnERR and the UnEEI bits are set. To remove this interrupt the software must either disable it by clearing the UnEEI bit or read the UnSTAT register (thus clearing the UnERR bit). 18.2.8 Break Generation and Detection the upper three bits of the baud rate divisor. This register is cleared upon reset. The register format is shown below. 7 654 UnPSC 3 2 UnDIV10 1 UnDIV9 0 UnDIV8 UnPSC Prescaler. This 5-bit field specifies the prescaler value used for dividing the system clock in the first stage of the two-stage divider chain. For the prescaler factors corresponding to each 5-bit value, see Table 19. UnDIV[10:8] Baud Rate Divisor (bits 10-8). This field contains the three highest-order bits (bits 10, 9, and 8) of the USART baud rate divisor used in the second stage of the two-stage divider chain. The remaining bits of the baud rate divisor are contained in the UnBAUD register. 18.3.4 USART Baud Rate Divisor (UnBAUD) A line break is generated when the BRK bit is set in the UnMDSL register. The TDXn line remains low until the program resets the BRK bit. A line break is detected if RDXn remains low for 10 bit times or longer after a missing stop bit is detected. 18.2.9 Parity Generation and Detection The USART Baud Rate Divisor Register is a byte-wide, read/ write register that contains the lower eight bits of the baud rate divisor. This register contents are unknown upon powerup and are left unchanged by a reset operation. The register format is shown below. 7 6 5 4 3 2 1 0 UnDIV7 UnDIV6 UnDIV5 UnDIV4 UnDIV3 UnDIV2 UnDIV1 UnDIV0 UnDIV[7:0] Parity is only generated or checked with the 7-bit and 8-bit data formats. It is not generated or checked in the diagnostic loopback mode, the attention mode, or in the normal mode with the 9-bit data format. Parity generation and checking are enabled and disabled via the PEN bit in the UnFRS register. The UnPSEL bits in the UnFRS register are used to select odd, even, mark, or space parity. Baud Rate Divisor (bits 7-0). This field contains the eight lowest-order bits of the USART baud rate divisor used in the second stage of the two-stage divider chain. The three highest-order bits are contained in the UnPSR register. The divisor value used is the 11-bit UnDIV value plus 1. 18.3.5 USART Frame Select Register (UnFRS) 18.3 USART REGISTERS The software interacts with the USART by accessing the USART registers. There are eight such registers: — — — — — — — — USART USART USART USART USART USART USART USART Receive Data Buffer (UnRBUF) Transmit Data Buffer (UnTBUF) Baud Rate Prescaler Register (UnPSR) Baud Rate Divisor Register (UnBAUD) Frame Select Register (UnFRS) Mode Select Register (UnMDSL) Status Register (UnSTAT) Interrupt Control Register (UnICTRL) The USART Frame Select Register is a byte-wide, read/write register that controls the frame format, including the number of data bits, number of stop bits, and parity type. This register is cleared upon reset. The register format is shown below. 7 6 5 4 3 2 1 0 Reserved UnPEN UnPSEL UnXB9 UnSTP UnCHAR UnCHAR Character Frame Format. This 2-bit field selects the number of data bits per frame, not including the parity bit, as follows: 00 = 01 = 10 = 11 = UnSTP eight data bits per frame seven data bits per frame nine data bits per frame loopback mode; nine data bits per frame 18.3.1 USART Receive Data Buffer (UnRBUF) The USART Receive Data Buffer is a byte-wide, read/write register used to receive each data byte. 18.3.2 USART Transmit Data Buffer (UnTBUF) The USART Transmit Data Buffer is a byte-wide, read/write register used to transmit each data byte. 18.3.3 USART Baud Rate Prescaler (UnPSR) The USART Baud Rate Prescaler Register is a byte-wide, read/write register that contains the 5-bit clock prescaler and UnXB9 Number of Stop Bits. This bit sets the number of stop bits transmitted in each frame. If this bit is 0, one stop bit is transmitted. If this bit is 1, two stop bits are transmitted. Transmit 9th Data Bit. This bit is the value of the ninth data bit, either 0 or 1, transmitted when the USART is configured to transmit nine data bits per frame. It has no effect when the USART is configured to transmit seven or eight data bits per frame. 75 www.national.com UnPSEL Parity Select. This 2-bit field selects parity type as follows: UnFE 00 01 10 11 = odd parity = even parity = mark (0) = space (1) UnDOE When the USART is configured to transmit nine data bits per frame, the parity bit is omitted and the UnPSEL field is ignored. Parity Enable. This bit enables (1) or disables (0) parity bit generation and parity checking. When the USART is configured to transmit nine data bits per frame, there is no parity bit and the UnPEN bit is ignored. USART Mode Select Register (UnMDSL) UnBKD UnPEN UnERR 18.3.6 The USART Mode Select Register is a byte-wide, read/write register that selects the clock source, synchronization mode, attention mode, and line break generation. This register is cleared upon reset. When the software writes to this register, the reserved bits must be cleared to 0 for proper operation. The register format is shown below. 7 654 Reserved 3 UnCKS 2 UnBRK 1 UnATN 0 UnMOD UnMOD UnATN UnBRK UnCKS Mode of Operation. Set to 0 for asynchronous operation or 1 for synchronous operation. Attention Mode. When set to 1, this bit selects the attention mode of operation for the USART. When cleared to 0, the attention mode is disabled. The hardware clears this bit after an address frame is received. An address frame is a 9-bit character with a 1 in the ninth bit position. Force Transmission Break. Setting this bit to 1 causes the TDXn pin to go low. TDXn remains low until the UnBRK bit is cleared to 0 by the software. Synchronous Clock Source. This bit controls the clock source when the USART operates in the synchronous mode (UnMOD=1). If the UnCKS bit is set to 1, the USART operates from an external clock provided on the CKXn pin. If the UnCKS bit is cleared to 0, the USART operates from the baud rate clock produced by the USART on the CKXn pin. This bit is ignored when the USART operates in the asynchronous mode. USART Status Register (UnSTAT) UnRB9 UnXMIP bit is automatically cleared to 0 by the hardware when the UnSTAT register is read. Framing Error. This bit is set to 1 when the USART fails to receive a valid stop bit at the end of a frame. This bit is automatically cleared to 0 by the hardware when the UnSTAT register is read. Data Overrun Error. This bit is set to 1 when a new character is received and transferred to the UnBUF register before the software has read the previous character from UnBUF. This bit is automatically cleared to 0 by the hardware when the UnSTAT register is read. Error Status Flag. This bit is set when a parity, framing, or overrun error occurs (any time that the UnPE, UnFE, or UnDOE bit is set). It is automatically cleared to 0 by the hardware when the UnPE, UnFE, and UnDOE bits are all 0. Break Detect. This bit is set to 1 when a line break condition occurs. This condition is detected if RDXn remains low for at least ten bit times after a missing stop bit has been detected at the end of a frame. The hardware automatically clears the UnBKD bit upon read of the UnSTAT register, but only if the break condition on RXDn no longer exists. If reading the UnSTAT register does not clear the UnBKD bit because the break is still actively driven on the line, the hardware clears the bit as soon as the break condition no longer exists (when RXDn returns to a high level). Received 9th Data Bit. With the USART configured to operate in the 9-bit data format, this is equal to the ninth data bit of the last frame received. Transmit In Progress. The hardware sets this bit to 1 when the USART is transmitting data and clears it to 0 at the end of the last frame bit. USART Interrupt Control Register (UnICTRL) 18.3.8 The USART Interrupt Control Register is a byte-wide register that contains the receive and transmit interrupt status flags (read-only bits) and the interrupt enable bits (read/write bits). The register is set to 01 hex upon reset. The register format is shown below. 7 UnEEI UnTBE 6 UnERI 5 UnETI 432 Reserved 1 UnRBF 0 UnTBE 18.3.7 The USART Status Register is a byte-wide, read-only register that contains the receive and transmit status bits. This register is cleared upon reset. Any attempt by the software to write to this register is ignored. The register format is shown below. 7 6 5 UnRB9 4 UnBKD 3 2 1 0 Reserved UnXMIP UnERR UnDOE UnFE UnPE UnRBF UnPE Parity Error. This bit is set to 1 when a parity error is detected within a received character. This Transmit Buffer Empty. This read-only bit is set to 1 by the hardware when the USART transfers data from the UnTBUF register to the transmit shift register for transmission. It is automatically cleared to 0 by the hardware on the next write to the UnTBUF register. Receive Buffer Full. This read-only bit is set by the hardware when the USART has received a complete data frame and has transferred the data from the receive shift register to the UnRBUF register. It is automatically cleared to 0 by the hardware when the UnRBUF register is read. www.national.com 76 UnETI UnERI UnEEI Enable Transmitter Interrupt. This read/write bit, when set to 1, enables generation of an interrupt when the hardware sets the UnTBE bit. Enable Receiver Interrupt. This read/write bit, when set to 1, enables generation of an interrupt when the hardware sets the UnRBF bit. Enable Receive Error Interrupt. This read/write bit, when set to 1, enables generation of an interrupt when the hardware sets the UnERR bit in the UnSTAT register. Note that the percent error is much lower than would be possible without the non-integer prescaler factor. Refer to the table below for more examples. System Clock 4 MHz 5 MHz 10 MHz 20 MHz 18.4.2 Desired Baud Rate 9600 9600 19200 19200 N P Actual Baud Rate 9615.385 9615.385 19230.769 19230.769 Percent Error 0.16 0.16 0.16 0.16 2 13 5 6.5 5 6.5 5 13 18.4 BAUD RATE CALCULATIONS The USART baud rate is determined by the system clock frequency and the values programmed into the UnPSR and UnBAUD registers. Unless the system clock frequency is an exact multiple of the desired baud rate, there will be a small amount of error in the resulting baud rate clock. The method of baud rate calculation depends on whether the USART is configured to operate in the asynchronous or synchronous mode. 18.4.1 Baud Rate in Asynchronous Mode Baud Rate in Synchronous Mode The equation for calculating the baud rate in synchronous mode is: SYS _ CLK BR = --------------------------(2 × N × P) where BR is the baud rate, SYS_CLK is the system clock, N is the value of the baud rate divisor + 1, and P is the prescaler divide factor selected by the value in the UnPSR register. Use the same procedure to determine the values of N and P as in the asynchronous mode. In this case, however, only integer prescaler values are allowed. The equation for calculating the baud rate in asynchronous mode is: SYS _ CLK B R = -----------------------------( 16 × N × P ) where BR is the baud rate, SYS_CLK is the system clock, N is the value of the baud rate divisor + 1, and P is the prescaler divide factor selected by the value in the UnPSR register. Assuming a system clock of 5 MHz and a desired baud rate of 9600, the NxP term according to the equation above is: ( 5 ×10 ) N × P = ---------------------------- = 32.552 ( 16 × 9600 ) The NxP term is then divided by each Prescaler Factor from Table 19 to obtain a value closest to an integer. The factor for this example is 6.5. 32.552 N = --------------- = 5.008 (N = 5) 6.5 The baud rate register is programmed with a baud rate divisor of 4 (N = baud rate divisor +1). This produces a baud clock of: ( 5 ×10 ) BR = --------------------------------- = 9615.385 ( 16 × 5 × 6.5 ) ( 9615.385 – 9600 ) % error = -------------------------------------------- = 0.16 9600 6 6 77 www.national.com 19.0 ACCESS.bus Interface The ACCESS.bus interface module (ACB) is a two wire serial interface compatible with the ACCESS.bus physical layer. It permits easy interfacing to a wide range of low-cost memories and I/O devices, including: EEPROMs, SRAMs, timers, A/D converters, D/A converters, clock chips and peripheral drivers. It is also compatible with Intel’s SMBus and Philips’ I2C bus. The module can be configured as a bus master or slave, and can maintain bi-directional communications with both multiple master and slave devices. This section presents an overview of the bus protocol, and its implementation by the module. ACCESS.bus, SMBus and I2C compliant ACCESS.bus master and slave Supports polling and interrupt controlled operation Generate a wake-up signal on detection of a Start Condition, while in power-down mode — Optional internal pull-up on SDA and SCL pins — — — — SDA SCL Data Line Stable: Data Valid Change of Data Allowed Figure 39. Bit Transfer 19.1 ACB PROTOCOL OVERVIEW Each data transaction is composed of a Start Condition, a number of byte transfers (set by the software), and a Stop Condition to terminate the transaction. Each byte is transferred with the most significant bit first, and after each byte (8 bits), an Acknowledge signal must follow. At each clock cycle, the slave can stall the master while it handles the previous data, or prepares new data. This can be done for each bit transferred or on a byte boundary by the slave holding SCL low to extend the clock-low period. Typically, slaves extend the first clock cycle of a transfer if a byte read has not yet been stored, or if the next byte to be transmitted is not yet ready. Some microcontrollers with limited hardware support for ACESS.bus extend the access after each bit, thus allowing the software time to handle this bit. Start and Stop The ACCESS.bus master generates Start and Stop Conditions (control codes). After a Start Condition is generated the bus is considered busy and it retains this status until a certain time after a Stop Condition is generated. A high-to-low transition of the data line (SDA) while the clock (SCL) is high indicates a Start Condition. A low-to-high transition of the SDA line while the SCL is high indicates a Stop Condition (Figure 40). The ACCESS.bus protocol uses a two-wire interface for bidirectional communications between the ICs connected to the bus. The two interface lines are the Serial Data Line (SDA), and the Serial Clock Line (SCL). These lines should be connected to a positive supply, via a pull-up resistor, and remain HIGH even when the bus is idle. The ACCESS.bus protocol supports multiple master and slave transmitters and receivers. Each IC has a unique address and can operate as a transmitter or a receiver (though some peripherals are only receivers). During data transactions, the master device initiates the transaction, generates the clock signal and terminates the transaction. For example, when the ACB initiates a data transaction with an attached ACCESS.bus compliant peripheral, the ACB becomes the master. When the peripheral responds and transmits data to the ACB, their master/slave (data transaction initiator and clock generator) relationship is unchanged, even though their transmitter/receiver functions are reversed. 19.1.1 Data Transactions SDA One data bit is transferred during each clock pulse. Data is sampled during the high state of the serial clock (SCL). Consequently, throughout the clock’s high period, the data should remain stable (see Figure 39). Any changes on the SDA line during the high state of the SCL and in the middle of a transaction aborts the current transaction. New data should be sent during the low SCL state. This protocol permits a single data line to transfer both command/control information and data using the synchronous serial clock. SCL S Start Condition P Stop Condition Figure 40. Start and Stop Conditions In addition to the first Start Condition, a repeated Start Condition can be generated in the middle of a transaction. This allows another device to be accessed, or a change in the direction of the data transfer. Acknowledge Cycle The Acknowledge Cycle consists of two signals: the acknowledge clock pulse the master sends with each byte trans- www.national.com 78 ferred, and the acknowledge signal sent by the receiving device (Figure 41). Acknowledgment Signal From Receiver SDA MSB SCL S Start Condition Byte Complete 1 2 3-6 7 8 9 ACK 1 2 3-8 9 ACK The address is the first seven bits after a Start Condition. The direction of the data transfer (R/W) depends on the bit sent after the address — the eighth bit. A low-to-high transition during a SCL high period indicates the Stop Condition, and ends the transaction (Figure 43). P Stop Condition SDA Interrupt Within Receiver Clock Line Held Low by Receiver While Interrupt is Serviced SCL S 1-7 8 9 1-7 Data 8 9 ACK 1-7 Data 8 9 ACK P Address R/W ACK Start Condition Figure 41. ACCESS.bus Data Transaction Stop Condition The master generates the acknowledge clock pulse on the ninth clock pulse of the byte transfer. The transmitter releases the SDA line (permits it to go high) to allow the receiver to send the acknowledge signal. The receiver must pull down the SDA line during the acknowledge clock pulse, thus signalling the correct reception of the last data byte, and its readiness to receive the next byte. Figure 42 illustrates the acknowledge cycle. Data Output by Transmitter Data Output by Receiver Transmitter Stays Off the Bus During the Acknowledgment Clock Acknowledgment Signal From Receiver SCL S Start Condition 1 2 3-6 7 8 9 Figure 43. A Complete ACCESS.bus Data Transaction When the address is sent, each device in the system compares this address with its own. If there is a match, the device considers itself addressed and sends an acknowledge signal. Depending upon the state of the R/W bit (1:read, 0:write), the device acts as a transmitter or a receiver. The I2C bus protocol allows sending a general call address to all slaves connected to the bus. The first byte sent specifies the general call address (0016) and the second byte specifies the meaning of the general call (for example, “Write slave address by software only”). Those slaves that require the data acknowledge the call and become slave receivers; the other slaves ignore the call. Arbitration on the Bus Multiple master devices on the bus, require arbitration between their conflicting bus-access demands. Control of the bus is initially determined according to address bits and clock cycle. If the masters are trying to address the same IC, data comparisons determine the outcome of this arbitration. In master mode, the device immediately aborts a transaction if the value sampled on the SDA lines differs from the value driven by the device. (Exceptions to this rule are SDA while receiving data; in these cases the lines may be driven low by the slave without causing an abort). The SCL signal is monitored for clock synchronization purpose and allow the slave to stall the bus. The actual clock period will be the one set by the master with the longest clock period or by the slave stall period. The clock high period is determined by the master with the shortest clock high period. When an abort occurs during the address transmission, the master that identify the conflict, give-up the bus and should switch to slave mode and continue to sample SDA to see if it is being addressed by the winning master on the ACCESS.bus. Figure 42. ACCESS.bus Acknowledge Cycle The master generates an acknowledge clock pulse after each byte transfer. The receiver sends an acknowledge signal after every byte received. There are two exceptions to the “acknowledge after every byte” rule. 1. When the master is the receiver, it must indicate to the transmitter an end of data by not-acknowledging (“negative acknowledge”) the last byte clocked out of the slave. This “negative acknowledge” still includes the acknowledge clock pulse (generated by the master), but the SDA line is not pulled down. 2. When the receiver is full, otherwise occupied, or a problem has occurred, it sends a negative acknowledge to indicate that it can not accept additional data bytes. Addressing Transfer Formats Each device on the bus has a unique address. Before any data is transmitted, the master transmits the address of the slave being addressed. The slave device should send an acknowledge signal on the SDA line, once it recognizes its address. 19.2 ACB FUNCTIONAL DESCRIPTION The ACB module provides the physical layer for an ACCESS.bus compliant serial interface. The module is configurable as either a master or slave device. As a slave device, the ACB module may issue a request to become the bus master. 79 www.national.com 19.2.1 Master Mode An ACCESS.bus transaction starts with a master device requesting bus mastership. It sends a Start Condition, followed by the address of the device it wants to access. If this transaction is successfully completed, the software can assume that the device has become the bus master. For a device to become the bus master, the software should perform the following steps: 1. Set ACBCTL1.START, and configure ACBCTL1.INTEN to the desired operation mode (Polling or Interrupt). This causes the ACB to issue a Start Condition on the ACCESS.bus, as soon as the ACCESS.bus is free (ACBCST.BB=0). It then stalls the bus by holding SCL low. 2. If a bus conflict is detected, (i.e., some other device pulls down the SCL signal before this device does), ACBST.BER is set. 3. If there is no bus conflict, ACBST.MASTER and ACBST.SDAST are set. 4. If ACBCTL1.INTEN is set, and either ACBST.BER or ACBST.SDAST is set, an interrupt is sent to the ICU. Sending the Address Byte Once this device is the active master of the ACCESS.bus (ACBST.MASTER is set), it can send the address on the bus. The address sent should not be this device’s own address as defined in ACBADDR.ADDR if ACBADDR.SAEN is set, nor should it be the global call address if ACBST.GCMTCH is set. To send the address byte use the following sequence: 1. Configure the ACBCTL1.INTEN bit according to the desired operation mode. For a receive transaction where the software wants only one byte of data, it should set the ACBCTL1.ACK bit. If only an address needs to be sent, set (1) the ACBCTL1.STASTRE bit. 2. Write the address byte (7-bit target device address), and the direction bit, to the ACBSDA register. This causes the module to generate a transaction. At the end of this transaction, the acknowledge bit received is copied to ACBST.NEGACK. During the transaction the SDA and SCL lines are continuously checked for conflict with other devices. If a conflict is detected, the transaction is aborted, ACBST.BER is set, and ACBST.MASTER is cleared. 3. If ACBCTL1.STASTRE is set, and the transaction was successfully completed (i.e., both ACBST.BER and ACBST.NEGACK are cleared), ACBST.STASTR is set. In this case, the ACB stalls any further ACCESS.bus operations (i.e., holds SCL low). If ACBCTL1.INTE is set, it also sends an interrupt to the core. 4. If the requested direction is transmit, and the start transaction was completed successfully (i.e., neither ACBST.NEGACK nor ACBST.BER is set, and no other master has accessed the device), ACBST.SDAST is set to indicate that the module awaits attention. 5. If the requested direction is receive, the start transaction was completed successfully and ACBCTL1.STASTRE is cleared, the module starts receiving the first byte automatically. 6. Check that both ACBST.BER and ACBST.NEGACK are cleared. If the ACBCTL1.INTEN bit is set, an interrupt is generated when either ACBST.BER or ACBST.NEGACK is set. Master Transmit After becoming the bus master, the device can start transmitting data on the ACCESS.bus. To transmit a byte, the software should: 1. Check that the BER and NEGACK bits in ACBST are cleared and ACBST.SDAST is set. Also, if ACBCTL1.STASTRE is set, check that ACBST.STASTR is cleared. 2. Write the data byte to be transmitted to the ACBSDA register. When the slave responds with a negative acknowledge, the ACBST.NEGACK bit is set and the ACBST.SDAST bit remains cleared. In this case, if ACBCTL1.INTEN is set, an interrupt is sent to the core. Master Receive After becoming the bus master, the device can start receiving data on the ACCESS.bus. To receive a byte, the software should: 1. Check that ACBST.SDAST is set and ACBST.BER is cleared. Also, if ACBCTL1.STASTRE is set, check that ACBST.STASTR is cleared. 2. Set the ACBCTL1.ACK bit to 1, if the next byte is the last byte that should be read. This causes a negative acknowledge to be sent. 3. Read the data byte from the ACBSDA register. Master Stop A Stop Condition may be issued only when this device is the active bus master (ACBST.MASTRER=1). To end a transaction, set (1) ACBCTL1.STOP before clearing the current stall flag (i.e., ACBST.SDAST, ACBST.NEGACK or ACBST.STASTR). This causes the module to send a Stop Condition immediately, and clear ACBCTL1.STOP . M aster Bus Stall The ACB module can stall the ACCESS.bus between transfers while waiting for the core’s response. The ACCESS.bus is stalled by holding the SCL signal low after the acknowledge cycle. Note that this is interpreted as the beginning of the following bus operation. The user must make sure that the next operation is prepared before the flag that causes the bus stall is cleared. The flags that can cause a stall in master mode are: — Negative acknowledge after sending a byte (ACBSTNEGACK=1). — ACBST.SDAST bit is set. — If ACBCTL1.STASTRE=1, after a successful start (ACBST.STASTR=1). Repeated Start A repeated start is performed when this device is already the bus master (ACBST.MASTER is set). In this case the ACCESS.bus is stalled and the ACB is awaiting the core handling due to: negative acknowledge (ACBST.NEGACK=1), www.national.com 80 empty buffer (ACBST.SDAST=1) and/or a stop after start (ACBST.STASTR=1). For a repeated start: — Set the ACBCTL1.START bit. — In master receive mode, read the last data item from ACBSDA. — Follow the address send sequence, as described in “Sending the Address Byte” on page 80. — If the ACB was awaiting handling due to ACBST.STASTR=1, clear it only after writing the requested address and direction to ACBSDA. Master Error Detections The ACB detects illegal Start or Stop Conditions (i.e., a Start or Stop Condition within the data transfer, or the acknowledge cycle) and a conflict on the data lines of the ACCESS.bus. If an illegal action is detected, BER is set, and the MASTER mode is exited (MASTER is cleared). Bus Idle Error Recovery When a request to become the active bus master or a restart operation fails, the ACBST.BER bit is set to indicate the error. In some cases, both this device and the other device may identify the failure and leave the bus idle. In this case, the start sequence may not be completed and the ACCESS.bus may remain deadlocked forever. To recover from deadlock, use the following sequence: 1. Clear the ACBST.BER bit and ACBCST.BB bit. 2. Wait for a time-out period to check that there is no other active master on the bus (i.e., ACBCST.BB remains cleared). 3. Disable, and re-enable the ACB to put it in the non-addressed slave mode. 4. At this point some of the slaves may not identify the bus error. To recover, the ACB becomes the bus master by issuing a Start Condition and sends an address field; then issue a Stop Condition to synchronize all the slaves. 19.2.2 Slave Mode ACBST.SDAST is set to indicate that the buffer is empty. — If ACBCTL1.INTEN is set, an interrupt is generated if both the INTEN and NMINTE bits in ACBCTL1 registers are set. — The software then reads the ACBST.XMIT bit to identify the direction requested by the master device. It clears the ACBST.NMATCH bit so future byte transfers are identified as data bytes. Slave Receive and Transmit Slave Receive and Transmit are performed after a match is detected and the data transfer direction is identified. After a byte transfer the ACB extend the acknowledge clock until the software reads or writes the ACBSDA register. The receive and transmit sequence are identical to those used in the master routine. Slave Bus Stall When operating as a slave, this device stalls the ACCESS.bus by extending the first clock cycle of a transaction in the following cases: — ACBST.SDAST is set. — ACBST.NMATCH, and ACBCTL1.NMINTE are set. Slave Error Detections The ACB detects illegal Start and Stop Conditions on the ACCESS.bus (i.e., a Start or Stop Condition within the data transfer or the acknowledge cycle). When an illegal Start or Stop Condition is detected, the BER bit is set and MATCH and GMATCH are cleared, setting the module to be an unaddressed slave. Power Down When this device is in Power Save, Idle, or Halt mode, the ACB module is not active but retains its status. If the ACB is enabled (ACBCTL2.ENABLE=1) on detection of a Start Condition, a wake-up signal is issued to the MIWU module. Use this signal to switch this device to Active mode. The ACB module cannot check the address byte following the start condition that has awaken this device for a match. The ACB responds with a negative acknowledge, and the device should re-send both the Start Condition and the address after this device has had time to wake up. Check that the ACBCST.BUSY bit is inactive before entering Power Save, Idle or Halt mode. This guarantees that this device does not acknowledge an address sent, and stop responding later. 19.2.3 SDA and SCL Pins Configuration A slave device waits in Idle mode for a master to initiate a bus transaction. Whenever the ACB is enabled, and it is not acting as a master (i.e., ACBST.MASTER is cleared), it acts as a slave device. Once a Start Condition on the bus is detected, this device checks whether the address sent by the current master matches either: — The ACBADDR.ADDR value if ACBADDR.SAEN is set. — The general call address if ACBCTL1.GCM is set. This match is checked even when ACBST.MASTER is set. If a bus conflict (on SDA or SCL) is detected, ACBST.BER is set, ACBST.MASTER is cleared and this device continues to search the received message for a match. If an address match, or a global match, is detected: — This device asserts its data pin during the acknowledge cycle. — The ACBCST.MATCH and ACBST.NMATCH bits are set. If ACBST.XMIT is set (i.e., slave transmit mode), The SDA and SCL are open-drain signals. For more information, see the I/O configuration section. 19.2.4 ACB Clock Frequency Configuration The ACB module permits the user to set the clock frequency used for the ACCESS.bus clock. The clock is set by the ACBCTL2.SCLFRQ field. This field determines the SCL clock period used by this device. This clock low period may be extended by stall periods initiated by the ACB module or by another ACCESS.bus device. In case of a conflict with another bus master, a shorter clock high period may be forced by the other bus master until the conflict is resolved. 81 www.national.com 19.3 — — — — — — ACB REGISTERS BER ACB ACB ACB ACB ACB ACB Serial Data Register (ACBSDA) Status Register (ACBST) Status Control Register (ACBCST) Control 1 Register (ACBCTL1) Control 2 Register (ACBCTL2) Own Address Register (ACBADDR) SDAST The ACCESS.bus Interface uses the following registers: 19.3.1 ACB Serial Data Register (ACBSDA) The ACB Serial Data Register (ACBSDA) is a byte-wide, read/write shift register used to transmit and receive data. The most significant bit is transmitted (received) first and the least significant bit is transmitted (received) last. Reading or writing to the ACBSDA register is allowed when ACBST.SDAST is set; or for repeated starts after setting the START bit. An attempt to access the register in other cases produces unpredictable results. 7 DATA 19.3.2 ACB Status Register (ACBST) 0 SLVSTP The ACB Status Register (ACBST) is a byte-wide, read-only register that maintains current ACB status. Upon reset, and when the module is disabled, ACBST is cleared (0016). 7 6 5 4 3 2 1 0 XMIT SLVSTP SDAST BER NEGACK STASTR NMATCH MASTER cleared when the module is disabled. Writing 0 to NEGACK is ignored. Bus Error. BER is set by the hardware when a Start or Stop Condition is detected during data transfer (i.e., Start or Stop Condition during the transfer of bits 2 through 8 and acknowledge cycle), or when an arbitration problem is detected. Writing 1 to BER clears it. It is also cleared when the module is disabled. Writing 0 to BER is ignored. SDA Status. When set, this bit indicates that the SDA data register is waiting for data (transmit - master or slave) or holds data that should be read (receive - master or slave). This bit is cleared when reading from the ACBSDA register during a receive, or when written to during a transmit. When ACBCTL1.START is set, reading ACBSDA register does not clear SDAST. This enables the ACB to send a repeated start in master receive mode. Slave Stop. If set, SLVSTP indicates that a Stop Condition was detected after a slave transfer (i.e., after a slave transfer in which MATCH or GCMATCH is set). Writing 1 to SLVSTP clears it. It is also cleared when the module is disabled. Writing 0 to SLVSTP is ignored. ACB Control Status Register (ACBCST) 19.3.3 XMIT MASTER NMATCH STASTR NEGACK Direction Bit. The XMIT bit is set when the ACB module is currently in master/slave transmit mode. Otherwise it is cleared. MASTER. When set, the MASTER bit indicates that the module is currently in master mode. It is set when a request for bus mastership succeeds. It is cleared upon arbitration loss (BER is set) or the recognition of a Stop Condition. New match. The NMATCH bit is set when the address byte following a Start Condition, or repeated starts, causes a match or a global-call match. NMATCH is cleared when 1 is written to it. Writing 0 to NMATCH is ignored. If ACBCTL1.INTEN is set, an interrupt is sent when this bit is set. Stall After Start. The STASTR bit is set by the successful completion of an address sending (i.e., a Start Condition sent without a bus error, or negative acknowledge) if ACBCTL1.STASTRE is set. This bit is ignored in slave mode. When STASTR is set, it stalls the ACCESS.bus by pulling down the SCL line, and suspends any other action on the bus (e.g., receives first byte in master receive mode). In addition, if ACBCTL1.INTEN is set, it also sends an interrupt to the core. Writing 1 to STASTR clears it. It is also cleared when the module is disabled. Writing 0 to STASTR has no effect. Negative acknowledge. This bit is set by hardware when a transmission is not acknowledged on the ninth clock. (In this case SDAST is not set.) Writing 1 to NEGACK clears it. It is also ACB Control Status Register (ACBCST) is a byte-wide, read/ write register that maintains current ACB status. Upon reset and when the module is disabled, the non-reserved bits of ACBCST are cleared (0). 7 6 5 TGSCL 4 TSDA 3 2 1 BB 0 BUSY Reserved GCMTCH MATCH BUSY BB BUSY. When BUSY is set, it indicates that the ACB module is: • Generating a Start Condition • In Master mode (ACBST.MASTER is set) • In Slave mode (ACBCST.MATCH or ACBCST.GCMTCH is set) • In the period between detecting a Start and completing the reception of the address byte. After this, the ACB either becomes not busy or enters slave mode. The BUSY bit is cleared by the completion of any of the above states, and by disabling the module. BUSY is a read only bit. It should always be written with 0. Bus Busy When set, BB indicates the bus is busy. It is set when the bus is active (i.e., a low level on either SDA or SCL), or by a Start Condition. It is cleared when the module is disabled, upon detection of a Stop Condition, or when writing 1 to this bit. See “Usage Hints” on page 84 for a description of the use of this bit. This bit should be set when either SDA or SCL are low. This should be done by sampling the SDA and SCL lines continuously and, setting the bit if one of them is low. The bit remains set www.national.com 82 MATCH GCMTCH TSDA TGSCL until cleared by a STOP condition or a one is written to it. Address Match. In slave mode, MATCH is set when ACBADDR.SAEN is set and the first seven bits of the address byte (the first byte transferred after a Start Condition) matches the 7-bit address in the ACBADDR register. It is cleared by Start Condition, repeated start and Stop Condition (including illegal Start or Stop Condition). Global Call Match bit. In slave mode, GCMTCH is set when ACBCTL1.GCMEN is set and the address byte (the first byte transferred after a Start Condition) is 0016. It is cleared by Start Condition, repeated Start and Stop Condition (including illegal Start or Stop Condition). Test SDA Line. Reads the current value of the SDA line. This bit can be used while recovering from an error condition in which the SDA line is constantly pulled low by a slave that went out of synch. This bit is a read-only bit. Data written to it is ignored. Toggle SCL Line. This bit enables toggling the SCL line during the process of error recovery. When the SDA line is low, writing 1 to this bit toggles the SCL line for one cycle. Writing 1 to TGSCL when SDA is high is ignored. The bit is cleared when the clock toggle is completed. STOP INTEN ACK 19.3.4 ACB Control 1 Register (ACBCTL1) GCMEN ACB Control 1 Register (ACBCTL1) is a byte-wide, read/ write register that configures and controls the ACB module. Upon reset and while the module is disabled (ACBCTL2.ENABLE=0), the ACBCTL1 is cleared (0016). 7 6 5 4 3 2 1 STOP 0 START STASTRE NMINTE GCMEN ACK Reserved INTEN START START. This bit is set when a Start Condition needs to be generated on the ACCESS.bus. The START bit is cleared when the Start Condition is sent, or upon detection of a Bus Error (ACBST.BER=1). This bit should be set only when in Master mode, or when requesting Master mode. If this device is not the active master of the bus (ACBST.MASTER=0), setting START generates a Start Condition as soon as the ACCESS.bus is free (ACBCST.BB=0). An address send sequence should then be performed. If this device is the active master of the bus (ACBST.MASTER=1), when START is set, a write to the ACBSDA register generates a Start Condition, then the ACBSDA data is transmitted as the slave’s address and the requested transfer direction. This case is a repeated Start Condition. It may be used to switch the direction of the data flow between the master and the slave, or to choose another slave device without using a Stop Condition in between. NMINTE STASTRE STOP In master mode, setting this bit gener. ates a Stop Condition that completes or aborts the current message transfer. This bit clears itself after the STOP is issued. Interrupt Enable. When INTEN is cleared ACB interrupt is disabled. When INTEN is set, interrupts are enabled. An interrupt is generated (the interrupt signals to the ICU is high) upon one of the following events: • An address MATCH is detected (ACBST.NMATCH=1) and NMINTE is set. • A Bus Error occurs (ACBST.BERR=1). • Negative acknowledge after sending a byte (ACBST.NEGACK=1). • An interrupt is generated upon acknowledge of each transaction (same as the hardware set of the ACBST.SDAST bit). • In master mode if ACBCTL1.STASTRE=1, after a successful start (ACBST.STASTR=1). • Detection of a Stop Condition while in slave receive mode (ACBST.SLVSTP=1). Acknowledge bit. When acting as a receiver (slave or master), this bit holds the value this device sends during the next acknowledge cycle. Setting this bit to 1 instructs the transmitting device to stop sending data, since the receiver either does not need, or cannot receive, any more data. This bit is cleared after the first acknowledge cycle. This bit is ignored when in transmit mode. Global Call Match enable. When this bit is set, it enables the match of an incoming address byte to the general call address (Start Condition followed by address byte of 0016) while the ACB is in slave mode. When cleared, the ACB does not respond to a global call. New Match Interrupt Enable. Set NMINTE to enable the interrupt on a new match (i.e., when ACBST.NMATCH is set). The interrupt is issued only if ACBCTL1.INTEN is set. Stall After Start Enable. When set enables the stall after start mechanism. In such a case, the ACB is stalled after the address byte. When STASTRE is cleared, ACBST.STASTR is always cleared. 19.3.5 ACB Control 2 Register (ACBCTL2) The ACB Control 2 register (ACBCTL2) is a byte-wide, read/ write register that enables/disables the module and determines ACB clock rate. Upon reset ACBCTL2 is set to 0016. 7 SCLFRQ ENABLE 1 0 ENABLE SCLFRQ Enable. When this bit is set, the ACB module is enabled. When the Enable bit is cleared, the ACB module is disabled, ACBCTL1, ACBST and ACBCST are cleared, and the clocks are halted. SCL Frequency. This field defines the SCL’s period (low time and high time) when this de- 83 www.national.com vice serves as a bus master. The clock low time and high time are defined as follows: tSCLl = tSCLh = 2*SCLFRQ*tCLK Where tCLK is this device’s clock cycle when in Active mode. SCLFRQ may be programmed to values in the range of 00010002 (810) through 11111112 (12710). Using any other value has unpredictable results. 19.3.6 ACB Own Address Register (ACBADDR) 4. In some cases the bus may get stuck with the SCL and/ or SDA lines active. A possible cause to this is an erroneous Start or Stop Conditions that occur in the middle of a slave receive session. When the SCL line is stuck active, there is nothing that can be done, and it is the responsibility of the module that holds the bus to release it. In case of SDA line is stuck active, the ACB module enable the release of the bus by using the following sequence. Note that in normal cases SCL may be toggled only by the bus master. This protocol is a recovery scheme which is an exception that should be used only in the case where there is no other master on the bus. The recovery scheme is as follows: a. Disable and re-enable the module to set it into the not addressed slave mode. b Set the ACBCTL1.START bit to make an attempt to issue a Start Condition. c. Check if the SDA line is active (low) by reading ACBCST.TSDA bit. If it is active, issue a single SCL cycle by writing 1 to ACBCST.TGSCL bit. If the SDA line is not active, continue from step ‘e’. d. Check if ACBST.MASTER is set, which indicates that the Start Condition was sent. If not, repeat step c and d until the SDA is released. e. Clear the BB bit. This enables the START bit to be executed. Continue according to “Bus Idle Error Recovery” on page 81. ACB Own Address Register (ACBADDR) is a byte-wide, read/write register that holds the module’s ACCESS.bus address. Reset value is undefined. 7 SAEN 6 ADDR 0 ADDR SAEN Own Address. Holds the 7-bit ACCESS.bus address of this device. When in slave mode, the first seven bits received after a Start Condition are compared to this field (first bit received to bit-6, and the last to bit-0). If the address field matches the received data and SAEN is set, a match is declared. Slave Address Enable. When set SAEN indicates that the ADDR field holds a valid address and enables the match of ADDR to an incoming address byte. When cleared, the ACB does not check for an address match. 19.4 USAGE HINTS 1. When the ACB is disabled the ACBCST.BB bit is cleared. After enabling the ACB (ACBCTL2.ENABLE is set to 1) in systems with more then one master, the bus may be in the middle of a transaction with another device, which is not reflected by BB. There is a need to allow the ACB to synchronize to the bus activity status before issuing a request to become the bus master, to prevent bus errors. Thus, before issuing a request to become the bus master for the first time, the software should check that there is no activity on the bus by checking the BB bit after the bus allowed time-out period. 2. When waking up from power down, before checking ACBCST.MATCH, use ACBCST.BUSY to make sure that the address transaction is over. 3. The BB bit is intended to solve a deadlock in which two, or more, devices detect a usage conflict on the bus and both devices cease being bus masters at the same time. In this situation, the BB bits of both devices are active (because each deduces that there is another master currently performing a transaction, while in fact no device is executing a transaction), and the bus would stay locked until some device sends a ACBCTL1.STOP condition. The ACBCST.BB bit allows the software to monitor bus usage, so it can avoid sending a STOP signal in the middle of the transaction of some other device on the bus. This bit detects whether the bus remains unused over a certain period, while the BB bit is set. www.national.com 84 20.0 CR16CAN Module The CR16CAN device contains a FULL-CAN class, CAN (Controller Area Network) serial bus interface for low/high speed applications. It supports the reception and transmission of extended frames with 29-bit identifier, standard frames with 11-bit identifier, applications that require a high speed (up to 1MBit/s), and a low speed CAN interface with CAN master capability. The data transfer between CAN and the CPU is established by 15 message buffers, which can be individually configured as receive or transmit buffers. Every message buffer includes a status/control register which provides information about its current status and capabilities to configure the buffer. All message buffers are able to generate an interrupt upon the reception of a valid frame or the successful transmission of a frame. In addition, an interrupt on bus errors can be generated. An incoming message is only accepted if the message identifier passes one of two acceptance filtering masks. The filtering mask can be configured to receive a single message ID per buffer or a group of IDs per receive buffer. One of the buffers uses a separate message filtering procedure. This provides the capability to establish a BASIC-CAN path. Remote transmission requests can be processed automatically by automatic reconfiguration to a receiver after transmission or by automated transmit scheduling upon reception. A priority decoder allows any buffer to have one of 16 transmit priorities including the highest or lowest absolute priority, totaling 240 different transmit priorities. A decided bit time counter (16-bit wide) is provided to support real time applications. The contents of this counter is captured into the message buffer RAM upon reception or transmission. The counter can be synchronized via the CAN network. This synchronization feature allows a reset of the counter after the reception or transmission of a message in buffer 0. The CR16CAN is a fast core bus peripheral which allows single cycle byte or word read/write access. The CPU controls the CR16CAN by modifying the various registers in the CR16CAN register block. This includes the initialization of the CAN baud rate, the CAN pin logic level, and the enable/ disable of the CR16CAN. A set of diagnostic features, such as loopback, listen only and error identification, support the development with the CR16CAN module and provide a sophisticated error management tool. The CR16CAN implements the following features: • CAN specification 2.0B — standard data and remote frames — extended data and remote frames — 0 - 8 bytes data length — programmable bit rate up to 1 Mbit/s 15 message buffers, each configurable as receive or transmit buffers — message buffers are 16-bit wide dual-port RAM — one buffer may be used as BASIC-CAN path Remote Frame support — automatic transmission after reception of a Remote Transmission Request (RTR) — auto receive after transmission of a RTR • Acceptance filtering — two filtering capabilities: global acceptance mask & individual buffer identifiers — one of the buffers uses an independent acceptance filtering procedure Programmable transmit priority Interrupt capability — one interrupt vector for all message buffers (receive/ transmit/error) — each interrupt source can be enabled/disabled 16-bit counter with time stamp capability on successful reception or transmission of a message Power Save capabilities with programmable Wake-Up over the CAN bus (alternate source for the Multi-Input Wake-Up module) Push-Pull capability of the input/output pins Diagnostic functions — error identification — loopback and listen-only features for test and initialization purposes • • • • • • 20.1 FUNCTIONAL DESCRIPTION As shown in Figure 44, the CR16CAN module is separated into three blocks: the CAN core, the interface management and a dual ported RAM containing the message buffers. There are two dedicated device pins for the CR16CAN interface, CANTX as the transmit output and CANRX as the receive input. The CAN Core implements the basic CAN protocol features such as bit-stuffing, CRC calculation/checking and error management. It controls the transceiver logic and creates error signals according to the bus rules. In addition, it converts the data stream from the CPU (parallel data) to the serial CAN bus data. The Interface Management is divided into the register block and the interface management processor. The register block provides the CAN Interface with control information from the CPU and in turn provides the CPU with status information from the CAN module. Additionally it generates the interrupt to the CPU. The interface management processor is a state machine executing the CPU’s transmission and reception commands and controlling the data transfer between several message buffers and RX/TX shift registers. Fifteen Message Buffers are memory mapped into RAM to transmit/receive data via the CAN bus. Eight 16-bit registers belong to each buffer. One of the registers contains control and status information about the message buffer configuration and the current state of the buffer. The other registers are used for the message identifier, a maximum of up to eight data bytes and the time stamp information. During the receive process the incoming message will be stored at first in a hidden receive buffer until the message is valid. Then the buffer contents will be copied into the first message buffer which accepts the ID of the received message. • • 85 www.national.com CANTX 2:1 01 CANRX wakeup CTX 01 2:1 CRX CAN CORE Transceiver Logic BTL, RX shift, TX shift, CRC Bit Stream Processor Error Management Logic control status RAM data INTERFACE MANAGEMENT Interface Management Processor Acceptance Filtering control TX/RX Message Buffer 0 STATUS REGISTER BTL CONFIG CAN PRESCALER CONTROL ACCEPTANCE MASKS data TX/RX Message Buffer 1 TX/RX Message Buffer 14 core bus Figure 44. Block Diagram CR16CAN Interface Every CAN Frame is broadcasted on the common bus. Each module receives every frame and filters out the frames which are not required for the module's task. For example, if a dashboard sends a request to switch on headlights, the CAN module responsible for brake lights must not process this message. A CAN master module has the ability to set a specific bit called the “remote data request bit” (RTR) in a frame. Such a 20.2 BASIC CAN CONCEPTS This section provides a generic overview of the basic concepts of the Controller Area Network (CAN). The CAN protocol is a message based protocol that allows a total of 2032 ( = 211-16) different messages in the standard format and 512 million ( = 229-16) different messages in the extended frame format. www.national.com 86 message is also called “Remote Frame”. It causes another module, either another master or a slave which accepts this remote frame, to transmit a data frame after the remote frame has been completed. Additional modules can be added to an existing network without a configuration change. These modules can either perform completely new functions requiring new data, or process existing data to perform a new functionality. As the CAN network is message oriented, a message can be used as a variable which is automatically updated by the con- trolling processor. If any module cannot process information, it can send an overload frame. The CAN protocol allows several transmitting modules to start a transmission at the same time as soon as they monitor the bus to be idle. During the start of transmission, every node monitors the bus line to detect whether its message is overwritten by a message with a higher priority. As soon as a transmitting module detects another module with a higher priority accessing the bus, it stops transmitting its own frame and switches to receive mode. For illustration, see Figure 45. TxPIN MODULE A RxPIN TxPIN MODULE B RxPIN BUS LINE RECESSIVE DOMINANT MODULE A SUSPENDS TRANSMISSION Figure 45. CAN message arbitration After five consecutive bits of the same value (including inserted stuff bits so that the stuffed bit stream will not have more than five consecutive bits of the same value), a stuff bit of the inverted value is inserted into the bit stream by the transmitter and deleted by the receiver. The following shows the stuffed and destuffed bit stream for consecutive ones and zeros. If a data or remote frame loses arbitration on the bus due to a higher-prioritized data or remote frame, or if it is destroyed by an error frame, the transmitting module will automatically retransmit it until the transmission was successful or the user has canceled the transmit request. If a transmitted message loses arbitration, the CR16CAN will restart transmission at the next possible time with the message which has the highest internal transmit priority. 20.2.1 CAN Frame Formats Communication via the CAN bus is basically established by means of four different frame types: — — — — data frame remote frame error frame overload frame original or destuffed bit stream stuffed bit stream 10000011111x a 01111100000x 1000001111101x 0111110000010x a. x = {0,1} Frame Fields Data and remote frames consist of the following different bit fields: — — — — — — — Start of Frame Arbitration Field Control Field Data Field CRC Field ACK Field EOF Field Data and remote frames can be used in both standard and extended frame format. If no message is being transmitted, i.e., the bus is idle, the bus is kept at the ‘recessive’ level. Remote and data frames are non-return to zero (NRZ) coded with bit-stuffing in every bit field, which holds computable information for the interface, i.e., start of frame, arbitration field, control field, data field (if present) and CRC field. Error and overload frames are also NRZ coded but without bit-stuffing. 87 www.national.com The Start of Frame indicates the beginning of data and remote frames. It consists of a single 'dominant' bit. A node is only allowed to start transmission when the bus is idle. All nodes have to synchronize to the leading edge (first edge after the bus was idle) caused by SOF of the node which starts transmission first. The Arbitration field consists of the identifier field and the RTR (Remote Transmission Request) bit. For extended frames there is also a SRR (Substitute Remote Request) and a IDE (ID Extension) bit inserted between ID18 and ID17 of the identifier field. The value of the RTR bit is 'dominant' in a data frame and 'recessive' in a remote frame. The Control field consists of six bits. For standard frames it starts with the ID Extension bit (IDE) and a reserved bit (RB0). For extended frames the control field starts with two reserved bits (RB1, RB0). These bits are followed by the 4bit Data Length Code (DLC). The CR16CAN receiver accepts all possible combinations of the reserved bits (RB1, RB0). The transmitter must be configured to send only '0' bits. The DLC indicates the number of bytes in the data field. It consists of four bits. The data field can be of length zero. The admissible number of data bytes for a data frame ranges from 0 to 8. The Data field consists of the data to be transferred within a data frame. It can contain 0 to 8 bytes. A remote frame has no data field. The CRC field consists of the CRC sequence followed by the CRC delimiter. The CRC sequence is derived by the transmitter from the modulo 2 division of the preceding bit fields, starting with the SOF up to the end of the data field, excluding stuff-bits, by the generator polynomial: x15 + x14 + x10 + x8 + x7 + x4 + x3 + 1 The remainder of this division is the CRC sequence transmitted over the bus. On the receiver side, the module divides all bit fields up to the CRC delimiter excluding stuff-bits, and checks if the result is zero. This will then be interpreted as a valid CRC. After the CRC sequence a single ‘recessive’ bit is transmitted as the CRC delimiter. The ACK field is two bits long and contains the ACK slot and the ACK delimiter. The ACK slot is filled with a ‘recessive’ bit by the transmitter. This bit is overwritten with a ‘dominant’ bit by every receiver that has received a correct CRC sequence. The second bit of the ACK field is a ‘recessive’ bit called the acknowledge delimiter. The End of Frame field closes a data and a remote frame. It consists of seven ‘recessive’ bits. STANDARD DATA FRAME (number of bits = 44 + 8N) START OF FRAME ID 10 8N ( 0 Arbitration Field Control Field ≤ N ≤ 8) 8 16 CRC FIELD CRC DEL ACKNOWLEDGEMENT ACK DEL DATA FIELD END OF FRAME 11 ID0 RTR IDE RB0 DLC3 4 DLC0 8 15 CRC d IDENTIFIER 10 ... 0 d dd DATA LENGTH CODE Bit Stuffing r rrrrrrrr EXTENDED DATA FRAME (number of bits = 64 + 8N) START OF FRAME ID28 8N ( 0 Arbitration Field Control Field ≤ N ≤ 8) 8 16 CRC FIELD CRC DEL ACK ACK DEL END OF FRAME DATA FIELD 11 ID18 SRR IDE ID17 18 ID0 RTR RB1 RB0 DLC3 4 DLC0 8 15 CRC d IDENTIFIER 28 ... 18 rr IDENTIFIER 17 ... 0 ddd DATA LENGTH CODE r rrrrrrrr Bit Stuffing Note: d = dominant r = recessive Figure 46. www.national.com CAN Data Frame (standard and extended) 88 A CAN data frame consists of the following fields as previously described: — — — — — Start of Frame (SOF) Arbitration field + Extended Arbitration Control field Data field Cyclic Redundancy Check field (CRC) — Acknowledgment field (ACK) — End of Frame (EOF) Remote Frame Figure 47 shows the structure of a standard and extended remote frame. STANDARD REMOTE FRAME (number of bits = 44) START OF FRAME ID 10 16 Arbitration Field Control Field CRC FIELD CRC DEL ACKNOWLEDGEMENT ACK DEL END OF FRAME 11 ID0 RTR IDE RB0 DLC3 ID3 4 DLC0 15 CRC d IDENTIFIER 10 ... 0 r dd DATA LENGTH CODE r rrrrrrr r EXTENDED REMOTE FRAME (number of bits = 64) START OF FRAME ID28 16 Arbitration Field Control Field CRC FIELD CRC DEL ACK ACK DEL END OF FRAME 11 ID18 SRR IDE ID17 18 ID0 RTR RB1 RB0 DLC3 4 DLC0 15 CRC d IDENTIFIER 28 ... 18 rr IDENTIFIER 17 ... 0 r dd DATA LENGTH CODE r rrrrrrr r Note: d = dominant r = recessive Figure 47. CAN Remote Frame (standard and extended) error is detected, transmission of the error flag starts at the bit following the acknowledge delimiter, unless an error flag for a previous error condition has already been started. If a device is in the error active state, it can send a ‘dominant’ error flag, whereas a error passive device is only allowed to transmit ‘recessive’ error flags. This is done to prevent the CAN bus from getting stuck due to a local defect. For the various CAN device states, please refer to Error Detection and Management on page 91. A remote frame is comprised of the following fields sections, which is the same as a data frame (see Frame Fields on page 87) except for the data field, which is not present. — — — — — — Start of Frame (SOF) Arbitration field + Extended Arbitration Control field Cyclic Redundancy Check field (CRC) Acknowledgment field (ACK) End of Frame (EOF) Note that the DLC must have the same value as the corresponding data frame to prevent contention on the bus. The RTR bit is ‘recessive’. Error Frame As shown in Figure 48, the Error Frame consists of the error flag and the error delimiter bit fields. The error flag field is built up from the various error flags of the different nodes. Therefore, its length may vary from a minimum of six bits up to a maximum of twelve bits depending on when a module has detected the error. Whenever a bit error, stuff error, form error, or acknowledgment error is detected by a node, this node starts transmission of an error flag at the next bit. If a CRC 89 www.national.com ERROR FRAME 6 DATA FRAME OR REMOTE FRAME ERROR FLAG ≤6 ECHO ERROR FLAG 8 ERROR DELIMITER INTER-FRAME SPACE OR OVERLOAD FRAME ddddddd ddr r r r r r r rd Note: d = dominant r = recessive An error frame can start anywhere within a frame. Figure 48. CAN Error Frame Overload Frame As shown in Figure 49, an overload frame consists of the overload flag and the overload delimiter bit fields. The bit fields have the same length as the error frame field: six bits for the overload flag and eight bits for the delimiter. The overload frame can only be sent after the end of frame (EOF) field and in this way destroys the fixed form of the intermission field. As a result, all other nodes also detect an overload con- dition and start the transmission of an overload flag. After an overload flag has been transmitted, the overload frame is closed by the overload delimiter. Note: The CR16CAN never initiates an overload frame due to its inability to process an incoming message. However, it is able to recognize and respond to overload frames initiated by other devices. OVERLOAD FRAME 6 END OF FRAME OR OVERLOAD ERROR DELIMITER OR FLAG OVERLOAD DELIMITER 8 OVERLOAD DELIMITER INTER-FRAME SPACE OR ERROR FRAME dddddddr r r r r r r r Note: d = dominant r = recessive An overload frame can only start at the end of a frame. Figure 49. CAN Overload Frame www.national.com 90 Interframe Space Data and remote frames are separated from every preceding frame (data, remote, error and overload frames) by the interframe space (see Figure 50). Error and overload frames are not preceded by an interframe space; they can be transmitted as soon as the condition occurs. The interframe space consists of a minimum of three bit fields depending on the error state of the node. INTERFRAME SPACE 3 INT ANY FRAME 8 SUSPEND TRANSMIT BUS IDLE START OF FRAME DATA FRAME OR REMOTE FRAME rrrrrrrrrrrrrrrrrrrr INT = Intermission Suspend Transmission is only for error passive nodes. rrrd Note: d = dominant r = recessive Figure 50. 20.2.2 Error Detection and Management CAN Interframe Space Error States The device can be in one of four states with respect to error handling (see Figure 51) — Synchronize Once the CR16CAN is enabled, it goes into a synchronization state to synchronize with the bus by waiting for 11 consecutive recessive bits. After that the CR16CAN becomes error active and can participate in the bus communication. This state must also be entered after waking-up the device via the Multi-Input Wake-Up feature. See System Start-Up and Multi-Input Wake-Up on page 113. — Error active An error active unit can participate in bus communication and may send an active (‘dominant’) error flag. — Error Warning The Error Warning state is a sub-state of Error Active to indicate a heavily disturbed bus. The CR16CAN behaves as in Error Active mode. The device is reset into the Error Active mode if the value of both counters is less than 96. — Error passive An error passive unit can participate in bus communication. However, if the unit detects an error it is not allowed to send an active error flag. The unit sends only a passive (‘recessive’) error flag. A device is error passive when the transmit error counter or the receive error counter is greater than 127. A device becoming error passive will send an active error flag. An error passive device becomes error active again when both transmit and receive error counter are less than 128. — Bus off A unit that is bus off has the output drivers disabled, i.e., it does not participate in any bus activity. A device is bus off when the transmit error counter is greater than 255. A bus off device will become error active again after monitoring 128*11 ‘recessive’ bits (including bus idle) on the bus. When the device goes from ‘bus off ’ to ‘error active’, both error counters will have the value ‘0’. There are multiple mechanisms in the CAN protocol to detect errors and inhibit erroneous modules from disabling all bus activities. Each CAN module includes two error counters, a receive and a transmit error counter, for error management. Error Types The following errors can be detected: — Bit Error A CAN device which is currently transmitting also monitors the bus. If the monitored bit value is different from the transmitted bit value, a bit error is detected. However, the reception of a ‘dominant’ bit instead of a ‘recessive’ bit during the transmission of a passive error flag, during the stuffed bit stream of the arbitration field or during the acknowledge slot is not interpreted as a bit error. — Stuff Error A stuff error is detected if the bit level after 6 consecutive bit times has not changed in a message field that has to be coded according to the bit stuffing method. — Form Error A form error is detected, if a fixed frame bit (e.g., CRC delimiter, ACK delimiter) does not have the specified value. For a receiver, a ‘dominant’ bit during the last bit of End of Frame does not constitute a frame error. — Bit CRC Error A CRC error is detected if the remainder of the CRC calculation of a received CRC polynomial is non-zero. — Acknowledgment Error An acknowledgment error is detected whenever a transmitting node does not get an acknowledgment from any other node (i.e., when the transmitter does not receive a ‘dominant’ bit during the ACK frame) 91 www.national.com SYNC external RESET or enable CR16CAN 11 consecutive ‘recessive’ bits received (TEC OR REC) > 95 (TEC OR REC) > 127 ERROR ACTIVE (TEC AND REC) < 96 ERROR WARNING (TEC AND REC) < 128 ERROR PASSIVE TEC > 255 128 occurrences of 11 consecutive ‘recessive’ bits BUS OFF Figure 51. Error Counters The CR16CAN module contains two error counters to perform the error management. The receive error counter (REC) and the transmit error counter (TEC) are 8-bits wide, located in the 16-bit wide CANEC register. The counters are modified Table 20 Conditiona Receive Error Counter Conditions b A receiver detects a Bit Error during sending an active error flag. A receiver detects a ‘dominant’ bit as the first bit after sending an error flag After detecting the 14th consecutive ‘dominant’ bit following an active error flag or overload flag, or after detecting the 8th consecutive ‘dominant’ bit following a passive error flag. After each sequence of additional 8 consecutive ‘dominant’ bits. Any other error condition (stuff, frame, CRC, ACK) A valid reception or transmission Transmit Error Counter Conditions A transmitter detects a Bit Error during sending an active error flag After detecting the 14th consecutive ‘dominant’ bit following an active error flag or overload flag or after detecting the 8th consecutive ‘dominant’ bit following a passive error flag. After each sequence of additional 8 consecutive ‘dominant’ bits. Any other error condition (stuff, frame, CRC, ACK) A valid reception or transmission increment by 8 increment by 8 increment by 8 increment by 8 increment by 8 CR16CAN Bus States by the CR16CAN according to the rules listed in Table 20 “Error Counter Handling”. The Error counters can be read by the users software as described under CAN Error Counter Register (CANEC) on page 112. Error Counter Handling Action increment by 1 decrement by 1 unless counter is already 0 increment by 8 decrement by 1 unless counter is already 0 a. This table provides an overview of the CAN error conditions and the behavior of the CR16CAN; for a detailed description of the error management and fault confinement rules, please refer to the CAN Specification 2.0B b. If the MSB (bit 7) of the REC is set, the node is error passive and the REC will not increment any further. www.national.com 92 Special error handling for the TEC counter is performed in the following situations: — A stuff error occurs during arbitration, when a transmitted ‘recessive’ stuff bit is received as a ‘dominant’ bit. This does not lead to an increment of the TEC. — An ACK-error occurs in an error passive device and no ‘dominant’ bits are detected while sending the passive error flag. This does not lead to an increment of the TEC. — If only one device is on the bus and this device transmits a message, it will get no acknowledgment. This will be detected as an error and the message will be repeated. When the device goes ‘error passive’ and detects an acknowledge error, the TEC counter is not incremented. Therefore the device will not go from ‘er- ror passive’ to the ‘bus off ’ state due to such a condition. 20.2.3 Bit Time Logic In the Bit Time Logic (BTL), the CAN bus speed and the Synchronization Jump Width can be configured by the user. CR16CAN divides a nominal bit time into three time segments: synchronization segment, time segment 1 (TSEG1) and time segment 2 (TSEG2). Figure 52 shows the various elements of a CAN bit time. CAN Bit Time The number of time quanta in a CAN bit (CAN Bit Time) lies between 4 and 25. The sample point is positioned between TSEG1 and TSEG2 and the transmission point is positioned at the end of TSEG2. INTERNAL TIME QUANTA CLOCK ONE TIME QUANTUM 4 to 25 tq A 1 tq TIME SEGMENT 1 (TSEG1) 2 to 16 tq TIME SEGMENT 2 (TSEG2) 1 to 8 tq A = synchronization segment (Sync) SAMPLE POINT TRANSMISSION POINT Figure 52. The time segment 1 includes the propagation segment and the phase segment 1 as specified in the CAN specification 2.0.B. The length of the time segment 1 in time quantas (tq) is defined by the TSEG1[3:0] bits. The time segment 2 represents the phase segment 2 as specified in the CAN specification 2.0.B. The length of the time segment 2 in time quantas (tq) is defined by the TSEG2[3:0] bits. The Synchronization Jump Width (SJW) defines the maximum number of time quanta (tq) by which a received CAN bit can be shortened or lengthened in order to achieve resynchronization on ‘recessive’ to ‘dominant’ data transitions on the bus. In the CR16CAN implementation the SJW has to be configured less or equal to TSEG1 or TSEG2, whatever is smaller. Synchronization A CAN device expects the transition of the data signal to be within the synchronization segment of each CAN bit time. This segment has the fixed length of one time quantum. However, two CAN nodes never operate at exactly the same clock rate and furthermore the bus signal may deviate from the ideal waveform due to the physical conditions of the network (bus length and load). In order to compensate for the various delays within a network, the sample point can be po- Bit Timing sitioned by programming the length of time segments 1 and 2 (see Figure 52). In addition to that, two types of synchronization are supported. The BTL logic compares the incoming edge of a CAN bit with the internal bit timing. The internal bit timing can be adapted by either hard or soft synchronization (re-synchronization). Hard synchronization is done at the beginning of a new frame with the falling edge on the bus while the bus is idle. This is interpreted as the SOF. It restarts the internal logic. Soft synchronization is used during the reception of a bit stream to lengthen or shorten the internal bit time. Depending on the phase error (e), the time segment 1 may be increased or the time segment 2 may be decreased by a specific value, the re-synchronization jump width (SJW). The phase error is given by the deviation of the edge to the SYNC segment, measured in CAN clocks. The value of the phase error is defined as: e = 0, if the edge occurs within the SYNC segment. e > 0, if the edge occurs within TSEG1 e < 0, if the edge occurs within TSEG2 of the previous bit. Re-synchronization is performed according to the following rules: 93 www.national.com • • If the magnitude of e is less or equal to the programmed value of SJW, re-synchronization will have the same effect as hard synchronization. If e > SJW, the time segment 1 will be lengthened by the value of the SJW (see Figure 53). • If e < -SJW, the time segment 2 will be shortened by the value SJW (see Figure 54). e BUS SIGNAL CAN CLOCK PREVIOUS BIT A TSEG1 “NORMAL” BIT TIME TSEG2 NEXT BIT PREVIOUS BIT A TSEG1 SJW TSEG2 NEXT BIT BIT TIME LENGTHENED BY SJW Figure 53. Re-synchronization (e > SJW) e BUS SIGNAL CAN CLOCK PREVIOUS A BIT TSEG1 “ NOMINAL” BIT TIME TSEG2 PREVIOUS A BIT TSEG1 BIT TIME SHORTENED BY SJW TSEG2 NEXT BIT Figure 54. 20.2.4 Clock Generator Re-synchronization (e < -SJW) The values of PSC and TSEG 1 and 2 are specified by the contents of the registers PSC, TSEG1 and TSEG2 as follows: PSC = PSC[5:0] + 2 TSEG1 = TSEG1[3:0] + 1 TSEG2 = TSEG2 [2 : 0] + 1 The CAN prescaler (PSC) is shown is Figure 55. It divides the CKI input clock by the value defined in the CTIM register. The resulting clock is called time quanta clock and defines the length of one time quanta (tq). Please refer to CAN Timing Register (CTIM) on page 109 for a detailed description of the CTIM register. Note: PSC is the value of the clock prescaler. TSEG1 and TSEG2 are the length of time segment 1 and 2 in tq. The resulting bus clock can be calculated by the equation: CKI busclock = -----------------------------------------------------------------------------------( PSC ) x ( 1 + TSEG 1 + TSEG 2 ) CKI : PSC : (1+TSEG1+TSEG2) bit rate internal time quanta clock (1/tq) Figure 55. Bit Rate Generation www.national.com 94 20.3 MESSAGE TRANSFER The CR16CAN has access to 15 independent message buffers, memory mapped in RAM. Each message buffer consists of 8 different 16-bit RAM locations and can be individually configured as a receive message buffer or as a transmit message buffer. A dedicated acceptance filtering procedure enables the user to configure each buffer to receive only a single message ID or a group of messages. One buffer uses an independent filtering procedure, which provides the possibility to establish a BASIC-CAN path. For reception of data frame or remote frames, the CR16CAN follows a “receive on first match” rule which means that a given message is only received by one buffer — the first one which matches to the received message ID. The transmission of a frame can be initiated by the user software writing to the transmit status and priority register. An alternate way to schedule a transmission is the automatic answer to remote frames. In the latter case, the CR16CAN will schedule every buffer for transmission to respond to remote frames with a given identifier if the acceptance mask matches. This implies that a single remote frame is able to poll multiple matching buffers configured to respond to the triggering remote transmission request. The acceptance filtering of incoming messages for buffer 14 is done via a separate filtering mask (BMASK) and by the buffer ID of each that buffer. Once a received object is waiting in the hidden buffer (see Receive Buffer Structure on page 97) to be copied into a buffer, CR16CAN scans all buffer configured as receive buffers for a matching filtering mask. The buffers 0 to 13 are checked in ascending order beginning with buffer 0. The contents of the hidden buffer are copied into the first buffer with matching filtering mask. Bits holding a “1” in the global filtering mask (GMASK) can be represented as a “don’t care” of the associated bit of each buffer identifier, regardless of whether the buffer identifier bit is “1” or “0”. This provides the capability to accept only a single ID per buffer or to accept a group of IDs. The following two examples illustrate the difference. Example 1: Acceptance of a Single Identifier If the global mask is set to 0016 the acceptance filtering of an incoming message is only determined by the individual buffer ID. This means that only one message ID is accepted per buffer. GMASK1 00000000 00000000 GMASK2 00000000 00000 20.4 ACCEPTANCE FILTERING Two 32-bit masks are used to filter unwanted messages from the CAN bus GMASK and BMASK. Figure 56 shows the mask and the buffers controlled by the masks. Buffer 0 BUFFER_ID BUFFER_ID1 10101010 10101010 BUFFER_ID2 10101010 10101 Accepted ID 10101010 10101010 10101010 10101 GMASK1 GMASK2 Buffer13 Figure 57. Acceptance of a Single Identifier Example 2: Reception of an Identifier Group BUFFER_ID Bits in the global mask register set to ‘1’ change the corresponding bit status within the buffer ID to “don’t care” (“X”). Therefore all messages which match the non-“don’t care” bits are accepted. GMASK1 00000000 11111111 GMASK2 00000000 00000 Buffer14 BMASK1 BMASK2 BUFFER_ID BUFFER_ID1 10101010 10101010 BUFFER_ID2 10101010 10101 Figure 56. Acceptance Filtering Structure 10101010 Accepted ID group XXXXXXXX 10101010 10101 The acceptance filtering of the incoming messages for the buffers 0...13 is done by means of a global filtering mask (GMASK) and by the buffer ID of each buffer. Figure 58. Acceptance of a Group of Identifiers 95 www.national.com A separate filtering path is used for buffer 14. For this buffer the acceptance filtering is established by the buffer ID in conjunction with the basic filtering mask. This basic mask uses the same method as the global mask. Setting a bit to “1” changes the associated bit in the buffer ID to a “don’t care” bit. Therefore the basic mask allows a large number of infrequent messages to be received by this buffer. Note: If the BMASK register is equal to the GMASK register, the buffer 14 can be used the same way as the buffers 0 to 13. The buffers 0 to 13 are scanned prior to buffer 14. Subsequently, the buffer 14 will not be checked for a matching ID when one of the buffers 0 to 13 has already received an object. By setting the BUFFLOCK bit in the configuration register, the receiving buffer is automatically locked after a reception of one valid frame. The buffer will be unlocked again after the received ID GMASK 01010 00000 10101010 11111111 CPU has read the data and has written RX_READY in the buffer status field. With this lock function, the user has the capability to save several messages with the same identifier or same identifier group into more than one buffer. For example, a buffer with the second highest priority will receive a message if the buffer with the highest priority has already received a message and is now locked (provided that both buffers use the same acceptance filtering mask). As shown in Figure 59, several messages with the same ID are received while BUFFLOCK is enabled. The filtering mask of the buffers 0, 1, 13 and 14 is set to accept this message. The first incoming frame will be received by buffer 0. As buffer 0 is now locked the next frame will be received by buffer 1, and so on. If all matching receive buffers are full and locked, a further incoming message will not be received by any buffer. 10101010 00000000 10101010 00000000 BUFFER0_ID BUFFER1_ID BUFFER13_ID 01010 01010 01010 XXXXXXXX XXXXXXXX XXXXXXXX 10101010 10101010 10101010 10101010 10101010 10101010 saved when buffer is empty saved when buffer is empty saved when buffer is empty BMASK BUFFER14_ID 00000 01010 11111111 XXXXXXXX 00000000 10101010 00000000 10101010 saved when buffer is empty Figure 59. Message Storage with BUFFLOCK Enabled 20.5 RECEIVE STRUCTURE All received frames will initially be buffered in a hidden receive buffer until the frame is valid. (The validation point for a received message is the penultimate bit of EOF.) The received identifier is then compared to every buffer ID together with the respective mask and the status. As soon as the validation point is reached, the whole contents of the hidden buffer is copied into the matching message buffer as shown in Figure 60. Note: The hidden receive buffer must not be accessed by the CPU. The following section gives an overview of the reception of the different types of frames. www.national.com 96 Buffer 0 BUFFER_ID Buffer 13 CR16CAN HIDDEN RECEIVE BUFFER BUFFER_ID All contents of the hidden receive buffer are always copied into the respective receive buffer. This includes the received message ID as well as the received Data Length Code (DLC); therefore when some mask bits are set to don’t care, the ID field will get the received message ID which could be different from the previous ID. The DLC of the receiving buffer will be updated by the DLC of the received frame. Note that the DLC of the received message is not compared with the DLC already present in the CNSTAT register of the message buffer. This implies that the DLC code of the CNSTAT register indicates how may data bytes actually belong to the latest received message. The remote frames are handled by the CR16CAN interface in two different ways. Firstly, remote frames can be received like data frames by configuring the buffer to be RX_READY and setting the ID bits including the RTR bit. In that case the same procedure applies as described for Data Frames. Secondly, a remote frame can trigger one or more message buffer to transmit a data frame upon reception. This procedure is described under To answer Remote Frames on page 99. 20.5.1 Receive Timing Buffer 14 BUFFER_ID Figure 60. Receive Buffer Structure The received data frame will be stored in the first matching receive buffer beginning with buffer 0. For example, if the message is accepted by buffer 5, then at the time the message will be copied, the RX request is cleared and CR16CAN will not try to match the frame to any subsequent buffer. ARBITRATION FIELD SOF + CONTROL BUS IDLE 1 BIT 12/29 BIT + 6 BIT DATA FIELD (IF PRESENT) n * 8 BIT As soon as CR16CAN receives a dominant bit on the CAN bus, the receive process is started. The received ID and data will be stored in the hidden receive buffer if the global or basic acceptance filtering matches. After the reception of the data, CR16CAN tries to match the buffer ID of buffer 0...14. The data will be copied into the buffer after the reception of the 6th EOF bit as a message is valid at this time. The copy process of every frame, regardless of the length, takes at least 17 CKI cycles (see also CPU Access to CR16CAN Registers/Memory on page 103). Figure 61 illustrates the receive timing. CRC FIELD 16 BIT ACK FIELD 2 BIT EOF 7 BIT IFS 3 BIT rx_start copy to buffer BUSY Figure 61. In order to indicate that a frame is waiting in the hidden buffer, the BUSY bit ST[0] of the selected buffer is set during the copy procedure. The BUSY bit will be cleared by CR16CAN right after the data bytes are copied into the buffer. After the copy process is finished, CR16CAN changes the status field to RX_FULL. In turn the CPU should change the status field to RX_READY when the data is processed. When a new object has been received by the same buffer, before the CPU changed the status to RX_READY, the CR16CAN will change the status to RX_OVERRUN to indicate that at least one frame has been overwritten by a new one. Table 21 summa- Receive Timing rizes the current status and the resulting update from the CR16CAN. Table 21 Writing to Buffer Status Code During RX_BUSY Current Status RX_READY RX_NOT_ACTIVE RX_FULL Resulting Status RX_FULL RX_NOT_ACTIVE RX_OVERRUN 97 www.national.com During the assertion of the BUSY bit, all writes to the receiving buffer are disabled with the exception of the status field. If the status is changed during BUSY being active, the status is updated by the CR16CAN as shown in Table 21. The buffer states are indicated and controlled by the ST[3:0] bits in the CNSTAT register (see Buffer Status/Control Register (CNSTAT) on page 104. The various receive buffer states are explained in RX Buffer States on page 99. 20.5.2 Receive Procedure Y read buffer read CNSTAT The user has to execute the following procedure to initialize a message buffer for the reception of a CAN message. 1. Configure the receive masks (GMASK or BMASK, respectively). 2. Configure the buffer ID. 3. Configure the message buffer status as RX_READY. In order to read the out of a received message, the CPU has to execute the following steps (see Figure 62): The first step is only applicable if polling is used to get the status of the receive buffer. It can be deleted for an interrupt driven receive routine. 1. Read the status (CNSTAT) of the receive buffer. If the status is RX_READY, no was the message received, exit. If the status is RX_BUSY, copy process from hidden receive buffer is not completed yet, read CNSTAT again. If a buffer is configured to RX_READY and its interrupt is enabled, it will generate an interrupt as soon as the buffer has received a message and entered the RX_FULL state (see also Interrupts on page 101). In that case the procedure described below should be followed. Read the status to determine if a new message has overwritten the one originally received which triggered the interrupt. Write RX_READY into CNSTAT. Read the ID/data and object control (DLC/RTR) from the message buffer. Read the buffer status again and check it is not RX_BUSYx. If it is, repeat this step until RX_BUSYx has gone away. If the buffer status is RX_FULL or RX_OVERRUN, one or more messages were copied. In that case, start over with step 2. If status is still RX_READY (as set by the CPU at step 2), clear interrupt pending bit and exit. RX_READY? N Y RX_BUSYx? N Interrupt Entry Point RX_OVERRUN? (optional, for information) write RX_READY read buffer (id/data/cntrl) read CNSTAT A new message has been received while reading data from the receive buffer 2. RX_BUSYx? N Y 3. 4. 5. RX_FULL? or RX_OVERRUN? Y N clear RX_PND 6. 7. exit Figure 62. Buffer Read Routine (BUFFLOCK Disabled) www.national.com 98 When the BUFFLOCK function is enabled (see BUFFLOCK on page 96), it is not necessary to check for new messages received during the read process from the buffer, as this buffer is locked after the reception of the first valid frame. A read from a locked receive buffer can be performed as shown in Figure 63. Interrupt Entry Point After successful transmission CR16CAN will reset the buffer status to TX_NOT_ACTIVE. When the transmission process fails, the buffer condition will remain TX_BUSYx for re-transmission until the frame was successfully transmitted or the CPU has canceled the transmission request. In order to Send a Remote Frame (Remote Transmission Request) to other CAN nodes, the user needs to set the RTR bit of the message identifier to “1” (see Storage of Remote Messages on page 107) and change the status of the message buffer to TX_ONCE. After this remote frame has been transmitted successfully, this message buffer will automatically enter the RX_READY state and is ready to receive the appropriate answer. Note that the mask bits RTR/XRTR need to be set to receive a data frame (RTR = 0) in a buffer which was configured to transmit a remote frame (RTR = 1). To answer Remote Frames if the CPU writes TX_RTR in the buffer status register, the buffer will wait for a remote frame. When a remote frame passes the acceptance filtering mask of one or more buffers, the buffer status will change to TX_ONCE_RTR, the contents of the buffer will be transmitted and afterwards CR16CAN will write TX_RTR in the status code register again. If the CPU writes TX_ONCE_RTR in the buffer status, the contents of the buffer will be transmitted, and the successful transmission the buffer goes into the “wait for Remote Frame” condition TX_RTR. 20.6.1 Transmit Scheduling read buffer (id/data/cntrl) write RX_READY clear RX_PND exit Figure 63. Buffer Read Routine (BUFFLOCK Enabled) For simplicity only the applicable interrupt routine is shown: 1. Read the ID/data and object control (DLC/RTR) from the message buffer. 2. Write RX_READY into CNSTAT. 3. Clear interrupt pending bit and exit. 20.5.3 RX Buffer States As shown in Figure 64, a receive procedure starts as soon as the user has set the buffer from the RX_NOT_ACTIVE state into the RX_READY state. The status section of CNSTAT register is set from 00002 to 00102. When a message is received, the buffer will be RX_BUSYx during the copy process from the hidden receive buffer into the message buffer. Afterwards this buffer is RX_FULL. Now the CPU can read the buffer data and either reset the buffer status to RX_READY or receive a new frame before the CPU reads the buffer. In the second case, the buffer state will automatically change to RX_OVERRUN to indicate that at least one message was lost. During the copy process the buffer will again be RX_BUSYx for a short time, but in this case the CNSTAT status section will be 01012, as the buffer was RX_FULL (01002) before. After finally reading the last received message, the CPU can reset the buffer to RX_READY. After writing TX_ONCE in the buffer status, the transmission process begins and the BUSY-bit is set. As soon as a buffer gets the TX_BUSY status, the buffer is not accessible anymore by the CPU except for the ST[3:1] bits of the CNSTAT register. Starting with the beginning of the CRC field of the current frame, CR16CAN looks for another buffer transmit request and selects the buffer with the highest priority for the next transmission by changing the buffer state from TX_ONCE to TX_BUSY. This transmit request can be canceled by the CPU or can be overwritten by another transmit request of a buffer with a higher priority as long as the transmission of the next frame has not yet started. This means that between the beginning of the CRC field of the current frame and the transmission start of the next frame, two buffers, the current buffer and the buffer scheduled for the next transmission, are in the BUSY status. In order to cancel the transmit request of the next frame, the CPU has to change the buffer state to TX_NOT_ACTIVE. When the transmit request has been overwritten by another request of a higher priority buffer, CR16CAN changes the buffer state from TX_BUSY to TX_ONCE. Thus, the transmit request remains pending. Figure 64 further illustrates the transmit timing. If the transmit process fails or the arbitration is lost, the transmission process will be stopped and will continue after the interrupting reception or the error signaling has finished (see Figure 65). In that case a new buffer select follows and the TX process is executed again. Note: The canceled message can be delayed by a TX request of a buffer with a higher priority. During TX_BUSY high, the user cannot change the contents of the message buffer object. In all cases writing to the BUSY bit will be ignored. 20.6 TRANSMIT STRUCTURE In order to transmit a CAN message, the user has to configure the message buffer by changing the buffer status to TX_NOT_ACTIVE. The buffer is configured for transmission if the ST[3] bit of the buffer status code (CNSTAT) is set to ‘1’. In TX_NOT_ACTIVE status, the buffer is ready to receive data from the CPU. After receiving all transmission data (ID, data bytes, DLC and PRI), the CPU can start the transmission by writing TX_ONCE into the buffer status register. During the transmission the status of the buffer is TX_BUSYx. 99 www.national.com ARBITRATION FIELD DATA FIELD (IF PRESENT) BUS IDLE SOF + CONTROL 1 BIT 12/29 BIT + 6 BIT n * 8 BIT CRC FIELD 16 BIT ACK FIELD 2 BIT EOF 7 BIT IFS 3 BIT TX_BUSY current buffer TX_BUSY next buffer CPU write TX_ONCE in buffer status begin selection of next buffer if new tx_request Figure 64. 20.6.2 Transmit Priority Data Transmission Table 23 shows the transmit priority configuration if TXPRI is different from the buffer number: Table 23 TXPRI 14 13 12 11 10 Transmit Priority (TXPRI not 0) Buffer Number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PRI 224 209 194 179 164 149 134 119 104 89 74 59 44 29 14 highest TX Priority lowest CR16CAN is able to generate a stream of scheduled messages without releasing the bus between two messages so that an optimized performance can be achieved. It will arbitrate for the bus right after sending the previous message and will only release the bus due to a lost arbitration. If more than one buffer is scheduled for transmission, the priority is built by the message buffer number and the priority code in the CNSTAT register. The 8-bit value of the priority is combined by the 4-bit TXPRI value and the 4-bit buffer number (0...14) as shown below. The lowest resulting number results in the highest transmit priority. TXPRI BUFFER # 9 8 7 6 Table 22 shows the transmit priority configuration if the priority is set to TXPRI = 0 for all transmit buffers: Table 22 TXPRI 0 0 : : 0 Transmit Priority (TXPRI=0) PRI 0 1 : : 14 : : lowest TX Priority highest Buffer Number 0 1 : : 14 5 4 3 2 1 0 Note: If two buffers have the same priority (PRI), the buffer with the lower buffer number will have the higher priority. www.national.com 100 20.6.3 Transmit Procedure 20.6.4 TX Buffer States The transmission of a CAN message has to be executed as follows (see also Figure 65) 1. Configure CNSTAT status field as TX_NOT_ACTIVE. If the status is TX_BUSY, a previous transmit request is still pending and the user has no access to the data contents of the buffer. In that case the user may choose to wait until the buffer becomes available again as shown. Other options are to exit from the update routine until the buffer has been transmitted with an interrupt generated, or the transmission is aborted by an error. 2. Load buffer identifier & data registers. (For remote frames the RTR bit of the identifier needs to be set and loading data bytes can be omitted.) 3. Configure CNSTAT status field to the desired value: — TX_ONCE to trigger the transmission process of a single frame. — TX_ONCE_RTR to trigger the transmission of a single data frame and then wait for a received remote frame to trigger consecutive data frames. — TX_RTR waits for a remote frame to trigger the transmission of a data frame. Writing TX_ONCE or TX_ONCE_RTR in the CNSTAT status field will set the internal transmit request for the CR16CAN. If a buffer is configured as TX_RTR and a remote frame is received, the data contents of the addressed buffer will be transmitted automatically without further CPU activity. The transmission process can be started after the user has loaded the buffer registers (data, ID, DLC, PRI) and set the buffer status from TX_NOT_ACTIVE to TX_ONCE, TX_RTR or TX_ONCE_RTR. When the CPU writes TX_ONCE, the buffer will be TX_BUSY as soon as CR16CAN has scheduled this buffer for the next transmission. After the frame could be successfully transmitted, the buffer status will be automatically reset to TX_NOT_ACTIVE when a data frame was transmitted or to RX_READY when a remote frame was transmitted. If the CPU configures the message buffer to TX_ONCE_RTR, it will transmit its data contents. During the transmission the buffer state is 11112 as the CPU wrote 11102 into the status section of the CNSTAT register. After the successful transmission the buffer enters the TX_RTR state and waits for a remote frame. When it receives a remote frame, it will go back into the TX_ONCE_RTR state, transmit its data bytes and return to TX_RTR. If the CPU writes 10102 into the buffer status section, it will only enter the TX_RTR state. But it will not send its data bytes before it waits for a remote frame. Figure 66 illustrates the possible transmit buffer states. 20.7 INTERRUPTS CR16CAN has access to one interrupt vector in the CR16 CPU. The interrupt process can be initiated from the following sources. • CAN data transfer — Reception of a valid data frame in the buffer. (Buffer state changes from RX_READY to RX_FULL or RX_OVERRUN). — Successful transmission of a data frame. (Buffer state changes from TX_ONCE to TX_NOT_ACTIVE or RX_READY) — Successful response to a remote frame. (Buffer state changes from TX_ONCE_RTR to TX_RTR). — Transmit scheduling. (Buffer state changes from TX_RTR to TX_ONCE_RTR). CAN error conditions is the detection of an CAN error. (The CEIPND bit in the CIPND register will be set as well as the corresponding bits in the error diagnostic register CEDIAG). write_buffer write TX_NOT_ACTIVE TX_BUSYx? N Y (see text) • write ID/data write TX_ONCE or TX_ONCE_RTR or TX_RTR The receive/transmit interrupt access to every message buffer can be individually enabled/disabled in the CIEN register. The pending flags of the message buffer are located in the CIPND register (read only) and can be cleared by resetting the flags in the CICLR registers. 20.7.1 Highest Priority Interrupt Code exit In order to reduce decoding time of the CIPND register, the buffer interrupt request with the highest priority is placed as interrupt status code into the IST[3:0] section of the CSTPND register. Figure 65. Buffer Write Routine 101 www.national.com TX_ONCE_RTR 1110 RTR received CAN schedules TX TX request CPU writes 1110 TX_BUSY2 1111 transmit failed TX done transmit request cancelled CPU writes 1000 CPU writes 1010 TX_RTR 1010 TX request CPU writes 1100 TX_NOT_ACTIVE 1000 TX done *1: TX request delayed by a TX request of higher priority message TX_ONCE 1100 CAN schedules TX *1 TX_BUSY0 1101 RX_READY 0010 Remote transmission request sent - now wait to receive a data frame transmit failed Figure 66. Transmit Buffer States transmit request cancelled CPU writes 1000 Each of the buffer interrupts as well as the error interrupt can be individually enabled or disabled in the CAN Interrupt Enable register (CIEN). As soon as an interrupt condition occurs, every interrupt request is indicated by a flag in the CAN Interrupt Pending register (CIPND). When the interrupt code logic for the present highest priority interrupt request is enabled, this interrupt will be translated into the IST[3:0] bits of the CAN Status Pending register (CSTPND). An interrupt request can be cleared by setting the corresponding bit in the CAN Interrupt Clear register (CICLR) to ‘1’. Figure 67 illustrates the CR16CAN interrupt management. CIEN CICLR clear interrupt flags of every message buffer individually CIPND CICEN ICODE IRQ IST3 IST2 IST1 IST0 Figure 67. www.national.com CR16CAN Interrupt Management 102 The highest priority interrupt source is translated into the bits IRQ and IST[3:0] as shown in Table 24. Table 24 Highest Priority Interrupt Code (ICEN=FFFF) or reception of a message. Figure 68 shows a simplified block diagram of the Time Stamp counter. +1 Reset CAN bits on the bus ACK slot & buffer 0 active ACK slot 16-bit counter CAN interrupt request no request Error interrupt Buffer 0 Buffer 1 Buffer 2 Buffer 3 Buffer 4 Buffer 5 Buffer 6 Buffer 7 Buffer 8 Buffer 9 Buffer 10 Buffer 11 Buffer 12 Buffer 13 Buffer 14 20.7.2 IRQ 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 IST3 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 IST2 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 IST1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 IST0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Figure 68. Time Stamp Counter TSTP register The timer can be synchronized over the CAN network by receiving or transmitting a message to/from buffer 0. In that case the TSTP register of buffer 0 captures the current CTMR value during the ACK slot of a message (as above) and afterwards the CTMR is reset to 00002. Synchronization can be enabled or disabled via the CGCR.TSTPEN bit. 20.9 MEMORY ORGANIZATION CR16CAN occupies 144 words in the memory address space. This space is separated into 15*8 + 8(reserved) words for the message buffers and 14 + 2(reserved) words for control and status. 20.9.1 CPU Access to CR16CAN Registers/Memory Usage Hints The interrupt code IST[3:0] can be used within the interrupt handler as a displacement in order to jump to the relevant subroutine. The CAN Interrupt Code Enable (CICEN) register is used in the CAN interrupt handler if the user wants to service all receive buffer interrupts first followed by all transmit buffer interrupts. In this case, the user can first enable only all receive buffer interrupts to be coded, scan and service all pending interrupt requests in the order of their priority. Then, the user changes the CICEN register to disable all receive buffers, but enable all transmit buffers and service all pending transmit buffer interrupt requests according to their priorities. All memory locations occupied by the message buffers are shared by the CPU and CR16CAN (dual ported RAM). The CR16CAN and the CPU normally have single cycle access to this memory. However, if an access contention occurs, the access to the memory is altered every cycle until the contention is resolved. This internal access arbitration is transparent to the user. Both word and byte access to the buffer RAM are allowed. If a buffer is busy during the reception of an object (copy process from the hidden receive buffer) or is scheduled for transmission, the CPU has no write access to the data contents of the buffer. Write to the status/control byte and read access to the whole buffer is always enabled. All configuration and status registers can either be accessed by CR16CAN or the CPU only. These registers provide single cycle word and byte access without any potential wait state. All register descriptions within the next sections utilize the following layout: bit 15 ... bit number ... bit 0 20.8 TIME STAMP COUNTER CR16CAN features a free running 16-bit timer (CTMR) incrementing every bit time recognized on the CAN bus. The value of this timer during the ACK slot is captured into the TSTP register of a message buffer after a successful transmission ... bit name ... ... reset value ... ... CPU access ... r = register bit is read only w = register bit is write only r/w = register bit is read/write 103 www.national.com 20.9.2 Message Buffer Organization The message buffers are the communication interfaces between CAN and the CPU for the transmission and the reception of CAN frames. There are 15 message buffers located at fixed addresses in the RAM location. As shown in Table 25, Table 25 ADDR xxxE16 xxxC16 xxxA16 xxx816 xxx616 xxx416 xxx216 xxx016 each buffer consists of two words reserved for the identifiers, 4 words reserved for up to eight CAN data bytes, one word is reserved for time stamp and one word for data length code, transmit priority code and the buffer status code. Message Buffer Organization 11 XI24 ID6 XI10 Data 1.3 Data 3.3 Data 5.3 Data 7.3 BUFFER register ID1 ID0 DATA0 DATA1 DATA2 DATA3 TSTP CNTSTAT 15 XI28 ID10 XI14 Data 1.7 Data 3.7 Data 5.7 Data 7.7 TSTP15 DLC3 14 XI27 ID9 XI13 Data 1.6 Data 3.6 Data 5.6 Data 7.6 TSTP14 DLC2 13 XI26 ID8 XI12 Data 1.5 Data 3.5 Data 5.5 Data 7.5 TSTP13 DLC1 12 XI25 ID7 XI11 Data 1.4 Data 3.4 Data 5.4 Data 7.4 TSTP12 DLC0 10 XI23 ID5 XI9 Data 1.2 Data 3.2 Data 5.2 Data 7.2 TSTP10 9 XI22 ID4 XI8 Data 1.1 Data 3.1 Data 5.1 Data 7.1 TSTP 9 8 XI21 ID3 XI7 Data 1.0 Data 3.0 Data 5.0 Data 7.0 TSTP 8 7 XI20 ID2 XI6 Data 2.7 Data 4.7 Data 6.7 Data 8.7 TSTP 7 PRI3 6 XI19 ID1 XI5 Data 2.6 Data 4.6 Data 6.6 Data 8.6 TSTP 6 PRI2 5 XI18 ID0 XI4 Data 2.5 Data 4.5 Data 6.5 Data 8.5 TSTP 5 PRI1 4 SRR RTR 3 IDE XI2 Data 2.3 Data 4.3 Data 6.3 Data 8.3 TSTP 3 ST3 2 XI17 XI1 Data 2.2 Data 4.2 Data 6.2 Data 8.2 TSTP 2 ST2 1 XI16 XI0 Data 2.1 Data 4.1 Data 6.1 Data 8.1 TSTP 1 ST1 0 XI15 RTR Data 2.0 Data 4.0 Data 6.0 Data 8.0 TSTP 0 ST0 XI3 Data 2.4 Data 4.4 Data 6.4 Data 8.4 TSTP 4 PRI0 TSTP11 Reserved 20.9.3 Buffer Status/Control Register (CNSTAT) The buffer status, the buffer priority and the data length code are controlled by manipulating the contents of the Buffer Status/Control Register (CNSTAT). CPU and CR16CAN have access to this register. 15 12 11 87 4 DLC[3:0] Reserved PRI[3:0] 0 r/w 3 ST[3:0] 0 PRI[3:0] DLC[3:0] ST[3:0] Buffer Status — The CNSTAT register has a status section, which contains the status information of the buffer as shown in Table 26. This section can be modified by CR16CAN. The ST0 bits acts as a buffer busy indication. When the BUSY bit is set, any write access to the buffer is disabled with the exception of the lower byte of the CNTSTAT register. The Table 26 CR16CAN sets this bit if the buffer data is currently copied from the hidden buffer or if a message is scheduled for transmission or is currently transmitting. The CR16CAN will always reset this bit on a status update. Transmit Priority Code. The PRI[3:0] bits contain the user defined transmit priority code for the message buffer. Data Length Code. The DLC[3:0] bits determine the number of data bytes within a received/transmitted frame. For transmission, these bits need to be set according to the number of data bytes to be transmitted. For reception, these bits indicate the number of valid received data bytes available in the message buffer. Table 27 shows the possible bit combinations for DLC[3:0] for data lengths from 0 to 8 bytes. Buffer Status Section of the CNSTAT Register ST0 (BUSY) 0 1 0 1 0 1 0 1 0 1 0 Buffer Status RX_NOT_ACTIVE Reserved for RX_BUSY a RX_READY RX_BUSY0 b RX_FULL RX_BUSY1 b RX_OVERRUN RX_BUSY2 b TX_NOT_ACTIVE Reserved for TX_BUSY c TX_ONCE ST3 (DIR) 0 0 0 0 0 0 0 0 1 1 1 www.national.com ST2 0 0 0 0 1 1 1 1 0 0 1 ST1 0 0 1 1 0 0 1 1 0 0 0 104 Table 26 ST3 (DIR) 1 1 1 1 ST2 1 0 0 1 ST1 0 1 1 1 Buffer Status Section of the CNSTAT Register ST0 (BUSY) 1 0 1 0 Buffer Status TX_BUSY0 d TX_RTR (automatic response to a remote frame) Reserved for TX_BUSY1 e TX_ONCE_RTR (changes to TX_RTR after transmission) 1 1 1 1 TX_BUSY2 d a. This condition indicates that the user wrote RX_NOT_ACTIVE to a buffer when the data copy process is still active. b. RX_BUSYx indicates that coping is in progress at three possible times - data is copied for the first time RX_READY → RX_BUSY0 - data is copied for the second time RX_FULL → RX_BUSY1 - data is copied for the third or more time RX_OVERRUN → R X_BUSY2 c. This state indicates that the user wrote TX_NOT_ACTIVE to a transmit buffer which is scheduled for transmission or is currently transmitting. d. TX_BUSYx indicates that a buffers is scheduled for transmission or is actively transmitting; it can be due to one of two cases: - a message is pending for transmission or is currently transmitting - an automated answer is pending for transmission or is currently transmitting e. This condition does not occur Table 27 Number of data bytes 0 1 2 3 4 5 6 7 8 Data Length Coding DLC3 0 0 0 0 0 0 0 0 1 DLC2 0 0 0 0 1 1 1 1 0 DLC1 0 0 1 1 0 0 1 1 0 DLC0 0 1 0 1 0 1 0 1 0 RTR Note: The maximum number of data bytes received/transmitted is 8, even if the data length code is set to a value greater than 8. Thus, if the data length code is greater or equal to eight bytes, the bits DLC2 to DLC0 are ignored. 20.9.4 Storage of Standard Messages During the processing of standard frames, the ExtendedIdentifier-bit (IDE) is set to “0”. The bits ID1[3:0], ID0[15:0] are “don’t care” bits. A standard frame with eight data bytes is shown in Table 28. IDE Identifier Extension. IDE is set to “0” to indicate that the message is a standard frame using 11 identifier bits. If IDE is set to “1”, the object stored in the buffer is handled as an extended frame. Remote Transmission Request. RTR is set to “1” to indicate that the message is a remote frame. For a data frame, the RTR bit is set to “0”. ID[10:0]The ID buffer bits ID10 to ID0 are used for the 11 standard frame identifier bits. Table 28 ADDR xxxE16 xxxC16 xxxA16 xxx816 xxx616 Standard Frame with 8 Data Bytes 11 ID6 BUFFER register ID1 ID0 DATA0 15 ID10 14 ID9 13 ID8 12 ID7 10 ID5 9 ID4 8 ID3 7 ID2 6 ID1 5 ID0 4 RTR 3 IDE 2 1 don’t care 0 don’t care Data 1.7 Data 3.7 Data 5.7 Data 1.6 Data 3.6 Data 5.6 Data 1.5 Data 3.5 Data 5.5 Data 1.4 Data 3.4 Data 5.4 Data 1.3 Data 3.3 Data 5.3 Data 1.2 Data 3.2 Data 5.2 Data 1.1 Data 3.1 Data 5.1 Data 1.0 Data 3.0 Data 5.0 Data 2.7 Data 4.7 Data 6.7 Data 2.6 Data 4.6 Data 6.6 Data 2.5 Data 4.5 Data 6.5 Data 2.4 Data 4.4 Data 6.4 Data 2.3 Data 4.3 Data 6.3 Data 2.2 Data 4.2 Data 6.2 Data 2.1 Data 4.1 Data 6.1 Data 2.0 Data 4.0 Data 6.0 DATA1 DATA2 105 www.national.com Table 28 ADDR xxx416 xxx216 xxx016 Standard Frame with 8 Data Bytes 11 Data 7.3 TSTP 11 BUFFER register DATA3 TSTP CNTSTAT 15 Data 7.7 TSTP 15 DLC3 14 Data 7.6 TSTP 14 DLC2 13 Data 7.5 TSTP 13 DLC1 12 Data 7.4 TSTP 12 DLC0 10 Data 7.2 TSTP 10 9 Data 7.1 TSTP 9 8 Data 7.0 TSTP 8 7 Data 8.7 TSTP 7 PRI3 6 Data 8.6 TSTP 6 PRI2 5 Data 8.5 TSTP 5 PRI1 4 Data 8.4 TSTP 4 PRI0 3 Data 8.3 TSTP 3 ST3 2 Data 8.2 TSTP 2 ST2 1 Data 8.1 TSTP 1 ST1 0 Data 8.0 TSTP 0 ST0 Reserved 20.9.5 Storage of Messages with Less Than 8 Data Bytes 20.9.6 Storage of Extended Messages The data bytes that are not used for data transfer are “don’t cares”. If the object is transmitted, the data within these bytes will be ignored. If the object is received, the data within these bytes will be overwritten with invalid data. Table 29 ADDR xxxE16 xxxC16 xxxA16 xxx8 16 xxx6 16 xxx4 16 xxx2 16 xxx0 16 If the IDE bit is set to “1”, the buffer handles extended frames. The storage of the extended ID follows the descriptions in Table 29. The SRR bit is at the bit position of the RTR bit for standard frame and needs to be transmitted as “1”. Extended Messages with 8 Data Bytes 11 ID24 ID10 Data 1.3 Data 3.3 Data 5.3 Data 7.3 TSTP 11 BUFFER register ID1 ID0 DATA0 15 ID28 ID14 Data 1.7 Data 3.7 Data 5.7 Data 7.7 TSTP 15 DLC3 14 ID27 ID13 Data 1.6 Data 3.6 Data 5.6 Data 7.6 TSTP 14 DLC2 13 ID26 ID12 Data 1.5 Data 3.5 Data 5.5 Data 7.5 TSTP 13 DLC1 12 ID25 ID11 Data 1.4 Data 3.4 Data 5.4 Data 7.4 TSTP 12 DLC0 10 ID23 ID9 Data 1.2 Data 3.2 Data 5.2 Data 7.2 TSTP 10 9 ID22 ID8 Data 1.1 Data 3.1 Data 5.1 Data 7.1 TSTP 9 8 ID21 ID7 Data 1.0 Data 3.0 Data 5.0 Data 7.0 TSTP 8 7 ID20 ID6 Data 2.7 Data 4.7 Data 6.7 Data 8.7 TSTP 7 PRI3 6 ID19 ID5 Data 2.6 Data 4.6 Data 6.6 Data 8.6 TSTP 6 PRI2 5 ID18 ID4 Data 2.5 Data 4.5 Data 6.5 Data 8.5 TSTP 5 PRI1 4 SRR ID3 Data 2.4 Data 4.4 Data 6.4 Data 8.4 TSTP 4 PRI0 3 IDE ID2 Data 2.3 Data 4.3 Data 6.3 Data 8.3 TSTP 3 ST3 2 ID17 ID1 Data 2.2 Data 4.2 Data 6.2 Data 8.2 TSTP 2 ST2 1 ID16 ID0 Data 2.1 Data 4.1 Data 6.1 Data 8.1 TSTP 1 ST1 0 ID15 RTR Data 2.0 Data 4.0 Data 6.0 Data 8.0 TSTP 0 ST0 DATA1 DATA2 DATA3 TSTP CNTSTAT Reserved SRR IDE RTR ID[28:0] Substitute Remote Request. SRR replaces the RTR bit used in standard frames at this bit position. The SRR bit needs to be set to “1” by the user if the buffer is configured to transmit a message with an extended identifier. It will be received as monitored on the CAN bus. Identifier Extension. IDE is set to “0” to indicate that the message is a standard frame using 11 identifier bits. If IDE is set to “1”, the object stored in the buffer is handled as an extended frame. Remote Transmission Request. RTR is set to “1” to indicate that the message is a remote frame. For a data frame, the RTR bit is set to “0”. The ID bits 28 to 0 are used to build the 29-bit identifier of an extended frame. www.national.com 106 20.9.7 Storage of Remote Messages During remote frame transfer, the buffer registers DATA[3:0] are “don’t cares”. If a remote frame is transmitted, the contents of these registers are ignored. If a remote frame is reTable 30 ADDR xxxE16 xxxC16 xxxA16 xxx816 xxx616 xxx416 xxx216 xxx016 ceived, the contents of these registers will be overwritten with invalid data. The structure of a message buffer set up for a remote frame with extended identifier is shown in Table 30. Extended Remote Frame 10 ID23 ID9 BUFFER register ID1 ID0 DATA0 DATA1 DATA2 DATA3 TSTP CNTSTAT 15 ID28 ID14 14 ID27 ID13 13 ID26 ID12 12 ID25 ID11 11 ID24 ID10 9 ID22 ID8 8 ID21 ID7 don’t care don’t care don’t care don’t care 7 ID20 ID6 6 ID19 ID5 5 ID18 ID4 4 SRR ID3 3 IDE ID2 2 ID17 ID1 1 ID16 ID0 0 ID15 RTR TSTP15 DLC3 TSTP14 DLC2 TSTP13 DLC1 TSTP12 DLC0 TSTP11 TSTP10 TSTP 9 TSTP 8 TSTP 7 PRI3 TSTP 6 PRI2 TSTP 5 PRI1 TSTP 4 PRI0 TSTP 3 ST3 TSTP 2 ST2 TSTP 1 ST1 TSTP 0 ST0 Reserved SRR IDE RTR ID[28:0] Substitute Remote Request. SRR replaces the RTR bit used in standard frames at this bit position. The SRR bit needs to be set to “1” by the user. Identifier Extension. IDE is set to “0” to indicate that the message is a standard frame using 11 identifier bits. If IDE is set to “1”, the object stored in the buffer is handled as an extended frame. Remote Transmission Request. RTR is set to “1” to indicate that the message is a remote frame. For a data frame, the RTR bit is set to “0”. The ID bits 28 to 0 are used to build the 29-bit identifier of an extended frame. The ID1 buffer bits ID28 to ID18 are used for the 11 standard frame identifier bits. CAN Global Configuration Register (CGCR) • enable/disable diagnostic functions 15 12 Reserved 11 10 9 8 EIT DIAGEN INTERNAL LOOPBACK 0 r/w 4 3 2 1 0 7 6 5 IGNACK LO DDIR TSTPEN BUFFLOCK CRX CTX CANEN 0 r/w CANEN CAN Enable. This bit enables/disables the CR16CAN. When the CR16CAN is disabled, all internal states and the TEC and REC counter registers are cleared. In addition the CR16CAN clock is disabled. All CR16CAN control registers and the contents of the object memory are left unchanged. The user needs to make sure that no message is pending for transmission before the CR16CAN is disabled. “0” CR16CAN is disabled “1” CR16CAN is enabled Control Transmit. This bit configures the logic level of the CAN transmit pin CANTX. “0” dominate state is “0”; recessive state is “1” “1” dominate state is “1”; recessive state is “0” Control Receive. This bit configures the logic level of the CAN receive pin CANRX. “0” dominate state is “0”; recessive state is “1” “1” dominate state is “1”; recessive state is “0” 20.9.8 The CAN Global Configuration Register (CGCR) is a 16-bit wide register used to: • • • • • • enable/disable the CR16CAN configure the BUFFLOCK function for the message buffer 0...14 enable/disable the time stamp synchronization set the logic levels of the CAN Input/Output pins CANRX/CANTX choose the data storage direction (DDIR) select the error interrupt type (EIT) CTX CRX 107 www.national.com BUFFLOC TSTPEN Buffer Lock. With this bit the user can configure the buffer lock function. If this feature is enabled, a buffer will be locked upon a successful frame reception. The buffer will be unlocked again by writing RX_READY in the buffer status register, i.e., after reading data. “0” lock function is disabled for all buffers “1” lock function is enabled for all buffers Time Sync Enable. The Time Sync bit enables or disables the time stamp synchronization function of the CR16CAN. “0” Time synchronization disabled. The Time Stamp counter value is not reset upon reception or transmission of a message to/ from buffer 0. Sequence of Data Bytes on the Bus ID Data1 Data2 Data3 Data4 DDIR “1” Time synchronization enabled. The Time Stamp counter value is reset upon reception or transmission of a message to/from buffer 0. Data Direction. By setting or resetting the DDIR bit, the user can select the direction the data bytes are transmitted and received. The CR16CAN transmits and receives the CAN data byte Data1 first and the data byte Data8 last (Data1, Data2,...,Data7, Data8). If DDIR is set to “0” the data contents of a received message is stored with the first byte at the highest data address and the last data at the lowest data address (see Figure 69). The same applies for transmitted data. Data5 Data6 Data7 Data8 CRC t Storage of Data Bytes in the Buffer Memory ADDR offset 0A16 0816 0616 0416 Data Bytes Data1 Data3 Data5 Data7 Data2 Data4 Data6 Data8 Figure 69. Data Direction Bit set to ‘0’ Setting the DDIR bit to “1” will cause the direction of the data storage to be reversed — the last byte received is stored at Sequence of Data Bytes on the Bus ID Data1 Data2 Data3 Data4 Data5 Data6 Data7 Data8 CRC the highest address and the first byte is stored at the lowest address. See Figure 70 for illustration. t Storage of Data Bytes in the Buffer Memory ADDRoffset 0A16 0816 0616 0416 Data Bytes Data8 Data6 Data4 Data2 Data7 Data5 Data3 Data1 Figure 70. LO Data Direction Bit set to ‘1’ Using this listen only function, the CR16CAN interface can be adjusted when it gets connected to an operating network with unknown bus speed. Ignore Acknowledge. If the ignore ACK function is enabled, then by setting the IGNACK bit to “1”, CR16CAN does not expect to receive a dominant ACK bit to indicate the validity of a Listen Only — By setting the LO-bit to “1” the CR16CAN interface is configured to behave only as a receiver. This means: • it cannot transmit any message. • it cannot send a dominant ACK bit. • when errors are detected on the bus, the CR16CAN will behave as in the error passive mode. IGNACK www.national.com 108 transmitted message. It will not send an error frame when the transmitted frame in not acknowledged by any other CAN node. This feature can be used in conjunction with the LOOPBACK option for stand-alone tests outside of a CAN network. LOOPBACK Loopback. By setting the LOOPBACK bit, all messages sent by CR16CAN can also be received by a CR16CAN buffer with a matching buffer ID. However, CR16CAN does not acknowledge a message sent by itself. Therefore CR16CAN will send an error frame when no other device connected to the bus has acknowledged the message. INTERNAL Internal. If the INTERNAL function is enabled, the TX- and RX-pin of the CR16CAN are internally connected to each other. This feature can be used in conjunction with the LOOPBACK mode. This means that CR16CAN can receive its own sent messages without connecting an external transceiver chip to the RX- and TXpin; it allows the user to run real stand-alone tests without any peripheral devices. Diagnostic Enable. The DIAGEN bit globally enables or disables the special diagnostic features of CR16CAN. This includes the following functions: • LO (Listen Only) • IGNACK (Ignore Acknowledge) • LOOPBACK (Loopback) • INTERNAL (Internal Loopback) • write access to hidden receive buffer Error Interrupt Type. This bit configures when the Error Interrupt Pending Bit (CIPND.EIPND) is set and an error interrupt is generated if enabled by the Error Interrupt Enable (CIEN.EIEN). “0” The EIPND bit is set on every error on the CAN bus. “1” The EIPND bit is set only if the error state (CSTPND.NS) changes as a result of incrementing either the receive or transmit error counter. 20.9.9 CAN Timing Register (CTIM) The Can Timing Register (CTIM) defines the configuration of the Bit Time Logic (BTL). 15 PSC[6:0] 9 8 76 32 0 SJW[1:0] TSEG1[3:0] TSEG2[2:0] 0 r/w PSC[6:0] Prescaler Configuration. These bits set the CAN prescaler. The settings are shown in Table 31 Table 31 CAN Prescaler Settings PS C3 0 0 0 0 0 : 1 1 PS C2 0 0 0 0 1 : 1 1 PS C1 0 0 1 1 0 : 0 1 PS C0 0 1 0 1 0 : 1 0/1 CAN prescaler (PSC) 2 3 4 5 6 : 127 128 PS C6 0 0 0 0 0 PS C5 0 0 0 0 0 : PS C4 0 0 0 0 0 : 1 1 DIAGEN 1 1 SJW[1:0] 1 1 EIT Synchronization Jump Width. These bits set the Synchronization Jump Width which can be programmed between 1 and 4 time quanta (see Table 32). Table 32 SJW Settings SJW1 0 0 1 1 SJW0 0 1 0 1 Synchronization Jump Width (SJW) 1 tq 2 tq 3 tq 4 tq Note: The settings of SJW has to be configured to be smaller or equal to TSEG1 and TSEG2 TSEG1[3:0] Time Segment 1. These bits configure the length of the Time Segment 1 (TSEG1). It is not recommended to configure the time segment 1 to be smaller than 2tq. (see Table 33). 109 www.national.com GM[28:15] Table 33 TSEG 13 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 TSEG 12 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Time Segment 1 Settings TSEG 11 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 TSEG 10 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Length of Time (TSEG1) not recommended 2 tq 3 tq 4 tq 5 tq 6 tq 7 tq 8 tq 9 tq 10 tq 11 tq 12 tq 13 tq 14 tq 15 tq 16 tq GM[14:0] 15 15 The following are the bits for the GMSKB register. 5 4 RTR 0 r/w 3 IDE 2 GM[17:15] 0 GM[28:18] The following are the bits for the GMSKX register. 1 GM[14:0] 0 r/w 0 XRTR For all GMSKB and GMSKX register bits, the following applies: — “0” is the incoming identifier bit must match the corresponding bit in the message buffer identifier register. — “1” accept “1” or “0” (“don’t care”) of the incoming ID bit independent from the corresponding bit in the message buffer ID registers. The corresponding ID bit in the message buffer will be overwritten by the incoming identifier bits. When an extended frame is received from the CAN bus, all Global Mask bits GM28 through GM0, IDE, RTR and XRTR are used to mask the incoming message. During the reception of standard frames only the Global Mask bits GM28 to GM18, RTR and IDE are utilized. Global Mask GM[28:18] RTR ID[10:0] a IDE IDE GM[17:0] unused XRTR TSEG2[2:0] Time Segment 2. The TSEG2[2:0] bits set the number of time quanta (tq) for phase segment 2 (see Table 34). Table 34 TSEG22 0 0 0 0 1 1 1 1 Time Segment 2 Settings TSEG20 0 1 0 1 0 1 0 1 Length of TSEG2 1 tq 2 tq 3 tq 4 tq 5 tq 6 tq 7 tq 8 tq standard frame RTR TSEG21 0 0 1 1 0 0 1 1 extended frame ID[28:18] SRR IDE ID[17:0] RTR a. the RTR bit has a different position in standard and extended frames — for standard frames the GMSK_RTR bit is used to mask this bit — for extended frames the GMSK_XRTR bit is used to mask this bit 20.9.11 Basic Mask Registers (BMSK — BMSKB and BMSKX) The two registers BMSKB and BMSKX allow to mask the buffer 14, or “don’t care” the incoming extended/standard identifier bits, RTR/XRTR and IDE. Throughout this document, the two 16-bit registers BMSKB and BMSKX are referenced to as a 32-bit register BMSK. BM[28:15] 15 BM[28:18] The following are the bits for the BMSKB register. 5 4 RTR 0 r/w 3 IDE 2 BM[17:15] 0 20.9.10 Global Mask Registers (GMSK — GMSKB and GMSKX) The GMSKB and GMSKX registers allow you to globally mask, or “don’t care” the incoming extended/standard identifier bits, RTR/XRTR and IDE. Throughout this document, the GMSKB and GMSKX 16-bit registers are referenced as a 32bit register GMSK. BM[14:0] 15 BM[14:0] The following are the bits for the BMSKX register. 1 0 r/w 0 XRTR www.national.com 110 For all BMSKB and BMSKX register bits the following applies: — “0” incoming identifier bit must match the corresponding bit in the message buffer identifier register. — “1” accept “1” or “0” (“don’t care”) of the incoming ID bit independent from the corresponding bit in the message buffer ID registers. The corresponding ID bit in the message buffer will be overwritten by the incoming identifier bits. When an extended frame is received from the CAN bus all Basic Mask bits BM28 through BM0, IDE, RTR and XRTR are used to mask the incoming message. During the reception of standard frames only the Basic Mask bits BM28 to BM18, RTR and IDE are utilized. Basic Mask standard frame BM[28:18] ID[10:0] RTR a RTR IDE IDE BM[17:0] XRTR unused EIPND IPND[14:0] Error Interrupt Pending — EIPND indicates the status change of TEC/REC and will execute an error interrupt if EIEN is set. The user has the responsibility to reset EIPND by means of the CICLR register. “0” CAN status is not changed “1” CAN status is changed Buffer Interrupt Pending — IPND[14:0] bits are set by CR16CAN following a successful transmission or reception of a message to or from message buffer 0...14, IPND14 for buffer 14 and IPND0 for buffer 0. “0” no interrupt pending for this message buffer “1” message buffer has generated an interrupt 20.9.14 CAN Interrupt Clear Register (CICLR) The bits in the CICLR register separately clear all CAN interrupt pending flags caused by the message buffers 0...14 and from the Error Management Logic. 15 14 EICLR 0 ICLR[14:0] 0 w Error Interrupt Clear. The EICLR bit can clear the EIPND bit: “0” the contents of the EIPND bit is unchanged “1” the contents of the EIPND bit is reset Buffer Interrupt Clear. The user is able to clear the buffer interrupt pending bits by ICLR[14:0]: “0” the contents of the respective IPND bit is unchanged “1” the contents of the respective IPND bit is reset extended frame ID[28:18] SRR IDE ID[17:0] RTR a. the RTR bit has a different position in standard and extended frames — for standard frames the BMSK_RTR bit is used to mask this bit — for extended frames the BMSK_XRTR bit is used to mask this bit 20.9.12 CAN Interrupt Enable Register (CIEN) The CAN Interrupt Enable (CIEN) register enables the transmit/receive interrupts of the message buffers 0 through 14 as well as the CAN Error Interrupt. 15 EIEN 14 IEN[14:0] 0 r/w EIEN Error Interrupt Enable. This bit allows the CR16CAN to interrupt the CPU if any kind of CAN receive/transmit errors are detected. This means any error status change in the error counter registers REC/TEC is able to generate an error interrupt if EIEN is enabled. “0” The error interrupt is disabled and no error interrupt will be generated. “1” The error interrupt is enabled and a change in REC/TEC will cause an interrupt to be generated. Buffer Interrupt Enable. The IEN[14:0] allow the user to enable/disable interrupt source for each of the message buffers i.e., IEN14 configures buffer14 and IEN0 configures buffer0. “0” buffer as interrupt source disabled “1” buffer as interrupt source enabled ICLR[14:0] 0 EICLR 20.9.15 CAN Interrupt Code Enable Register (CICEN) The CAN Interrupt Code Enable Register (CICEN) determines whether the interrupt pending flag in IPND should be translated into the Interrupt Code field of the CSTPND register. All interrupt requests, CAN error and buffer 0...14 interrupts can be enabled/disabled separately for the interrupt code indication field. 15 EICEN 14 ICEN[14:0] 0 r/w EICEN Error Interrupt Code Enable: “0” error interrupt pending is not indicated in the interrupt code “1” error interrupt pending is indicated in the interrupt code Buffer Interrupt Code Enable: “0” buffer interrupt pending is not indicated in the interrupt code “1” buffer interrupt pending is indicated in the interrupt code 0 IEN[14:0] 20.9.13 CAN Interrupt Pending Register (CIPND) The CIPND register indicates any CAN Receive/Transmit Interrupt Requests caused by the message buffers 0..14 and CAN error occurrences. 15 14 EIPND 0 IPND[14:0] 0 r ICEN[14:0] 111 www.national.com 20.9.16 CAN Status Pending Register (CSTPND) The CAN Status Pending Register (CSTPND) contains the status of the CAN Node and the Interrupt Code. 15 Reserved 8 7 5 NS[2:0] 0 r 4 IRQ 3 IST[3:0] 0 20.9.17 CAN Error Counter Register (CANEC) The Can Error Counter Register contains the value of the CAN Receive Error Counter and the CAN Transmit Error Counter. 15 REC[7:0] 0 r REC[7:0] TEC[7:0] CAN Receive Error Counter. The bits REC[7:0] holds the value of the receive error counter. CAN Transmit Error Counter. The bits TEC[7:0] holds the value of the transmit error counter. 8 7 TEC[7:0] 0 NS[2:0] CAN Node Status. This bits indicate the status of the CAN node as it is described in Table 35. Table 35 CAN Node Status NS0 0 0 1 X X Node Status Not Active Error active Error Warning Level Error passive Bus off NS2 0 0 0 1 1 NS1 0 1 1 0 1 20.9.18 CAN Error Diagnostic Register (CEDIAG) The CAN Error Diagnostic (CEDIAG) register provides information about the last detected error. CR16CAN is able to identify the field within the CAN frame format, in which the error occurred, and it identifies the bit number of the erroneous bit within the according frame field. The CPU has read only access and all bits will be cleared upon reset. 15 14 13 12 11 0 r 10 9 4 3 0 Reserved DRIVE MON CRC STUFF TXE EBID[5:0] EFID[3:0] IRQ,IST[3:0] Interrupt Code. This section of the Status Pending Register represents the interrupt source of the highest priority interrupt currently pending and enabled in the CICEN register. Table 36 shows the several interrupt codes for CICEN=FFFF. Table 36 Highest Priority Interrupt Code (CICEN = FFFF) IRQ 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 IST3 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 IST2 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 IST1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 IST0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 EFID[3:0] Error Field Identifier. The EDIAG bits 3...0 identify the frame field in which the last error occurred. How the various frame fields are coded into the EFID bits is shown in Table 37. Table 37 Error Field Identifier EFID3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 EFID2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 EFID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 EFID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CAN interrupt request no request Error interrupt Buffer 0 Buffer 1 Buffer 2 Buffer 3 Buffer 4 Buffer 5 Buffer 6 Buffer 7 Buffer 8 Buffer 9 Buffer 10 Buffer 11 Buffer 12 Buffer 13 Buffer 14 Field ERROR ERROR DEL ERROR ECHO BUS IDLE ACK EOF INTERMISSION SUSPEND TRANSMISSION SOF ARBITRATION IDE EXTENDED ARBITRATION R1/R0 DLC DATA CRC www.national.com 112 EBID[5:0] Error Bit Identifier. The EDIAG[9:4] bits contain the number (position) of the incorrect bit within the erroneous frame field. The bit number starts with the value equal to the respective frame field length minus one at the beginning of each field and is decremented with each CAN bit. Figure 71 shows an example on how the EBID is calculated. ment from the value 000016 after a hardware reset. If the Timer Stamp enable flag (TSTPEN) in the CAN global configuration register (CGCR) is set, the counter will also be reset upon a message transfer of the message buffer 0. As described in Time Stamp Counter on page 103, the contents of CTMR are captured into the Time Stamp register of the message buffer after successfully sending or receiving a frame. 20.10 rrrrrr incorrect bit data field SYSTEM START-UP AND MULTI-INPUT WAKE-UP After system start-up, all CR16CAN related registers are in their reset state. The CR16CAN module can be enabled after all configuration registers are set to their desired value. The following initial setting need to be made: — configure the CAN Timing register (CTIM) See “Bit Time Logic” on page 93. — configure every buffer to its function as receive/transmit Buffer Status/Control Register (CNSTAT) on page 104. — set the acceptance filtering masks. See “Acceptance Filtering” on page 95. — enable the CR16CAN interface. See “CAN Global Configuration Register (CGCR)” on page 107. Before disabling the CR16CAN module, the user has to make sure that no transmission is still pending. Note: The device can be awaken from a power saving mode by an activity on the CAN bus by selecting the CAN RX pin as an input to the Multi-Input Wake-Up module. In this case the CR16CAN module must not be disabled before entering the power saving mode. Disabling the CR16CAN module also disables the CAN RX pin. As an alternative, the CAN RX pin can be connected to any other input pin of the Multi-Input Wake-Up module. This input channel must then be configured to trigger a wake-up event on a falling edge (if a dominant bit is represented by a low level). In this case the CR16CAN module can be disabled before entering a power saving mode. After the device has been waken up, the user has to manually enable the CR16CAN again. All configuration and buffer registers still contain the same data as prior to the power down phase. 20.10.1 External Connection The CR16CAN uses two external pins, CANTX and CANRX to connect to the physical layer of the CAN interface. They provide the functionality as described in Table 38. Figure 71. EBID Example Assume the EFID resulted in 11102 and the EBID showed a value of 1110012. This means that faulty field was the data field. To calculate the bit position of the error, the DLC of the message needs to be known. For example, for a DLC of 8 data bytes, the bit counter starts with the value: 8 x 8 - 1 = 63; so when EBID[5:0] = 111001 2 = 57, then the bit number was 63 - 57 = 6. The following bits provide an information of the error type. TXE Transmit Error. If set, this bit indicates that the CR16CAN was an active transmitter at the time the error occurred. If reset, the CR16CAN was a receiver. Stuff Error. if set, this bit indicates that a the bit stuffing rule was violated at the time the error occurred. Note that certain bit fields do no use bit stuffing and therefore this bit may be ignored in those. CRC Error. if set, this bit indicates that the CRC is invalid. This bit should only be used if the EFID shows the code of the ACK field. Monitor. This bit shows the bus value on the CANRX pin as seen by the CR16CAN at the time of the error. Drive. This bit shows the output value on the CANTX pin at the time of the error. Note that a receiver will not drive the bus except during ACK and during an active error flag. STUFF CRC MON DRIVE 20.9.19 CAN Timer Register (CTMR) The current value of the Time Stamp counter as described in section 20.8 can be monitored via the CAN Timer Register. 15 CTMR[15:0] 0 r The CAN Time register is a free running 16-bit counter. It contains the number of CAN bits recognized by CR16CAN since the register has been reset. The counter starts to incre0 Table 38 Signal Name CANTX CANRX External CR16CAN Pins Description Transmit data to the CAN bus Receive data from the CAN bus Type Output Input The logic levels are configurable by means of two control flags CTX and CRX of the Global Configuration Register CGCR (see “CAN Global Configuration Register (CGCR)” on page 107. 113 www.national.com 20.10.2 Transceiver Connection An external Transceiver Chip needs to be connected between the CAN block and the bus. It is used to establish a bus connection in differential mode and furthermore provides the driver and protection requirements. Figure 72 shows a possible ISO-High-Speed configuration. 120 termination The minimum duration of the four CAN bit times is determined by the following Bit Time Logic settings: PSC = PSCmin = 2 TSEG1 = TSEG1min = 2 TSEG2 = TSEG2min = 1 bit time = Synch + Time Segment 1 + Time Segment 2 = (1 + 2 + 1) tq = 4 tq = (4 tq x PSC) clock cycles = (4 tq x 2) clock cycles = 8 clock cycles For these minimum BTL settings, four CAN bit times take 32 clock cycles. The following is an example that assumes typical case: — — — — minimum BTL settings reception and copy of a remote frame update of one buffer from TX_RTR schedule of one buffer from transmit CORE BUS CAN Bus Line to other modules CR16CAN Transceiver Chip VCC 3 5 REF BUS_H 7 CANRX 4 RX BUS_L 6 1 TX RS GND CANTX 8 2 GND GND 120 VCC Figure 72. External Transceiver Connection (ISO-High-Speed) As outlined in Table 39 the copy process, update and scheduling the next transmission gives a total of 17+3+2=22 clock cycles. Therefore under these conditions there is no timing restriction. The following example assumes the worst case: — — — — minimum BTL settings reception and copy of a remote frame update of the 14 remaining buffers from TX_RTR schedule of one buffer for transmit 20.10.3 Timing Requirements Processing messages and updating message buffers require a certain number of clock cycles by CR16CAN as shown in Table 39. These requirements may lead to some restrictions regarding the Bit Time Logic settings and the overall CR16CAN performance which are described below in more detail. Table 39 CR16CAN Internal Timing task # cycles a occurrence/ frame b copy hidden buffer to receive 17 0-1 message buffer update status from TX_RTR 3 0-15 to TX_ONCE_RTR schedule a message for trans2 0-1 mission a. Wait cycles need to be added for CPU access to the object memory as described in CPU Access to CR16CAN Registers/Memory on page 103. b. Depends on the number of matching identifiers. The critical path derives from receiving a remote frame which triggers the transmission of one or more data frames. There are a minimum of four bit times in-between two consecutive frames. These bit times start at the validation point of received frame (reception of 6th EOF bit) and end at the earliest possible transmission start of the next frame, which is after the third intermission bit at 100% burst bus load. These four bit times have to be set in perspective with the timing requirements of the CR16CAN. All these actions in total require 17 + 14 x 3 + 2 = 61 clock cycles to be executed by CR16CAN. This leads to the limitation of the Bit Time Logic of 61 / 4 = 15.25 clock cycles per CAN bit as a minimum, resulting in the minimum clock frequencies listed below (the frequency depends on the desired baud rate and assumes the worst case scenario can occur in the application). Table 40 gives examples for the minimum clock frequency in order to ensure proper functionality at various CAN bus speeds. Table 40 Min. Clock Frequency Requirements min. clock frequency 15.25MHz 7.625MHz 3,81MHz Baud Rate 1Mbit/sec 500kbit/sec 250kbit/sec 20.10.4 Bit Time Logic Calculation Examples The calculation of the CAN bus clocks using CKI = 16MHz is shown in the following examples. The desired baud rate for both examples is 1Mbit/s. Example 1 PSC = PSC[5:0] + 2 = 0 + 2 = 2 TSEG1 = TSEG1[3:0] + 1 = 3 + 1 = 4 TSEG2 = TSEG2[2:0] + 1 = 2 + 1 = 3 SJW = TSEG2 = 3 www.national.com 114 — sample point positioned at 62.5% of bit time — bit time = 125ns x (1 + 4 + 3 ± 3) = (1 ± 0.375)µs — busclock = 16MHz / (2 x (1 + 4 + 3)) = 1Mbit/s (nominal) Example 2 PSC = PSC[5:0] + 1 = 2 + 2 = 4 TSEG1 = TSEG1[3:0] + 1 = 1 + 1 = 2 TSEG2 = TSEG2[2:0] + 1 = 0 + 1 = 1 SJW = TSEG2 = 1 • • • sample point positioned at 75% of bit time bit time = 250ns x (1 + 2 + 1 ± 1) = (1 ± 0.25)µs busclock = 16MHz / (2 x (1 + 4 + 3)) = 1Mbit/s (nominal) 20.10.5 Acceptance Filter Considerations The CR16CAN provides two acceptance filter masks GMSK and BMSK as described in Acceptance Filtering on page 95, Global Mask Registers (GMSK — GMSKB and GMSKX) on page 110 and Basic Mask Registers (BMSK — BMSKB and BMSKX) on page 110. These masks allow filtering of up to 32 bits of the message object, which includes the standard identifier, the extended identifier as well as the frame control bits RTR, SRR and IDE. 20.10.6 Remote Frames Remote frames can be automatically processed by the CR16CAN interface. However, to fully enable that feature, the RTR/XRTR bits (for both standard and extended frames) within the BMSK and/or GMSK register need to be set to “don’t care”. This is because a remote frame with the RTR bit being set to “1” should trigger the transmission of a data frame with the RTR bit set to “0” and therefore the ID bits of the received message need to pass through the acceptance filter. The same applies to transmitting remote frames and switching to receive the corresponding data frames. 115 www.national.com 21.0 Analog Comparators The Dual Analog Comparator (ACMP2) module contains two independent analog comparators with all necessary control logic. Each comparator unit compares the analog input voltages applied to two input pins and determines which voltage is higher. The comparison results can be placed on two output pins and/or read by the software from a register. Figure 73 is a block diagram of the Dual Analog Comparator module. The two comparators are designated Comparator 1 (CMP1) and Comparator 2 (CMP2). Each comparator has a positive and a negative input, called CMP1P and CMP1N for Comparator 1 and CMP2P and CMP2N for Comparator 2. An optional output, CMP1O for Comparator 1 or CMP2O for Comparator 2, allows the external hardware to read the comparison results. If the positive input is greater than the negative input, the result is a logic 1. Otherwise, the result is a logic 0. These same results are available to the software by reading the CMPCTRL register. CMP1OP and CMP2OP are the direct outputs of the analog comparator. These signals are connected to the channels of the Multi-Wake-Up module. Comparator 2 is disabled (CMP2EN=0), setting the CMP2OE bit results in a logic 0 on the CMP2O output pin. 21.2 ANALOG COMPARATOR USAGE The comparator I/O pins are alternate functions of the Port L pins. In order for a comparator to operate, its two input pins must be configured to operate as inputs in the alternate function mode. Using a comparator's output pin is optional. If it is to be used, it must be configured to operate as an output in the alternate function mode. The comparison result bits in the CMPCTRL register are available to the CPU whether or not the output pin is enabled. Note: There is a setup time for the comparator. The programmer needs to add at least one nop instruction between enabling the comparator and reading back the comparison result if the parts is running above 24MHz. The comparators uses DC current whenever they are enabled. Therefore, in order to reduce power consumption, it is recommended that the comparators be disabled when they are not needed, especially before entering any of the Power Save modes. 21.1 ANALOG COMPARATOR CONTROL/ STATUS REGISTER (CMPCTRL) The CMPCTRL register is a byte-wide, read/write register that controls the comparator module and contains the comparison results. The control bits are read/write bits and the result bits are read-only bits. This register is cleared upon reset. The register format is shown below. 7 6 5 4 3 2 1 0 Reserved CMP2OE CMP1OE CMP2EN CMP1EN CMP2RD CMP1RD CMP1RD CMP2RD CMP1EN CMP2EN CMP1OE CMP2OE Comparator 1 Read. This read-only bit contains the output of Comparator 1 when the comparator is enabled (CMP1EN=1). CMP1RD is set to 1 when the voltage on CMP1P is greater than the voltage on CMP1N. This bit is always 0 when Comparator 1 is disabled. Comparator 2 Read. This read-only bit contains the output of Comparator 2 when the comparator is enabled (CMP2EN=1). CMP2RD is set to 1 when the voltage on CMP2P is greater than the voltage on CMP2N. This bit is always 0 when Comparator 2 is disabled. Comparator 1 Enable. This read/write bit enables (1) or disables (0) Comparator 1. Comparator 2 Enable. This read/write bit enables (1) or disables (0) Comparator 2. Comparator 1 Output Enable. This read/write bit, when set to 1, enables the use of the CMP1O pin as the output of Comparator 1 when Comparator 1 is enabled (CMP1EN=1). If Comparator 1 is disabled (CMP1EN=0), setting the CMP1OE bit results in a logic 0 on the CMP1O output pin. Comparator 2 Output Enable. This read/write bit, when set to 1, enables the use of the CMP2O pin as the output of Comparator 2 when Comparator 2 is enabled (CMP2EN=1). If www.national.com 116 CMP1P + CMP1 _ CMP1OP CMP1N CMP1EN CONTROL + STATUS CMP2EN CMP2P CMP2N + CMP2 _ CMP2OP Figure 73. Dual Analog Comparator Block Diagram CMP2OE CMP1OE CMP1O CMP2O 117 www.national.com 22.0 A/D Converter The A/D Converter (ADC) module is a 12-channel, multiplexed-input, analog-to-digital converter. The A/D Converter receives an analog voltage on an input pin and converts that voltage into an 8-bit digital value using successive approximation. The CPU can then read the result from a memorymapped register. The module supports four automated operating modes, providing single-channel or 4-channel scanned operation in single-conversion or continuous mode. Figure 74 is a block diagram of the A/D Converter module. The analog input signal is selected from the analog inputs using a 12-channel analog multiplexer. The input pins are alternate functions of Port I. A sample-and-hold circuit samples the analog voltage prior to conversion and holds it stable throughout the conversion process. A programmable initial delay period allows the sampled voltage to stabilize before the conversion process begins. The input voltage range is from 0V to VREF (the A/D reference voltage). The device has a separate pin, VREF, for the reference voltage. A capacitor should be connected between the VREF and the AVCC pin in order to minimize noise. The recommended value for this capacitor is about 0.47µF. The internal analog-to-digital converter block is based on a successive approximation algorithm, which compares the sampled voltage against an internally generated sequence of analog voltages. The result is a linear conversion of the analog voltage to an unsigned 8-bit value ranging from 00 hex for 0.0 volts to FF hex for V REF. The clock used by the converter block is generated by a clock divider that scales down the system clock by a programmable factor. The conversion algorithm requires ten A/D Converter clock cycles, or 10 microseconds at the maximum allowed A/D Converter clock rate of 2 MHz. Conversion can start after the power supply is stable and ADCEN set for 30 µs. The conversion results are stored in a 4-level data buffer. Depending on the operating mode, the buffer can hold the results of four successive conversions from a single channel or four conversions from adjacent channels scanned in sequence. 22.1 OPERATING MODES The A/D Converter can be configured to operate in any one of four modes: — — — — Single channel, single conversion Single channel, continuous conversion 4-channel scan, single conversion 4-channel scan, continuous conversion The configuration is set by the SCAN and CONT fields in the ADC Control 2 Register (ADCCNT2), as indicated in Table 41. The A/D converter must be disabled when switching to a different mode. Table 41 SCAN CONT 00 00 01 01 22.1.1 0 1 0 1 ADC Operation Modes Mode Single Channel, Single Conversion Single Channel, Continuous Conversion 4 Channels Scan, Single Conversion 4 Channel Scan, Continuous Conversion Single Channel, Single Conversion Mode In the single channel, single conversion mode, the A/D Converter performs a single conversion using a specified channel. The software starts a conversion by setting the START bit in the ADCCNT2 register. Upon completion of the conversion, the A/D Converter places the result in register ADDATA0, clears the START bit, and sets the EOC (end of conversion) bit in the ADCST register. If the A/D Converter interrupt is enabled, an interrupt to the CPU is generated at this time. 4 CONFIGURATION CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9 CH10 CH11 STATUS & CONTROL PERIPHERAL ANALOG 12:1 ANALOG MUX TO SAMPLE & HOLD VREF Figure 74. DIGITAL CONVERTER CLOCK DIVIDER CLK A/D Converter Block Diagram DATA BUFFER BUS CLK www.national.com 118 22.1.2 Single Channel, Continuous Conversion Mode In the single channel, continuous conversion mode, the A/D Converter performs conversions repeatedly using the same specified channel. The software starts a conversion sequence by setting the START bit. The A/D Converter performs four A/D conversions in sequence using the same channel, pausing only for the programmable sampling delay time used in all conversion operations. It loads the four results into the A/D data registers in sequence, starting with ADDATA0 and ending with ADDATA3. After it loads all four registers, it sets the EOC (end of conversion) bit. If the A/D Converter interrupt is enabled, an interrupt to the CPU is generated at this time. The START bit remains set until cleared by the software. If the software does not clear the START bit, the A/D Converter continues performing conversions using the same input channel, storing the results in ADDATA0 following ADDATA3. To prevent an overrun error, the software must read the results from the data registers before the A/D Converter writes the next result into ADDATA0 following ADDATA3. When the software clears the START bit, the A/D Converter first completes the conversion currently in progress, then stops and sets the EOC bit. A 2-bit buffer pointer in the ADCST register points to the register containing the final result. 22.1.3 4-Channel Scan, Single Conversion Mode software must read the results from the data registers before the A/D Converter writes the next result into ADDATA0. When the software clears the START bit, the A/D Converter first completes the 4-channel conversion sequence currently in progress, then stops and sets the EOC bit. 22.2 A/D CONVERTER REGISTERS The software controls the A/D Converter and reads the A/D results by accessing the ADC registers. There are eight such registers: — — — — — ADC ADC ADC ADC ADC Status Register (ADCST) Control 1 Register (ADCCNT1) Control 2 Register (ADCCNT2) Control 3 Register (ADCCNT3) Data Registers (ADDATA0 through ADDATA3) 22.2.1 ADC Status Register (ADCST) The ADCST register is a byte-wide register that indicates the current status of the A/D Converter. One bit in this register, the OVF flag bit, is cleared by writing a 1 to its bit position. The other bits are read-only bits, so the values written to them are ignored. Upon reset, the register is set to 30 hex. The register format is shown below. 7 6 Reserved EOC 5 4 BUFPTR 3 Reserved 2 OVF 1 BUSY 0 EOC In the 4-channel scan, single conversion mode, the A/D Converter performs four conversions using four adjacent input channels. The software starts the conversion sequence by setting the START bit. The A/D Converter performs four A/D conversions in sequence using four adjacent channels, starting with the specified channel and pausing only for the programmable sampling delay time. It loads the four results into the A/D data registers in sequence, starting with ADDATA0 and ending with ADDATA3. After it loads all four registers, it clears the START bit and sets the EOC (end of conversion) bit. If the A/ D Converter interrupt is enabled, an interrupt to the CPU is generated at this time. 22.1.4 Channel Scan, Continuous Conversion Mode BUSY OVF In the 4-channel scan, continuous conversion mode, the A/D Converter performs conversions repeatedly using four adjacent input channels. The software starts conversion operations by setting the START bit. The A/D Converter performs four A/D conversions in sequence using four adjacent channels, starting with the specified channel and pausing only for the programmable sampling delay time. It loads the four results into the A/D data registers in sequence, starting with ADDATA0 and ending with ADDATA3. After it loads all four registers, it sets the EOC (end of conversion) bit. If the A/D Converter interrupt is enabled, an interrupt to the CPU is generated at this time. The START bit remains set until cleared by the software. If the software does not clear the START bit, the A/D Converter continues performing conversions, repeating the same sequence using the same four input channels and the same sequence of data registers. To prevent an overrun error, the BUFPTR End of Conversion. This read-only bit reports the status of the most recent A/D Converter operation. When cleared to 0, it indicates that the conversion is not complete. When set to 1, it indicates that the conversion is complete. The hardware sets this bit when it places the conversion results in the buffer and clears it when any of the data registers are read. ADC Busy. This read-only bit is set to 1 when the A/D Converter is busy converting data and is cleared to 0 when the A/D Converter is idle or disabled. Overflow. The hardware sets this bit to 1 when the A/D Converter finishes a conversion and attempts to store the results in one of the data registers (ADDATA0-ADDATA3) while the register is full. When this happens, the A/D Converter overwrites the data in the data register, sets the OVF flag, and continues operating. The OVF flag remains set until cleared by the software. The software clears the flag by writing a 1 to it. Writing a 0 to this bit has no effect. Buffer Pointer. This 2-bit, read-only field identifies the data register that was most recently written with new data: 00 = ADDATA0 01 = ADDATA1 10 = ADDATA2 11 = ADDATA3 This register is initialized to 11 when a new conversion is started (when ADCCNT2.START is changed from 0 to 1) and is automatically incremented every time a result is written to buffers ADDATA0-ADDATA3. The result is a four- 119 www.national.com entry cyclic FIFO buffer, with BUFPTR pointing to the last entry written by the A/D Converter. 22.2.2 ADC Control 1 Register (ADCCNT1) SCAN The ADCCNT1 register is a byte-wide, read/write register used to enable the A/D Converter and its interrupts, and also to control the reference voltage source. When writing to this register, all reserved bits must be written with 0 for the A/D Converter to function properly. Changing any bits other than ADCEN (bit 0) is not allowed while the A/D Converter is active (ADCST.BUSY or ADCCNT2.START set). Upon reset, all non-reserved bits are cleared to 0. The register format is shown below. 7 654 Reserved 3 2 INTE 1 Reserved 0 ADCEN START ADCEN INTE A/D Converter Enable. Setting this bit enables the A/D Converter and allows a conversion to be started by setting the start bit (ADCCNT2.START). Clearing the ADCEN bit disables the A/D Converter, terminates any conversion in progress, and clears the ADC status flags (ADCST.EOC, ADCST.BUSY, ADCST.OVF, and ADCCNT2.START). Interrupt Enable. This bit enables (1) or disables (0) A/D Converter interrupts. If enabled, and interrupt occurs at the end of a conversion sequence or when the ADC data buffer is full, depending on the operating mode. pletion of the programmed conversion cycle (a single conversion or a sequence of four conversions on four channels). When set to 1, the A/D Converter operates continuously by repeating the programmed conversion cycle. Scan Mode. This 2-bit field selects the singleconversion mode or 4-channel scan mode as follows: 00 = single-conversion mode 01 = 4-channel scan mode 1X = reserved Start Conversion. The software sets this bit to 1 to start a conversion or a 4-channel conversion cycle. In the “continuous” mode, this bit remains set until cleared by the software. In the “single” (non-continuous) mode, the hardware clears this bit upon completion of the programmed conversion cycle. The software should not attempt to set this bit while the A/D Converter is busy (ADCST.BUSY=1). ADC Control 3 Register (ADCCNT3) 22.2.4 The ADCCNT3 register is a byte-wide, read/write register used to specify the analog sampling time delay and the divide-by factor for generating the ADC clock. This register should be written only when the A/D Converter is disabled (ADCCNT1.ADCEN=0). Upon reset, the non-reserved bits of the ADCCNT3 register are cleared to 0. The register format is shown below. 7 Reserved CDIV 6 PWREN 5 4 3 DELAY 2 1 CDIV 0 All reserved bits must be written with 0 for ADC to operate properly. 22.2.3 ADC Control 2 Register (ADCCNT2) The ADCCNT2 register is a byte-wide, read/write register used to specify the A/D Converter operating mode and to start conversion operations. All register fields other than the START bit should be changed only while the A/D Converter is inactive (START=0). Data written to the SCAN and CONT fields is ignored if the START bit is already set. Upon reset, the non-reserved bits of this register are cleared to 0. The register format is shown below. 7 START CHANNEL 6 5 SCAN 4 CONT 3 2 1 0 CHANNEL CONT Channel Select. This 4-bit field selects one of the twelve analog input channels as follows: 0000 = ACH0 0001 = ACH1 0010 = ACH2 0011 = ACH3 0100 = ACH4 0101 = ACH5 0110 = ACH6 0111 = ACH7 1000 = ACH8 1001 = ACH9 1010 = ACH10 1011 = ACH11 11XX = reserved Continuous Conversion. When cleared to 0, the A/D Converter stops operating upon com- DELAY Clock Divide. This 3-bit field sets the divide-by factor for generating the A/D Converter clock from the system clock. The frequency of the A/ D Converter clock is equal to the system clock divided by the programmed factor. The resulting A/D Converter clock frequency must be less than or equal to 2 MHz. The divide-by factor is defined as follows: 000 = divide by 1 001 = divide by 2 010 = divide by 4 011 = divide by 8 100 = divide by 16 101 = divide by 32 Other = reserved Sampling Time Delay. This 3-bit field defines the number of A/D Converter clock cycles of delay from the time that the input channel is selected until the analog voltage is sampled. The programmed delay should be sufficient, dependent on the source impedance, to allow the sampled signal to reach its final level before the conversion begins. The delay is defined as follows: 000 = 1 A/D Converter clock cycle 001 = 2 A/D Converter clock cycles 010 = 4 A/D Converter clock cycles 011 = 8 A/D Converter clock cycles 100 = 16 A/D Converter clock cycles 101 = 32 A/D Converter clock cycles www.national.com 120 PWREN 110 = 64 A/D Converter clock cycles 111 = reserved Power Down Enable. controls the condition when the ADC is powered down. When PWREN is cleared (0), the ADC powers down upon reset. When PWREN is set (1), the ADC powers down when the ADCEN bit is low. ADC Data Registers (ADDATA0-ADDATA3) 22.2.5 The four ADC Data Registers (ADDATA0 through ADDATA3) are byte-wide, read/write registers that hold the conversion results, which are stored sequentially starting with ADDATA0 and ending with ADDATA3. The results held in these registers are valid only after the ADCST.EOC flag is set. Upon reset, the contents of these registers are undefined. The value read from a data register is a linear mapping of the analog input voltage to an 8-bit value. The value 00 hex represents 0.0 volts and the value FF hex represents the reference voltage, VREF. The programmable sampling time delay should be made small for faster operation, but large enough to allow the input voltage to settle. The internal resistance and capacitance of the A/D Converter, together with the source resistance of the device that drives the A/D input determine the charge-up time required for the voltage to settle. Figure 75 shows a schematic of the charge-up circuit. For the values of RAIN and CAIN, see Section 25.0. Interrupts or polling can be used to read the A/D Converter results. For interrupts, the A/D Converter interrupt must be enabled by setting the ADCCNT1.INTE bit. The interrupt is cleared automatically when any one of the data registers (ADDATA0-ADDATA3) is read. For polling, the software reads the ADCST.EOC bit to determine whether the conversion sequence is completed. Once the A/D Converter configuration has been set up, the software can use the following procedure to perform an A/D conversion sequence: 1. Enable the A/D Converter by setting the ADCCNT1.ADCEN bit and wait 30 µs before performing any conversion. 2. Select the operating mode and channel by writing to the SCAN, CONT, and CHANNEL fields of the ADCCNT2 register. At the same time, start the conversion by setting the START bit in the same register. 3. Wait until the conversion is finished, either by polling or using the A/D Converter interrupt. 4. Read the conversion results from the data registers, ADDATA0 through ADDATA3 (or just ADDATA0 in the single-channel, single-conversion mode). 5. In the continuous conversion modes, repeat Step 3 and Step 4 for as long as samples are needed. Then stop the A/D Converter by clearing either the START bit (ADCCNT2.START) or the A/D Converter enable bit (ADCCNT1.ADCEN). To minimize power consumption, the A/D Converter should be disabled when it is not needed, especially before entering a Power Save mode. 22.3 A/D CONVERTER PROGRAMMING The software should set the A/D Converter configuration before it enables the A/D Converter module. The configuration consists of the following settings: — ADC clock rate: ADCCNT3.CDIV — Sampling delay: ADCCNT3.DELAY — Interrupt enable (if required): ADCCNT1.INTE The ADC clock is created by scaling down the system clock. The fastest allowable clock for the A/D Converter is 2 MHz. Therefore, for the fastest possible operation of the A/D Converter, use the smallest available divide-by factor that results in a clock frequency of 1 MHz or lower. The available divideby factors are 1, 2, 4, 8, 16, and 32. For example, if the system clock is 10 MHz, use a divide-by factor of 16. In that case, the A/D Converter clock frequency is 625 kHz, the clock period is 1.6 microseconds, and the A/ D conversion time is 16 microseconds (ten clock A/D Converter clock cycles). RSOURCE Input signal RAIN CAIN Analog Multiplexer Sample & Hold A/D Converter Figure 75. Sample-and-Hold Charge-Up Schematic 121 www.national.com 23.0 Memory Map The CompactRISC architecture supports a uniform linear address space of 2 megabytes. The device implementation of this architecture uses only the lowest 128K bytes of address space, ranging from 0000 to 1FFFF hex. Table 42 is a memTable 42 Address Range (hex) 0000-BFFF C000-CFFF E000-E5FF E800-EFFF F000-F07F F400-F7FF F800-FAFF FB00-FB06 FB00-FBFF FB10-FB16 FC00-FFFF FC40-FC8A FCA0-FCA8 FCC0-FCC8 FF00-FF08 FD20-FD28 FE00-FE1E FE40-FE4E FE60-FE66 FE80-FE8E FEC0-FECA FEE0-FEE8 FF20-FF2A FF40-FF50 FF60-FF70 FF80-FFA4 FFC0-FFD0 FFE0-FFE0 10000-1BFFF Description Flash Program Memory (48K bytes) Static RAM (4K bytes) ISP Memory(1.5K bytes) Zone 0 N/A Zone 1 ory map showing the types of memory and peripherals that occupy this memory space. Address ranges not listed in the table are reserved and should not be read or written. Device Memory Map BIU Zone Lower Endurance Flash EEPROM Data Memory (2K N/A bytes) High Endurance Flash EEPROM Data Memory (128 bytes) CAN buffers and registers (1K bytes) BIU Peripherals (768 bytes) Port B registers I/O Expansion + Ports PB & PC (256 bytes) Port C registers Peripherals and other I/O Ports (1K bytes) Clock, Power Management, and Wake-Up registers Port G registers Port H registers Port L registers Port F registers Interrupt Control Unit registers USART 1 registers MICROWIRE registers USART 2 registers ACCESS.bus registers Port I registers Timer and WATCHDOG registers Multi-function Timer1 registers Multi-function Timer2 registers Versatile Timer Unit registers A/D Converter registers Analog Comparator register Flash Program Memory (48K bytes) Zone 0 N/A I/O Expansion www.national.com 122 Table 43 is a detailed memory map showing the specific memory address of the memory, I/O ports, and registers. The table shows the starting address, the size, and a brief description of each memory block and register. For detailed information on using these memory locations, see the applicable sections in the data sheet. All addresses not listed in the table are reserved and should not be read or written. An attempt to access an unlisted address will have unpredictable results. Each byte-wide register occupies a single address and can be accessed only in a byte-wide transaction. Each word-wide register occupies two consecutive memory addresses and can be accessed only in a word-wide transaction. Both the Table 43 byte-wide and word-wide registers reside at word boundaries (even addresses). Thus, each byte-wide register uses only the lowest eight bits of the internal data bus. Most device registers are read/write registers. However, some registers are read-only or write-only, as indicated in the table. An attempt to read a write-only register or to write a read-only register will have unpredictable results. When the software writes to a register in which one or more bits are reserved, it must write a zero to each reserved bit unless indicated otherwise in the description of the register. Reading a reserved bit returns an undefined value. Device Detailed Memory Map Register Name Size 48K 4K 2K 1.5K 128 Register Address Access Type (hex) 0000 C000 E800 E000 F000 F400 F402 F404 F406 F408 F40A F40C F40E F410 F420 F430 F440 F450 F460 F470 F480 F490 F4A0 F4B0 F4C0 F4D0 F4E0 F500 F502 F504 F508 F50C F50E F510 Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write On-Chip RAM Contents Flash EEPROM Program Memory Low Endurance Flash EEPROM Data Memory ISP Memory High Endurance Flash EEPROM Data Memory CAN message buffer 0 Status Register CAN message buffer 0 Time stamp Register CAN message buffer 0 Data 3 Register CAN message buffer 0 Data 2 Register CAN message buffer 0 Data 1 Register CAN message buffer 0 Data 0 Register CAN message buffer 0 Identifier 0 Register CAN message buffer 0 Identifier 1 Register CAN message buffer 1 Register CAN message buffer 2 Register CAN message buffer 3 Register CAN message buffer 4 Register CAN message buffer 5 Register CAN message buffer 6 Register CAN message buffer 7 Register CAN message buffer 8 Register CAN message buffer 9 Register CAN message buffer 10 Register CAN message buffer 11 Register CAN message buffer 12 Register CAN message buffer 13 Register CAN message buffer 14 Register CAN Global Configuration Register CAN Timing Register CAN Global Mask Registers CAN Basic Mask Registers CAN Interrupt Enabled Register CAN Interrupt Pending Register CAN Interrupt Clear Register www.national.com CMB0_CNTSTAT CMB0_TSTP CMB0_DATA3 CMB0_DATA2 CMB0_DATA1 CMB0_DATA0 CMB0_ID0 CMB0_ID1 CMB1 CMB2 CMB3 CMB4 CMB5 CMB6 CMB7 CMB8 CMB9 CMB10 CMB11 CMB12 CMB13 CMB14 CGCR CTIM GMSKX and GMSK GMSKX and GMSKB CIEN CIPND CICLR word word word word word word word word 8-word 8-word 8-word 8-word 8-word 8-word 8-word 8-word 8-word 8-word 8-word 8-word 8-word 8-word word word word word word word word 123 Table 43 Device Detailed Memory Map Register Name CICEN CSTPND CANEC CEDIAG CTMR BCFG IOCFG SZCFG0 SZCFG1 MCFG MSTAT FLCTRL1 FLSEC ISPKEY FLCTRL2 DMCSR DMPSLR DMSTART DMTRAN DMPROG DMERASE DMEND DMPCNT DMCNT DMKEY FLCSR FLPSLR FLSTART FLTRAN FLPROG FLERASE FLEND FLPCNT FLCNT1 FLCNT2 PGMKEY PBDIR PBDIN PBDOUT PBWKPU PCDIR PCDIN PCDOUT PCWKPU Size word word word word word byte word word word byte byte byte byte byte word byte byte byte byte byte byte byte byte word byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte Register Address Access Type (hex) F512 F514 F516 F518 F51A F900 F902 F904 F906 F910 F914 F930 F932 F934 F936 F940 F942 F944 F946 F948 F94A F94C F94E F950 F954 F960 F962 F964 F966 F968 F96A F96C F96E F970 F972 F974 FB00 FB02 FB04 FB06 FB10 FB12 FB14 FB16 Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read Only Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read Only Read/Write Read/Write Read/Write Read Only Read/Write Read/Write Contents CAN Interrupt Code Enable Register CAN Status Pending Register CAN Error Counter Register CAN Error Diagnostic Register CAN Timer Register BIU Configuration Register I/O Zone Configuration Register Static Zone 0 Configuration Register Static Zone 1 Configuration Register Module Configuration Register Module Status Register Flash EEPROM Program Memory Control Register 1 Flash EEPROM Program Memory Security Register ISP Memory Write Key Register Flash EEPROM Program Memory Control Register 2 EEPROM Data Memory Control and Status Register EEPROM Data Memory Prescaler Register Data Memory Start Time Reload Register Data Memory Transition Time Reload Register Data Memory Programming Time Reload Register Data Memory Erase Time Reload Register Data Memory End Time Reload Register Data Memory Prescaler Count Register Data Memory Timer Count Register EEPROM Data Memory Write Key Register Flash EEPROM Program Memory Control and Status Register Flash EEPROM Program Memory Prescaler Register Program Memory Start Time Reload Register Program Memory Transition Time Reload Register Program Memory Programming Time Reload Register Program Memory Erase Time Reload Register Program Memory End Time Reload Register Program Memory Prescaler Count Reload Register Program Memory Timer Count Register 1 Program Memory Timer Count Register 2 Flash EEPROM Program Memory Write Key Register Port B Direction Register Port B Data Input Register Port B Data Output Register Port B Weak Pull-Up Register Port C Direction Register Port C Data Input Register Port C Data Output Register Port C Weak Pull-Up Register www.national.com 124 Table 43 Device Detailed Memory Map Register Name CRCTRL PRSSC PRSSC1 PMCSR WKEDG WKENA WKICT1 WKICTL2 WKPND WKPCL PGALT PGDIR PGDIN PGDOUT PGWKPU PHALT PHDIR PHDIN PHDOUT PHWKUP PFALT PFDIR PFDIN PFDOUT PFWKPU IVCT NMISTAT EXNMI ISTAT0 ISTAT1 IENAM0 IENAM1 IDBG U1TBUF U1RBUF U1ICTRL U1STAT U1FRS U1MDSL U1BAUD U1PSR MWDAT MWCTL MWSTAT U2TBUF Size byte byte byte byte word word word word word word byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte word word word word word byte byte byte byte byte byte byte byte byte byte word byte Register Address Access Type (hex) FC40 FC42 FC44 FC60 FC80 FC82 FC84 FC86 FC88 FC8A FCA0 FCA2 FCA4 FCA6 FCA8 FCC0 FCC2 FCC4 FCC6 FCC8 FD20 FD22 FD24 FD26 FD28 FE00 FE02 FE04 FE0A FE0C FE0E FE10 FE1A FE40 FE42 FE44 FE46 FE48 FE4A FE4C FE4E FE60 FE62 FE64 FE80 Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read Set Write Only Read/Write Read/Write Read/Write Read Only Read/Write Read/Write Read/Write Read/Write Read Only Read/Write Read/Write Read/Write Read/Write Read Only Read/Write Read/Write Read Only Read Only Read/Write Read Only Read Only Read/Write Read/Write Read/Write Read/Write Read Only Read/Write Read Only Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Contents Clock and Reset Control Register Slow Clock Prescaler Register Prescaler Slow Clock 1 Register Power Management Control/Status Register Wake-Up Edge Detection Register Wake-Up Enable Register Wake-Up Interrupt Control Register 1 Wake-Up Interrupt Control Register 2 Wake-Up Pending Register Wake-Up Pending Clear Register Port G Alternate Function Register Port G Direction Register Port G Data Input Register Port G Data Output Register Port G Weak Pull-Up Register Port H Alternate Function Register Port H Direction Register Port H Data Input Register Port H Data Output Register Port H Weak Pull-Up Register Port F Alternate Function Register Port F Direction Register Port F Data Input Register Port F Data Output Register Port F Weak Pull-Up Register Interrupt Vector Register NMI Status Register External NMI Control/Status Register Interrupt Status Register 0 Interrupt Status Register 1 Interrupt and Enable Mask Register 0 Interrupt and Enable Mask Register 1 Interrupt Debug Register USART 1 Transmit Data Buffer USART 1 Receive Data Buffer USART 1 Interrupt Control Register USART 1 Status Register USART 1 Frame Select Register USART 1 Mode Select Register USART 1 Baud Rate Divisor Register USART 1 Baud Rate Prescaler MICROWIRE Data Register MICROWIRE Control Register MICROWIRE status Register USART 2 Transmit Data Buffer www.national.com 125 Table 43 Device Detailed Memory Map Register Name U2RBUF U2ICTRL U2STAT U2FRS U2MDSL ACBSDA U2BAUD U2PSR ACBST ACBCST ACBCTL1 ACBADDR ACBCTL2 PIALT PIDIR PIDIN PIDOUT PIWKPU PLALT PLDIR PLDIN PLDOUT PLWKPU TWCFG TWCP TWMT0 T0CSR WDCNT WDSDM T1CNT1 T1CRA T1CRB T1CNT2 T1PRSC T1CKC T1CTRL T1ICTL T1ICLR T2CNT2 T2CRA T2CRB T2CNT2 T2PRSC Size byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte word byte byte byte word word word word byte byte byte byte byte word word word word byte Register Address Access Type (hex) FE82 FE84 FE86 FE88 FE8A FEC0 FE8C FE8E FEC2 FEC4 FEC6 FEC8 FECA FEE0 FEE2 FEE4 FEE6 FEE8 FF00 FF02 FF04 FF06 FF08 FF20 FF22 FF24 FF26 FF28 FF2A FF40 FF42 FF44 FF46 FF48 FF4A FF4C FF4E FF50 FF60 FF62 FF64 FF66 FF68 Read Only Read/Write Read Only Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read Only Read/Write Read/Write Read/Write Read/Write Read Only Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Write Only Write Only Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Contents USART 2 Receive Data Buffer USART 2 Interrupt Control Register USART 2 Status Register USART 2 Frame Select Register USART 2 Mode Select Register ACB Serial Data Register USART 2 Baud Rate Divisor Register USART 2 Baud Rate Prescaler ACB Status Register ACB Control Status Register ACB Control 1 Register ACB Own Address Register ACB Control 2 Register Port I Alternate Function Register Port I Direction Register Port I Data Input Register Port I Data Output Register Port I Weak Pull-Up Register Port L Alternate Function Register Port L Direction Register Port L Data Input Register Port L Data Output Register Port L Weak Pull-Up Register Timer and WATCHDOG Configuration Register Timer and WATCHDOG Clock Prescaler Register TWM Timer 0 Register TWMT0 Control and Status Register WATCHDOG Count Register WATCHDOG Service Data Match Register T1 Timer/Counter I Register T1 Reload/Capture A Register T1 Reload/Capture B Register T1 Timer/Counter II Register T1 Clock Prescaler Register T1 Clock Unit Control Register T1 Timer Mode Control Register T1 Timer Interrupt Control Register T1 Timer Interrupt Clear Register T2 Timer/Counter I Register T2 Reload/Capture A Register T2 Reload/Capture B Register T2 Timer/Counter II Register T2 Clock Prescaler Register www.national.com 126 Table 43 Device Detailed Memory Map Register Name T2CKC T2CTRL T2ICTL T2ICLR MODE IO1CTL IO2CTL INTCTL INTPND CLK1PS COUNT1 PERCAP1 DTYCAP1 COUNT2 PERCAP2 DTYCAP2 CLK2PS COUNT3 PERCAP3 DTYCAP3 COUNT4 PERCAP4 DTYCAP4 ADCST ADCCNT1 ADCCNT2 ADCCNT3 ADDATA0 ADDATA1 ADDATA2 ADDATA3 CMPCTRL Size byte byte byte byte word word word word word word word word word word word word word word word word word word word byte byte byte byte byte byte byte byte byte Register Address Access Type (hex) FF6A FF6C FF6E FF70 FF80 FF82 FF84 FF86 FF88 FF8A FF8C FF8E FF90 FF92 FF94 FF96 FF98 FF9A FF9C FF9E FFA0 FFA2 FFA4 FFC0 FFC2 FFC4 FFC6 FFCA FFCC FFCE FFD0 FFE0 Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read Only Read Only Read Only Read Only Read/Write Contents T2 Clock Unit Control Register T2 Timer Mode Control Register T2 Timer Interrupt Control Register T2 Timer Interrupt Clear Register Mode Control Register I/O Control Register 1 I/O Control Register 2 Interrupt Control Register Interrupt Pending Register Clock Prescaler Register 1 Counter Register 1 Period/Capture Register 1 Duty Cycle/Capture Register 1 Count Register 2 Period/Capture Register 2 Duty Cycle/Capture Register 2 Clock Prescaler Register 2 Count Register 3 Period/Capture Register 3 Duty Cycle/Capture Register 3 Count Register 4 Period/Capture Register 4 Duty Cycle/Capture Register 4 A/D Converter Status Register A/D Converter Control 1 Register A/D Converter Control 2 Register A/D Converter Control 3 Register A/D Converter Data 0 Register A/D Converter Data 1 Register A/D Converter Data 2 Register A/D Converter Data 3 Register Analog Comparator Control/Status Register 127 www.national.com 24.0 Register Layouts The following tables show the functions of the bit fields of the device registers. For more information on using these registers, see the detailed description of the applicable function elsewhere in this data sheet. 24.1 REGISTER LAYOUT 15 XI28 ID10 XI14 Data 1.7 Data 3.7 Data 5.7 Data 7.7 CAN Memory Registers CMBn.ID1 CMBn.ID0 CMBn.DATA0 CMBn.DATA1 CMBn.DATA2 CMBn.DATA3 CMBn.TSTP CMBn.CNTSTAT 14 XI27 ID9 XI13 Data 1.6 Data 3.6 Data 5.6 Data 7.6 13 XI26 ID8 XI12 Data 1.5 Data 3.5 Data 5.5 Data 7.5 12 XI25 ID7 XI11 Data 1.4 Data 3.4 Data 5.4 Data 7.4 11 XI24 ID6 XI10 Data 1.3 Data 3.3 Data 5.3 Data 7.3 10 XI23 ID5 XI9 Data 1.2 Data 3.2 Data 5.2 Data 7.2 9 XI22 ID4 XI8 Data 1.1 Data 3.1 Data 5.1 Data 7.1 8 XI21 ID3 XI7 Data 1.0 Data 3.0 Data 5.0 Data 7.0 7 XI20 ID2 XI6 Data 2.7 Data 4.7 Data 6.7 Data 8.7 6 XI19 ID1 XI5 Data 2.6 Data 4.6 Data 6.6 Data 8.6 5 XI18 ID0 XI4 Data 2.5 Data 4.5 Data 6.5 Data 8.5 4 SRR RTR XI3 Data 2.4 Data 4.4 Data 6.4 Data 8.4 3 2 1 0 IDE XI2 Data 2.3 Data 4.3 Data 6.3 Data 8.3 XI17 XI1 Data 2.2 Data 4.2 Data 6.2 Data 8.2 XI16 XI0 Data 2.1 Data 4.1 Data 6.1 Data 8.1 XI15 RTR Data 2.0 Data 4.0 Data 6.0 Data 8.0 TSTP15 TSTP14 TSTP13 TSTP12 TSTP11 TSTP10 TSTP9 TSTP8 TSTP7 TSTP6 TSTP5 TSTP4 TSTP3 TSTP2 TSTP1 TSTP0 DLC3 DLC2 DLC1 DLC0 Reserved PRI3 PRI2 PRI1 PRI0 ST3 ST2 ST1 ST0 CAN Control/ Status CGCR CTIM GMSKB GMSKX BMSKB BMSKX CIEN CIPND CICLR CICEN CSTPND CANEC CEDIAG CTMR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved EIT DIAGEN INTERNAL LOOPBACK IGNACK LO DDIR TSTPEN BUFFLOCK CRX CTX CANEN PSC[6:0] GM[28:18] SJW[1:0] TSEG1[3:0] RTR IDE TSEG2[2:0] GM[17:15] XRTR GM[14:0] BM[28:18] BM[14:0] EIEN EIPND EICLR EICEN Reserved REC[7:0] Reserved DRIVE MON CRC STUFF TXE EBID[5:0] RTR IDE BM[17:15] XRTR IEN[14:0] IPND[14:0] ICLR[14:0] ICEN[14:0] NS[2:0] IRQ TEC[7:0] EFID[3:0] IST[3:0] CTMR[15:0] www.national.com 128 System Configuration Registers MCFG MSTAT 7 Reserved 6 5 CLK2OE Reserved 4 Reserved 3 2 CLK1OE Reserved 1 CLKOE OENV1 0 Reserved OENV0 PGMBUSY BIU Registers BCFG IOCFG SZCFG0 SZCFG1 15 12 11 10 9 8 7 6 5 4 3 2 1 0 EWR Reserved Reserved Reserved Reserved IPST Res FRE IPRE IPST Res FRE IPRE IPST Res BW BW BW Reserved Reserved Reserved HOLD HOLD HOLD WAIT WAIT WAIT ISP Registers FLCTRL1 FLCTRL2 FLSEC ISPKEY 15 13 12 10 9 8 7 6 5 4 3 BOOTAREA 2 1 0 Reserved EMPTY Reserved Reserved Reserved FROMWR CODEAREA FROMRD ISPKYVAL Flash Data Memory Registers DMCSR DMPSLR DMSTART DMTRAN DMPROG DMERASE DMEND DMPCNT DMCNT DMKEY 15 14 10 9 8 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved ERASE DMBUSY ZEROWS Reserved FTDIV FTSTART FTTRAN FTPROG FTER FTEND FTPCNT FTCNT DMKEYVAL 129 www.national.com Flash EEPROM Program Memory Registers FLCSR FLPSLR FLSTART FLTRAN FLPROG FLERASE FLEND FLPCNT FLCNT1 FLCNT2 PGMKEY 7 MERASE 6 5 Reserved 4 3 2 1 PMER 0 Reserved PMLFULL PMBUSY FTDIV FTSTART FTTRAN FTPROG FTER FTEND FTPCNT FTCNTL (0:7) Reserved PMKEYVAL FTCNTL (8:9) GPIO Registers PxALT PxDIR PxDIN PxDOUT PxWPU 7 6 5 4 3 2 1 0 Px Pins Alternate Function Enable Px Port Direction Px Port Output Data Px Port Input Data Px Port Weak Pull-up Enable ICU31L Registers IVCT NMISTAT EXNMI ISTAT0 ISTAT1 IENAM0 IENAM1 IDBG 15 12 11 8 7 0 6 0 5 4 3 2 1 0 Reserved INTVECT Reserved EXT ENLCK IST(15:0) IST(31:16) IENA(15:0) IENA(31:16) PIN EN Reserved Reserved IRQVECT INTVECT www.national.com 130 MIWU16 Registers WKEDG WKENA WKICTL1 WKICTL2 WKPND WKPCL 15 14 13 12 11 10 9 8 WKED WKEN 7 6 5 4 3 2 1 0 WKINTR7 WKINTR15 WKINTR6 WKINTR14 WKINTR5 WKINTR13 WKINTR4 WKINTR12 WKINTR3 WKINTR11 WKINTR2 WKINTR10 WKINTR1 WKINTR0 WKINTR9 WKINTR8 WKPD WKCL Dual Clock + Reset Registers CRCTRL PRSSC PRSSC1 7 6 5 4 3 2 1 POR 0 SCLK Reserved SCDIV SCDIV2 SCDIV1 Power Management Register PMCSR 7 OLFC 6 OHFC 5 WBPSM 4 Reserved 3 HALT 2 IDLE 1 DHF 0 PSM USART Registers UnTBUF UnRBUF UnICTRL UnSTAT UnFRS UnMDSL UnBAUD UnPSR 7 6 5 4 UnTBUF UnRBUF 3 2 1 0 UnEEI Reserved Reserved UnERI UnXMIP UnPEN UnETI UnRB9 UnBKD Reserved UnERR UnXB9 UnCKS UnDIV[7]: UnDIV[0] UnDOE UnSTP UnBRK UnRBF UnFE UnTBE UnPE UnPSEL UnCHAR UnATN UnMOD Reserved UnPSC UnDIV[10]: UnDIV[8] MWSPI16 Registers MWDAT MWCTL MWSTAT 15 9 8 7 6 5 MWDAT 4 3 2 1 0 MCDV MIDL MSKM MEIW MEIR MEIO MECH MMOD MOVR MMNS MRBF MEN MBSY Reserved 131 www.national.com ACB Registers ACBSDA ACBST ACBCST ACBCTL1 ACBADDR ACBCTL2 7 6 5 4 DATA 3 2 1 0 SLVSTP SDAST BER TGSCL GCMEN NEGACK TSDA ACK STASTR GMATCH Reserved ADDR NMATCH MATCH INTEN MASTER BB STOP XMIT BUSY START Reserved STASTRE SAEN NMINTE SCLFRQ ENABLE TIMER Registers TnCNT1 TnCRA TnCRB TnCNT2 TnPRSC TnCKC TnCTRL TnICTL TnICLR 15 8 7 6 5 4 TnCNT1 TnCRA TnCRB TnCNT2 3 2 1 0 Reserved Reserved Reserved TnAOUT TnDIEN TnCIEN TnBEN TnBIEN C2CSEL TnAEN TnAIEN TnBEDG TnDPND TnDCLR CLKPS C1CSEL TnAEDG TnCPND TnCCLR MDSEL TnBPND TnBCLR TnAPND TnACLR Reserved www.national.com 132 VTU Registers MODE IO1CTL IO2CTL INTCTL INTPND CLK1PS COUNT1 PERCAP1 DTYCAP1 COUNT2 PERCAP2 DTYCAP2 CLK2PS COUNT3 PERCAP3 DTYCAP3 COUNT4 PERCAP4 DTYCAP4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TMOD4 P4POL P8POL I4DEN I4DPD I4CEN I4CPD T8RUN T7RUN C4EDG C8EDG I4BEN I4BPD I4AEN I4APD TMOD3 P3POL P7POL I3DEN I3CEN I3DPD I3CPD T6RUN T5RUN C3EDG C7EDG I3BEN I3BPD I3AEN I3APD TMOD2 P2POL P6POL I2DEN I2DPD I2CEN I2CPD T4RUN T3RUN C2EDG C6EDG I2BEN I2BPD I2AEN I2APD TMOD1 P1POL P5POL I1DEN I1DPD I1CEN I1CPD T2RUN T1RUN C1EDG C5EDG I1BEN I1BPD I1AEN I1APD C2PRSC CNT1 PCAP1 DCAP1 CNT2 PCAP2 DCAP2 C4PRSC CNT3 PCAP3 DCAP3 CNT4 PCAP4 DCAP4 C1PRSC C3PRSC TWM Registers TWCFG TWCP TIMER0 T0CSR WDCNT WDSDM 15 8 7 6 5 WDSDME 4 WDCT0I 3 LWDCNT 2 LTWMT0 1 LTWCP MDIV 0 LTWCFG Reserved Reserved PRESET Reserved PRESET RSTDATA T0INTE TC RST 133 www.national.com A/D Registers ADCST ADCCNT1 ADCCNT2 ADCCNT3 ADDATA0 ADDATA1 ADDATA2 ADDATA3 7 Reserved 6 5 BUFPTR Reserved 4 3 Reserved Reserved 2 OVF INTE 1 BUSY Reserved 0 EOC ADCEN START Reserved SCAN PWREN CONT DELAY RESULT 1 DATA RESULT 2 DATA RESULT 3 DATA RESULT 4 DATA CHANNEL CDIV Analog Comp. Registers CMPCTRL 7 6 5 CMP2OE 4 CMP1OE 3 CMP2EN 2 CMP1EN 1 CMP2RD 0 CMP1RD Reserved www.national.com 134 25.0 ELECTRICAL AND THERMAL CHARACTERISTICS Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (VCC) Voltage at Any Pin * ESD Protection Level Total Current into V CC Pin (Source) 7V –0.6V to V CC +0.6V 2 kV (Human Body Model) 200 mA Total Current out of GND Pin (Sink) Storage Temperature Range 200 mA –65°C to +150°C Note: Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings. * The latch-up tolerance on Access Bus pins 14 and 15 meets 150mA. Thermal Characteristics Characteristics Average junction temperature Ambient temperature Package thermal resistance (junction-to-ambient) 80-pin quad flat pack (QFP) Total power dissipation1 PD Symbol TJ TA ~JA Value TA + (PD X ~JA) User-determined 49.8 PINT + PI/O or K TJ + 273°C IDD X VDD User-determined PD x (TA + 273°C) + ~ JA x PD2 Unit °C °C °C/W W Device internal power dissipation I/O pin power dissipation2 A constant 3 PINT PI/O K W W W, °C 1. This is an approximate value, neglecting PI/O. 2. For most applications PI/O