CS1301

Geode™ CS1301/CS1311 Multimedia Companion: Media Data Processor Preliminary August 2002 Revision 2.2 Geode™ CS1301/CS1311 Multimedia Companion: Media Coprocessor General Description The National Semiconductor® Geode™ CS1301 and CS1311 multimedia companions act as coprocessors to decode multimedia in National’s Geode single chip processor-based systems (i.e., SC1200/SC1201, SC2200, and SC3200, hereafter referred to as SCx200). They provide a multimedia experience for an Information Appliance (IA) user that cannot typically be achieved on a PC. By implementing a dedicated coprocessor to perform multimedia tasks, a high quality video viewing experience can be achieved. This high quality is achieved by having a coprocessor architecture that is ideally suited for decoding digital media. In addition, since the decoding is not occurring on the SCx200, system events cannot interrupt the coprocessor’s task of decoding media and thereby causing stuttering of sound or interruptions in the video. Lower power consumption can also be achieved using the SCx200/CS1301 or SCx200/CS1311 solution. The CS1301/CS1311 has an architecture specifically designed for decoding media. The architecture is such that while decoding media, power is not consumed by portions of the system that are not used to decode media. Since the SCx200 is not decoding the media locally, it is able to go into a lower power state. When the CS1301/CS1311 is not decoding media, it uses almost no power. Additionally, since the architecture is designed for decoding media, fewer CS1301/CS1311 cycles are required. Internal Block Diagram SDRAM 32-Bit Data (up to 664 MB/sec) Main Memory Interface CCIR-656 Digital Video YUV 4:2:2 up to 81 MHz (40 Mpix/sec) Stereo Digital Audio 8/16-bit data I2S DC, up to 22 MHz AI_SCK Video In Video Out CCIR-656 Digital Video 2/4/6/8 Ch. Digital Audio 16/32-Bit Data I2S DC, up to 22 MHz AO_SCK IEC958 up to 40 Mbit/sec Audio In Audio Out VLD Coprocessor Huffman Decoder Slice-At-A-Time MPEG-1 & 2 S/PDIF Out Timers ACCESS.bus Interface ACCESS.bus Interface to EEPROM VLIW CPU 32K I$ 16K D$ Image Coprocessor Down and Up Scaling YUV --> RGB (50 Mpix/sec) PCI Interface External Bus PCI V2.1 (32 bits, 33 MHz) National Semiconductor and Virtual System Architecture are registered trademarks of National Semiconductor Corporation. Geode, MacPHYTER, WebPAD, and VSA are trademarks of National Semiconductor Corporation. For a complete listing of National Semiconductor trademarks, please visit www.national.com/trademarks. © 2002 National Semiconductor Corporation 1 www.national.com Geode™ CS1301/CS1311 Features General Features s Physical s Process 0.25-micron CMOS s Packaged in a 292-terminal TEPBGA (Thermally VLD Coprocessor s Parses MPEG-1 and MPEG-2 elementary bit streams generating run-level pairs and filling macroblock headers Timers s Four 32-bit wide timers Enhanced Plastic Ball Grid Array) s Power supply: — CS1301: 2.5V Core; 3.3V I/O (5V tolerant) — CS1311: 2.2V Core; 3.3V I/O (5V tolerant) s Consumption 1300 mA; 3.5W s Power-down 300 mA s Case Temperature 0° to 85°C Input/Output Support s PCI Interface: — — — — PCI 2.1 compliant Speed 33 MHz Bus width 32 bits Voltage drive and receive at 3.3V Central Processing Unit s Clock speed: s Audio In (AI): — CS1301: 180 MHz — CS1311: 166 MHz s Instruction length variable (2 to 23 bytes) s Instruction set arithmetic and logical operations, — Two I2S compliant channels — Sample size 8 or 16-bit samples per channel s Audio Out (AO): — Eight I2S compliant channels — Sample size 16 or 32-bit samples per channel s Video In (VI): load/store operations, special multimedia and DSP operations, IEEE compliant floating point operations s Functional units 27, pipelined Caches s Data 16 KB, instructions 32 KB — Supported signals CCIR-601/656: – 8-bit video (up to 40 Mpix/sec) — Image sizes all sizes, subject to sample rate — Provides programmable on-the-fly 2X horizontal resolution subsampling s Video Out (VO): Memory System s Speed 166 MHz SDRAM s CPU/Memory programmable; 1:1, 5:4, 4:3, 3:2, and 2:1 speed ratios s Memory size 512 KB to 64 MB (up to four banks) s Recommended configurations: — Image sizes flexible, including CCIR-601; max. 4K x 4K pixels (subject to 80 MB/sec data rate) — Outputs CCIR-601/656 8-bit video, PAL or NTSC — Clock rates programmable (4-80 MHz), typical 27 MB/sec (13.5 Mpix/sec for NTSC, PAL; 40 Mpix/sec in YUV 4:2:2 mode) — Features full 129-level alpha blending, GenLock mode, frame synchronization chroma key, programmable YUV color clipping s S/PDIF Out: — 16 MB: Two 4M x 16 or two 2M x 32 — 32 MB: Four 2M x 32 or four 4M x 16 s Width 32-bit bus s Max. bandwidth 664 MB/sec (at 166 MHz) — Number of channels up to 6 — Sample size 16 or 24 bits per channel — IEC-958, output up to 40 Mbits/sec s ACCESS.bus Interface: Image Coprocessor s Scaling programmable scale factor (0.2X to 10X) using 5-tap filters: — Horizontal or vertical scaling and filtering of individual Y, U or V — Horizontal scaling and filtering with color conversion and overlay — HYUV to RGB, RGB overlay and alpha blending, bit mask blanking — Supported modes single master only — Addressing 7-bit — Rates up to 400 Kbps www.national.com 2 Revision 2.2 Geode™ CS1301/CS1311 1.0 System Architecture 1.1 IMPORTANT DESIGN NOTE The CS1301/CS1311 was designed to be a general purpose media data processor. As such, the CS1301/CS1311 is capable of far more than the current National CS1301/CS1311 solution. The solution that National is providing is only one possible implementation of the CS1301/CS1311 and only this implementation is fully supported by National Semiconductor. In order to maintain software compatibility with National’s provided software, any deviation of the CS1301/CS1311 section of the schematic is strongly discouraged. For those wishing to deviate from the schematic, or wishing to take advantage of other features of the CS1301/CS1311, documentation is available on the Philips Semiconductors SDE CD-ROM to support design variations. However, additional support to implement these variations must be obtained from one of the TriMedia Alliance Partners who support the CS1301/CS1311, its software, and the peripheral functions. For a list of TriMedia Alliance Partners, visit: http://www.trimedia.com/TAPP/ The CS1301/CS1311 multimedia companion acts as a coprocessor to decode multimedia in National’s Geode SC1200/SC1201, SC2200, and SC3200 (SCx200 unless otherwise specified). Figure 1-1 provides a typical system block diagram. Media decoding is one of the most demanding system applications. If media is decoded on the main processor, a much higher performance processor is required to achieve even comparable levels of media decoding quality. Such a system would be significantly over-designed for other tasks, such as browsing the Internet. Using a low-cost processor that is ideally suited for all tasks, and adding the coprocessor for the high performance media decoding requirement, results in a cost-effective solution. Another advantage of an processor/coprocessor solution is that an OEM (Original Equipment Manufacturer) can provide a scalable solution. A single board can be designed that supports the coprocessor. If it is desired to support a low-end product that does not support the high quality media decoding capabilities, the coprocessor and its supporting components can be excluded from the system, which results in additional savings in an already cost-effective design. SDRAM Flash or M-Systems’ DiskOnChip XpressROM BIOS Control IDE CompactFlash Data AMP LM4880 Sub-ISA Codec LM4549 CCIR 656 VIP WM8725 DAC PCI Bus USB 1, 2, 3 GeodeTM SCx200 IRDA SDRAM GeodeTM CS1301/ CS1311 Display: TV, CRT, or TFT EEPROM Figure 1-1. System Block Diagram Revision 2.2 3 www.national.com Geode™ CS1301/CS1311 System Architecture (Continued) 1.2 SOFTWARE MPEG-2 Decoding • Program stream (ISO 13818-1): DVD style MPEG-2 program stream • Video stream (ISO 13818-2) - Main level at main profile: — Full screen NTSC (720x480) at 29.97 fps — Full screen PAL (720x576) at 25 fps • Audio stream - MPEG-2 audio: — Layers 1 and 2 (ISO 13818-3) at 32 KHz, 44.1 KHz or 48 KHz sample rate — AC3 audio at 32 KHz, 44.1 KHz or 48 KHz sample rate MPEG-1, MPEG-2 Layer 3 Audio Decoding (MP3) 1.2.1 Software Support National provides a reference schematic and the associated software for a processor/coprocessor solution using the Geode SCx200 and the CS1301/CS1311. This implementation is currently supplied as a multimedia decoder for CE player under Microsoft Windows CE.net or Linux. Future support for Microsoft Windows XP is planned. Since this is a software-based DSP (Digital Signal Processor) coprocessor rather than strictly a silicon-based coprocessor, the software can be upgraded to support evolving media standards without a redesign of the hardware. 1.2.2 Software Features Support The CS1301/CS1311 multimedia solution supports the following software components: General Support • Reverse 3:2 pull down • Progressive display output • Capture Video Input MPEG-1 Decoding • System stream (ISO 11172-1): — Up to 1.5 Mbps • Video stream (ISO 11172-2): — CIF (up to 360x288) resolution — 29.97 fps (NTSC) — 25 fps (PAL) — Up to 1.12 Mbps • Audio stream (ISO 11172-3): MPEG-1 layers 1 and 2: — Up to 384 Kbps, 32 KHz, 44.1 KHz or 48 KHz sample rate Windows Media Player Integration An implementation has been developed to seamlessly integrate Windows Media Player with WindowsCE.net or Linux. National has taken advantage of the native playback features supported by Microsoft DirectShow and has extended that functionality to the CS1301/CS1311. WindowsCE.net ships with an ActiveX control that wraps the filter graph manager and provides a very high level API (Application Programming Interface). It also supports a browser plug-in. An application writer can use the ActiveX control interface to playback MPEG-1/MPEG-2 media types. The user can also open the MPEG-1/MPEG-2/WMT files in Windows Media Player by double clicking on the file or by launching WMP, then opening the selected media. New codecs are continually being developed and added (see National’s IA Developer’s web site for a list of supported codecs). The CS1301/CS1311 software and reference schematic is provided for a system that decodes media quickly with no original software development needed. As part of the CS1301/CS1311 purchase (see Section A.1 "Ordering Information" on page 24 for purchase details), National will license for the use of the operating system drivers and media decoder codecs in object form, which include: • Communications manager driver. • Video filter: Takes the video from the VIP (Video Input Port) of the Geode SCx200 and plays it back through the operating system media player. • Various multimedia codecs. • Up to 384 Kbps • Up to 48 KHz sample rate • Fixed bit rate decoding MPEG-4 Decoding • Video stream - “Simple profile”: — CIF resolution at 30 fps, up to 384 Kbps • Audio stream - “High quality profile”: — MPEG-4 AAC low complexity and MPEG-4 CELP WMT (Windows Media Technology) Decoding • Video stream - Windows Media Video v8, also supports v7 decode: — CIF resolution at 30 fps, up to 1 Mbps • Audio stream - Windows Media Audio v8, also supports v7 decode: — Up to 128 Kbps and 48 KHz sample rate www.national.com 4 Revision 2.2 Geode™ CS1301/CS1311 System Architecture (Continued) 1.2.3 Software Architecture Overview Figure 1-2 demonstrates the interaction between the various software layers. Note: The shaded boxes indicate components provided by Microsoft Corporation. Windows Media Player ActiveX Control Filter Graph Manager File Source DirectShow Filter TMComm TMMan32/HostComm/LibLoad/TMCRT Video Renderer Geode™ SCx200 TMMan Driver Geode Part TMMan Driver TM Part TMMan32/HostComm/LibLoad/TMCRT CommTM To SCx200 Video Input Port DAC Geode™ CS1301/CS1311 ExolTMpeg Application TSSA* Video Decoder TRead Demux Audio Decoder * TriMedia Streaming Software Architecture VTransCrystal Video Renderer Audio Renderer Figure 1-2. Software Architecture Diagram Revision 2.2 5 www.national.com Geode™ CS1301/CS1311 System Architecture (Continued) 1.2.4 Software Component Pricing and Licensing National delivers and supports a complete software solution when paired up with the WindowsCE.net or Linux operating system. The delivered software is a compilation of software created by National Semiconductor, Philips Semiconductors and Microsoft. Customers may need separate pricing and support agreements for Windows Media Technology (Microsoft), BIOS, Operating System, and middleware. National’s pricing excludes fundamental patents: MPEG-1, -2, -4 (MPEG-LA) and MP3 (Thomson Multimedia/Fraunhofer ILS). The following tables list the associated software, their respective owners and the licensing requirements for each. 1.2.4.1 Codec Software The codec software includes video and audio decoders and operates on the CS1301/CS1311 (see Table 1-1). This software performs the task of decoding the encoded media content, which are the workhorses of the solution. 1.2.4.2 Host Filter Software The DirectShow filter is the core piece of software that integrates the CS1301/CS1311 media companion with Microsoft DirectShow (see Table 1-2). Table 1-1. Codec Software Components TM MP3 Decoder TM MP3 Basic Application TM MPEG-1 Video Decoder TM MPEG-1 Audio Decoder TM MPEG-2 Video Decoder TM MPEG-2 Audio Decoder TM AC-3 Audio Decoder TM MPEG-2 Program Stream Demux TM MPEG-2 Basic Application TM MPEG-4 Video Decoder TM MPEG-4 AAC Audio Decoder TM MPEG-4 CELP Audio Decoder TM MPEG-1 File Parser and Demultiplexer TM MPEG-4 Basic Application TM WMT v8 Video Decoder TM WMT v8 Audio Decoder National Semiconductor Microsoft Binary Microsoft WMT license required. IP Owner(s) Philips Semiconductors Available as Source/Binary Binary Licensing Requirements Licensee is responsible for licensing of all fundamental patents. Table 1-2. Host Filter Software Components DirectShow Filter IP Owner National Semiconductor Available as Source/Binary Binary Licensing Requirements Not licensed as source code. www.national.com 6 Revision 2.2 Geode™ CS1301/CS1311 System Architecture (Continued) 1.2.4.3 Communications Driver Software The communications driver software includes most of the components that perform the communication and control tasks between the Geode SCx200 and the CS1301/CS1311 (see Table 1-3). 1.2.4.4 Software Development Kit The Software Development Kit (SDK) includes the core software components that run on the TM32A core of the CS1301/CS1311. These are the supporting software components that enable the execution of the codec software on the CS1301/CS1311 (see Table 1-4). 1.2.4.5 System Software To expand system functionality beyond media decoding, Geode software components are included. These are standard components to be used in a non-media enabled application to support the required functions of an Information Appliance. In some cases, these drivers have been optimized to work with the CS1301/CS1311 (see Table 1-5). Table 1-3. Communications Driver Software Components Host TMMan Driver TM TMMan Library TMComm Library HostComm Library TMCRT Library TMMan 32 LibLoad TriMedia Technologies, Inc. Binary NA IP Owner(s) National Semiconductor Philips Semiconductors Available as Source/Binary Open Source Licensing Requirements Per Philips Semiconductors public source license provisions. Table 1-4. SDK Software Components COMMTM Video Renderer Audio Renderer TRead VTrans Crystal PSOS VxWorks Binary OS run-time licenses. IP Owner(s) National Semiconductor Philips Semiconductors Available as Source/Binary Binary Licensing Requirements NA Table 1-5. System Software Components Graphics Driver (Linux, WinCE.net) Audio Driver (Linux, WinCE.net) WinCE.net Power Management OAL Touchscreen Driver (Linux, WinCE.net) National’s DP83815 MacPHYTER™ Network Driver (Linux, WinCE.net) IP Owner(s) National Semiconductor Available as Source/Binary Source Licensing Requirements National source code license. Revision 2.2 7 www.national.com Geode™ CS1301/CS1311 2.0 Signal Definitions Table 2-1 shows the types of I/O circuits used by the CS1301/CS1311 series. Note that the # symbol in a signal name indicates that the active or asserted state occurs when the signal is at a low voltage level. Otherwise, the signal is asserted when at a high voltage level. This section defines the signals and describes the external interface of the CS1301/CS1311 media companion. Figure 2-1 shows the signals organized by their functional groups. The remaining subsections of this chapter describe: • Section 2.1 "Ball Assignments": Provides a ball assignment diagram and tables listing the signals sorted according to ball number and alphabetically by signal name. • Section 2.2 "Signal Descriptions": Detailed descriptions of each signal according to functional group. • Section 2.3 "Reference Voltages": Discussion on ball reference voltages. Table 2-1. Ball Type Descriptions Modes I O OD I/O I/OD Description Input only, except during boundary scan. Output only, except during boundary scan. Open Drain output, active pull low, no active drive high, requires external pull-up. Input or Output. Input with Open Drain output, active pull low, no active drive high, requires external pull-up. 2.1 BALL ASSIGNMENTS The CS1301/CS1311 has a total of 169 functional pins, excluding VDDQ, VSSQ, VREF_PCI, VREF_PERIPH, and digital power/ground. For pins with 5.0V input capability, the VREF_PCI or VREF_PERIPH determines 3.3V or 5.0V input tolerance. Unused pins can remain floating/unconnected; all pins that drive a clock should drive a series resistor. TRI_CLKIN TRI_USERIRQ TRI_TIMER_CLK TRI_RESET# VREF_PCI VREF_PERIPH MM_CLK [ 1:0] MM_A [13:00] MM_DQ [ 31: 00] MM_CKE[1:0] MM_CS[ 3:0] # MM_RAS# MM_CAS# MM_WE# MM_DQM[ 3:0] PCI_CLK PCI_AD [31: 00] PCI_C/BE[3:0]# PCI_PAR PCI_FRAME# PCI_IRDY# PCI_TRDY# PCI_STOP# PCI_IDSEL PCI_DEVSEL# PCI_REQ# PCI_GNT# PCI_PERR# PCI_SERR# PCI_INTA# PCI_INTB# PCI_INTC# PCI_INTD# IIC-SDA IIC-SCL System Interface VI_CLK VI_DVALID VI_DATA[09:00] VO_CLK VO_IO[2:1] VO_DATA[07:00] Video In Interface Video Out* Interface Geode™ CS1301/CS1311 Memory Interface AI_OSCLK AI_SCK AI_SD AI_WS AO_OSCLK AO_SCK AO_SD[4:1] AO_WS SPDO JTAG_TDI JTAG_TDO JTAG_TCK JTAG_TMS BOOT_CLK TESTMODE SCANCPU VDDQ VSSQ (Total of 24) VDD (Total of 40) VCC (Total of 55) VSS (Total of 8) NC Audio In* Interface Audio Out Interface S/PDIF Interface JTAG Interface Test and Measurement Interface Power, Ground and No Connections PCI Bus Interface ACCESS.bus Interface *Video In and Audio In are supported by third party software solutions, not by the National Semiconductor solution. Figure 2-1. Functional Block Diagram www.national.com 8 Revision 2.2 Geode™ CS1301/CS1311 Signal Definitions (Continued) 1 A B C D E F G H J K L M N P R T U V W Y 2 3 4 5 6 7 8 9 NC NC PCIIA# VDD 10 11 12 13 14 15 16 17 18 19 20 NC NC VCC VCC NC NC VCC VCC SPDO AOSD2 AOSC AOWS AISCK AOSD4 OSD1 AOOCK AIOCK AIWS AOSD3 VDD VDD VDD VCC VCC AISD VCC VSS VSS VILD VIDT8 VIDT5 VIDT4 PAD23 PIDSEL PAD24 PAD27 PAD28 PAD31 PCIID# PCIIB# PAD20 PAD19 PCBE3# PAD26 PGT# PAD30 PRQ# PCIIC# PAD18 PAD21 PAD22 PAD25 PAD16 PCBE#2 PAD17 VSS PIRD# PFM# VSS VSS VSS VSS PAD29 VCC VCC VCC VDD VDD A B C D E F G H J K L M N P R T U V W Y VIDT9 VIDT7 VIDT3 VIDT2 VIDT6 VRPER VIDT1 VSS VSS VIDT0 VSS VICK NC SCNCPU NC JTTMS PDVSL# VRPC PTRD# VCC PPR# PSTP# PPAR PSR# VCC VDD VCC VDD VSS VSS VSS VSS VSS VSS Geode™ VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCC VCC VDD VDD VCC VCC VDD VDD VCC JTTDO JTTCK JTTDI VCC TRRST# TRUSIQ VDD TRTRCK VOIO2 VOIO1 VOCLK VODT7 VCC VCC VODT6 VSSQ VDDQ TRCKIN PAD14 PAD15 PCBE1# VDD PAD12 PAD13 PAD11 PAD9 PAD7 PAD5 PAD3 PAD0 PAD10 VCC VCC VCC VCC PAD8 PCBE0# VDD PAD6 PAD4 PAD2 PCICK VDD VCC PAD1 VSS VDD VCC VCC VSS VSS VCC MDQ19 VCC VCC VODT3 VODT4 VODT5 VDD VCC VODT1 VODT2 TEST VODT0 CS1301/CS1311 Multimedia Companion VDD VDD VDD MMA6 VCC VCC VCC VCC VDD MMA10 VDD VDD VCC VCC VCC MDQ15 VSS VSS VCC MDQM1 ICSDA ICSCL VSS VSS MDQ7 MDQM0 BTCK MCE1 MCS0# MCS2# VSS MDQ4 MCS3# MCS1# MDQM2 MDQ24 MDQ25 MDQM3 VSS MDQ9 MDQ1 MDQ5 MDQ6 MDQ26 MDQ27 MDQ30 MDQ23 MDQ21 MDQ18 MDQ16 MMA8 MMA5 MMCK1 MMA2 MMA0 MMA12 MRS# MWE# MDQ13 MDQ11 MDQ8 MDQ2 MDQ3 MDQ28 MDQ29 MDQ31 MDQ22 MDQ20 MDQ17 MMA9 MMA7 MMA4 MMCK0 MMA3 MMA1 MMA11 MMA13 MCS# MDQ14 MDQ12 MDQ10 MCE0 MDQ0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Note: Signal names have been abbreviated in this figure due to space constraints. = GND Connection = CS1301 2.5V Core Power Connection; CS1311 2.2V Core Power Connection = 3.3V I/O Power Connection Figure 2-2. 292-TEPBGA Ball Assignment Diagram Revision 2.2 9 www.national.com Geode™ CS1301/CS1311 Signal Definitions (Continued) Table 2-2. Ball Assignment Sorted by Ball Number Ball No. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 Signal Name PCI_AD23 PCI_IDSEL PCI_AD24 PCI_AD27 PCI_AD28 PCI_AD31 PCI_INTD# PCI_INTB# NC NC NC SPDO AO_SD2 AO_SCK AO_WS AI_SCK VI_DVALID VI_DATA8 VI_DATA5 VI_DATA4 PCI_AD20 PCI_AD19 PCI_C/BE3# PCI_AD26 PCI_GNT# PCI_AD30 PCI_REQ# PCI_INTC# NC NC NC AO_SD4 AO_SD1 AO_OSCLK AI_OSCLK AI_WS VI_DATA9 VI_DATA7 VI_DATA3 VI_DATA2 PCI_AD18 PCI_AD21 PCI_AD22 PCI_AD25 VSS PCI_AD29 VCC VDD PCI_INTA# VCC VCC AO_SD3 Type I/O I I/O I/O I/O I/O I/OD I/O/OD ------O O I/O I/O I/O I I I I I/O I/O I/O I/O I I/O O I/OD ------O O O O I/O I I I I I/O I/O I/O I/O GND I/O PWR PWR I/OD PWR PWR O Ball No. C13 C14 C15 C16 C17 C18 C19 C20 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 E1 E2 E3 E4 E17 E18 E19 E20 F1 F2 F3 F4 F17 F18 F19 F20 G1 G2 G3 G4 G17 G18 Signal Name VDD VCC AI_SD VSS VI_DATA6 VREF_PERIPH VI_DATA1 VI_CLK PCI_AD16 PCI_C/BE#2 PCI_AD17 VSS VSS VCC VCC VDD VDD VCC VCC VDD VDD VCC VCC VSS VSS VI_DATA0 NC SCANCPU PCI_IRDY# PCI_FRAME# VSS VSS VSS VSS NC JTAG_TMS PCI_DEVSEL# VREF_PCI PCI_TRDY# VCC VCC JTAG_TDO JTAG_TCK JTAG_TDI PCI_PERR# PCI_STOP# VCC VCC VCC VCC Type PWR PWR I GND I PWR I I/O I/O I/O I/O GND GND PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR GND GND I --I I/O I/O GND GND GND GND --I I/O PWR I/O PWR PWR I/O I I I/O I/O PWR PWR PWR PWR Ball No. G19 G20 H1 H2 H3 H4 H8 H9 H10 H11 H12 H13 H17 H18 H19 H20 J1 J2 J3 J4 J8 J9 J10 J11 J12 J13 J17 J18 J19 J20 K1 K2 K3 K4 K8 K9 K10 K11 K12 K13 K17 K18 K19 K20 L1 L2 L3 L4 L8 Signal Name TRI_RESET# TRI_USERIRQ PCI_PAR PCI_SERR# VDD VDD VSS VSS VSS VSS VSS VSS VDD VDD TRI_TIMER_CLK VO_IO2 PCI_AD14 PCI_AD15 PCI_C/BE1# VDD VSS VSS VSS VSS VSS VSS VDD VO_IO1 VO_CLK VO_DATA7 PCI_AD12 PCI_AD13 VCC VCC VSS VSS VSS VSS VSS VSS VCC VCC VO_DATA6 VDDQ PCI_AD11 PCI_AD10 VCC VCC VSS Type I I I/O OD PWR PWR GND GND GND GND GND GND PWR PWR I I/O I/O I/O I/O PWR GND GND GND GND GND GND PWR I/O I/O O I/O I/O PWR PWR GND GND GND GND GND GND PWR PWR O PWR I/O I/O PWR PWR GND www.national.com 10 Revision 2.2 Geode™ CS1301/CS1311 Signal Definitions (Continued) Table 2-2. Ball No. L9 L10 L11 L12 L13 L17 L18 L19 L20 M1 M2 M3 M4 M8 M9 M10 M11 M12 M13 M17 M18 M19 M20 N1 N2 N3 N4 N8 N9 N10 N11 N12 N13 N17 N18 N19 N20 P1 P2 P3 P4 P17 P18 P19 P20 R1 R2 R3 R4 Signal Name VSS VSS VSS VSS VSS VCC VCC VSSQ TRI_CLKIN PCI_AD09 PCI_AD08 PCI_C/BE0# VDD VSS VSS VSS VSS VSS VSS VDD VO_DATA3 VO_DATA4 VO_DATA5 PCI_AD07 PCI_AD06 VDD VDD VSS VSS VSS VSS VSS VSS VDD VDD VO_DATA1 VO_DATA2 PCI_AD05 PCI_AD04 VCC VCC VCC VCC TESTMODE VO_DATA0 PCI_AD03 PCI_AD02 PCI_AD01 VCC Type GND GND GND GND GND PWR PWR T4 GND I I/O I/O I/O PWR GND GND GND GND GND GND PWR O O O I/O I/O PWR PWR GND GND GND GND GND GND PWR PWR O O I/O I/O PWR PWR PWR PWR I O I/O I/O I/O PWR V17 U12 U13 U14 U15 U16 U17 U18 U19 U20 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 T17 T18 T19 T20 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 Ball Assignment Sorted by Ball Number (Continued) Ball No. R17 R18 R19 R20 T1 T2 T3 Signal Name VCC MM_DQM1 IIC_SDA IIC_SCL PCI_AD00 PCI_CLK VSS VSS VSS MM_DQ07 MM_DQM0 BOOT_CLK MM_CKE1 MM_CS0# MM_CS2# VSS VSS VCC VCC VDD VDD VCC VCC VDD VDD VCC VCC VSS VSS MM_DQ04 MM_CS3# MM_CS1# MM_DQM2 MM_DQ24 MM_DQ25 MM_DQM3 VSS MM_DQ19 VCC VDD MM_A06 VCC VCC MM_A10 VDD VCC MM_DQ15 VSS MM_DQ09 Type PWR O I/OD I/OD I/O I GND GND GND I/O O I O O O GND GND PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR GND GND I/O O O O I/O I/O O GND I/O PWR PWR O PWR PWR O PWR PWR I/O GND I/O Ball No. V18 V19 V20 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Signal Name MM_DQ01 MM_DQ05 MM_DQ06 MM_DQ26 MM_DQ27 MM_DQ30 MM_DQ23 MM_DQ21 MM_DQ18 MM_DQ16 MM_A08 MM_A05 MM_CLK1 MM_A02 MM_A00 MM_A12 MM_RAS# MM_WE# MM_DQ13 MM_DQ11 MM_DQ08 MM_DQ02 MM_DQ03 MM_DQ28 MM_DQ29 MM_DQ31 MM_DQ22 MM_DQ20 MM_DQ17 MM_A09 MM_A07 MM_A04 MM_CLK0 MM_A03 MM_A01 MM_A11 MM_A13 MM_CAS# MM_DQ14 MM_DQ12 MM_DQ10 MM_CKE0 MM_DQ00 Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O O O O O O O I/O I/O I/O O I/O Revision 2.2 11 www.national.com Geode™ CS1301/CS1311 Signal Definitions (Continued) Table 2-3. Ball Assignment Sorted Alphabetically by Signal Name Signal Name AI_OSCLK AI_SCK AI_SD AI_WS AO_OSCLK AO_SCK AO_SD1 AO_SD2 AO_SD3 AO_SD4 AO_WS BOOT_CLK IIC_SCL IIC_SDA JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS MM_A00 MM_A01 MM_A02 MM_A03 MM_A04 MM_A05 MM_A06 MM_A07 MM_A08 MM_A09 MM_A10 MM_A11 MM_A12 MM_A13 MM_CAS# MM_CKE0 MM_CKE1 MM_CLK0 MM_CLK1 MM_CS0# MM_CS1# MM_CS2# MM_CS3# MM_DQ00 MM_DQ01 MM_DQ02 MM_DQ03 MM_DQ04 MM_DQ05 MM_DQ06 MM_DQ07 MM_DQ08 MM_DQ09 MM_DQ10 Ball No. B15 A16 C15 B16 B14 A14 B13 A13 C12 B12 A15 T20 R20 R19 F19 F20 F18 E20 W12 Y12 W11 Y11 Y9 W9 V9 Y8 W8 Y7 V12 Y13 W13 Y14 Y15 Y19 U1 Y10 W10 U2 U20 U3 U19 Y20 V18 W19 W20 U18 V19 V20 T18 W18 V17 Y18 PCI_AD00 PCI_AD01 PCI_AD02 PCI_AD03 PCI_AD04 PCI_AD05 PCI_AD06 PCI_AD07 PCI_AD08 PCI_AD09 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 Signal Name MM_DQ11 MM_DQ12 MM_DQ13 MM_DQ14 MM_DQ15 MM_DQ16 MM_DQ17 MM_DQ18 MM_DQ19 MM_DQ20 MM_DQ21 MM_DQ22 MM_DQ23 MM_DQ24 MM_DQ25 MM_DQ26 MM_DQ27 MM_DQ28 MM_DQ29 MM_DQ30 MM_DQ31 MM_DQM0 MM_DQM1 MM_DQM2 MM_DQM3 MM_RAS# MM_WE# NC (Total of 8) Ball No. W17 Y17 W16 Y16 V15 W7 Y6 W6 V6 Y5 W5 Y4 W4 V2 V3 W1 W2 Y1 Y2 W3 Y3 T19 R18 V1 V4 W14 W15 A9, A10, A11, B9, B10, B11, E19, D19 T1 R3 R2 R1 P2 P1 N2 N1 M2 M1 L2 L1 K1 K2 J1 J2 D1 D3 C1 B2 B1 C2 Signal Name PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 PCI_C/BE0# PCI_C/BE1# PCI_C/BE2# PCI_C/BE3# PCI_CLK PCI_DEVSEL# PCI_FRAME# PCI_GNT# PCI_IDSEL PCI_INTA# PCI_INTB# PCI_INTC# PCI_INTD# PCI_IRDY# PCI_PAR PCI_PERR# PCI_REQ# PCI_SERR# PCI_STOP# PCI_TRDY# SCANCPU SPDO TESTMODE TRI_CLKIN TRI_RESET# TRI_TIMER_CLK TRI_USERIRQ VCC (3.3V I/O Power Supply, Total of 40) Ball No. C3 A1 A3 C4 B4 A4 A5 C6 B6 A6 M3 J3 D2 B3 T2 F1 E2 B5 A2 C9 A8 B8 A7 E1 H1 G1 B7 H2 G2 F3 D20 A12 P19 L20 G19 H19 G20 C7, C10, C11, C14, D6, D7, D10, D11, D14, D15, F4, F17, G3, G4, G17, G18, K3, K4, K17, K18, L3, L4, L17, L18, P3, P4, P17, P18, R4, R17, U6, U7, U10, U11, U14, U15, V7, V10, V11, V14 VDDQ VI_CLK VI_DATA0 VI_DATA1 VI_DATA2 VI_DATA3 VI_DATA4 VI_DATA5 VI_DATA6 VI_DATA7 VI_DATA8 VI_DATA9 VI_DVALID VO_CLK VO_DATA0 VO_DATA1 VO_DATA2 VO_DATA3 VO_DATA4 VO_DATA5 VO_DATA6 VO_DATA7 VO_IO1 VO_IO2 VREF_PCI VREF_PERIPH VSS (Ground Connection, Total of 55) Signal Name VDD (2.5V Core Power Supply, Total of 24) Ball No. C8, C13, D8, D9, D12, D13, H3, H4, H17, H18, J4, J17, M4, M17, N3, N4, N17, N18, U8, U9, U12, U13, V8, V13 K20 C20 D18 C19 B20 B19 A20 A19 C17 B18 A18 B17 A17 J19 P20 N19 N20 M18 M19 M20 K19 J20 J18 H20 F2 C18 C5, C16, D4, D5, D16, D17, E3, E4, E17, E18, H8, H9, H10, H11, H12, H13, J8, J9, J10, J11, J12, J13, K8, K9, K10, K11, K12, K13, L8, L9, L10, L11, L12, L13, M8, M9, M10, M11, M12, M13, N8, N9, N10, N11, N12, N13, T3, T4, T17, U4, U5, U16, U17, V5, V16, L19 VSSQ www.national.com 12 Revision 2.2 Geode™ CS1301/CS1311 Signal Definitions (Continued) 2.2 2.2.1 SIGNAL DESCRIPTIONS System Interface Signals Ball No. L20 Signal Name TRI_CLKIN Type I Description Main Input Clock. The SDRAM clock outputs (MM_CLK0 and MM_CLK1) can be set to 2x or 3x this frequency. The on-chip DSPCPU clock (DSPCPU_CLK) can be set to 1x, 5/4, 4/3, 3/2 or 2x the SDRAM clock frequency. The maximum recommended ppm level is ±100 ppm or lower to improve jitter on generated clocks. The duty cycle should not exceed 30/70% asymmetry. The operating limits of the internal PLLs are: • 27 MHz < Output of the SDRAM PLL < 200 MHz • 33 MHz < Output of the CPU PLL < 266 MHz These are not the speed grades of the chips, just the PLL limits. TRI_USERIRQ TRI_TIMER_CLK TRI_RESET# G20 H19 G19 I I I General Purpose Level/Edge Interrupt Input. Vectored interrupt source number 4. External General Purpose Clock Source for Timers. Maximum 40 MHz. CS1301/CS1311 RESET Input. This pin can be tied to the PCI_RST# signal in the PCI bus systems. Upon releasing RESET, CS1301/CS1311 initiates its boot protocol. PCI Voltage Reference. Determines the mode of operation of the PCI pins. VREF_PCI must be connected to VSS (0V) for use in 3.3V PCI signaling environment, as is the case for a Geode SCx200 system. The supply to this pin should be AC bypassed and provide 40 mA of DC sink or source capability. VREF_PCI F2 PWR VREF_PERIPH C18 PWR Peripheral Voltage Reference. Determines the mode of operation of the I/O pins listed in Section 2.3 "Reference Voltages" on page 22. VREF_PERIPH must be connected to 5.0V if the designated I/O pins listed in Section 2.3 should be 5.0V input voltage capable. VREF_PERIPH must be connected to VSS (0V) if the designated I/O pins listed in Section 2.3 are 3.3V only inputs. The supply to this pin should be AC bypassed and provide 40 mA of DC sink or source capability. Revision 2.2 13 www.national.com Geode™ CS1301/CS1311 Signal Definitions (Continued) 2.2.2 Memory Interface Signals Ball No. Y10 W10 Signal Name MM_CLK0 MM_CLK1 Type O Description SDRAM Output Clock (at 2x or 3x TRI_CLKIN frequency). Two identical outputs are provided to reliably drive several small memory configurations without external glue. A series terminating resistor close to CS1301/CS1311 is required to reduce ringing. For driving a 50Ω trace, a resistor of 27 to 33Ω is recommended. The use of higher impedance traces in the SDRAM signals is not recommended. MM_A[13:00] See Table 2-3 on page 12 O Address Bus. Used for row and column addresses. WARNING: Do not connect MM_A[13:11] directly to SDRAM A[13:11] pins. Refer to Chapter 12 SDRAM Memory System of the Philips Semiconductor PNX1300 Series Media Processors Data Book for accurate connection diagrams. MM_DQ[31:00] See Table 2-3 on page 12 Y19 U1 U2 U20 U3 U19 W14 Y15 W15 T19 R18 V1 V4 I/O 32-Bit Data I/O Bus. The Main Memory Interface module also supports a 16-bit I/O interface. Clock Enable Output to SDRAMs. Two identical outputs are provided in order to reliably drive several small memory configurations without external glue. Chip Select for DRAM rank n; active low. The chip select pins may be used as address pins to support the 256-Mbit SDRAM device organized in x16. MM_CKE0 MM_CKE1 MM_CS0# MM_CS1# MM_CS2# MM_CS3# MM_RAS# MM_CAS# MM_WE# MM_DQM0 MM_DQM1 MM_DQM2 MM_DQM3 O O O O O O Row Address Strobe; active low. Column Address Strobe; active low. Write Enable; active low. Data Mask Enable. These are byte-enable signals for the 32-bit MM_DQ bus. www.national.com 14 Revision 2.2 Geode™ CS1301/CS1311 Signal Definitions (Continued) 2.2.3 PCI Interface Signals Ball No. T2 Signal Name PCI_CLK Type I Description PCI Clock. All PCI input signals are sampled with respect to the rising edge of this clock. All PCI outputs are generated based on this clock. This clock is required for normal operation of the PCI module. Multiplexed Address and Data. PCI_AD[31:00] See Table 2-3 on page 12 M3 J3 D2 B3 H1 E2 E1 F3 G2 A2 F1 B7 B5 G1 H2 C9 A8 B8 A7 I/O PCI_C/BE0# PCI_C/BE1# PCI_C/BE2# PCI_C/BE3# PCI_PAR PCI_FRAME# PCI_IRDY# PCI_TRDY# PCI_STOP# PCI_IDSEL PCI_DEVSEL# PCI_REQ# PCI_GNT# PCI_PERR# PCI_SERR# PCI_INTA# PCI_INTB# PCI_INTC# PCI_INTD# I/O Multiplexed Bus Commands and Byte-Enables. High for command, low for byte-enable. I/O I/O I/O I/O I/O I I/O O I I/O OD I/OD I/O/OD I/OD I/OD Parity. Even parity across AD and C/BE# lines. Frame Sustained TRI-STATE. Frame is driven by a master to indicate the beginning and duration of an access. Initiator Ready Sustained TRI-STATE. Initiator Ready indicates that the bus master is ready to complete the current data phase. Target Ready Sustained TRI-STATE. Target Ready indicates that the bus target is ready to complete the current data phase. Stop Sustained TRI-STATE. Indicates that the target is requesting that the master stop the current transaction. ID Select. Used as chip select during configuration read/write cycles. Device Select Sustained TRI-STATE. Indicates whether any device on the bus has been selected. Request. Driven by the CS1301/CS1311 as a PCI bus master to request use of the PCI bus. Grant. Indicates to the CS1301/CS1311 that access to the PCI bus has been granted. Parity Error Sustained TRI-STATE. Parity error generated/received by CS1301/CS1311. System Error. This signal is asserted when operating as a target and detecting an address parity error. PCI Interrupts A, B, C, and D. Can operate as an input (power-up default) or output, as determined by direction control bits in PCI MMIO register INT_CTL. As an input, PCI_INT# can be used to receive PCI interrupt requests (normal PCI use is active low, level-sensitive mode, but the VIC can be set to treat these as a positive edge triggered mode). As an input, PCI_INT# can also be used as a general interrupt request if not needed for PCI. As an output, the value of a PCI_INT# can be programmed through PCI MMIO registers to generate interrupts for other PCI masters. Note: Current buffer design allows drive/receive from either 3.3V or 5.0V PCI bus. Revision 2.2 15 www.national.com Geode™ CS1301/CS1311 Signal Definitions (Continued) 2.2.4 Video In Interface Signals Ball No C20 Signal Name VI_CLK Type I/O Description Clock. This signal can be configured as either an input or an output: If configured as an input (power-up default): A positive transition on this incoming video clock pin samples VI_DATA[09:00] if VI_DVALID is high. If VI_DVALID is low, VI_DATA[09:00] is ignored. Clock and data rates of up to 81 MHz are supported. The CS1301/CS1311 supports an additional mode where VI_DATA[09:08] in message passing mode are not affected by the VI_DVALID signal. If configured as an output: VI_CLK performs as a programmable output clock to drive an external video A/D converter. It can be programmed to emit integral dividers of DSPCPU_CLK. If used as an output, a board level 27 to 33Ω series resistor is recommended to reduce ringing. VI_DVALID A17 I Data Valid. VI_DVALID indicates that valid data is present on VI_DATA[09:00]. If high, VI_DATA will be accepted on the next VI_CLK positive edge. If low, VI_DATA[09:00] will not be sampled. However, the CS1301/CS1311 supports an additional mode where VI_DATA[9:8] in message passing mode are not affected by the VI_DVALID signal. Data Bus Lines [7:0]. CCIR-656 style YUV 4:2:2 data from a digital camera or general purpose high speed data input pins. Sampled on VI_CLK if VI_DVALID is high. Data Bus Lines [9:8]. Extension high speed data input bits to allow use of 10-bit video A/D converters in raw10 modes. VI_DATA[08] serves as START and VI_DATA[09] as END message input in message passing mode. Sampled on positive transitions of VI_CLK if VI_DVALID is high. The CS1301/CS1311 supports an additional mode where VI_DATA[09:08] in message passing mode are not affected by the VI_DVALID signal. VI_DATA[07:00] B18, C17, A19, A20, B19, B20, C19, D18 B17, A18 I VI_DATA[09:08] Note: Video In and Audio In are supported by third party software solutions, not by the National solution. www.national.com 16 Revision 2.2 Geode™ CS1301/CS1311 Signal Definitions (Continued) 2.2.5 Video Out Interface Signals Ball No. J19 Signal Name VO_CLK Type I/O Description Clock. The VO module emits VO_DATA[07:00] on a positive edge of VO_CLK. VO_CLK can be configured as an input (reset default) or output. If configured as an input: VO_CLK is received from external display clock master circuitry. If configured as an output: The CS1301/CS1311 emits a programmable clock frequency. The emitted frequency can be set between approximately 4 and 81 MHz with a sub-Hertz resolution. The clock generated is frequency accurate and has low jitter properties due to a combination of an on-chip DDS (Direct Digital Synthesizer) and VCO/PLL. If used as an output, a board level 27 to 33Ω series resistor is recommended to reduce ringing. VO_IO1 J18 I/O Input/Output 1. This pin can function as HS (Horizontal Sync) output or as STMSG (Start Message) output. If set as HS output: VO_IO1 outputs the HS output signal. In message passing mode, VO_IO1 acts as the STMSG output signal. VO_IO2 H20 I/O Input/Output 2. This pin can function as FS (Frame Sync) input, FS output or as ENDMSG (End Message) output. If set as FS input, it can be set to respond to positive or negative edge transitions. If the VO module operates in external sync mode and the selected transition occurs, the VO module sends two fields of video data. Note: this works only once after a reset. In message passing mode, this pin acts as ENDMSG output signal. VO_DATA[07:00] K20, K12, M20, M19, M18, N20, N19, P20 O Data Bus. CCIR-656 style YUV 4:2:2 digital output data, or general purpose high-speed data output channel. Output changes on positive edge of VO_CLK. Revision 2.2 17 www.national.com Geode™ CS1301/CS1311 Signal Definitions (Continued) 2.2.6 Audio In Interface Signals Ball No. B15 Signal Name AI_OSCLK Type O Description Over-Sampling Clock. This output can be programmed to emit any frequency up to 40 MHz with a sub-Hertz resolution. It is intended for use as the 256fs or 384fs over-sampling clock by external A/D subsystem. A board level 27 to 33Ω series resistor is recommended to reduce ringing. Serial Clock. When the AI module is programmed as a serial-interface timing slave (power-up default), AI_SCK is an input. AI_SCK receives the serial bit clock from the external A/D subsystem. This clock is treated as fully asynchronous to the CS1301/CS1311 main clock. When the AI module is programmed as the serial-interface timing master, AI_SCK is an output. AI_SCK drives the serial clock for the external A/D subsystem. The frequency is a programmable integral divisor of the AI_OSCLK frequency. AI_SCK is limited to 22 MHz. The sample rate of valid samples embedded within the serial stream is variable. If used as an output, a board level 27 to 33Ω series resistor is recommended to reduce ringing. AI_SCK A16 I/O AI_SD C15 I Serial Data. Serial data from external A/D subsystem. Data on this pin is sampled on positive or negative edges of AI_SCK as determined by the CLOCK_EDGE bit in the AI_SERIAL register. Word-Select. AI_WS is the word-select or frame-synchronization signal from/to the external A/D subsystem. When the AI module is programmed as the serial-interface timing slave (power-up default), AI_WS acts as an input. AI_WS is sampled on the same edge as selected for AI_SD. When the AI module is programmed as the serial-interface timing master, AI_WS acts as an output. It is asserted on the opposite edge of the AI_SD sampling edge. AI_WS B16 I/O Note: The AI module always acts as receiver, but can be master or slave for A/D timing. Video In and Audio In are supported by third party software solutions, not by the National solution. www.national.com 18 Revision 2.2 Geode™ CS1301/CS1311 Signal Definitions (Continued) 2.2.7 Audio Out Interface Signals Ball No. B14 Signal Name AO_OSCLK Type O Description Over-Sampling Clock. This output can be programmed to emit any frequency up to 40 MHz, with a sub-Hertz resolution. It is intended for use as the 256 or 384 fs over-sampling clock by the external D/A conversion subsystem. A board-level 27 to 33Ω series resistor is recommended to reduce ringing. Serial Clock. When the Audio Out (AO) module is programmed to act as the serial interface timing slave (power-up default), AO_SCK acts as an input. It receives the Serial Clock from the external audio D/A subsystem. The clock is treated as fully asynchronous to the CS1301/CS1311 main clock. When the AO module is programmed to act as the serial interface timing master, AO_SCK acts as an output. It drives the serial clock for the external audio D/A subsystem. The clock frequency is a programmable integral divisor of the AO_OSCLK frequency. AO_SCK is limited to 22 MHz. The sample rate of valid samples embedded within the serial stream is variable. If used as an output, a board-level 27 to 33Ω series resistor is recommended to reduce ringing. AO_SCK A14 I/O AO_SD1 AO_SD2 AO_SD3 AO_SD4 AO_WS B13 A13 C12 B12 A15 O Serial Data Buses. Serial data to external stereo audio D/A subsystem. The timing of transitions on this output is determined by the CLOCK_EDGE bit in the AO_SERIAL register, and can be on positive or negative AO_SCK edges. Word-Select or Frame synchronization. Signal from/to the external D/A subsystem. Each audio channel receives 1 sample for every WS period. When the AO module is programmed as the serial interface timing slave (power-up default), AO_WS acts as an input. AO_WS is sampled on the opposite AO_SCK edge from which AO_SDx are asserted. When the AO module is programmed as serial interface timing master, AO_WS acts as an output. AO_WS is asserted on the same AO_SCK edge as AO_SDx. I/O Note: The AO module always acts as sender, but can be master or slave for D/A timing. 2.2.8 S/PDIF Interface Signals Ball No. A12 Signal Name SPDO Type O Description S/PDIF Data Out. Self-clocking serial data stream as per IEC958, with 1937 extensions. Note that the low impedance output buffer requires a 27 to 33Ω series terminator close to CS1301/CS1311 in order to match the board trace impedance. This series terminator must be part of the voltage divider needed to create the coaxial output through the AC isolation transformer. Revision 2.2 19 www.national.com Geode™ CS1301/CS1311 Signal Definitions (Continued) 2.2.9 ACCESS.bus Interface Signals Ball No. R19 R20 Signal Name IIC_SDA IIC_SCL Type I/OD I/OD Description ACCESS.bus Serial Data. ACCESS.bus Serial Clock. 2.2.10 JTAG Interface Signals Signal Name JTAG_TDI JTAG_TDO JTAG_TCK JTAG_TMS Ball No. F20 F18 F19 E20 Type I I/O I I Description JTAG Test Data Input. JTAG Test Data Output. This pin can either drive active low, high or float. JTAG Test Clock Input. JTAG Test Mode Select Input. 2.2.11 Test and Measurement Interface Signals Signal Name BOOT_CLK TESTMODE SCANCPU Ball No. T20 P19 D20 Type I I I Description Boot Clock. Used for testing purposes. Must be connected to TRI_CLKIN for normal operation. Test Mode. Used for testing purposes. Must be connected to VSS for normal operation. Scan CPU. Used for testing purposes. Must be connected to VSS for normal operation. www.national.com 20 Revision 2.2 Geode™ CS1301/CS1311 Signal Definitions (Continued) 2.2.12 Power, Ground, and No Connections Signal Name VDDQ Ball No. K20 Type PWR Description Quiet VDD for the PLL Subsystem. Should be supplied from VDD through a low-Q series inductor. It should be bypassed for AC to VSSQ, using a dual capacitor bypass (high and low frequency AC bypass). Quiet VSS for the PLL Subsystem. Should be AC bypassed to VDDQ, otherwise left DC floating. It is connected on-chip to VSS. No external coil or other connection to board ground is needed; such a connection would create a ground loop. 2.5V CS1301 Core Power Connection (Total of 24). 2.2V CS1311 Core Power Connection (Total of 24). VSSQ L19 GND VDD See Table 2-3 on page 12 See Table 2-3 on page 12 See Table 2-3 on page 12 A9, A10, A11, B9, B10, B11, E19, D19 PWR VCC PWR 3.3V I/O Power Connection (Total of 24). VSS GND Ground Connection (Total of 50). NC --- No Connection. For normal operation, leave unconnected. Revision 2.2 21 www.national.com Geode™ CS1301/CS1311 Signal Definitions (Continued) 2.3 REFERENCE VOLTAGES VREF_PERIPH and VREF_PCI determine input voltage clamping, not input signal thresholds or output levels. Outputs always drive to a level determined by the 3.3V I/O voltage, with the exception of Open Drain mode outputs. VREF_PCI Determined Mode PCI_AD00 PCI_AD01 PCI_AD02 PCI_AD03 PCI_AD04 PCI_AD05 PCI_AD06 PCI_AD07 PCI_AD08 PCI_AD09 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 PCI_CLK PCI_C/BE#0 PCI_C/BE#1 PCI_C/BE#2 PCI_C/BE#3 PCI_PAR PCI_FRAME# PCI_IRDY# PCI_TRDY# PCI_STOP# PCI_IDSEL PCI_DEVSEL# PCI_REQ# PCI_GNT# PCI_PERR# PCI_SERR# PCI_INTA# PCI_INTB# PCI_INTC# PCI_INTD# TRI_RESET# VREF_PERIPH Determined Mode TRI_USERIRQ TRI_TIMER_CLK JTAG_TDI JTAG_TDO JTAG_TCK JTAG_TMS VI_CKL VI_DVALID VI_DATA0 VI_DATA1 VI_DATA2 VI_DATA3 VI_DATA4 VI_DATA5 VI_DATA6 VI_DATA7 VI_DATA8 VI_DATA9 IIC_SDA IIC_SCL VO_IO1 VO_IO2 VO_CLK AI_SCK AI_SD AI_WS AO_SCK AO_WS SDRAM Interface (3.3V Mode) MM_CLK0 MM_CLK1 MM_A00 MM_A01 MM_A02 MM_A03 MM_A04 MM_A05 MM_A06 MM_A07 MM_A08 MM_A09 MM_A10 MM_A11 MM_A12 MM_A13 MM_DQ00 MM_DQ01 MM_DQ02 MM_DQ03 MM_DQ04 MM_DQ05 MM_DQ06 MM_DQ07 MM_DQ08 MM_DQ09 MM_DQ10 MM_DQ11 MM_DQ12 MM_DQM0 MM_DQM1 MM_DQM2 MM_DQM3 MM_DQ13 MM_DQ14 MM_DQ15 MM_DQ16 MM_DQ17 MM_DQ18 MM_DQ19 MM_DQ20 MM_DQ21 MM_DQ22 MM_DQ23 MM_DQ24 MM_DQ25 MM_DQ26 MM_DQ27 MM_DQ28 MM_DQ29 MM_DQ30 MM_DQ31 MM_CKE0 MM_CKE1 MM_CS0# MM_CS1# MM_CS2# MM_CS3# MM_RAS# MM_CAS# MM_WE# Inputs (3.3V Mode) TRI_CLKIN BOOT_CLK TESTMODE SCANCPU Output Only Pins VO_DATA0 VO_DATA1 VO_DATA2 VO_DATA3 VO_DATA4 VO_DATA5 VO_DATA6 VO_DATA7 AO_OSCLK AO_SCK AO_SD1 AO_SD2 AO_SD3 AO_SD4 SPDO www.national.com 22 Revision 2.2 Geode™ CS1301/CS1311 3.0 Package Specifications NOTES: UNLESS OTHERWISE SPECIFIED. 1) 2) 3) 4) SOLDER BALL COMPOSITION: SN 63%, PB 37%. DIMENSION IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, PARALLEL TO PRIMARY DATUM N. THE MOLD SURFACE AREA MAY INCLUDE DIMPLE FOR A1 BALL CORNER IDENTIFICATION. REFERENCE JEDEC REGISTRATION MS-034, VARIATION BAL-1. Figure 3-1. 292-Terminal TEPBGA (Body Size: 27x27x2.33 mm; Pitch: 1.27 mm) Revision 2.2 23 www.national.com Geode™ CS1301/CS1311 Appendix A Support Documentation A.1 ORDERING INFORMATION Order Number (NSID) CS1301 CS1311 Part Marking CS1301 CS1311 Core Frequency (MHz) 180 166 Core Voltage (V) 2.5 2.2 Temperature (Degree C) 0 - 85 0 - 85 Package TEPBGA TEPBGA Note: Due to licensing agreements, the CS1301/CS1311 can only be purchased by those customers using a Geode processor-based design. A.2 CUSTOMER SUPPORT National is the primary contact for all technical support issues. For certain software modules listed, National does not have access to source code. For these software modules, National will work directly with intellectual property owners of these software modules to provide customer support. A.3 PRODUCT BRIEF REVISION HISTORY This section is a report of the revision/creation process of the product brief for the Geode CS1301/CS1311. Any revisions (i.e., additions, deletions, parameter corrections, etc.) are recorded in the table below. Note: This product brief must be used in conjunction with the Philips Semiconductor PNX1300 Series Media Processors Data Book for a complete understanding of the CS1301/CS1311 (posted on National’s IA Developer’s web site). Table A-1. Revision History Revision # (PDF Date) 1.0 (November 2001) 2.0 (April 2002) 2.1 (July 2002) 2.2 (August 2002) Revisions / Comments First draft of product brief. (Confidential) Updated to include a list of supported software and software block diagram. (Confidential) Updated to include Signal Definitions and Package Specifications sections. (No longer confidential, to be posted on National external web site in the product folders.) Replaced “Product Brief” with “Preliminary”. Updated package specifications to use National supplied drawing and changed HBGA to TEPBGA. (These changes were made to meet Corporate standard requirements, revision 2.1 was never posted on National external web site.) www.national.com 24 Revision 2.2 Geode™ CS1301/CS1311 Multimedia Companion: Media Data Processor LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Corporation Americas Email: new.feedback@nsc.com National Semiconductor Europe Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 87 90 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: ap.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 Email: nsj.crc@jksmtp.nsc.com www.national.com National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.