CS5535

Geode™ CS5535 I/O Companion: Multi-Function South Bridge Preliminary July 2003 Revision 0.8 Geode™ CS5535 I/O Companion Multi-Function South Bridge General Description The National Semiconductor® Geode™ CS5535 is a complete I/O companion for an integrated processor North Bridge component such as the Geode GX2 processor series. Together, the GX2 and CS5535 provide a systemlevel solution well suited for the high-performance and lowpower needs of a host of information appliances that include digital set-top boxes, personal access devices, and thin client applications. The internal architecture has been greatly simplified over previous I/O companions by use of a single, high-performance modular structure based on GeodeLink™ architecture. This architecture yields high internal speed (over 4 GB/s) data movement and extremely versatile internal power management. The GeodeLink architecture is transparent to application software. Communication with the GX2 processor is over a 33/66 MHz PCI bus. The CS5535 incorporates many I/O functions, including those found in typical SuperI/O chips, simplifying many system designs. Since the graphics subsystem is entirely contained in the GX2 processor, system interconnect is simplified. The device contains state-of-the-art power management that enables systems, especially battery powered systems, to significantly reduce power consumption. Audio is supported by an internal controller, designed to connect to multiple AC97 compatible codecs such as National’s LM4550. An IR (infrared) port supports all popular IR communication protocols. The IR port is shared with one of two industry-standard serial ports that can reach speeds of 115.2 kbps. An LPC (low pin count) port is provided to facilitate connections to a SuperI/O should additional expansion, such as a floppy drive, be necessary, and/or to an LPC ROM for the system BIOS. Geode™ CS5535 Block Diagram Test/Reset Interface External USB Ports 1-1 & 1-2 External USB Ports 2-1 & 2-2 External Audio GeodeLink™ Control Processor (GLCP) USB Controller #1 (USBC1) USB Controller #2 (USBC2) AC97 Controller (ACC) GeodeLink™ Interface Unit (GLIU) Geode™ GX2 Interface PCI 33 or 66 MHz GeodeLink™ PCI South Bridge (GLPCI_SB) Diverse Integration Logic (DIVIL) 82xx PC Legacy UART (2) & IR (1) SMB Controller Flash Interface LPC Port GPIO Power Mgmnt MFGP Timers External I/O www.national.com External IDE/Flash ATA-5 Controller (ATAC) System Power Voltages Low Voltage Detect (LVD) Power Good for Power On Reset (POR) RTC & CMOS RAM Diverse Device (DD) National Semiconductor and Virtual System Architecture are registered trademarks of National Semiconductor Corporation. Geode, GeodeLink, MacPHYTER, WebPAD, and VSA are trademarks of National Semiconductor Corporation. For a complete listing of National Semiconductor trademarks, please visit www.national.com/trademarks. © 2003 National Semiconductor Corporation Geode™ CS5535 General Description (Continued) The hard disk controller is an ATA-5 compatible bus mastering IDE controller; includes support for two ATA-compliant devices on one channel. Two dual-port USBs (universal serial buses, USB specification v1.1 compliant) provide four ports with both low and full-speed capabilities for Plug & Play expansion for a variety of consumer peripheral devices such as a keyboard, mouse, printer, and digital camera. A battery-backed RTC (real-time clock) keeps track of time and provides calendar functions. A suite of 82xx devices provide the legacy PC functionality required by most designs, including two PICs (programmable interrupt controllers), one PIT (programmable interval timer) with three channels, and DMA (direct memory access) functions. The CS5535 contains eight MFGPTs (multi-function general purpose timers) that can be used for a variety of functions. A number of GPIOs (general purpose input/outputs) are provided, and are assigned to system functions on power-up (i.e., LPC port); each of these may be reassigned and given different I/O characteristics such as debounce, edge-triggering, etc. State-of-the-art power management features are attained with the division of the device into two internal power domains. The GPIOs and multi-function timers are distributed into each of the two domains to allow these to act as wakeup sources for the device. In addition to full ACPI (Advanced Configuration Power Interface) compliance and support of industry-standard Wakeup and Sleep modes, the device automatically disables clocks from internal blocks when they are not being used. GeodeLink Control Processor ■ SUSP#/SUPA# handshake with power management logic provides Sleep control of all GeodeLink devices ■ System software debug support using built-in “logic analyzer” with: — 8192-bit capture memory — Capture memory can be organized wide or narrow — “Analyzer” can be connected to thousands of possible internal nodes — Synchronous operation with GX2 GeodeLink Control Processor — JTAG interface and system bus interfaces — For debug use, able to conduct any GeodeLink transaction via the JTAG interface — Manufacturing test support ATA-5 Controller ■ 66 MB per second IDE Controller in UDMA mode per the ATA-5 specification ■ 3.3V interface ■ Legacy and Enhanced PIO (Programmable I/O), MDMA (Multi DMA), and UDMA (Ultra DMA) modes ■ One channel with two devices ■ Multiplexed with Flash interface Flash Interface ■ Multiplexed with IDE interface Features General Features ■ Designed for use with National’s Geode GX2 processor ■ Connects to array of industry standard NAND Flash and/or NOR Flash ■ NOR optional execute-in-place boot source ■ NAND optional file system ■ General purpose ISA bus slave-like devices supported series ■ 208-Terminal PBGA (plastic ball grid array) package ■ 3.3V I/O and 1.5V (nominal) Core operation ■ Low power operation: less than 1.0W in Working state ■ Working and Standby power domains ■ IEEE 1149.1 compliant TAP and boundary scan with configurable chip selects ■ Hardware support for SmartMedia type ECC (Error Correcting Code) calculation off loading software intensive algorithm USB Controllers 1 and 2 ■ Two independent host USB controllers; doubles the GeodeLink PCI Bridge (South Bridge) ■ Provides a PCI interface for GeodeLink devices: throughput of a single controller ■ Each controller has two ports; total of four ports ■ USB specification v1.1 compliant, with external crimp — — — — — PCI specification v2.2 compliant 32-Bit, 33/66 MHz operation Transaction FIFOs (first in/first out) Bus master or slave Converts selected PCI configuration bus cycles to internal MSR (Model Specific Register) cycles — Capable of handling in-bound transactions immediately after reset - no setup — Mapping of PCI virtual configuration space to MSR space is done completely in VSA™ (Virtual System Architecture®) code — Serialized processor control interface protection diodes ■ OHCI (Open Host Controller Interface) specification v1.0 compliant ■ Supports wakeup events ■ Second generation proven core design ■ Over-current and power control support ■ GeodeLink master burst reads and writes www.national.com 2 Revision 0.8 Geode™ CS5535 Features (Continued) Audio Codec 97 (AC97) Controller ■ AC97 specification v2.1 compliant interface to multiple ■ General Purpose I/Os (GPIOs): audio codecs: Serial In, Serial Out, Sync Out, Bit Clock In ■ Legacy “PC Beep” support ■ Eight-channel buffered GeodeLink mastering interface ■ ASMI and IRQ support ■ Multiple codec support ■ Surround sound support — Programmable: In, Out, I/O, Open-Drain, PullUp/Down, and Invert — Parallel bit read and write — Individual bit access eliminates Read-Modify-Write cycles — Input Conditioning Functions (ICF): – Input debounce/filter — Input event counter — Input edge detect ■ Multi-Function General Purpose Timers (MFGPTs): Diverse Device ■ 82xx Legacy Devices: — Two 8259A-equivalent PICs: – Shadow registers allow reading of internal registers — One 8254-equivalent PIT — Two 8237A-equivalent DMA controllers: – 8-bit DMA supported (only) — Serial Ports 1 and 2: – Port 1 is shared with an IR port – 16550A and 16450 software compatible – Shadow register support for write-only bit monitoring – UART data rates up to 115.2 kbps ■ IR (Infrared) Communication Port: — Eight MFGPTs - two are multiplexed with GPIOs for external usage — Two MFGPTs are powered by Standby power and can be used as wakeups — Watchdog timer generates reset, IRQ, ASMI, or NMI — Pulse Width Modulation (PWM) — Pulse Density Modulation (PDM) — Blink ■ Real-Time Clock (RTC) with CMOS RAM: — — — — — — — Shared with Serial Port 1 16550A and 16450 software compatible Shadow register support for write-only bit monitoring Consumer-IR (TV-Remote) mode Data rate up to 115.2 kbps (SIR) HP-SIR (same as SIR above) Selectable internal or external modulation/demodulation (Sharp-IR) — ASK-IR option of SHARP-IR — DASK-IR option of SHARP-IR — Consumer Remote Control supports RC-5, RC-6, NEC, RCA, and RECS 80 ■ System Management Bus (SMB) Controller: — Battery backed-up century calendar in days, day of the week, date of month, months, years and century, with automatic leap-year adjustment — Battery backed-up time of day in seconds, minutes, and hours that allows a 12 or 24 hour format and adjustments for daylight savings time — BCD or binary format for time keeping — DS1287, MC146818, and PC87911 compatibility — Selective lock mechanisms for the RTC RAM — Real-time alarm — VBAT or VSTANDBY power sources with automatic switching between them — 242 bytes of battery-backed CMOS RAM in two banks ■ Power Management Controller: — Compatible with Intel System Management Bus, Phillips I2C, and ACCESS.bus — Bus master and slave operation ■ LPC (Low Pin Count) Port: — — — — — — Based on Intel LPC Interface specification v1.0 Serial IRQ support Serial DMA support (8-bit only) Boot source typically off external LPC Supports firmware hub protocol External bus masters not supported — ACPI (Advanced Configuration Power Interface) specification v2.0 compliant timer and register set — Supports APM (Advanced Power Management) and Legacy PM — PME (power management event) from GPIOs and/or on-chip sources — Working, Sleep, and Standby states — Wakeup circuits powered by Standby power rails while rest of component and system powered off — Automatic clock-off gating reduces power to inactive blocks — Flexible power supply controls including On/Off and Sleep button inputs — Generic Sleep output controls — ACPI-compliant four second fail-safe off — Low-voltage detect function for battery-powered applications — Suspend/Acknowledge handshake with GX2 — System over-temperature support — Low Voltage Detect (LVD) provides Power On Reset (POR) as well as continuous voltage monitoring for automatic system reset on a low voltage condition Revision 0.8 3 www.national.com Geode™ CS5535 Features (Continued) GeodeLink Interface Unit ■ 64-Bit, 66 MHz operation ■ Transparent to applications software and BIOS due to ■ Programmable use and activity monitors that generate optional ASMIs (asynchronous system management interrupts) for legacy power management purposes ■ Programmable SSMI (synchronous system manage- PCI VSM (virtual system module) implementation ■ Non-blocking arbitration and routing of request and data packets ■ Programmable routing descriptors ment interrupt) generators for selected range of addresses; intended for virtual device emulation (future support, if needed) ■ ATA-5 Controller, GLIU, and Diverse Device are the only SSMI sources www.national.com 4 Revision 0.8 Geode™ CS5535 Table of Contents 1.0 Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.1 1.2 1.3 1.4 1.5 1.6 GEODELINK PCI SOUTH BRIDGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 GEODELINK CONTROL PROCESSOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 ATA-5 CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 UNIVERSAL SERIAL BUS CONTROLLERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 AUDIO CODEC 97 (AC97) CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 DIVERSE DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.6.1 Legacy DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.6.2 Programmable Interval Timers - Legacy Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.6.3 Programmable Interrupt Controller - Legacy Interrupt . . . . . . . . . . . . . . . . . . . . . . . . 14 1.6.4 Keyboard Emulation Logic - Legacy Support Interface . . . . . . . . . . . . . . . . . . . . . . . 14 1.6.5 Universal Asynchronous Receiver Transmitter and IR Port . . . . . . . . . . . . . . . . . . . . 14 1.6.6 System Management Bus Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.6.7 Low Pin Count Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.6.8 General Purpose I/Os with Input Conditioning Functions (ICF) . . . . . . . . . . . . . . . . . 14 1.6.9 Multi-Function General Purpose Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.6.10 Flash Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.6.11 Real-Time Clock with CMOS RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.6.12 Power Management Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 GEODELINK INTERFACE UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 LOW VOLTAGE DETECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 PROCESSOR SUPPORT / SYSTEM OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.7 1.8 1.9 2.0 Signal Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.1 BALL ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.1.1 Buffer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.1.2 Boot Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.1.3 Ball Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.2.1 System Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.2.2 PCI Interface Signals () . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.2.3 IDE/Flash Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.2.4 USB Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.2.5 System Management Bus (SMB) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.2.6 Low Pin Count (LPC) Interface () . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.2.7 Audio Codec 97 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.2.8 GPIOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.2.9 Debug and Manufacturing Test Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 2.2.10 Power, Ground, and No Connects () . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 2.2 3.0 Global Concepts and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.1 GEODELINK ARCHITECTURE OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.1.2 Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.1.3 Response Packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.1.4 ASMI and Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.1.5 Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.1.6 Address Spaces and MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.1.7 Special Cycles and BIZZARO Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Revision 0.8 5 www.national.com Geode™ CS5535 Table of Contents (Continued) 3.2 3.3 3.4 3.5 CS5535 MSR ADDRESSING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 TYPICAL CS5535 GEODELINK DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 EMBEDDED PCI ADAPTER (PA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 CLOCK CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.5.1 Clock Domain Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.5.2 Clock Controls and Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 RESET CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 MEMORY AND I/O MAP OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.7.2 PCI Bus Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.7.3 GLIU Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.7.4 Legacy Keyboard Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.7.5 GeodeLink Device Decoding Except Diverse Device . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.7.6 Diverse Device Decoding Except Legacy I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.7.7 Legacy I/O Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 STANDARD GEODELINK DEVICE MSRS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 3.8.1 MSR Address 0: Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 3.8.2 MSR Address 1: Master Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 3.8.3 MSR Address 2: SMI Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 3.8.4 MSR Address 3: Error Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 3.8.5 MSR Address 4: Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 POWER MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 3.9.1 Power Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 3.9.2 ACPI Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 3.9.3 APM Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 COMPONENT REVISION ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 3.6 3.7 3.8 3.9 3.10 4.0 Module Functional Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4.1 GEODELINK INTERFACE UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 4.1.1 GLIU Port Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 4.1.2 Descriptor Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 GEODELINK PCI SOUTH BRIDGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 4.2.1 GeodeLink Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 4.2.2 FIFOs/Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 4.2.3 Transaction Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 4.2.4 PCI Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 4.2.5 CPU Interface Serial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 4.2.6 Programmable ID Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 4.2.7 SSMI and EXCEP Support in GLIU Read/Write Response Packets . . . . . . . . . . . . . 78 4.2.8 Subtractive Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 4.2.9 Byte Enable Checking in I/O Address Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 4.2.10 IDE Data Port Read Prefetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 4.2.11 IDE Data Port Write Posting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 4.2.12 Other Typical Slave Write Posting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 4.2.13 Memory Writes with Send Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 4.2.14 CPU Interface Serial (CIS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 4.2.15 Exception Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 4.2.16 Out-Bound Write Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 4.2.17 Out-Bound Read Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 4.2.18 In-Bound Write Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 4.2.19 In-Bound Read Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 4.2 www.national.com 6 Revision 0.8 Geode™ CS5535 Table of Contents (Continued) 4.3 AC97 AUDIO CODEC CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 4.3.1 Audio Bus Masters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 4.3.2 Bus Master Audio Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 4.3.3 AC Link Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 4.3.4 Codec Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 4.3.5 AC Link Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 4.3.6 Bus Mastering Buffer Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 4.3.7 ACC Software Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 ATA-5 CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 4.4.1 PIO Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 4.4.2 Bus Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 UNIVERSAL SERIAL BUS CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 4.5.1 GeodeLink Adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 4.5.2 PCI Adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 4.5.3 USB Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 4.5.4 Host Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 4.5.5 USB Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 DIVERSE INTEGRATION LOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 4.6.1 LBARs and Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 4.6.2 Standard MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 PROGRAMMABLE INTERVAL TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 4.7.1 Programming the 8254 PIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 PROGRAMMABLE INTERRUPT CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 4.8.1 Mapper and Masks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 4.8.2 Extended PIC (XPIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 4.8.3 Legacy PIC (LPIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 4.8.4 PIC Subsystem Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 KEYBOARD EMULATION LOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 4.9.1 Keyboard Emulation and Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 4.9.2 Keyboard Emulation Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 4.9.3 Theory - Keyboard / Mouse Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 4.9.4 Theory - Keyboard Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 4.9.5 Emulation Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 4.9.6 Theory - KEL EEs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 4.9.7 Theory - Mixed Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 4.9.8 Theory - Force A20 Low Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 4.9.9 Theory - Processor Initialize Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 4.9.10 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 4.9.11 Keyboard Emulation Logic MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 4.9.12 Related Diverse Device Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 4.9.13 Emulation Event Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 SYSTEM MANAGEMENT BUS CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 4.10.1 Data Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER AND IR PORT CONTROLLER . 125 4.11.1 Operational Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 4.11.2 Modem Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 4.11.3 Dongle Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 DIRECT MEMORY ACCESS MODULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 4.12.1 DMA Mapper Source Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 Revision 0.8 7 www.national.com Geode™ CS5535 Table of Contents (Continued) 4.13 LOW PIN COUNT PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 4.13.1 LPC Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 4.13.2 Cycle Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 4.13.3 Serial IRQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 4.13.4 Firmware Hub Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 REAL-TIME CLOCK FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 4.14.1 External Use Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 GENERAL PURPOSE INPUT/OUTPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 4.15.1 Programming for Recommended Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 4.15.2 Register Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 4.15.3 Lock Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 4.15.4 GPIO Basic I/O Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 4.15.5 Input Conditioning Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 MULTI-FUNCTION GENERAL PURPOSE TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 4.16.1 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 4.16.2 I/O Registers Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 4.16.3 Clock Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 4.16.4 Single MFGPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 4.16.5 Working Power Domain Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 4.16.6 Power Domain Crossing Interface Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 POWER MANAGEMENT CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 4.17.1 Power Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 4.17.2 Power States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 4.17.3 Software Power Management Actions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 4.17.4 PMC Power Management States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 4.17.5 PMC Power Management Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 FLASH CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 4.18.1 NAND Flash Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 4.18.2 NOR Flash Controller/General Purpose Chip Select . . . . . . . . . . . . . . . . . . . . . . . . 171 4.18.3 Flash Controller Interface Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 GEODELINK CONTROL PROCESSOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 4.19.1 GeodeLink Power Management Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 4.19.2 GLCP Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 TAP CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 4.20.1 EXTEST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 4.20.2 TAPSCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 4.20.3 TAPFUNC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 4.20.4 GL_ADDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 4.20.5 GL_DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 4.20.6 PADACC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 4.20.7 PROGMISR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 4.20.8 MB_ADDR_ACT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 4.20.9 TST_IDDQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 4.20.10 REVID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 4.20.11 TRISTATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 4.20.12 BISTDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 4.20.13 IDCODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 4.20.14 BYPASS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 4.14 4.15 4.16 4.17 4.18 4.19 4.20 www.national.com 8 Revision 0.8 Geode™ CS5535 Table of Contents (Continued) 5.0 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 5.1 GEODELINK INTERFACE UNIT REGISTER DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . 186 5.1.1 Standard GeodeLink Device MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 5.1.2 P2D Descriptor MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 5.1.3 GLIU Specific MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 5.1.4 IOD Descriptor MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 GEODELINK PCI SOUTH BRIDGE REGISTER DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . 213 5.2.1 Standard GeodeLink Device MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 5.2.2 GLPCI_SB Specific MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 5.2.3 PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 AC97 AUDIO CODEC CONTROLLER REGISTER DESCRIPTIONS . . . . . . . . . . . . . . . . . . 230 5.3.1 Standard GeodeLink Device MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 5.3.2 ACC Native Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 ATA-5 CONTROLLER REGISTER DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 5.4.1 Standard GeodeLink Device MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 5.4.2 ATAC Specific MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 5.4.3 ATAC Native Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 USB CONTROLLER REGISTER DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 5.5.1 Standard GeodeLink Device MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 5.5.2 USB Specific MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 5.5.3 USB Embedded PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 5.5.4 Host Controller Native Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 DIVERSE INTEGRATION LOGIC REGISTER DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . 295 5.6.1 Standard GeodeLink Device MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 5.6.2 DIVIL Specific MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 FLOPPY PORT REGISTER DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 5.7.1 Floppy Port Specific MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 PROGRAMMABLE INTERVAL TIMER REGISTER DESCRIPTIONS . . . . . . . . . . . . . . . . . . 323 5.8.1 PIT Specific MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 5.8.2 PIT Native Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 PROGRAMMABLE INTERRUPT CONTROLLER REGISTER DESCRIPTIONS . . . . . . . . . 331 5.9.1 PIC Specific MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 5.9.2 PIC Native Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 KEYBOARD EMULATION LOGIC REGISTER DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . 347 5.10.1 KEL Specific MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 5.10.2 KEL Native Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 SYSTEM MANAGEMENT BUS REGISTER DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . 353 5.11.1 SMB Native Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 UART AND IR PORT REGISTER DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360 5.12.1 UART/IR Controller Specific MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 5.12.2 UART/IR Controller Native Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 5.12.3 Bank 0 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 5.12.4 Bank 1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 5.12.5 Bank 2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 5.12.6 Bank 3 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 5.12.7 Bank 4 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 5.12.8 Bank 5 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390 5.12.9 Bank 6 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391 5.12.10 Bank 7 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 5.12 Revision 0.8 9 www.national.com Geode™ CS5535 Table of Contents (Continued) 5.13 DIRECT MEMORY ACCESS REGISTER DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . 400 5.13.1 DMA Specific MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403 5.13.2 DMA Native Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405 LOW PIN COUNT REGISTER DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418 5.14.1 LPC Specific MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419 REAL-TIME CLOCK REGISTER DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 5.15.1 RTC Specific MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422 5.15.2 RTC Native Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424 GPIO SUBSYSTEM REGISTER DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432 5.16.1 Atomic Bit Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436 5.16.2 GPIO Low/High Bank Feature Bit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438 5.16.3 GPIO Input Conditioning Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454 5.16.4 GPIO Interrupt and PME Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462 MULTI-FUNCTION GENERAL PURPOSE TIMER REGISTER DESCRIPTIONS . . . . . . . . 466 5.17.1 MFGPT Specific MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467 5.17.2 MFGPT Native Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472 POWER MANAGEMENT CONTROLLER REGISTER DESCRIPTIONS . . . . . . . . . . . . . . . 477 5.18.1 PMC Specific MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479 5.18.2 ACPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479 5.18.3 PM Support Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487 FLASH CONTROLLER REGISTER DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501 5.19.1 Flash Controller Specific MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502 5.19.2 Flash Controller Native Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507 GEODELINK CONTROL PROCESSOR REGISTER DESCRIPTIONS . . . . . . . . . . . . . . . . . 513 5.20.1 Standard GeodeLink Device MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514 5.20.2 GLCP Specific MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518 5.14 5.15 5.16 5.17 5.18 5.19 5.20 6.0 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525 6.1 GENERAL SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525 6.1.1 Electro Static Discharge (ESD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525 6.1.2 Power/Ground Connections and Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525 6.1.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525 6.1.4 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526 6.1.5 Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526 DC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527 AC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530 6.3.1 Clock Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532 6.3.2 Reset and Test Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533 6.3.3 PCI and Related Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534 6.3.4 IDE Signals in IDE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535 6.3.5 IDE Signals in Flash Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539 6.3.6 USB Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540 6.3.7 System Management Bus (SMB) Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542 6.3.8 AC97 Codec Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543 6.3.9 Low Pin Count (LPC) Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544 6.3.10 Power Management and Processor Control Signals . . . . . . . . . . . . . . . . . . . . . . . . 545 6.3.11 Miscellaneous Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546 6.3.12 UART and IR Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547 6.3.13 GPIO Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548 6.3.14 MFGPT Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549 6.3.15 JTAG Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550 6.2 6.3 www.national.com 10 Revision 0.8 Geode™ CS5535 Table of Contents (Continued) 6.4 6.5 POWER SUPPLY SEQUENCE REQUIREMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551 LOW VOLTAGE DETECT (LVD) PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552 7.0 Package Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553 Support Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554 A.1 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554 Appendix A Revision 0.8 11 www.national.com Geode™ CS5535 1.0 Architecture Overview • Universal Serial Bus 1 Controller with Ports 1-1 and 1-2 • Universal Serial Bus 2 Controller with Ports 2-1 and 2-2 • Audio Codec 97 (AC97) Controller • Diverse Device — Legacy DMA, Timer, and Interrupt (82xx PC Legacy) — UARTs (2) and IR (1) Port (shared with UART1) — System Management Bus (SMB) Controller — Low Pin Count (LPC) Controller — General Purpose I/O (GPIO) with Input Conditioning Functions (ICF) — Multi-Function General Purpose Timers (MFGPTs) — Flash Interface (multiplexed with IDE interface) — Real-Time Clock (RTC) with CMOS RAM Power Management Controller (PMC)The Low Voltage Detect (LVD) circuit is not a GeodeLink Device (GLD) but is connected to the Power Management Controller for voltage monitoring support. The Geode™ CS5535 provides interfaces for all the common peripherals of an information appliance, plus offers expansion for additional needs, if required. Featuring a 33/66 MHz PCI interface to the GX2, the I/O companion is internally connected using the GeodeLink™ packet architecture. This architecture supports multiple simultaneous transactions and is totally transparent to all application software. GeodeLink architecture related operations are managed via Model Specific Registers (MSRs) that are detailed in Section 3.1.6 "Address Spaces and MSRs" on page 52. As shown in Figure 1-1, the CS5535 is implemented with one GeodeLink Interface Unit (GLIU) that connects to the: • GeodeLink PCI South Bridge • GeodeLink Control Processor • ATA-5 Controller (IDE Controller multiplexed with Flash Interface) Test/Reset Interface External USB Ports 1-1 & 1-2 External USB Ports 2-1 & 2-2 External Audio GeodeLink™ Control Processor (GLCP) USB Controller #1 (USBC1) USB Controller #2 (USBC2) AC97 Controller (ACC) GeodeLink™ Interface Unit (GLIU) Geode™ GX2 Interface PCI 33 or 66 MHz GeodeLink™ PCI South Bridge (GLPCI_SB) Diverse Integration Logic (DIVIL) 82xx PC Legacy UART (2) & IR (1) SMB Controller Flash Interface LPC Port GPIO Power Mgmnt MFGP Timers External I/O Revision 0.8 External IDE/Flash ATA-5 Controller (ATAC) System Power Voltages Low Voltage Detect (LVD) Power Good for Power On Reset (POR) RTC & CMOS RAM Diverse Device (DD) Figure 1-1. Internal Block Diagram www.national.com 12 Geode™ CS5535 Architecture Overview (Continued) 1.1 GEODELINK PCI SOUTH BRIDGE 1.4 UNIVERSAL SERIAL BUS CONTROLLERS The GeodeLink PCI South Bridge (GLPCI_SB) provides a PCI interface for the CS5535. It acts as a PCI master or slave in providing PCI transactions to and from the CS5535 and the PCI bus. A special serial interface to the GX2 processor, the CPU Interface Serial (CIS), is provided that assists in the transfer of information between the CS5535 and the GX2. The interface is complaint to PCI specification v2.2 and may operate at up to 66 MHz. Optional bus signals PERR#, SERR#, LOCK#, and CLKRUN are not implemented. Within a PCI burst, zero wait state operation is achieved. The PCI interface supports programmable IDSEL selection, and can handle inbound transactions immediately after system reset. The CS5535 provides four USB ports, controlled by two independent controllers (USBC1 and USBC2) for 2x enhanced system performance. There are two ports associated with each controller for a total of four. Separate power and ground pins for the transceivers are provided to accommodate various system designs and provide superior noise immunity. Each pair of ports has an associated power control line, and there is a common over-current sense line for all four ports, compatible with National’s LM3526 dual-port USB power switch. The controllers are OpenHost Controller Interface (OHCI) v1.0 compliant, and the ports adhere to the USB v1.1 specification, with external crimp protection diodes. 1.5 1.2 GEODELINK CONTROL PROCESSOR The GeodeLink Control Processor is responsible for debug support and monitors system clocks in support of PMC operations. The GLCP interfaces with a JTAG compatible Test Access Port (TAP) Controller that is IEEE 1149.1 compliant. During debug, it can be used to pass GeodeLink packets to/from the GLIU. It is also used to support manufacturing test. AUDIO CODEC 97 (AC97) CONTROLLER The audio subsection of the CS5535 consists of three 32bit stereo-buffered bus masters (two for output, one for input) and five 16-bit mono-buffered bus masters (three for output, two for input), whose function is to transport audio data between system memory and external AC97 codecs. This arrangement is capable of producing multi-channel 5.1 surround sound (left, center, right, left rear, right rear, and low frequency effects). The codec interface is AC97 v2.1 compliant and contains Serial In (x2), Serial Out, Sync Out, and Bit Clock allowing support for any AC97 codec with Sample Rate Conversion (SRC). Additionally, the interface supports the industrystandard 16-bit pulse code modulated (PCM) format. 1.3 ATA-5 CONTROLLER The CS5535 integrates a fully-buffered, ATA-5 compliant (UDMA/66) IDE interface. The IDE interface supports one channel, which in turn supports two devices that can operate in PIO modes 1 to 4, MDMA modes 0 to 2, or UDMA/66 modes 0 to 4. This interface is shared with the Flash interface, using the same balls. The interface usage, immediately after reset, is defined by the boot options selected (see Table 2-5 "Boot Options Selection" on page 29). After reset, the interface may be dynamically altered using the Ball Options MSR (see Table 2-6 "DIVIL_BALL_OPT" on page 29). The IDE interface provides a variety of features to optimize system performance, including 32-bit disk access, post write buffers, bus master, MDMA, look-ahead read buffer, and prefetch mechanism. The IDE interface timing is completely programmable. Timing control covers the command active and recover pulse widths, and command block register accesses. The IDE data transfer speed for each device on each channel can be independently programmed allowing high-speed IDE peripherals to coexist on the same channel as older, compatible devices. The CS5535 also provides a software accessible buffered reset signal to the IDE drive. The IDE_RST# signal is driven low during reset to the CS5535 and can be driven low or high as needed for device-power-off conditions. 1.6 DIVERSE DEVICE A suite of 82xx devices provide all the legacy PC functionality required by most designs, including two PICs (programmable interrupt controllers), one PIT (programmable interval timer) with three channels, and DMA (direct memory access) functions. The CS5535 contains eight MFGPTs (multi-function general purpose timers) that can be used for a variety of functions. A number of GPIOs (general-purpose input/outputs) are provided, and are assigned to system functions on power-up (i.e., LPC port); each of these may be reassigned and given different I/O characteristics such as debounce, edge-triggering, and so forth. The Diverse Integration Logic (DIVIL) holds the devices together and provides overall control and management via MSRs. 1.6.1 Legacy DMA The CS5535 DMA controller consists of two cascaded 8237A-type DMA controllers that together support four 8bit channels. The DMA controller is used to provide high speed transfers between internal chip sources. It has full 32-bit address range support via high-page registers. An internal mapper allows routing of any of seven internal DMA sources to the four 8-bit DMA channels. Revision 0.8 13 www.national.com Geode™ CS5535 Architecture Overview (Continued) 1.6.2 Programmable Interval Timers - Legacy Timers The Programmable Interval Timer (PIT) generates programmable time intervals from the divided clock of an external clock input. The PIT is an 8254-style timer that contains three 16-bit independently programmable counters. A 14.318 MHz external clock signal (from a crystal oscillator or a clock chip) is divided by 12 to generate 1.19 MHz for the clocking reference of all three counters. 1.6.3 Programmable Interrupt Controller - Legacy Interrupt The Programmable Interrupt Controller (PIC) consists of two 8259A-compatible programmable interrupt controllers connected in cascade mode through interrupt number two. Request mask capability and edge-level controls are provided for each of the 15 channels along with a 15-level priority controller. An IRQ mapper takes up to 62 discrete interrupt request (IRQ) inputs and maps or masks them to the 15 PIC inputs and to one ASMI (asynchronous system management interrupt). All 62 inputs are individually maskable and status readable. In addition to the above 8259A features, there are shadow registers to obtain the values of legacy 8259A registers that have not been historically readable. 1.6.4 Keyboard Emulation Logic - Legacy Support Interface The PS2 Keyboard Emulation Logic (KEL) provides a virtual 8042 keyboard controller interface that may be used to map non-legacy keyboard and mouse sources to this traditional interface. Flexible keyboard emulation logic allows PS2 keyboard emulation traditionally used for USB legacy keyboard emulation. For example, USB sources may be ‘connected’ to this interface via SMM (System Management Mode) software. It also allows mixed environments with one LPC legacy device and one USB device. Universal Asynchronous Receiver Transmitter and IR Port Two Universal Asynchronous Receiver Transmitters (UARTs) provide a system interface to the industry standard serial interface consisting of the basic transmit and receive signals. One of the UARTs can be coupled with infrared logic and be connected to an infrared sensor. The UARTs are both 16550A and 16450 software-compatible and contain shadow register support for write-only bit monitoring. The ports have data rates up to 115.2 kbps. Serial port 1 can be configured as an infrared communications port that supports Sharp-IR, Consumer-IR, and HPSIR as well as many popular consumer remote-control protocols. 1.6.5 1.6.6 System Management Bus Controller The System Management Bus (SMB) Controller provides a system interface to the industry standard SMB. The SMB allows easy interfacing to a wide range of low-cost memory and I/O devices, including: EEPROMs, SRAMs, timers, ADC, DAC, clock chips, and peripheral drivers. These lines are shared with two GPIOs and must be configured as SMB ports in order for this interface to be functional. The SMB is a two-wire synchronous serial interface compatible with the System Management Bus physical layer. The SMB Controller can be configured as a bus master or slave, and can maintain bidirectional communication with both multiple master and slave devices. As a slave device, the SMB Controller may issue a request to become the bus master. 1.6.7 Low Pin Count Port This port provides a system interface to the industry standard Low Pin Count (LPC) bus. The controller can convert an internal Local bus memory or I/O cycle to an external LPC cycle. It receives serial IRQs from the LPC and converts them to parallel form so they can be routed to the IRQ mapper. Lastly, it interacts with Legacy DMA logic to perform DMA between on-chip or off-chip DMA devices. The LPC interface is based on the Intel’s Low Pin Count (LPC) Interface specification v1.0. In addition to the required signals/pins specified in the Intel specification, it also supports two optional signals: • LPC_DRQ# - LPC DMA Request • LPC_SERIRQ - LPC Serial encoded IRQ The LPC interface supports memory, I/O, DMA, and Intel’s firmware hub interfaces. 1.6.8 General Purpose I/Os with Input Conditioning Functions (ICF) There are 32 GPIOs in the CS5535, 28 are externally available, that offer a variety of user-selectable configurations including accessing auxiliary functions within the chip, and input conditioning such as debounce and edge detect. Register access is configured in such a way as to avoid Read-Modify-Write operations; each GPIO may be directly and independently configured. Several groups of GPIOs are multiplexed between the LPC Controller, the SMB Controller, access to the UARTs and MFGPTs, and power management controls including system power and Sleep buttons. Six of the GPIOs are in the Standby power domain, giving them increased versatility as wakeup event sources when only Standby power is applied. A GPIO interrupt and power management event (PME) mapper can map any subset of GPIOs to the PICs (eight interrupts available) or Power Management Subsystem (eight events available). www.national.com 14 Revision 0.8 Geode™ CS5535 Architecture Overview (Continued) Versatile input filtering is available for each GPIO input. Each preliminary input is optionally connected to a digital filter circuit that is optionally followed by an event counter. Lastly followed by an edge detector that together provide eight different ICFs (input conditioning functions), plus an auto-sense feature for determining the initial condition of the pin. 1.6.9 Multi-Function General Purpose Timers This module contains eight Multi-Function General Purpose Timers (MFGPTs), six are in the normal VDD Working power domain, while the other two are in the Standby power domain. The timers are very versatile and can be configured to provide a Watchdog timer (trigger GPIO output, interrupt or reset), perform Pulse Width Modulation (PWM) or Pulse Density Modulation (PDM), create Blink (low frequency pulse for LED), generate GPIO outputs, or act as general purpose timers. Each MFGPT operates independently and has the following features: • 32 kHz or 14.318 MHz clock selectable by software (applies to MFGPT0 to MFGPT5, in Working power domain, only). • MFGPT6 and MFGPT7, in Standby power domain, use 32 kHz clock. • Programmable input clock prescaler divisor to divide input clock by 2i, where i = 0 to 15. • Provide outputs for generating reset (limited to MFGPT0 to MFGPT5), IRQs, NMI, and ASMIs (indirectly through PICs). 1.6.10 Flash Interface The CS5535 has a Flash device interface that supports popular NOR Flash and inexpensive NAND Flash devices. This interface is shared with the IDE interface (ATA-5 Controller (ATAC)), using the same balls. NOR or NAND Flash may co-exist with IDE devices using PIO (Programmed I/O) mode. The 8-bit interface supports up to four “lanes” of byte-wide Flash devices through use of four independent chip selects, and allows for booting from the array. Hardware support is present for SmartMedia-type ECC (Error Correction Code) calculations, off-loading software from having to support this task. All four independent chip selects may be used as general purpose chip selects to support other ISA-like slave devices. Up to 1 kB of address space (without external latches) may be supported using these signals. 1.6.11 Real-Time Clock with CMOS RAM The CS5535 maintains a real-time clock for system use. The clock is powered by an external battery and so continues to keep accurate time even when system power is removed. The clock can be set to make automatic Daylight Savings Time changes in the spring and fall without user intervention. There are separate registers for seconds, minutes, hours, days (both day of the week and day of the month), months, and years. Alarms can be set for any time within the range of these registers, which have a 100-year capability. The clock uses an external 32 kHz oscillator or crystal as the timing element. The same battery that keeps the clock continuously powered also provides power to a block of 242 bytes of CMOS RAM, used for storing non-volatile system parameters. 1.6.12 Power Management Controller The CS5535 has state-of-the-art power management capabilities designed into every module. Independent clock controls automatically turn clocks off to sections of the chip that are not being used, saving considerable power. In addition, the chip supports full Sleep and Wakeup states with multiple methods of inducement. A suite of external signals support power management of devices on the system board. Legacy Power Management (PM), Advanced Power Management (APM), and Advanced Configuration and Power Interface (ACPI) techniques and requirements are supported. The GPIO subsystem can be configured to transmit any of several wakeup events into the system. The CS5535 is divided into two main power domains: Working and Standby, plus circuits such as the real-time clock and CMOS RAM that are battery-backed. Most of the CS5535 is in the Working power domain, except for GPIO[31:24] and MFGPT[7:6]. This allows these devices to be used for wakeup events or output controls. 1.7 GEODELINK INTERFACE UNIT The GeodeLink Interface Unit (GLIU) makes up the internal bus derived from the GeodeLink architecture. It has eight ports, one of which is dedicated to itself, leaving seven for use by internal GeodeLink devices. Figure 1-1 "Internal Block Diagram" on page 12 shows this device as the central element of the architecture, though its presence is basically transparent to the end user. 1.8 LOW VOLTAGE DETECT The Low Voltage Detect (LVD) circuit monitors: Standby I/O voltage, Standby Core voltage, and Working Core voltage. Working I/O voltage is not monitored and is assumed to track with Working Core voltage. The LVD monitors these voltages to provide Working and Standby power-good signals (resets) for the respective working and standby power domains. Additionally, the PMC monitors the working power-good signal to shut-down and/or re-start the system as appropriate. Revision 0.8 15 www.national.com Geode™ CS5535 Architecture Overview (Continued) 1.9 PROCESSOR SUPPORT / SYSTEM OVERVIEW show typical block diagrams for a WebPAD™ system and thin client application based on the GX2 and CS5535. As previously stated, the CS5535 was designed to interface with GX2 processor series. Figure 1-2 and Figure 1-3 SDRAM SODIMM CE Geode™ GX2 LVDS TFT LCD DSTN LCD Optional Cardbus Controller Cardbus Socket PADCard Connector CPLD LPC XpressROM LPC Bus Compact Flash 2-Wire UART I/F Geode™ CS5535 LM4549 M-Systems LPC DiskOnChip IDE LM3544 USB USB Port 3 Port 3 Charger Includes: LM2676 LM3430 LM4880 Headphone USB USB Port 2 Port 2 Mic In Internal Mic PCI1211 TPS2211 PCI COP8™ Touchscreen Interface Choose 1 Power Section AC Cube LiIon Battery AC Adapter or Battery Power LM2633 CPU Core, I/O, & Memory LM2951 5V/3.3V Clock Generator for all clocks Figure 1-2. Typical WebPAD™ System Block Diagram www.national.com 16 Revision 0.8 Geode™ CS5535 Architecture Overview (Continued) DC to DC LM2633 VCC3V Reg. SDRAM Server Memory Bus Philips MacPHYTER™ DP83815 10/100 Ethernet PCI Bus Flash/ ROM M-Systems LPC DiskOnChip LPC Bus IDE I2C RGB Out Geode™ GX2 CRT Digital RGB LM2633 VCCCore Reg. DSTN or TFT LM2951 VCC5V Reg. Clocks Headphones Choose 1 Compact Flash Geode™ CS5535 LM4549 AC97 Codec USB 4 Ports LM4881 Boomer® Amp LM3544 Figure 1-3. Thin Client Application System Block Diagram Revision 0.8 17 www.national.com Geode™ CS5535 2.0 Signal Definitions The GPIOs are configurable (e.g., any GPIO input can be mapped to an interrupt, ASMI, or PME). Figure 2-1 shows the signals organized in typical functional groups - not all possible multiplexing is shown. Where signals are multiplexed, the primary signal name is listed first and is separated by a plus sign (+). A slash (/) in a signal name means that the function is always enabled and available (i.e., time multiplexed). This section defines the signals and describes the external interface of the Geode CS5535. Signal multiplexing has been utilized to a high degree. For example, the IDE and Flash interfaces are multiplexed on the same balls. Configuration is dependent upon the boot options selected (see Table 2-5 "Boot Options Selection" on page 29). If Flash is selected, the user has the option of using NOR and/or NAND Flash devices. MHZ66_CLK MHZ48_CLK MHZ14_CLK KHZ32_XCI KHZ32_XCO RESET_WORK# RESET_STAND# RESET_OUT# WORKING SUSP#/CIS SUSPA# IRQ13 VBAT VSS_BAT1 Note: Bold-italicized signal VSS_BAT2 names in parenthesis denote LVD_EN# System Interface Signals USB Interface Signals USB_PWR_EN1 USB_PWR_EN2 USB_OC_SENS# USB1_1_DATPOS USB1_1_DATNEG USB1_2_DATPOS USB1_2_DATNEG USB2_1_DATPOS USB2_1_DATNEG USB2_2_DATPOS USB2_2_DATNEG AVSS_USB AVDD_USB a “recommended” use for a specific GPIO. See Table 2-8 "GPIO Options" on page 42 for additional details. PCI_CLK AD[31:0] C/BE[3:0]# PAR FRAME# DEVSEL# IRDY# TRDY# STOP# REQ# GNT# LPC Interface Signals PCI Interface Signals LPC_CLK LPC_AD[3:0]+GPIO[19:16] LPC_DRQ#+GPIO20 LPC_SERIRQ+GPIO21 LPC_FRAME#+GPIO22 Audio Codec 97 Interface Signals AC_S_OUT+BOS1 AC_S_IN AC_S_SYNC+BOS0 AC_CLK GPIOs and “Recommended” Usage GPIO1+AC_BEEP GPIO2+IDE_IRQ0 GPIO10+THRM_ALRM# GPIO11+SLP_CLK_EN#+MFGPT_C2 GPIO24+WORK_AUX GPIO25+LOW_BAT#+MFGPT7_C2 GPIO28+PWR_BUT# GPIO13+SLEEP_BUT GPIO0 (PCI_INTA#) GPIO7+MFGPT2_C1+SLEEP_X (PCI_INTB#) GPIO12+AC_S_IN2+SLEEP_Y GPIO26+MFGPT7_RS (PME#) GPIO14+SMB_CLK GPIO15+SMB_DATA GPIO8+UART1_TX+UART1_IR_TX GPIO9+UART1_RX+UART1_IR_RX GPIO4+UART2_TX (DDC_SDA) GPIO3+UART2_RX (DDC_SCL) GPIO5+MFGPT1_RS+MFGPT0_C1 GPIO6+MFGPT0_RS+MFGPT1_C1+MFGPT2_C2 GPIO27+MFGPT7_C1+32KHZ VCORE [Total of 8] VCORE_VSB [Total of 1] VIO [Total of 14] VIO_VSB [Total of 1] VSS [Total of 18] NC [Total of 19] IDE_RESET# IDE_AD0+FLASH_AD25/AD[0]+CLE IDE_AD[2:1]+FLASH_AD[27:26]/AD[2:1] IDE_DATA15+FLASH_ALE IDE_DATA[14:8]+FLASH_AD[24:18]/AD[9:3] IDE_DATA[7:0]+FLASH_AD[17:10]/IO[7:0] IDE_CS0#+FLASH_CS0#+CE0# IDE_CS1#+FLASH_CS1#+CE1# IDE_DREQ0+FLASH_CS2#+CE2# IDE_DACK0#+FLASH_CS3#+CE3# IDE_IOR0#+FLASH_RE# IDE_IOW0#+FLASH_WE# IDE_RDY0+FLASH_IOCHRDY+RDY/BUSY# IDE/Flash Interface Signals TCK TMS TDI TDO T_DEBUG_IN T_DEBUG_OUT LVD_TEST TEST_MODE FUNC_TEST Debug and Manufacturing Interface Signals Power, Ground, and No Connects Figure 2-1. Typical Signal Groups www.national.com 18 Revision 0.8 Geode™ CS5535 Signal Definitions (Continued) 2.1 BALL ASSIGNMENTS — Includes a column labeled Configuration with references to: – BOS[1:0] - See Section 2.1.2 "Boot Options" on page 29. – Ball Opt MSR - See Section 2.1.3 "Ball Options" on page 29. – AUX_IN, AUX_OUT_1, and AUX_OUT_2 - See Section 2.2.8 "GPIOs" on page 42. • Table 2-3 "Ball Assignments: Sorted Alphabetically by Signal Name" on page 25: — Quick-reference list, sorted alphabetically with primary signal listed first. The tables in this section use several abbreviations. Table 2-1 lists the mnemonics and their meanings. As illustrated in Figure 2-1 on page 18, the CS5535 is configurable. Boot options and register programming are used to set various modes of operation and specific signals on specific balls. This section describes the ball assignments and interface options: • Figure 2-2 "208-PBGA Ball Assignment Diagram" on page 20: — Top view looking through package. • Table 2-2 "Ball Assignments: Sorted by Ball Number" on page 21: — Primary signal name is listed first. — Includes a column labeled Buffer Type. See Section 2.1.1 "Buffer Types" on page 28 for details. Table 2-1. Abbreviations/Definitions Mnemonic A AVSS AVDD GND I I/O O OD Ball Opt MSR PD PWR PU TS VCORE VCORE_VSB VIO VIO_VSB VSS # Definition Analog Analog Ground Connection Analog Power Connection Ground Input Bidirectional Output Open-drain Model Specific Register Ball Options: A register is used to configure balls with multiple functions. Refer to Section 2.1.3 "Ball Options" on page 29 for further details. Pull-down resistor Power Pull-up resistor TRI-STATE 1.5V Core Power Working Connection 1.5V Core Power Standby Connection 3.3V I/O Power Working Connection 3.3V I/O Power Standby Connection Ground The “#” symbol at the end of a signal name indicates that the active, or asserted state occurs when the signal is at a low voltage level. When “#” is not present after the signal name, the signal is asserted when at a high voltage level. A “/” in a signal name indicates the function is always enabled (i.e., time multiplexed - available when needed). A “+” in a signal name indicates the function is available on the ball, but that either strapping options or register programming is required to select the desired function. / + Revision 0.8 19 www.national.com Geode™ CS5535 Signal Definitions (Continued) 1 A GPIO11 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 A NC VBAT KHZ32I RST# TSTM VCORE GPIO28 GPIO25 MHZ66 IDE_A0 IDE_A1 IDE_RDY IDE_DQ# IDE_D1 NC IDE_D12 B NC VSS_VBAT2 KHZ32O NC NC VIO_VSB GPIO26 RSTSD# LVDTST IDE_CS0# IDE_A2 GPIO2 IDE_IOR# IDE_D0 IDE_D14 IDE_D13 IDE_D4 B C MHZ14 GPIO7 GPIO10 VSS_VBAT1 WRKG RSTWRK# LVDEN# GPIO27 GPIO24 IDE_CS1# NC IDE_DK0# IDE_IOW# IDE_D15 IDE_D2 IDE_D3 IDE_D11 C D GPIO9 GPIO6 GPIO5 VIO VSS VIO VSS VCORE VIO VCORE VSS VIO VSS VIO IDE_D5 IDE_D10 IDE_D9 D E GPIO3 GPIO4 GPIO8 VSS VSS IDE_D6 IDE_D7 IDE_D8 E F GPIO15 GPIO13 FTST VIO VIO IDE_RST# AVSS_USB AVDD_USB F G LPC_DQ# LPC_SQ GPIO14 VSS H LCP_CLK LPC_A0 LPC_FRM# VCORE Geode™ CS5535 I/O Companion (Top View - Looking Through Package) G VSS NC USB2_2N USB2_2P H VCORE NC USB2_1N USB2_1P J LPC_A2 LPC_A1 GPIO12 VSS J VSS NC AVSS_USB AVDD_USB K LPC_A3 IRQ13 B AC_SIN GPIO1 B VSS VCORE K VCORE NC USB1_1P USB1_1N L M AC_CLK L VSS NC USB1_2P USB1_2N AC_SOUT AC_SSYNC M VIO NC AVSS_USB AVDD_USB DBUGI DBUGO VIO N SUSPA# TCK TMS VSS VSS USB_OC# USB_PW2E MHZ48 N P TDI TDO SUSP# VIO VSS VIO VSS VCORE VIO VCORE VSS VIO VSS VIO AD7 AD4 USB_PW1E P R GNT# GPIO0 NC AD28 AD26 C/BE3# AD21 AD18 NC IRDY# DEVSEL# AD15 AD12 AD9 AD6 AD2 AD0 R T REQ# NC AD30 AD27 AD25 AD23 AD20 AD17 C/BE2# TRDY# STOP# AD14 AD11 AD8 AD5 AD3 AD1 T U AD31 NC AD29 PCI_CLK AD24 AD22 AD19 AD16 FRAME# PAR C/BE1# AD13 AD10 C/BE0# NC NC NC U 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Note: Signal names have been abbreviated in this figure due to space constraints. = GND terminal = PWR terminal = Multiplexed signal B = BOS (Boot Option Select) Figure 2-2. 208-PBGA Ball Assignment Diagram Order Number: CS5535-UDC www.national.com 20 Revision 0.8 Geode™ CS5535 Signal Definitions (Continued) Table 2-2. Ball Assignments: Sorted by Ball Number Ball No. A1 Signal NameNote 1 GPIO11 SLP_CLK_EN# MFGPT1_C2 A2 A3 A4 A5 A6 A7 A8 NC VBAT KHZ32_XCI RESET_OUT# TEST_MODE VCORE_VSB GPIO28 PWR_BUT# A9 GPIO25 LOW_BAT# MFGPT7_C2 A10 A11 MHZ66_CLK IDE_AD0 FLASH_AD25/AD0 FLASH_CLE A12 IDE_AD1 FLASH_AD26/AD1 A13 IDE_RDY0 FLASH_IOCHRDY FLASH_RDY/BUSY# A14 IDE_DREQ0 FLASH_CS2# FLASH_CE2# A15 IDE_DATA1 FLASH_AD11/IO1 A16 A17 NC IDE_DATA12 FLASH_AD22/AD7 B1 B2 B3 B4 B5 B6 B7 NC VSS_VBAT2 KHZ32_XCO NC NC VIO_VSB GPIO26 MFGPT7_RS B8 B9 B10 RESET_STAND# LVD_TEST IDE_CS0# FLASH_CS0# FLASH_CE0# B11 IDE_AD2 FLASH_AD27/AD2 Type I/O O O --Wire Wire O Wire PWR I/O I I/O I O I O O O O O I I I I O O I/O I/O --I/O O --AGND Wire ----PWR I/O I I Wire (O) O O O O O IDE BOS[1:0] = 00 or 11 BOS[1:0] = 10 C17 Bare_Wire Bare_Wire IDE BOS[1:0] = 00 or 11 BOS[1:0] = 10 FLASH_AD13/IO3 IDE_DATA11 FLASH_AD21/AD6 I/O I/O O IDE FLASH_AD12/IO2 C16 IDE_DATA3 I/O I/O IDE --AVSS_USB Bare_Wire ------C14 Q7 AUX_IN C15 FLASH_ALE IDE_DATA2 O I/O IDE FLASH_WE# IDE_DATA15 O I/O IDE C13 FLASH_CS3# FLASH_CE3# IDE_IOW0# O O O IDE BOS[1:0] = 00 or 11 BOS[1:0] = 10 BOS[1:0] = 00 or 11 BOS[1:0] = 10 BOS[1:0] = 00 or 11 BOS[1:0] = 10 BOS[1:0] = 00 or 11 BOS[1:0] = 10 BOS[1:0] = 00 or 11 BOS[1:0] = 10 --IDE BOS[1:0] = 00 or 11 BOS[1:0] = 10 IDE BOS[1:0] = 00 or 11 BOS[1:0] = 10 FLASH_CS1# FLASH_CE1# C11 C12 NC IDE_DACK0# O O --O --IDE BOS[1:0] = 00 or 11 BOS[1:0] = 10 IDE BOS[1:0] = 00 or 11 BOS[1:0] = 10 C9 IDE IDE BOS[1:0] = 00 or 11 BOS[1:0] = 10 BOS[1:0] = 00 or 11 BOS[1:0] = 10 C3 Q3 IDE BOS[1:0] = 00 or 11 BOS[1:0] = 10 C1 C2 Q7 AUX_IN AUX_OUT_2 FLASH_AD14/IO4 MHZ14_CLK GPIO7 MFGPT2_C1 SLEEP_X GPIO10 THRM_ALRM# C4 C5 C6 C7 C8 VSS_VBAT1 WORKING RESET_WORK# LVD_EN# GPIO27 MFGPT7_C1 32KHZ GPIO24 WORK_AUX C10 IDE_CS1# I/O I I/O O O I/O I AGND O I Wire I/O O O I/O O O IDE SMB AUX_OUT_1 BOS[1:0] = 00 or 11 BOS[1:0] = 10 AVSS_USB SMB Q7 Bare_Wire Q7 AUX_OUT_1 AUX_OUT_2 Q7 AUX_IN Q7 PCI AUX_OUT_1 AUX_OUT_2 B17 --Bare_Wire_ BP Bare_Wire Q7 Bare_Wire --Q7 AUX_IN FLASH_AD23/AD8 IDE_DATA4 O I/O IDE B16 B15 FLASH_AD10/IO0 IDE_DATA14 FLASH_AD24/AD9 IDE_DATA13 I/O I/O O I/O IDE IDE FLASH_RE# B14 IDE_DATA0 O I/O IDE Buffer TypeNote 2 Q7 AUX_OUT_1 AUX_OUT_2 B13 Configuration Ball No. B12 Signal NameNote 1 GPIO2 IDE_IRQ0 IDE_IOR0# Type I/O I O IDE Buffer TypeNote 2 IDE AUX_IN BOS[1:0] = 00 or 11 BOS[1:0] = 10 BOS[1:0] = 00 or 11 BOS[1:0] = 10 BOS[1:0] = 00 or 11 BOS[1:0] = 10 BOS[1:0] = 00 or 11 BOS[1:0] = 10 BOS[1:0] = 00 or 11 BOS[1:0] = 10 Configuration Revision 0.8 21 www.national.com Geode™ CS5535 Signal Definitions (Continued) Table 2-2. Ball No. D1 Signal NameNote 1 GPIO9 UART1_RX UART1_IR_RX D2 GPIO6 MFGPT0_RS MFGPT1_C1 MFGPT2_C2 D3 GPIO5 MFGPT1_RS MFGPT0_C1 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 VIO VSS VIO VSS VCORE VIO VCORE VSS VIO VSS VIO IDE_DATA5 FLASH_AD15/IO5 D16 IDE_DATA10 FLASH_AD20/AD5 D17 IDE_DATA9 FLASH_AD19/AD4 E1 GPIO3 UART2_RX E2 GPIO4 UART2_TX E3 GPIO8 UART1_TX UART1_IR_TX E4 E14 E15 VSS VSS IDE_DATA6 FLASH_AD16/IO6 E16 IDE_DATA7 FLASH_AD17/IO7 E17 IDE_DATA8 FLASH_AD18/AD3 F1 GPIO15 SMB_DATA Type I/O I I I/O I O O I/O I O PWR GND PWR GND PWR PWR PWR GND PWR GND PWR I/O I/O I/O O I/O O I/O I I/O O I/O O O GND GND I/O I/O I/O I/O I/O O I/O I/O SMB AUX_IN and AUX_OUT_1 IDE IDE ----IDE BOS[1:0] = 00 or 11 BOS[1:0] = 10 BOS[1:0] = 00 or 11 BOS[1:0] = 10 BOS[1:0] = 00 or 11 BOS[1:0] = 10 J3 GPIO17 GPIO12 AC_S_IN2 SLEEP_Y I/O I/O I O Q7 AUX_IN AUX_OUT_2 J2 Q7 AUX_OUT_1 AUX_OUT_2 SMB AUX_OUT_1 SMB AUX_IN H4 H14 H15 H16 H17 J1 IDE IDE ------------G3 ----------IDE BOS[1:0] = 00 or 11 BOS[1:0] = 10 BOS[1:0] = 00 or 11 BOS[1:0] = 10 BOS[1:0] = 00 or 11 BOS[1:0] = 10 GPIO22 VCORE VCORE NC USB2_1_DATNEG USB2_1_DATPOS LPC_AD2 GPIO18 LPC_AD1 I/O PWR PWR --I/O I/O I/O I/O I/O PCI ------Bare_Wire Bare_Wire PCI Ball Opt MSR [6] = 1 Ball Opt MSR [6] = 0 Ball Opt MSR [6] = 1 Ball Opt MSR [6] = 0 H3 G4 G14 G15 G16 G17 H1 H2 VSS VSS NC USB2_2_DATNEG USB2_2_DATPOS LPC_CLK LPC_AD0 GPIO16 LPC_FRAME# GND GND --I/O I/O I I/O I/O O PCI ------Bare_Wire Bare_Wire Q7 PCI Ball Opt MSR [6] = 1 Ball Opt MSR [6] = 0 Ball Opt MSR [6] = 1 Ball Opt MSR [6] = 0 MFGPT2_RS GPIO14 SMB_CLK I I/O I/O SMB AUX_IN and AUX_OUT_1 G2 LPC_SERIRQ GPIO21 I/O I/O PCI Q7 AUX_IN AUX_OUT_1 GPIO20 I/O Q7 AUX_IN AUX_OUT_1 AUX_OUT_2 Ball Assignments: Sorted by Ball Number (Continued) Buffer TypeNote 2 Q7 AUX_IN F3 F4 F14 F15 F16 F17 G1 Configuration Ball No. F2 Signal NameNote 1 GPIO13 SLEEP_BUT FUNC_TEST VIO VIO IDE_RESET# AVSS_USB AVDD_USB LPC_DRQ# Type I/O I I PWR PWR O AGND APWR I SMB ----IDE AVSS_USB AVDD_USB PCI Ball Opt MSR [6,4] = 1,1 Ball Opt MSR [6] = 0 Ball Opt MSR [6,5] = 1,1 Ball Opt MSR [6] = 0 AUX_IN Buffer TypeNote 2 Q7 AUX_IN Configuration www.national.com 22 Revision 0.8 Geode™ CS5535 Signal Definitions (Continued) Table 2-2. Ball No. J4 J14 J15 J16 J17 K1 Signal NameNote 1 VSS VSS NC AVSS_USB AVDD_USB LPC_AD3 GPIO19 K2 K3 IRQ13 GPIO1 AC_BEEP MFGPT0_C2 K4 K14 K15 K16 K17 L1 L2 VCORE VCORE NC USB1_1_DATPOS USB1_1_DATNEG AC_S_IN AC_S_OUT BOS1 L3 AC_S_SYNC BOS0 L4 L14 L15 L16 L17 M1 M2 M3 M4 M14 M15 M16 M17 N1 N2 N3 N4 N14 N15 N16 N17 P1 P2 P3 VSS VSS NC USB1_2_DATPOS USB1_2_DATNEG AC_CLK T_DEBUG_IN T_DEBUG_OUT VIO VIO NC AVSS_USB AVDD_USB SUSPA# TCK TMS VSS VSS USB_OC_SENS# USB_PWR_EN2 MHZ48_CLK TDI TDO SUSP# CIS P4 P5 P6 VIO VSS VIO Type GND GND --AGND APWR I/O I/O I I/O O O PWR PWR --I/O I/O I O I O I GND GND --I/O I/O I I O PWR PWR --AGND APWR I I I GND GND I O I I O, TS O O PWR GND PWR ------------Bare_Wire Bare_Wire Q7 Q5 Q5 ------AVSS_USB AVDD_USB Q7 Q7 Q7 ----Q7 Q7 Q3 Q5 Q5 Q3 Q7 ------Bare_Wire Bare_Wire Q7 Q7 Q7 Q7 Default AUX_OUT_1 AUX_OUT_2 Ball Assignments: Sorted by Ball Number (Continued) Buffer TypeNote 2 ------AVSS_USB AVDD_USB PCI Ball Opt MSR [6] = 1 Ball Opt MSR [6] = 0 Configuration Ball No. P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 U1 U2 U3 U4 U5 U6 Signal NameNote 1 VSS VCORE VIO VCORE VSS VIO VSS VIO AD7 AD4 USB_PWR_EN1 GNT# GPIO0 NC AD28 AD26 C/BE3# AD21 AD18 NC IRDY# DEVSEL# AD15 AD12 AD9 AD6 AD2 AD0 REQ# NC AD30 AD27 AD25 AD23 AD20 AD17 C/BE2# TRDY# STOP# AD14 AD11 AD8 AD5 AD3 AD1 AD31 NC AD29 PCI_CLK AD24 AD22 Type GND PWR PWR PWR GND PWR GND PWR I/O I/O O I I/O --I/O I/O I/O I/O I/O --I/O I/O I/O I/O I/O I/O I/O I/O O --I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O --I/O I I/O I/O Buffer TypeNote 2 ----------------PCI PCI Q7 PCI PCI --PCI PCI PCI PCI PCI --PCI PCI PCI PCI PCI PCI PCI PCI PCI --PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI --PCI Q3 PCI PCI Configuration Revision 0.8 23 www.national.com Geode™ CS5535 Signal Definitions (Continued) Table 2-2. Ball No. U7 U8 U9 U10 U11 U12 U13 Signal NameNote 1 AD19 AD16 FRAME# PAR C/BE1# AD13 AD10 Type I/O I/O I/O I/O I/O I/O I/O Ball Assignments: Sorted by Ball Number (Continued) Buffer TypeNote 2 PCI PCI PCI PCI PCI PCI PCI Configuration Ball No. U14 U15 U16 U17 Signal NameNote 1 C/BE0# NC NC NC Type I/O ------Buffer TypeNote 2 PCI ------Configuration Note 1. Note 2. The primary signal name is listed first. See Table 2-4 "Buffer Type Characteristics" on page 28 for buffer type definitions. www.national.com 24 Revision 0.8 Geode™ CS5535 Signal Definitions (Continued) Table 2-3. Ball Assignments: Sorted Alphabetically by Signal Name Signal Name 32KHZ AC_BEEP AC_CLK AC_S_IN AC_S_IN2 AC_S_OUT AC_S_SYNC AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 AVDD_USB GPIO12, SLEEP_Y BOS1 BOS0 Muxed with GPIO27, MFGPT7_C1 GPIO1, MFGPT0_C2 Ball No. C8 K3 M1 L1 J3 L2 L3 R17 T17 R16 T16 P16 T15 R15 P15 T14 R14 U13 T13 R13 U12 T12 R12 U8 T8 R8 U7 T7 R7 U6 T6 U5 T5 R5 T4 R4 U3 T3 U1 F17, J17, M17 F16, J16, M16 AC_S_SYNC AC_S_OUT L3 L2 U14 U11 GPIO6 Signal Name C/BE2# C/BE3# CIS DEVSEL# FLASH_AD10/IO0 FLASH_AD11/IO1 FLASH_AD12/IO2 FLASH_AD13/IO3 FLASH_AD14/IO4 FLASH_AD15/IO5 FLASH_AD16/IO6 FLASH_AD17/IO7 FLASH_AD18/AD3 FLASH_AD19/AD4 FLASH_AD20/AD5 FLASH_AD21/AD6 FLASH_AD22/AD7 FLASH_AD23/AD8 FLASH_AD24/AD9 FLASH_AD25/AD0 FLASH_AD26/AD1 FLASH_AD27/AD2 FLASH_ALE FLASH_CE0# FLASH_CE1# FLASH_CE2# FLASH_CE3# FLASH_CLE FLASH_CS0# FLASH_CS1# FLASH_CS2# FLASH_CS3# FLASH_IOCHRDY IDE_DATA0 IDE_DATA1 IDE_DATA2 IDE_DATA3 IDE_DATA4 IDE_DATA5 IDE_DATA6 IDE_DATA7 IDE_DATA8 IDE_DATA9 IDE_DATA10 IDE_DATA11 IDE_DATA12 IDE_DATA13 IDE_DATA14 IDE_AD0 IDE_AD1 IDE_AD2 IDE_DATA15 IDE_CS0# IDE_CS1# IDE_DREQ0# IDE_DACK0# IDE_AD0 IDE_CS0# IDE_CS1# IDE_DREQ0# IDE_DACK0# IDE_RDY0 SUSP# Muxed with Ball No. T9 R6 P3 R11 B14 A15 C15 C16 B17 D15 E15 E16 E17 D17 D16 C17 A17 B16 B15 A11 A12 B11 C14 B10 C10 A14 C12 A11 B10 C10 A14 C12 A13 A13 B13 C13 U9 F3 R1 R2 AC_BEEP, MFGPT0_C2 IDE_IRQ0 UART2_RX UART2_TX MFGPT1_RS, MFGPT0_C1 MFGPT0_RS, MFGPT1_C1, MFGPT2_C2 K3 B12 E1 E2 D3 D2 IDE_DATA0 IDE_DATA1 IDE_DATA2 IDE_DATA3 IDE_DATA4 IDE_DATA5 IDE_DATA6 IDE_DATA7 IDE_DATA8 IDE_DATA9 IDE_DATA10 IDE_CS1# IDE_DACK0# IDE_AD1 IDE_AD2 IDE_CS0# GPIO26 GPIO27 GPIO28 IDE_AD0 GPIO22 GPIO24 GPIO25 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21 GPIO10 GPIO11 GPIO8 GPIO9 Signal Name GPIO7 Muxed with MFGPT2_C1, SLEEP_X UART1_TX, UART1_IR_TX UART1_RX, UART1_IR_RX THRM_ALRM# SLP_CLK_EN#, MFGPT1_C2 AC_S_IN2, SLEEP_Y SLEEP_BUT SMB_CLK SMB_DATA LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_DRQ LPC_SERIRQ, MFGPT2_RS LPC_FRAME# WORK_AUX LOW_BAT#, MFGPT7_C2 MFGPT7_RS MFGPT7_C1, 32KHZ PWR_BUT# FLASH_AD25/AD0, FLASH_CLE FLASH_AD26/AD1 FLASH_AD27/AD2 FLASH_CS0#, FLASH_CE0# FLASH_CS1#, FLASH_CE1# FLASH_CS3#, FLASH_CE3# FLASH_AD10/IO0 FLASH_AD11/IO1 FLASH_AD12/IO2 FLASH_AD13/IO3 FLASH_AD14/IO4 FLASH_AD15/IO5 FLASH_AD16/IO6 FLASH_AD17/IO7 FLASH_AD18/AD3 FLASH_AD19/AD4 FLASH_AD20/AD5 Ball No. C2 E3 D1 C3 A1 J3 F2 G3 F1 H2 J2 J1 K1 G1 G2 H3 C9 A9 B7 C8 A8 A11 A12 B11 B10 C10 C12 B14 A15 C15 C16 B17 D15 E15 E16 E17 D17 D16 FLASH_RDY/BUSY# IDE_RDY0 FLASH_RE# FLASH_WE# FRAME# FUNC_TEST GNT# GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 IDE_IOR0# IDE_IOW0# AVSS_USB BOS0 BOS1 C/BE0# C/BE1# Revision 0.8 25 www.national.com Geode™ CS5535 Signal Definitions (Continued) Table 2-3. Signal Name IDE_DATA11 IDE_DATA12 IDE_DATA13 IDE_DATA14 IDE_DATA15 IDE_DREQ0# IDE_IOR0# IDE_IOW0# IDE_IRQ0 IDE_RDY0 Ball Assignments: Sorted Alphabetically by Signal Name (Continued) Ball No. C17 A17 B16 B15 C14 A14 B13 C13 B12 A13 MFGPT7_RS MHZ14_CLK MHZ48_CLK MHZ66_CLK NC (Total of 19) MFGPT7_C1 MFGPT7_C2 Signal Name MFGPT2_RS Muxed with GPIO21, LPC_SERIRQ GPIO27, 32KHZ GPIO25, LOW_BAT# GPIO26 Ball No. G2 C8 A9 B7 C1 N17 A10 A2, A16, B1, B4, B5, C11, G15, H15, J15, K15, L15, M15, R3, R9, T2, U2, U15, U16, U17 U10 U4 GPIO28 A8 T1 A5 B8 C6 GPIO13 GPIO7, MFGPT2_C1 AC_S_IN2, GPIO12 GPIO11, MFGPT1_C2 GPIO14 GPIO15 F2 C2 J3 A1 G3 F1 T11 CIS P3 N1 M2 M3 N2 P1 P2 A6 VCORE_VSB UART1_TX UART2_RX UART2_TX USB_OC_SENS# USB_PWR_EN1 USB_PWR_EN2 USB1_1_DATNEG USB1_1_DATPOS USB1_2_DATNEG USB1_2_DATPOS USB2_1_DATNEG USB2_1_DATPOS USB2_2_DATNEG USB2_2_DATPOS VBAT VCORE (Total of 8) Signal Name THRM_ALRM# TMS TRDY# UART1_IR_RX UART1_IR_TX UART1_RX GPIO9, UART1_RX GPIO8, UART1_TX GPIO9, UART1_IR_RX GPIO8, UART1_IR_TX GPIO3 GPIO4 Muxed with GPIO10 Ball No. C3 N3 T10 D1 E3 D1 E3 E1 E2 N15 P17 N16 K17 K16 L17 L16 H16 H17 G16 G17 A3 D8, D10, H4, H14, K4, K14, P8, P10 A7 Muxed with FLASH_AD21/AD6 FLASH_AD22/AD7 FLASH_AD23/AD8 FLASH_AD24/AD9 FLASH_ALE FLASH_CS2#, FLASH_CE2# FLASH_RE# FLASH_WE# GPIO2 FLASH_IOCHRDY, FLASH_RDY/BUSY # IDE_RESET# IRDY# IRQ13 KHZ32_XCI KHZ32_XCO LOW_BAT# LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_CLK LPC_DRQ# LPC_FRAME# LPC_SERIRQ LVD_EN# LVD_TEST MFGPT0_C1 MFGPT0_C2 MFGPT0_RS GPIO5, MFGPT1_RS AC_BEEP, GPIO1 GPIO6, MFGPT1_C1, MFGPT2_C2 GPIO6, MFGPT0_RS, MFGPT2_C2 GPIO11, SLP_CLK_EN# GPIO5, MFGPT0_C1 GPIO7, SLEEP_X GPIO6, MFGPT0_RS, MFGPT1_C1 GPIO20 GPIO22 GPIO21, MFGPT2_RS GPIO25, MFGPT7_C2 GPIO16 GPIO17 GPIO18 GPIO19 F15 R10 K2 A4 B3 A9 H2 J2 J1 K1 H1 G1 H3 G2 C7 B9 D3 K3 SLEEP_Y D2 SLP_CLK_EN# D2 SMB_CLK SMB_DATA A1 D3 C2 D2 STOP# SUSP# SUSPA# T_DEBUG_IN T_DEBUG_OUT TCK TDI TDO TEST_MODE PAR PCI_CLK PWR_BUT# REQ# RESET_OUT# RESET_STAND# RESET_WORK# SLEEP_BUT SLEEP_X MFGPT1_C1 MFGPT1_C2 MFGPT1_RS MFGPT2_C1 MFGPT2_C2 www.national.com 26 Revision 0.8 Geode™ CS5535 Signal Definitions (Continued) Table 2-3. Signal Name VIO (Total of 14) Ball Assignments: Sorted Alphabetically by Signal Name (Continued) Ball No. D4, D6, D9, D12, D14, F4, F14, M4, M14, P4, P6, P9, P12, P14 B6 Signal Name VSS (Total of 18) Muxed with Ball No. D5, D7, D11, D13, E4, E14, G4, G14, J4, J14, L4, L14, N4, N14, P5, P7, P11, P13 Signal Name VSS_VBAT1 VSS_VBAT2 WORK_AUX WORKING GPIO24 Muxed with Ball No. C4 B2 C9 C5 Muxed with VIO_VSB Revision 0.8 27 www.national.com Geode™ CS5535 Signal Definitions (Continued) 2.1.1 Buffer Types Table 2-2 "Ball Assignments: Sorted by Ball Number" on page 21 includes a column labeled “Buffer Type”. The details of each buffer type listed in this column are given in Table 2-4. The column headings in Table 2-4 are identified as follows: TS: Indicates whether the buffer may be put into the TRISTATE mode. Note some pins that have buffer types that allow TRI-STATE may never actually enter the TRI-STATE mode in practice, since they may be inputs or provide other signals that are always driven. To determine if a particular signal can be put in the TRI-STATE mode, consult the individual signal descriptions in Section 2.2 "Signal Descriptions" on page 31. OD: Indicates if the buffer is open-drain, or not. Open-drain outputs may be wire ORed together and require a discrete pull-up resistor to operate properly. 5VT: Indicates if the buffer is 5-volt tolerant, or not. If it is 5volt tolerant, then 5 volt TTL signals may be safely applied to this pin. Backdrive Protected: Indicates that the buffer may have active signals applied even when the CS5535 itself is powered down. PU/PD: Indicates if an internal, programmable pull-up or pull-down resistor may be present. Current High/Low (mA): This column gives the current source/sink capacities when the voltage at the pin is high, and low. The high and low values are separated by a “/” and values given are in milli-amps (mA). Rise/Fall @ Load: This column indicates the rise and fall times for the different buffer types at the load capacitance indicated. These measurements are given in two ways: rise/fall time between the 20%-80% voltage levels, or, the rate of change the buffer is capable of, in volts-per-nanosecond (V/ns). See Section 6.3 "AC Characteristics" on page 530 for details. Note the presence of several “wire” type buffers in this table. Signals identified as one of the wire-types are not driven by a buffer, hence no rise/fall time or other measurements are given; these are marked “NA” in Table 2-4. The wire-type connection indicates a direct connection to internal circuits such as power, ground, and analog signals. Table 2-4. Buffer Type Characteristics Backdrive Protected Current High/Low (mA) 24/24 24/24 24/24 0.5/1.5 16/16 X X X Name Q3 Q5 Q7 PCI IDE SMB TS X X X X X OD 5VT PU/PD X X X Rise/Fall @ Load 3 ns @ 50 pF 5 ns @ 50 pF 7 ns @ 50 pF 1-4 V/ns @ 10 pF 1.25 V/ns @ 40 pF Rise: 1 µs @ 400 pF Fall: 300 ns @ 400 pF Bare_Wire Bare_Wire_BP AVDD_USB AVSS_USB NA NA NA NA NA NA NA NA X NA NA NA NA NA NA NA NA NA NA NA NA www.national.com 28 Revision 0.8 Geode™ CS5535 Signal Definitions (Continued) 2.1.2 Boot Options Two balls on the device, L2 and L3, the Boot Options Select balls (BOS[1:0]), serve to specify the location of the boot device as the system undergoes a full reset. Since boot devices may reside in Flash or on an IDE device, the IDE/Flash interface is necessarily selected as operating in one of the two modes by the Boot Options. After Reset, the function of these interfaces may be changed with the Ball Options MSR (see Section 2.1.3 "Ball Options"). Both these balls are multiplexed with other functions as identified in Section 2.2.7 "Audio Codec 97 Interface" on page 41 and function as BOS[1:0] only when RESET_OUT# is asserted. Table 2-5 indicates how these two balls should be configured to select the desired boot device. Both balls contain an internal pull-up, active only during reset, so if a ball is required to be high during this time, it may be left unconnected. If a ball is desired to be low during reset, a pull-down (i.e., not a hard tie to ground) should be added. During reset, both balls’ output drivers are in the TRISTATE mode. 2.1.3 Ball Options Table 2-6 shows the Ball Options MSR (DIVIL MSR 51400015h), through which the function of certain groups of multiplexed balls may be dynamically changed after the reset period ends. Specifically, the functions LPC/GPIO and IDE/Flash groups are selected, and certain individual balls, as specified in the MSR, are controlled. Table 2-5. Boot Options Selection BOS1 (Ball L2) 0 BOS0 (Ball L3) 0 Description Boot from Memory Device on the LPC Bus. IDE pins come up connected to IDE Controller (see Section 2.2.3 "IDE/Flash Interface Signals" on page 35 and Table 2-6 "DIVIL_BALL_OPT" on page 29). Reserved. Boot from NOR Flash on the IDE Bus. IDE pins come up connected to Flash Controller (see Section 2.2.3 "IDE/Flash Interface Signals" on page 35 and Table 2-6 "DIVIL_BALL_OPT" on page 29). NOR Flash, ROM, or other random access devices must be connected to “FLASH_CS_3”. 1 1 Boot from Firmware Hub on the LPC Bus. IDE pins come up connected to IDE Controller (see Section 2.2.3 "IDE/Flash Interface Signals" on page 35 and Table 2-6 "DIVIL_BALL_OPT" on page 29). 0 1 1 0 Table 2-6. DIVIL_BALL_OPT Bit 31:12 11:10 Name RSVD SEC_BOOT_LOC Description Reserved. Reads always return 0. Writes have no effect; by convention, always write 0. Secondary Boot Location. Determines which chip select asserts for addresses in the range F00F0000h to F00F3FFFh. Defaults to the same value as boot option: 00: LPC ROM. 01: Reserved . 10: Flash. 11: FirmWare Hub. 9:8 7 BOOT_OP_ LATCHED(RO) RSVD Latched Value of Boot Option (Read Only). For values, see Table 2-5 "Boot Options Selection" on page 29. Reserved. Reads return value written. By convention, always write 0. Defaults low. Revision 0.8 29 www.national.com Geode™ CS5535 Signal Definitions (Continued) Table 2-6. DIVIL_BALL_OPT (Continued) Bit 6 Name PIN_OPT_LALL Description All LPC Pin Option Selection. 0: All LPC pins become GPIOs including LPC_DRQ# and LPC_SERIRQ. Ball H3 functions as GPIO22 Ball H2 functions as GPIO16 Ball J2 functions as GPIO17 Ball J1 functions as GPIO18 Ball K1 functions as GPIO19 Ball G1 functions as GPIO20 Ball G2 functions as GPIO21 1: All LPC pins are controlled by the LPC controller except LPC_DRQ# and LPC_SERIRQ use are determined by bits [5:4]. (Default) Ball H3 functions as LPC_FRAME# Ball H2 functions as LPC_AD0 Ball J2 functions as LPC_AD1 Ball J1 functions as LPC_AD2 Ball K1 functions as LPC_AD3 When this bit is low, there is an implied high for LPC_DISABLE_IO and LPC_DISABLE_MEM in MSR_LEG_IO (DD MSR 51400014h). 5 PIN_OPT_LIRQ LPC_SERIRQ or GPIO21 Pin Option Selection. 0: Ball G2 is GPIO21. 1: Ball G2 functions as LPC_SERIRQ. (Default) 4 PIN_OPT_LDRQ LPC_DRQ# or GPIO20 Pin Option Selection. 0: Ball G1 is GPIO20. 1: Ball G2 functions as LPC_DRQ#. (Default) 3:2 PRI_BOOT_LOC [1:0] Primary Boot Location. Determines which chip select asserts for addresses at or above F0000000h. Except those in the range specified by SEC_BOOT_LOC[1:0]. Defaults to the same value as boot option. 00: LPC ROM. 01: Reserved . 10: Flash. 11: FirmWare Hub. 1 0 RSVD PIN_OPT_IDE Reserved. Reads return value written. By convention, always write 0. Defaults low. IDE or Flash Controller Pin Function Selection. 0: All IDE pins associated with Flash Controller. Default if BOS[1:0] = 10. 1: All IDE pins associated with IDE Controller. Default if BOS[1:0] = 00 or 11. IDE_IRQ0 is multiplexed with GPIO2; therefore, this bit has no affect with regards to programming IDE_IRQ0. www.national.com 30 Revision 0.8 Geode™ CS5535 Signal Definitions (Continued) 2.2 SIGNAL DESCRIPTIONS Information in the tables that follow may have duplicate information in multiple tables. Multiple references all contain identical information. 2.2.1 System Interface Signals Ball No. A10 N17 C1 A4 Type I I I Wire Description 66 MHz Clock. This is the main system clock. It is also used by the IDE interface. USB Clock. This is the 48 MHz clock for the UARTs and SMB Controller. 14.31818 MHz Timer Clock. This is the input clock for power management functions and the Programmable Interval Timers (PITs). 32 kHz Input. This input is used for the real-time clock (RTC), GPIOs, MFGPTs, and power management functions. This input may come from either an external oscillator or one side of a 32.768 kHz crystal. If an external oscillator is used, it should be powered by VIO_VSB. This signal takes approximately one second to lock after power-up. KHZ32_XCO B3 Wire 32 kHz Input 2. This input is to be connected to the other side of the crystal oscillator connected to KHZ32_XCI, if used. Leave open (not connected) if an oscillator (not a crystal) is connected to KHZ32_XCI. Reset Working Power Domain. This signal, when asserted, is the master reset for all CS5535 interfaces that are in the Working power domain. See Section 3.9 "Power Management" on page 72 for a description of the Working power domain. RESET_WORK# must be asserted for at least 10 ns in order to be properly recognized. If LVD_EN# is enabled (tied low) use of this input is not required. See the LVD_EN# signal description for further details. RESET_STAND# B8 I Reset Standby Power Domain. This signal, when asserted, is the master reset for all CS5535 interfaces that are in the Standby power domain. See Section 3.9 "Power Management" on page 72 for a description of the Standby power domain. If LVD_EN# is enabled (tied low) use of this input is not required. See the LVD_EN# discussion in this table. Tie directly to VIO_VSB if not used. RESET_OUT# A5 O Reset Output. This is the main system reset signal. RESET_OUT# is de-asserted synchronously with the low-to-high edge of PCI_CLK. The de-assertion is delayed from internal reset by up to 32 seconds, with an 8 ms default value, using a programmable counter driven by the 32 kHz clock. Note this counter default is established by RESET_STAND# and is not affected by RESET_WORK#. Therefore, the delay value may be changed and the system reset with the new value. Working State. Indicates the chip is in the Working state when high. This signal is intended to be used to control power to off-chip devices in a system. Open-drain. External pull-up required. Signal Name MHZ66_CLK MHZ48_CLK MHZ14_CLK KHZ32_XCI RESET_WORK# C6 I WORKING C5 O Revision 0.8 31 www.national.com Geode™ CS5535 Signal Definitions (Continued) 2.2.1 System Interface Signals (Continued) Ball No. P3 Type O Description Suspend. This signal goes low in response to events as determined by the CS5535’s internal power management logic. It requests the GX2 to enter the Suspend state. This is the default state for this ball at reset. Not used in normal operation. CPU Interface Serial. A 20-bit serial status word is output on this ball, synchronized to PCI_CLK. Data changes on the rising edge and is stable on the falling edge of PCI_CLK. This word is output whenever one of the internally-monitored signals changes states. See Section 4.2.14 "CPU Interface Serial (CIS)" on page 79 for details. Used in normal operation. Suspend Acknowledge. This input signal is driven low by the GX2 processor when it has successfully entered the Suspend state. Interrupt Request Level 13. Floating Point error. Connect directly to IRQ13 of the GX2 processor. Real-Time Clock Battery Back-Up. Battery voltage on this ball keeps the real-time clock and CMOS RAM circuits continuously powered. If not used, tie to ground. 2.4-3.6V, typical 3.0V. 10 µA max. 5 µAs typical. This ball incorporates a reverse bias protection diode on-chip. There is no need for an external diode. VSS_VBAT1 VSS_VBAT2 LVD_EN# C4 B2 C7 Wire Low Voltage Detect Enable. LVD_EN# enables/disables the on-chip low voltage detect circuit. When disabled, the external subsystem must assert RESET_STAND# as Standby power is applied and must assert RESET_WORK# as Working power is applied. When LVD is enabled, use of these two resets are optional. Generally, RESET_STAND# would be tied high (not used) while RESET_WORK# would be tied to a reset output that is typically available from the power supply. However, a system could just have a simple regulator circuit and also tie RESET_WORK# high. Tie to VSS to enable. Tie to VIO_VSB to disable. AGND Real-Time Clock Battery Grounds 1 and 2 Signal Name SUSP# CIS O SUSPA# N1 I IRQ13 VBAT K2 A3 I Wire www.national.com 32 Revision 0.8 Geode™ CS5535 Signal Definitions (Continued) 2.2.2 PCI Interface Signals (Note 1) Ball No. U4 U1, T3, U3, R4, T4, R5, T5, U5, T6, U6, R7, T7, U7, R8, T8, U8, R12, T12, U12, R13, T13, U13, R14, T14, P15, R15, T15, P16, T16, R16, T17, R17 R6, T9, U11, U14 Type I I/O Description PCI Clock. 33 MHz or 66 MHz. PCI Address/Data. AD[31:0] is a physical address during the first clock of a PCI transaction; it is the data during subsequent clocks. When the CS5535 is a PCI master, AD[31:0] are outputs during the address and write data phases, and are inputs during the read data phase of a transaction. When the CS5535 is a PCI slave, AD[31:0] are inputs during the address and write data phases, and are outputs during the read data phase of a transaction. Signal Name PCI_CLK AD[31:0] C/BE[3:0]# I/O PCI Bus Command and Byte Enables. During the address phase of a PCI transaction, when FRAME# is active, C/BE[3:0]# define the bus command. During the data phase of a transaction, C/BE[3:0]# are the data byte enables. C/BE[3:0]# are outputs when the CS5535 is a PCI master and inputs when it is a PCI slave. PAR U10 I/O PCI Parity. PAR is the parity signal driven to maintain even parity across AD[31:0] and C/BE[3:0]#. The CS5535 drives PAR one clock after the address phase and one clock after each completed data phase of write transactions as a PCI master. It also drives PAR one clock after each completed data phase of read transactions as a PCI slave. FRAME# U9 I/O PCI Cycle Frame. FRAME# is asserted to indicate the start and duration of a transaction. It is de-asserted on the final data phase. FRAME# is an input when the CS5535 is a PCI slave. Normally connected to a 10k to15k Ω external pull-up. This signal is TRI-STATE after reset. DEVSEL# R11 I/O PCI Device Select. DEVSEL# is asserted by a PCI slave, to indicate to a PCI master and subtractive decoder that it is the target of the current transaction. As an input, DEVSEL# indicates a PCI slave has responded to the current address. As an output, DEVSEL# is asserted one cycle after the assertion of FRAME# and remains asserted to the end of a transaction as the result of a positive decode. DEVSEL# is asserted four cycles after the assertion of FRAME# if DEVSEL# has not been asserted by another PCI device when the CS5535 is programmed to be the subtractive decode agent. Normally connected to a 10k to 15k Ω external pull-up. This signal is TRI-STATE after reset. Revision 0.8 33 www.national.com Geode™ CS5535 Signal Definitions (Continued) 2.2.2 PCI Interface Signals (Note 1) (Continued) Ball No. R10 Type I/O Description PCI Initiator Ready. IRDY# is driven by the master to indicate valid data on a write transaction, or that it is ready to receive data on a read transaction. When the CS5535 is a PCI slave, IRDY# is an input that can delay the beginning of a write transaction or the completion of a read transaction. Wait cycles are inserted until both IRDY# and TRDY# are asserted together. Normally connected to a 10k to15k Ω external pull-up. This signal is TRI-STATE after reset. TRDY# T10 I/O PCI Target Ready. TRDY# is asserted by a PCI slave to indicate it is ready to complete the current data transfer. TRDY# is an input that indicates a PCI slave has driven valid data on a read or a PCI slave is ready to accept data from the CS5530A on a write. TRDY# is an output that indicates the CS5535 has placed valid data on AD[31:0] during a read or is ready to accept the data from a PCI master on a write. Wait cycles are inserted until both IRDY# and TRDY# are asserted together. Normally connected to a 10k to15k Ω external pull-up. This signal is TRI-STATE after reset. STOP# T11 I/O PCI Stop. As an input, STOP# indicates that a PCI slave wants to terminate the current transfer. The transfer is either aborted or retried. STOP# is also used to end a burst. As an output, STOP# is asserted with TRDY# to indicate a target disconnect, or without TRDY# to indicate a target retry. The CS5535 asserts STOP# during any cache line crossings if in single transfer DMA mode or if busy. Normally connected to a 10k to15k Ω external pull-up. This signal is TRI-STATE after reset. REQ# T1 O PCI Bus Request. The CS5535 asserts REQ# to gain ownership of the PCI bus. The REQ# and GNT# signals are used to arbitrate for the PCI bus. REQ# should connect to the REQ2# of the GX2-series processor and function as the highest-priority PCI master. GNT# R1 I PCI Bus Grant. GNT# is asserted by an arbiter that indicates to the CS5535 that access to the PCI bus has been granted. GNT# should connect to GNT2# of the GX2-series processor and function as the highest-priority PCI master. Note 1. Use RESET_OUT# for PCI reset. For SMI, PME, INTA#, and INTB# functions see Table 2-8 "GPIO Options" on page 42. Signal Name IRDY# www.national.com 34 Revision 0.8 Geode™ CS5535 Signal Definitions (Continued) 2.2.3 IDE/Flash Interface Signals The IDE and Flash interface signals are multiplexed together on the same balls as shown in Table 2-7. Section 2.2.3.1 provides the names and functions of these signals when the interface is in the IDE mode and Section 2.2.3.2 when in Flash mode (NOR Flash/GPCS and NAND Flash modes). Table 2-7. IDE and Flash Ball Multiplexing NOR Flash/GPCS Mode Ball No. B11, A12 A11 B15, B16, A17, C17, D16, D17, E17 E16, E15, D15, B17, C16, C15, A15, B14 C14 B10 C10 B13 C13 A14 (Note 1) C12 A13 Note 1. IDE Mode IDE_AD[2:1] IDE_AD0 IDE_DATA[14:8] IDE_DATA[7:0] IDE_DATA15 IDE_CS0# IDE_CS1# IDE_IOR0# IDE_IOW0# IDE_DREQ0 IDE_DACK0# IDE_RDY0 Address Phase FLASH_AD[27:26] FLASH_AD25 FLASH_AD[24:18] FLASH_AD[17:10] FLASH_ALE FLASH_CS0# FLASH_CS1# FLASH_RE# FLASH_WE# FLASH_CS2# FLASH_CS3# (Boot Flash Chip Select) FLASH_IOCHRDY Data Phase FLASH_AD[2:1] FLASH_AD0 FLASH_AD[9:3] FLASH_IO[7:0] NAND Flash Mode --FLASH_CLE --FLASH_IO[7:0] FLASH_ALE FLASH_CE0# FLASH_CE1# FLASH_RE# FLASH_WE# FLASH_CE2# FLASH_CE3# FLASH_RDY/BUSY# Ball A14 is the only ball that changes direction from IDE to Flash (input when in IDE mode, output when in Flash mode). If this interface is to be switched between IDE and Flash modes, then ball A14 needs an external pull-up to keep it high during IDE mode. 2.2.3.1 IDE Interface Signals Ball No. B12 Type I Description IDE Interrupt Request Channel 0. This signal is required for all IDE applications that use IDE DMA modes. It is available on GPIO2, which must be configured in the AUX_IN mode. If an IDE application will not use IDE DMA modes, or if the Flash interface will be used instead of the IDE interface, then this signal may be used as GPIO2. IDE Reset. An internal reset that is the functional “OR” of inputs RESET_WORK# and RESET_STAND#. It may also be controlled directly via an MSR (see Section 5.4.2.2 "Reset Decode (ATAC_RESET)" on page 254). This signal resets all the devices that are attached to the IDE interface. IDE Address Bits. These address bits are used to access a register or data port in a device on the IDE bus. IDE Data Lines. IDE_DATA[15:0] transfers data to/from the IDE devices. Signal Name IDE_IRQ0 IDE_RESET# F15 O IDE_AD[2:0] IDE_DATA[15:0] B11, A12, A11 C14, B15, B16, A17, C17, D16, D17, E17, E16, E15, D15, B17, C16, C15, A15, B14 O I/O Revision 0.8 35 www.national.com Geode™ CS5535 Signal Definitions (Continued) 2.2.3.1 IDE Interface Signals (Continued) Ball No. B13 Type O Description IDE I/O Read. This output is asserted on read accesses to corresponding IDE port addresses. When in Ultra DMA/33 mode, this signal is redefined: • IDE_HDMA_RDY - Host DMA Ready for Ultra DMA data-in bursts • IDE_HDMA_DS - Host DMA Data Strobe for Ultra DMA data-out bursts IDE_IOW0# C13 O IDE I/O Write. This output is asserted on write accesses to corresponding IDE port addresses. When in Ultra DMA/33 mode, this signal is redefined: • IDE_STOP - Stop Ultra DMA data burst IDE_CS0# IDE_CS1# IDE_DREQ0 B10 C10 A14 O O I IDE Chip Select 0. This chip select signal is used to select the Command Block registers in IDE Device 0. IDE Chip Select. This chip select signal is used to select the Command Block registers in IDE Device 1. DMA Request. The DREQ input is used to request a DMA transfer from the CS5535. The direction of the transfers are determined by the IDE_IOR0# and IDE_IOW0# signals. Note: Ball A14 is the only ball that changes direction from IDE to Flash (input when in IDE mode, output when in Flash mode). If this interface is to be switched between IDE and Flash modes, then ball A14 needs an external pull-up to keep it high during IDE mode. Signal Name IDE_IOR0# IDE_DACK0# IDE_RDY0 C12 A13 O I DMA Acknowledge. The DACK# output acknowledges the IDE_DREQ0 request to initiate DMA transfers. I/O Ready. When de-asserted, this signal extends the transfer cycle of any host register access when the device is not ready to respond to the data transfer request. When in Ultra DMA/33 mode, this signal is redefined: • IDE_DDMA_DS - Device DMA Data Strobe for Ultra DMA data-in bursts • IDE_DDMA_RDY - Device DMA Ready for Ultra DMA data-out bursts www.national.com 36 Revision 0.8 Geode™ CS5535 Signal Definitions (Continued) 2.2.3.2 Flash Controller Interface Ball No. Type Description Signal Name NOR Flash / GPCS Mode FLASH_CS[3:0]# C12, A14, C10, B10 O Chip Selects. Combine with FLASH_RE#/WE# strobes to access external NOR Flash devices or some simple devices such as UART. CS3# is dedicated to a boot Flash device. Note: Ball A14 is the only ball that changes direction from IDE to Flash (input when in IDE mode, output when in Flash mode). If this interface is to be switched between IDE and Flash modes, then ball A14 needs an external pull-up to keep it high during IDE mode. FLASH_RE# FLASH_WE# FLASH_ALE FLASH_AD[27:26]/ AD[2:1], FLASH_AD25/ AD0, FLASH_AD[24:18]/ AD[9:3] FLASH_AD[17:10]/ IO[7:0] B13 C13 C14 B11, A12, A11, B15, B16, A17, C17, D16, D17, E17 O O O O Read Enable Strobe. This signal is asserted during READ operations from the NOR array. Write Enable Strobe. This signal is asserted during WRITE operations to the NOR array. Address Latch Enable. Controls external latch (e.g., 74x373) for latching the higher address bits in address phase. Address Bus. During the address phase, address [27:18] is put on the bus. During the data phase, address [9:0] is put on the bus. E16, E15, D15, B17, C16, C15, A15, B14 A13 I/O Multiplexed Address and I/O Bus. During the address phase, NOR address [17:10] are placed on these lines. During the data phase, it is the NOR I/O data bus. I/O Channel Ready. When a device is hanging off the bus and wants to extend its current cycle, it pulls this signal low to insert the wait state. FLASH_IOCHRDY I NAND Flash Mode FLASH_CE[3:0]# C12, A14, C10, B10 O Chip Enables. The signals remain low during entire period of a NAND cycle. Note: FLASH_RE# FLASH_WE# FLASH_ALE FLASH_CLE FLASH_IO[7:0] B13 C13 C14 A11 E16, E15, D15, B17, C16, C15, A15, B14 A13 O O O O I/O Ball A14 is the only ball that changes direction from IDE to Flash. Needs external pull-up for Flash use. Read Enable Strobe. This signal is asserted during READ operations from the NAND array. Write Enable Strobe. This signal is asserted during WRITE operations to the NAND array. Address Latch Enable. Level signal to indicate an address byte is writing to the NAND Flash device. Command Latch Enable. Indicates a Command byte is being written to the device. I/O Bus. I/O Bus for NAND Flash devices. Command, address, and data are sent on this bus. This bus is actively driven to zero with or without an LPC_CLK from and after reset. Ready/Busy#. NAND Flash pulls this signal low to indicate it is busy with an internal operation. No further action is accepted except read status. FLASH_RDY/BUSY# I Revision 0.8 37 www.national.com Geode™ CS5535 Signal Definitions (Continued) 2.2.4 USB Interface Ball No. P17 Type O Description USB Power Enable 1. This signal is intended to be used to enable an external USB power source for Port 1, such as the National LM3526. USB_PWR_EN1 is an active high signal. If low, it indicates that the external USB power source for Port 1 is turned off. Defaults off from reset. USB_PWR_EN2 N16 O USB Power Enable 2. This signal is intended to be used to enable an external USB power source for Port 2, such as the National LM3526. USB_PWR_EN2 is an active high signal. If low, it indicates that the external USB power source for Port 2 is turned off. Defaults off from reset. USB_OC_SENS# N15 I USB Over Current Sense. This signal is the logical OR or wired-OR from all external USB power supply devices, such as the National LM3526, and is shared by USB1 and USB2 (all four ports). When pulled low it causes both USB_PWR_EN1 and USB_PWR_EN2 to de-assert and generate an interrupt. Tie high if not used. USB Port 1_1 Data Positive. This is the positive differential side of the USB data for port 1_1. (Note 1, Note 2.) USB Port 1_1 Data Negative. This is the negative differential side of the USB data for port 1_1. (Note 1, Note 2.) USB Port 1_2 Data Positive. This is the positive differential side of the USB data for port 1_2. (Note 1, Note 2.) USB Port 1_2 Data Negative. This is the negative differential side of the USB data for port 1_2. (Note 1, Note 2.) USB Port 2_1 Data Positive. This is the positive differential side of the USB data for port 2_1. (Note 1, Note 2.) USB Port 2_1 Data Negative. This is the negative differential side of the USB data for port 2_1. (Note 1, Note 2.) USB Port 2_2 Data Positive. This is the positive differential side of the USB data for port 2_2. (Note 1, Note 2.) USB Port 2_2 Data Negative. This is the negative differential side of the USB data for port 2_2. (Note 1, Note 2.) USB Analog Circuit Ground. Total of three ground balls for the USB transceivers. Most applications should connect this to signal ground. USB Analog Circuit Power. Total of three power balls for the USB transceivers. Most applications should connect this to VIO. Signal Name USB_PWR_EN1 USB1_1_DATPOS USB1_1_DATNEG USB1_2_DATPOS USB1_2_DATNEG USB2_1_DATPOS USB2_1_DATNEG USB2_2_DATPOS USB2_2_DATNEG AVSS_USB AVDD_USB K16 K17 L16 L17 H17 H16 G17 G16 F16, J16, M16 F17, J17, M17 I/O I/O I/O I/O I/O I/O I/O I/O AGND APWR Note 1. Use external 27 Ω series resistor on output. From reset, these outputs are in TRI-STATE. At board level, a 15 kΩ pull-down resistor is required per the USB specification. Note 2. External clamping diodes may be needed to meet over voltage requirements. www.national.com 38 Revision 0.8 Geode™ CS5535 Signal Definitions (Continued) 2.2.5 System Management Bus (SMB) Interface Ball No. G3 Type I/O Description SMB Clock. This is the clock for the System Management bus. It is initiated by the master of the current transaction. Data is sampled during the high state of the clock. An external pull-up resistor is required. Shared with GPIO14. Set GPIO14 to AUX_IN and AUX_OUT_1 modes simultaneously to use as SMB_CLK. See Table 2-8 "GPIO Options" on page 42. External voltage applied to this ball should not exceed VIO. SMB_DATA F1 I/O SMB Data. This is the bidirectional data line for the System management Bus. Data may change during the low state of the SMB clock and should remain stable during the high state. An external pull-up resistor is required. Shared with GPIO15. Set GPIO15 to AUX_IN and AUX_OUT_1 modes simultaneously to use as SMB_DATA. See Table 2-8 "GPIO Options" on page 42. External voltage applied to this ball should not exceed VIO. Signal Name SMB_CLK Revision 0.8 39 www.national.com Geode™ CS5535 Signal Definitions (Continued) 2.2.6 Low Pin Count (LPC) Interface (Note 1) Ball No. H1 K1, J1, J2, H2 Type I I/O Description LPC Clock. 33 MHz LPC bus shift clock. LPC Address/Data Bus. This is the 4-bit LPC bus. Address, control, and data are transferred on this bus between the CS5535 and LPC devices. An external pull-up of 100 kΩ is required on these balls if is used in LPC mode to maintain a high level when the signals are in TRISTATE. From reset, these signals are not driven. LPC_AD3 is shared with GPIO19. LPC_AD2 is shared with GPIO18. LPC_AD1 is shared with GPIO17. LPC_AD0 is shared with GPIO16. See Table 2-8 "GPIO Options" on page 42 for further details. LPC_DRQ# G1 I LPC DMA Request. This is the LPC DMA request signal. Peripherals requiring service pull it low and then place a serially-encoded requested channel number on this line to initiate a DMA transfer. If the device wakes up from Sleep, at least six LPC_CLKs must occur before this input is asserted. Shared with GPIO20. See Table 2-8 "GPIO Options" on page 42. Tie high if selected as LPC_DRQ# but not used. LPC_SERIRQ G2 I/O LPC Encoded IRQ. This is the LPC serial interrupt request line, used to report ISA-style interrupt requests. It may be activated by either the CS5535 or an LPC peripheral. An external pull-up of 100 kΩ is required if this ball is used in LPC mode to maintain a high level when the signal is in TRI-STATE. From reset, this signal is not driven. If the device wakes up from Sleep, at least six LPC_CLKs must occur before this input is asserted if operating in Quiet mode. Shared with GPIO21. See Table 2-8 "GPIO Options" on page 42. LPC_FRAME# H3 O LPC Frame. This signal provides the active-low LPC FRAME signal used to start and stop transfers on the LPC bus. Shared with GPIO22. See Table 2-8 "GPIO Options" on page 42. Note 1. All the LPC signals, except the LPC_CLK (LPC Clock) are shared on GPIO balls (see Table 2-8 "GPIO Options" on page 42). The CS5535 powers up with this group of balls set to the LPC mode; in order to use them as GPIOs they must be explicitly reprogrammed. The LPC may be switched to GPIO use via the Ball Opt MSR (see Table 26 "DIVIL_BALL_OPT" on page 29). Use RESET_OUT# for LPC reset. Use any GPIO assigned as a PME for the LPC PME. Use any GPIO assigned as an SMI for the LPC SMI. Use general Sleep and Standby controls (SLEEP_X, ball C2 and SLEEP_Y, ball J3) in place of LPCPD# for LPC power-down. Signal Name LPC_CLK LPCAD[3:0] www.national.com 40 Revision 0.8 Geode™ CS5535 Signal Definitions (Continued) 2.2.7 Audio Codec 97 InterfaceNote 1 Ball No. M1 Type I Description Audio Bit Clock. The serial bit clock from the codec. The frequency of the bit clock is 12.288 MHz and is derived from the 24.576 MHz crystal input to the external audio codec. Not required if audio not used; tie low. Audio Controller Serial Data Out. This output transmits audio data to the codec. This data stream contains both control data and the DAC audio data. The data is sent on the rising edge of the AC_CLK. Connect to the audio codec’s serial data input pin. Boot Options Select Bit 1. During system reset, this ball is the MSB of the two-bit boot option (balls L2 and L3), used to determine the location of the system boot device. It should be pulled low if required by Table 2-5 "Boot Options Selection" on page 29, otherwise, an internal pull up, asserted during reset, will pull it high. During reset, the ball output drivers are held in TRI-STATE, and the ball is sampled on the rising edge of RESET_OUT# (i.e., when external reset is de-asserted). After reset, this signal defaults low (off). Audio Controller Serial Data Input. This input receives serial data from the audio codec. This data stream contains both control data and ADC audio data. This input data is sampled on the falling edge of AC_CLK.Connect to the audio codec’s serial data output pin. Audio Controller Sync. This is a 48 kHz sync pulse that signifies the beginning of a serial transfer on AC_S_OUT, AC_S_IN, and AC_S_IN2. AC_S_SYNC is synchronous to the rising edge of AC_CLK. Connect to the audio codec’s SYNC pin. Boot Options Select Bit 0. During system reset, this ball is the LSB of the two-bit boot option (balls L2 and L3), used to determine the location of the system boot device. It should be pulled low if required by Table 2-5 "Boot Options Selection" on page 29, otherwise, an internal pull up, asserted during reset, will pull it high. During reset, the ball drivers are held in TRI-STATE, and the ball is sampled on the rising edge of RESET_OUT# (i.e., when external reset is de-asserted). After reset, this signal defaults low (off). Legacy PC/AT Speaker Beep. Connect to codec’s PC_BEEP. This function is only available when GPIO1 is programmed to AUX_OUT_1. See Table 2-8 "GPIO Options" on page 42. AC_S_IN2 J3 I Audio Controller Serial Data Input 2. This input receives serial data from a second codec. This data stream contains both control data and ADC audio data. This input data is sampled on the falling edge of AC_CLK. If the codec’s Ready bit is set in this stream (slot 0, bit 15), then it is functionally ORed with AC_S_IN. Connect to a second codec’s serial data output. This function is only available when GPIO12 is programmed to AUX_IN. See Table 2-8 "GPIO Options" on page 42. Note 1. Use RESET_OUT# for AC97 reset. Signal Name AC_CLK AC_S_OUT L2 O BOS1 I AC_S_IN L1 I AC_S_SYNC L3 O BOS0 I AC_BEEP K3 O Revision 0.8 41 www.national.com Geode™ CS5535 Signal Definitions (Continued) 2.2.8 GPIOs Table 2-8 gives the dedicated functions associated with each GPIO. These functions may be invoked by configuring the associated GPIO to the AUX_IN, AUX_OUT_1, or AUX_OUT_2 modes. (The functions themselves are described in Table 2-9 "GPIOx Available Functions Descriptions" on page 44.) The column “Recommended Use” is a guideline for system designers to assign GPIO functionality. Any GPIO input can be mapped to an interrupt, ASMI, or PME. Details of configuring the GPIOs are given in Section 5.16 "GPIO Subsystem Register Descriptions" on page 432. All GPIOs have selectable pull-up or pull-down resistors available on the output, except for those indicated by Note 1 in the “Weak PU/PD” column of Table 2-8. Table 2-8. GPIO Options Post Reset GPIO GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21 GPIO22 GPIO24 GPIO25 GPIO26 GPIO27 GPIO28 Note 1. Note 2. Ball No. R2 K3 B12 E1 E2 D3 D2 C2 E3 D1 C3 A1 J3 F2 G3 F1 H2 J2 J1 K1 G1 G2 H3 C9 A9 B7 C8 A8 Power Buffer Domain Type W W W W W W W W W W W W W W W W W W W W W W W S S S S S PCI Q7 IDE SMB SMB Q7 Q7 PCI Q7 Q7 Q7 Q7 Q7 Q7 SMB SMB PCI PCI PCI PCI PCI PCI PCI SMB Q7 Q7 Q7 Q7 Weak PU/PD (Note 1) PU (Note 1) (Note 1) (Note 1) Autosense Autosense (Note 1) PU PU PU PU PD PU (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) I/O Config Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled LPC (Note 6) LPC (Note 6) LPC (Note 6) LPC (Note 6) LPC (Note 6) LPC (Note 6) Disabled Disabled Disabled Disabled Input Enabled (Note 8) Recommended Use PCI_INTA# (Note 2) ----DDC_SCL (Note 3) DDC_SDA (Note 3) ----PCI_INTB# (Note 2) ------- (Note 4) ------- (Note 4) --- (Note 5) --- (Note 5) LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_DRQ# LPC_SERIRQ LPC_FRAME# ----PME# (Note 7) --PWR_BUT# (Note 9) PWR_BUT# LOW_BAT# MFGPT7_RS MFGPT7_C1 32KHZ WORK_AUX MFGPT7_C2 MFGPT2_RS AC_S_IN2 SLEEP_BUT SMB_CLK_IN SMB_DATA_IN SMB_CLK_OUT SMB_DATA_OUT UART1_RX or UART1_IR_RX THRM_ALRM# SLP_CLK_EN# MFGPT1_C2 SLEEP_Y MFGPT1_RS MFGPT0_RS IDE_IRQ0 UART2 RX UART2 TX MFGPT0_C1 MFGPT1_C1 MFGPT2_C1 UART1_TX MFGPT2_C2 SLEEP_X UART1_IR_TX AC_BEEP MFGPT0_C2 Function Programming Options AUX_IN AUX_OUT_1 AUX_OUT_2 (Note 1) LPC (Note 6) No internal pull-up/down available. If not used, tie low. Any GPIO can be used as an interrupt input without restriction. These particular GPIOs have PCI I/O buffer types for complete PCI bus compatibility. However, such strict compatibility is generally not required. www.national.com 42 Revision 0.8 Geode™ CS5535 Signal Definitions (Continued) Note 3. Applications incorporating a CRT often require support for the Display Data Channel (DDC) serial interface. These particular GPIOs have open collector SMB I/O buffer types required by the DDC interface specification. The DDC protocol supplied by National is provided via software implementation and defaults to these GPIOs. However, any design not needing strict DDC electrical support can use other GPIOs. Lastly, applications not incorporating DDC use at all may use these GPIOs without restriction. Internal signal is active high. Use GPIO invert for active low external. When both AUX_IN and AUX_OUT are enabled, I/O direction on this ball is controlled by the SMB Controller. Defaults to LPC use. Use Ball Options MSR (see Table 2-6 on page 29) to switch this ball to GPIO control. Any GPIO can be used as a Power Management Event (PME) wakeup input without restriction. PMEs are supported for both Sleep and Standby wakeup. However, if Standby wakeup is desired, a GPIO on the Standby power domain must be used. Only GPIO[24:28] are supplied via the Standby Power Rail and are typically used as follows: GPIO24 - Auxiliary Working Power Control GPIO25 - Low Battery Alarm GPIO26 - PME GPIO27 - MFGPT setup to provide a blink GPIO28 - Power Button Depending on application use, the PME function could be moved to GPIO[24:27]. If only external PME wakeup from Sleep is required, the PME function could be moved to GPIO[0:23]. Lastly, the PME function could simply not be used, making more GPIOs available for other uses. Note 8. Note 9. GPIOH_IN_EN (GPIO Offset A0h) and GPIOH_IN_AUX1_SEL (GPIO Offset B4h) are enabled. Reset default. Note 4. Note 5. Note 6. Note 7. Revision 0.8 43 www.national.com Geode™ CS5535 Signal Definitions (Continued) 2.2.8.1 GPIO Functions and Recommended Usage Functions listed in Table 2-9 are functions that may be assigned to specific GPIO balls. The “Ball No.” column gives the ball that must be used if this function is selected, and the “GPIOx” column gives the GPIO that the function is associated with. Table 2-9. GPIOx Available Functions Descriptions Function Name 32KHZ Ball No. C8 GPIO[x] GPIO27 Type O Description 32 kHz Clock. When invoked, this ball produces a buffered output of the 32 kHz clock provided on the 32kHz XCI and XCO pins. This option is invoked by selecting the AUX_OUT_2 option of GPIO27. Note that since GPIO27 is in the Standby power domain, the 32 kHz clock output will continue in Sleep and Standby states. AC_BEEP DDC_SCL K3 E1 GPIO1 GPIO3 O I/O Legacy PC/AT Speaker Beep. Connect to codec’s PC_BEEP. DDC Serial Clock. This is a “recommended use” for GPIO3, because this is one of the few GPIOs that have a high drive capacity, open-drain output. The serial clock function must be implemented in software to support DDC monitors. There is no dedicated DDC clock function within the CS5535. DDC Serial Data. This is a “recommended use” for GPIO4, because this is one of the few GPIOs that have a high drive capacity, open-drain output. The serial data function must be implemented in software to support DDC monitors. There is no dedicated DDC data function within the CS5535. Low Battery Detect. This is a “recommended use” for GPIO25 in battery-powered systems. It is invoked by setting GPIO25 to the AUX_IN mode. The signal is intended to be driven low by an external circuit when the battery voltage falls below a preset value (determined by the external circuit). It could be used to generate a PME (interrupt) - connected to LowBat function in the Power Management Controller that would then de-assert WORKING and WORK_AUX, if no software action is taken within a programmable time. Multi-Function General Purpose Counter #0 - Compare 1 Out. An output from the counter that, when asserted, indicates the counter has reached the conditions set up in the counter’s Compare 1 registers. Multi-Function General Purpose Counter #0 - Compare 2 Out. An output from the counter that, when asserted, indicates the counter has reached the conditions set up in the counter’s Compare 2 registers. Multi-Function General Purpose Counter #0 - Restart. An input to the counter that causes it to be reset to initial conditions and then to resume counting. Multi-Function General Purpose Counter #1 - Compare 1 Out. An output from the counter that, when asserted, indicates the counter has reached the conditions set up in the counter’s Compare 1 registers. Multi-Function General Purpose Counter #1 - Compare 2 Out. An output from the counter that, when asserted, indicates the counter has reached the conditions set up in the counter’s Compare 2 registers. Multi-Function General Purpose Counter #1 - Restart. An input to the counter that causes it to be reset to initial conditions and then to resume counting. DDC_SDA E2 GPIO4 I/O LOW_BAT# A9 GPIO25 I MFGPT0_C1 D3 GPIO5 O MFGPT0_C2 K3 GPIO1 O MFGPT0_RS D2 GPIO6 I MFGPT1_C1 D2 GPIO6 O MFGPT1_C2 A1 GPIO11 O MFGPT1_RS D3 GPIO5 I www.national.com 44 Revision 0.8 Geode™ CS5535 Signal Definitions (Continued) Table 2-9. GPIOx Available Functions Descriptions (Continued) Function Name MFGPT2_C1 Ball No. C2 GPIO[x] GPIO7 Type O Description Multi-Function General Purpose Counter #2 - Compare 1 Out. An output from the counter that, when asserted, indicates the counter has reached the conditions set up in the counter’s Compare 1 registers. Multi-Function General Purpose Counter #2 - Compare 2 Out. Output from the counter that, when asserted, indicates the counter has reached the conditions set up in the counter’s Compare 2 registers. Multi-Function General Purpose Counter #2 - Restart. An input to the counter that causes it to be reset to initial conditions and then to resume counting. Multi-Function General Purpose Counter #7 - Compare 1 Out. An output from the counter that, when asserted, indicates the counter has reached the conditions set up in the counter’s Compare 1 registers. Multi-Function General Purpose Counter #7 - Compare 2 Out. An output from the counter that, when asserted, indicates the counter has reached the conditions set up in the counter’s Compare 2 registers. Multi-Function General Purpose Counter #7 - Restart. An input to the counter that causes it to be reset to initial conditions and then to resume counting. PCI Interrupt A. This is a “recommended use” for GPIO0, because this GPIO has a PCI-compatible output type. PCI Interrupt B. This is a “recommended use” for GPIO7, because this GPIO has a PCI-compatible output type. Power Management Event. This is a “recommended use” for GPIO26. By mapping this GPIO (or any other) to the PME# function, the CS5535 may be awakened from a Sleep state when the mapped ball (in the recommended case, ball B7) is pulled low. MFGPT2_C2 D2 GPIO6 O MFGPT2_RS G2 GPIO21 I MFGPT7_C1 C8 GPIO27 O MFGPT7_C2 A9 GPIO25 O MFGPT7_RS B7 GPIO26 I PCI_INTA# PCI_INTB# PME# R2 C2 B7 GPIO0 GPIO7 GPIO26 I I I Revision 0.8 45 www.national.com Geode™ CS5535 Signal Definitions (Continued) Table 2-9. GPIOx Available Functions Descriptions (Continued) Function Name PWR_BUT# Ball No. A8 GPIO[x] GPIO28 Type I Description Power Button. This GPIO can be mapped to the PMC “buttonpush” event, that may be used to implement the power ON and the four-second-delay power OFF functions. Note that GPIO28 comes up in the AUX_IN mode after reset, enabling this feature. Any power button change on this input must be at least two KHZ32_XCI edges (approximately 62 µs) in duration to be correctly detected. If spurious transitions smaller than this are possible, then use on-chip GPIO input filter function to insure proper operation. Additionally, the rise or fall time on this input must be less than 10 µs. If transition times longer than this are possible, then use the on-chip GPIO input filter function to insure proper operation. From the first power-up of the Standby power domain under which no filter is enabled, spurious transitions on the first high-to-low power button push are acceptable as long as the input is eventually low at least two KHZ32_XCI edges. Additionally, transition times as slow as one milli-second are acceptable for the first push. Note that these relaxed requirements work because this input is effectively a “don’t care” at the hardware level after the first powerup until software enables use of the power button. Before enabling use, the software can setup the GPIO filter or other functions as needed. Per the discussion of the “skip” feature in Section 4.17 "Power Management Control" on page 159, this input may be tied to ground in order for the system to come on immediately when Standby and Working power are available. Specifically, systems that do not incorporate a power button should tie this input to ground. One side effect of the “skip” feature, is that the platform design must insure that this input is not low when Standby power is applied if the “skip” feature is not desired. Specifically, systems that do incorporate use of a power button must insure that this input ramps to a “high” no more than 1 µs behind VIO_VSB rampup. Failure to quickly establish a “high” on this input during powerup could result in a spurious “skip”. AC_S_IN2 J3 GPIO12 I Audio Controller Serial Data Input 2. This input receives serial data from a second codec. This data stream contains both control data and ADC audio data. This input data is sampled on the falling edge of AC_CLK. If the codec’s Ready bit is set in this stream (slot 0, bit 15), then it is functionally OR-ed with AC_SDATA_IN1. Connect to second codec’s serial data output. Sleep Clock Enable. This signal is a control that is intended to be connected to the external system clock generator chip. The intended use is, when high, the clock generator runs; when low, the clock generator turns off. From reset, a pull-up makes this GPIO high. The active state of this signal indicates that the CS5535 is in the Sleep state. Sleep Button. This GPIO can be mapped to a PME “button-push” type event, that may be used to request the system software to put the system to Sleep. SLP_CLK_EN# A1 GPIO11 O SLEEP_BUT F2 GPIO13 I www.national.com 46 Revision 0.8 Geode™ CS5535 Signal Definitions (Continued) Table 2-9. GPIOx Available Functions Descriptions (Continued) Function Name SLEEP_X Ball No. C2 GPIO[x] GPIO7 Type O Description Sleep X. This general purpose power control output becomes active as the CS5535 enters and exits various power management modes. It may be used by external devices to control their power states synchronous with power state changes in the CS5535. It may be configured as active high or active low. Sleep Y. This general purpose power control output becomes active as the CS5535 enters and exits various power-management modes. It may be used by external devices to control their power states synchronous with power state changes in the CS5535. It may be configured as active high or active low. SMB Clock In / SMB Clock Out. This is the clock for the SMB. In order to use it properly, the associated GPIO (GPIO14) should be set to AUX_IN and AUX_OUT_1 simultaneously. The SMB controller determines the direction (in or out) of the associated ball. SMB Data In / SMB Data Out. This is the data line for the SMB. In order to use it properly, the associated GPIO (GPIO15) should be set to AUX_IN and AUX_OUT_1 simultaneously. The SMB controller determines the direction (in or out) of the associated ball. Thermal Alarm. When connected to an external thermal monitor, this input can act as a thermal fail-safe to shut down power by signalling the power management controller to de-assert WORKING and WORK_AUX. Set GPIO10 to the AUX_IN mode to enable this feature. IDE Interrupt. Indicates the external IDE device has completed the DMA operation. UART1 Infrared Transmit. This signal is the data output (TX) from the infrared mode of UART1. It is available when GPIO8 is switched to the AUX_OUT_2 mode UART1 Receive or UART1 Infrared Receive. This signal is the data input (RX) to the UART1. It acts as the input in both IR and conventional modes of UART1. It is available when GPIO9 is switched to the AUX_IN mode. UART1 Transmit. This signal is the data output (TX) from the conventional mode of UART1. It is available when GPIO8 is switched to the AUX_OUT_1 mode. UART2 Receive. This signal is the data input (RX) to the UART2. It acts as the input of UART2. It is available when GPIO3 is switched to the AUX_IN mode. UART2 Transmit. This signal is the data output (TX) from the conventional mode of UART1. It is available when GPIO4 is switched to the AUX_OUT_1 mode. Working Auxiliary. This output is intended to be used to control external power sources to all devices except memory (which is intended to be controlled by WORKING). WORK_AUX de-asserts in synchronism with WORKING. SLEEP_Y J3 GPIO12 O SMB_CLK_IN SMB_CLK_OUT G3 GPIO14 I O SMB_DATA_IN SMB_DATA_OUT F1 GPIO15 I O THRM_ALRM# C3 GPIO10 I IDE_IRQ0 UART1_IR_TX B12 E3 GPIO2 GPIO8 I O UART1_RX UART1_IR_RX D1 GPIO9 I I UART1_TX E3 GPIO8 O UART2_RX E1 GPIO3 I UART2_TX E2 GPIO4 O WORK_AUX C9 GPIO24 O 2.2.9 Debug and Manufacturing Test Interface Ball No. N2 Type I Description JTAG Test Clock. 47 www.national.com Signal Name TCK Revision 0.8 Geode™ CS5535 Signal Definitions (Continued) 2.2.9 Debug and Manufacturing Test Interface (Continued) Ball No. N3 P1 P2 Type I I O, TS Description JTAG Test Mode Select. JTAG Test Data In. JTAG Test Data Out. From reset, this output is TRI-STATE. It is only enabled and driven when commanded to output or pass-through data per JTAG standards. Test Debug Input. Input to GeodeLink Control Processor (GLCP) from GX2. Test Debug Out. Output from GeodeLink Control Processor (GLCP) to GX2. Low Voltage Detect Test. Manufacturing test only. No operational use. Make no connection. Test Mode. Manufacturing test only. No operational use. Tie low. Functional Test. Manufacturing test only. No operational use. Tie low. Signal Name TMS TDI TDO T_DEBUG_IN T_DEBUG_OUT LVD_TEST TEST_MODE FUNC_TEST M2 M3 B9 A6 F3 I O O I I www.national.com 48 Revision 0.8 Geode™ CS5535 Signal Definitions (Continued) 2.2.10 Power, Ground, and No Connects (Note 1) Signal Name VCORE Ball No. D8, D10, H4, H14, K4, K14, P8, P10 A7 D4, D6, D9, D12, D14, F4, F14, M4, M14, P4, P6, P9, P12, P14 B6 D5, D7, D11, D13, E4, E14, G4, G14, J4, J14, L4, L14, N4, N14, P5, P7, P11, P13 A2, A16, B1, B4, B5, C11, G15, H15, J15, K15, L15, M15, R3, R9, T2, U2, U15, U16, U17 Type PWR Description 1.5V (Nominal) Core Power Working Connection (Total of 8) VCORE_VSB VIO PWR PWR 1.5V (Nominal) Core Power Standby Connection 3.3V (Nominal) I/O Power Connection (Total of 14) VIO_VSB VSS PWR GND 3.3V (Nominal) I/O Power Standby Connection Ground Connection (Total of 18) NC --- No Connection (Total of 19). These lines must be left disconnected. Connecting any or these lines to a pull-up/-down resistor, an active signal, power, or ground could cause unexpected results and possible malfunctions. Note 1. For module specific power and ground signals see: Section 2.2.1 "System Interface Signals" on page 31. Section 2.2.4 "USB Interface" on page 38. Revision 0.8 49 www.national.com Geode™ CS5535 3.0 3.1 Global Concepts and Features GEODELINK ARCHITECTURE OVERVIEW • All outputs from the GLIU to a GLD are registered. Furthermore, there are dedicated output registers for each GLD. • GLD inputs from the GLIU need not be registered but they are buffered at the interface. • All connections between the GLDs and GLIU are dedicated point-to-point connections with one source and one load. There are no TRI-STATE buses. • The GLIU itself is a GLD and is always Port 0. The GLIU implements the “bus”. Transactions between GLDs and GLIUs are conducted with packets. The GLIU accepts request packets from masters and routes them to slaves. Similarly, slave response packets are routed back to the master. The bus is non-blocking. Several requests can be pending but order is guaranteed. Broadcasts are not allowed. All packets have one source and one destination. 3.1.2 Routing The Physical To Device (P2D) descriptors control the routing of the packets. The descriptors are initialized by software at system setup. They establish the address map to be used by the system. They associate a memory or I/O address range with a GLIU port. GLD3 The information in this section provides a basic understanding of the architecture used to internally connect GeodeLink Devices. The actual existence of architecture is generally invisible to the user and the system programmer. National Semiconductor Core BIOS software provides all GeodeLink initialization and support, including related Model Specific Registers (MSRs). Additionally, this software provides a Virtual PCI Configuration Space that abstracts the architecture to industry standard interfaces. From this interface, all GeodeLink devices appear in one PCI multi-function configuration space header on the external PCI bus. 3.1.1 Introduction This component is based on the GeodeLink packet architecture. It consists of a set of GeodeLink Devices (GLDs) and a GeodeLink Control Processor (GLCP) connected through the GeodeLink Interface Unit (GLIU). A simplified view of a GLIU connected with three generic GLDs is illustrated in Figure 3-1. The following points are relevant: • All outputs from a GLD to the GLIU are registered. GLD1 GLD2 RO HS DO RO HS DO RO HS DO P2D ARB Data Mux GLIU RI DI RI DI RI DI RO - Request Out DO - Data Out RI - Request In DI - Data In HS - Handshake P2D - Physical to Device Descriptors ARB - Arbiter Figure 3-1. Simplified GLIU with Generic GeodeLink Devices www.national.com 50 Revision 0.8 Geode™ CS5535 Global Concepts and Features (Continued) When a request packet arrives from a Request Out (RO) port, the address and other attributes in the packet are used to look up the destination port. If the port Request In (RI) is available, the request is passed. If there are multiple requests, priorities are used to establish which requestor and destination port utilize the transfer cycle. A transfer from an RO to an RI takes one clock edge. 3.1.3 Response Packets Earlier in this section, it was indicated that an RO can be used to present a write data packet or a read response packet. The use and need of a read response packet for a read request is obvious. However, there is also an optional write response packet. This tells the requestor that the write has completed. This is used to hold a processor I/O write instruction until the response is received, that is, I/O writes are never posted. Memory writes are always posted. The response packet is also used to generate Synchronous System Management Interrupts (SSMIs). System Management Mode (SMM) is used for hardware emulation and other traps. An SSMI can be generated by a GLD or via special GLIU descriptors. When the response arrives back at the processor, interface circuits generate an SMI to invoke the SMM software. Lastly, all response packets contain an exception flag that can be set to indicate an error. 3.1.4 ASMI and Error Two additional signals are needed to complete this GeodeLink architecture overview: Asynchronous System Management Interrupt (ASMI) and Error. Each GLD outputs these ASMI and Error signals. An ASMI is much like a legacy interrupt, except it invokes the SMM handler. As the name suggests, an ASMI is an asynchronous event, while an SSMI is synchronous to the instruction that generated it. The Error signal simply indicates some type of unexpected error has occurred. A device asserts this signal when an unexpected error occurs. In a normal operating system, this would not be asserted. For example, a disk read error or ethernet network error would be signaled using normal GeodeLink packet mechanisms. This signal is reserved for the truly unexpected. Each GLD has mechanisms for enabling and mapping multiple internal sources down to these singular outputs. The mechanism consists of the logical “OR” of all enabled sources. The GLIU receives the ASMI and Error pair from each GLD. It has the same “OR” and enable mechanism that finally results in a single ASMI and Error pair for the whole component (see Figure 3-2). The ASMI is routed to the processor, while the Error is routed to the GLCP. Within the GLCP, the Error signal can be mapped into an ASMI for routing back into the GLIU. CS5535 ASMI to GX2 GLCP ASMI & Error ASMI & Error ASMI & Error ASMI & Error ASMI & Error ASMI & Error Enable ASMI & Error ASMI & Error GLIU ASMI & Error CS5535 Error to GLCP Debug or conversion to ASM OR www.national.com ACC DD ATAC USBC2 GLPCI_SB Figure 3-2. GeodeLink Architecture ASMI and Error Routing Revision 0.8 51 OR USBC1 Enable Geode™ CS5535 Global Concepts and Features (Continued) 3.1.5 Topology The connection of the GLIU to the seven GLDs of the CS5535 is illustrated in Figure 3-3. Note the circled number next to each GLD. This is the port number of the GLD. By design convention, the GLIU is always port zero. Part of the physical to device (P2D) descriptor is a port number. When there is a hit on the descriptor address, the port number indicates which GLD to route the packet to. If there is no hit, then the packet is routed to the default port. For the CS5535, the default is always Port 4, that is, the Diverse Device (DD). 3.1.6 Address Spaces and MSRs The GLIU and GLDs support the traditional memory and I/O spaces. The memory space supports a traditional 32bit byte address with associated byte enables. The I/O space is a 20-bit byte address with byte enables. I/O registers can be 8, 16, or 32 bits. The GLIU has both memory and I/O P2Ds for routing. In addition to the above spaces, there is a Model Specific Register (MSR) space that is tied to the GeodeLink topology. As introduced in the previous section, the GLIU has eight ports with Port 0 assigned to the GLIU. An MSR “address” is relative to the device making a request to it and the topology between the requestor and the MSR. Thus, for the GX2 processor to address an MSR in the CS5535, it specifies a series of ports that must be traversed to get there. Once a specific device port is identified, additional address bits are available to select a specific MSR within a given device. MSR space is functionally similar to PCI configuration space. At boot time system initialization, the Core BIOS (see Section 3.1 "GeodeLink Architecture Overview" on page 50) traverses the topology of the system to determine what is present. By convention, the first MSR at each port is an ID register that indicates a specific device. Once the Core BIOS knows what is present, it assigns devices to specific locations in the appropriate memory or I/O address space using MSRs. Generally, MSRs are used to configure and set up GLDs, but are not used for ongoing operations. The “assignment” MSRs are located in the GLIUs as “descriptors”. The “assignment descriptor” basically says: “route a request packet containing address X to port Y”. Port Y can be the final device or another GLIU. This second GLIU must have assignments to route address X to port Z. This process continues until the final device port is specified. GLPCI_SB Data Out Req Out Data In Req In Req In Data In Diag Req In Port 1 Port 2 GLIU Port 0 Port 3 Port 6 Port 7 Data In Req Out Data Out Diag Req In Data In Req Out Data Out Diag Req In Data In Req Out Data Out Diag USBC2 Req Out Data Out Diag Req In Data In Req Out Data Out Diag Req In Data In Req Out Data Out Diag GLCP ATAC USBC1 DD Port 4 Port 5 ACC Figure 3-3. CS5535 GeodeLink Architecture Topology www.national.com 52 Revision 0.8 Geode™ CS5535 Global Concepts and Features (Continued) In addition to the “positive” address decode above, each GLIU has a subtractive port that takes all addresses not assigned to a specific port. There is always a default subtractive port path to the boot ROM to allow the central processor to start executing code from time zero. Thus, from system reset, there is a default memory address path that allows the first processor instruction fetch to: 1) 2) 3) 4) Proceed down through the two GX2 GLIUs; cross the PCI bus to the CS5535; proceed down through the CS5535 GLIU to the default port connected to the DD; and access the boot device connected to the DD. that is, the address value 0 accesses one 64-bit register, the address value 1 accesses one 64-bit register, the address value 2 accesses one 64-bit register, etc. There are no MSR byte enables. All 64 bits are always written and read. Many CS5535 MSRs are only 32 bits in physical size. In these cases, interface logic discards the upper 32 bits on writes and pads the upper 32 bits on reads. Read padding is undefined. Lastly, CS5535 GLDs only decode enough bits of the address to select one of N MSRs, where N is the total number of MSRs in the device. For example, if a GLD has only 16 MSRs, then the addresses 0x2001, 0x0201, 0x0021, and 0x0x0001 all access MSR number 1, while the addresses 0x200F, 0x020F, 0x002F, and 0x0x000F all access MSR number 15. To access a given GLD, use Table 3-2 "CS5535 MSR Addresses from GX2 Processor" on page 54. Note the target device addresses: GLPCI_SB GLIU USBC2 ATAC DD ACC USBC1 GLCP 5100xxxxh 5101xxxxh 5120xxxxh 5130xxxxh 5140xxxxh 5150xxxxh 5160xxxxh 5170xxxxh 3.1.7 Special Cycles and BIZZARO Flag The BIZZARO flag is used to indicate special cycles and exceptions to normal packet operation. All special cycles traverse the GLIU system as I/O packets with the BIZZARO flag set. The special cycles are: 1) 2) 3) Interrupt Acknowledge: I/O read from address zero. Shutdown: I/O write to address zero. Halt: I/O write to address one. 3.2 CS5535 MSR ADDRESSING An MSR address consists of the fields shown in Table 3-1. When a GLIU receives an MSR packet, it routes the packet to the port specified in Field 0 but shifts address bits [31:14] to the left by three bits and replaces bits [16:14] with zero. Thus, Field 1 is moved to Field 0, Field 2 is moved to Field 1, etc. The address field always remains unchanged and selects one 64-bit MSR per address value, The xxxx portion refers to the MSR addresses as they appear any place within Section 5.0 "Register Descriptions" on page 184. To form a complete MSR address, “OR” an address provided in a register description section with the appropriate address above. Table 3-1. MSR Routing Conventions Routing Field 0 Bits [31:29] Routing Field 1 Bits [28:26] Routing Field 2 Bits [25:23] Routing Field 3 Bits [22:20] Routing Field 4 Bits [19:17] Routing Field 5 Bits [16:14] Address Field Bits [13:0] Revision 0.8 53 www.national.com Geode™ CS5535 Global Concepts and Features (Continued) Table 3-2. CS5535 MSR Addresses from GX2 Processor Routing Field 0 Bits [31:29] Routing Field 1 Bits [28:26] Routing Field 2 Bits [25:23] Routing Field 3 Bits [22:20] Routing Field 4 Bits [19:17] Routing Field 5 Bits [16:14] GLD Target Name & Address GLPCI_SB 5100xxxxh These bits are shifted off to the left and never enter the CS5535. These bits are shifted into positions [31:23] by the time they reach the CS5535. Bits in positions [22:14] are always 0 after shifting. 000 000 000 Comment This all-zero convention indicates to the GLPCI_SB that the MSR packet coming across the PCI bus is actually for the GLCPI_SB. This non-zero convention indicates to the GLPCI_SB that the MSR packet coming across the PCI bus should be forwarded to the GLIU. The GLIU only looks at [22:20] and hence, keeps the packet. The GLIU can not send any packets back to the port it came from. 010 100 010 010 100 010 000 Non-zero value GLIU 5101xxxxh 010 010 010 010 010 010 010 100 100 100 100 100 100 100 010 010 010 010 010 010 010 001 010 011 100 101 110 111 Any value Any value Any value Any value Any value Any value Any value Illegal USBC2 5120xxxxh ATAC 5130xxxxh DD 5140xxxxh ACC 5150xxxxh USBC1 5160xxxxh GLCP 5170xxxxh www.national.com 54 Revision 0.8 Geode™ CS5535 Global Concepts and Features (Continued) 3.3 TYPICAL CS5535 GEODELINK DEVICE The GLA sits between the GLIU and the Local bus. The Local bus is a traditional address/data bus supporting GLA to NB transactions (slave transactions) and NB to GLA transactions (master transactions). However, it is a single transaction bus in that any given slave or master transaction runs to completion before another transaction can start. This is compatible with the NBs listed above (i.e., ACC, ATAC, and DD), which are all single transaction devices. As suggested by Figure 3-4, the GLA contains no registers and is strictly speaking, just a bridge. The MSRs are conceptually separate from the NB and GLA and generally provide overall GLD configuration and control. In most designs they are physically separated as shown. There are six standard MSRs that are detailed in Section 3.8 "Standard GeodeLink Device MSRs". All GLDs have these standard MSRs. GLDs may also incorporate additional MSRs as appropriate. On the upper right of the figure, the connections between the GLA and GLIU are illustrated. All of these signals were covered previously in Section 3.1 "GeodeLink Architecture Overview". The Clock Control Units (CCU) are a key component in the Active Hardware Clock Gating (AHCG) infrastructure. They provide the mechanism for turning off clocks to sections of logic that are Not Busy. Furthermore, they take an asynchronous global reset signal and synchronize it to the applicable clock domain. A typical or “generic” CS5535 GeodeLink Device (GLD) is illustrated in Figure 3-4 along with internal and external connections. The GLD consists of the Native Block (NB), GeodeLink Adapter (GLA), MSRs, and Clock Control Units (CCU). Each of these is discussed in the following paragraphs. Before going into the blocks of the typical device, it should be noted that the following modules in CS5535 follow this model very closely: — AC97 Controller (ACC) — ATA-5 Controller (ATAC) — Diverse Device (DD) Specifically, they all use the GLA. The NB performs the “useful” work for the device. For example, in a serial port device, the transmit parallel to serial shift register is located in this block. The NB connects to the outside world, that is, external devices, via the I/O cells and pads. The NB contains registers that are manipulated by software to perform the “work”. These are operational registers that are typically manipulated by device drivers. The NBs are covered in detail in the corresponding GeodeLink Device register descriptions. Native Block (NB) MSRs Native Block Registers Local Bus Interface GL Adapter (GLA) Reg In Data In Reg Out Data Out Diag ASMI ERR GLIU Other Device Connections MSRs CCU GL Clock CCU Local Bus Clock CCU Busy Signals GL Device to GLCP Side-band signals to other Native Blocks External Device Interface Native Clock Global internal_reset I/O Cells & Pads Figure 3-4. Typical CS5535 GeodeLink Device Revision 0.8 55 www.national.com Geode™ CS5535 Global Concepts and Features (Continued) 3.4 EMBEDDED PCI ADAPTER (PA) • Capable of responding to both single data phase as well as burst transactions. • Closely follows the functioning of the GLA. • Capable of issuing retries to the master when the Local bus side is taking too long to complete the current transaction. • Safely handles all the error conditions possible during normal and configuration PCI transactions. Using the Virtual PCI Configuration Space (see Section 3.1 "GeodeLink Architecture Overview" on page 50), the Core BIOS lifts this embedded physical interface into the multifunction PCI configuration space header mentioned previously. A GeodeLink Device with an embedded PCI bus is illustrated in Figure 3-5. Note the similarity with Figure 3-4 "Typical CS5535 GeodeLink Device" on page 55. The only difference is the PCI Adapter (PA) located in the center of the figure. The PA allows a module designed for the PCI bus to be easily embedded in a GeodeLink architecture. It is used to embed the USB core into the GeodeLink architecture. The PA provides the following features: • Converts GLA Local Bus transactions to/from PCI bus transactions. • Provides PCI bus configuration transactions from GLD MSR transactions. • Performs PCI bus protocol checking and sets the GLD Error Flag if appropriate. Native Block (NB) Embedded PCI Bus Interface PCI Adapter (PA) MSRs Native Block Registers Local Bus Interface GL Adapter (GLA) Reg In Data In Reg Out Data Out Diag ASMI ERR CCU CCU CCU I/O Cells & Pads GeodeLink Device Side-band signals to other Native Blocks External Device Interface Figure 3-5. CS5535 GeodeLink Device With Embedded PCI Bus www.national.com 56 Revision 0.8 Geode™ CS5535 Global Concepts and Features (Continued) 3.5 CLOCK CONSIDERATIONS 3.5.1 Clock Domain Definitions Table 3-3 lists the clock sources and domains. Table 3-3. CS5535 Clock Sources and Clock Domains Component Pin MHZ66_CLK Inverted MHZ66_CLK (Note 1) Domain Name ATAC_LB GLIU_GLA GLIU_STAT GLPCI_GLIU USBC2_GLIU ATAC_GLIU DD_GLIU ACC_GLIU USBC1_GLIU GLCP_GLIU MHZ66_CLK divided by two (Note 2) USBC2_LB ACC_LB USBC1_LB PCI_CLK GLPCI_TRNA GLPCI_INTF GLCP_PCI MHZ48_CLK MHZ48_CLK divided by two (Note 2) USBC#2_COR USBC#1_COR SMB_COR UART1_COR UART2_COR LPC_CLK DD_LB LPC_COR PIT_COR DMA_COR AC_CLK MHZ14_CLK (Note 3) ACC_COR MFGPT_COR_14M PMC_SLP PIT_REF KHZ32_XCI (Note 3) RTC_COR MFGPT_COR_32K MFGPT_COR_32K_S PMC_STB GPIO_COR GPIO_COR_S TCK (Note 3) (Note 4) Note 1. Note 2. Note 3. Note 4. TAP_CNTRL GLCP_DBG Description ATAC Local bus and ATAC core GLIU GLA interface and related logic GLIU Statistics Counters GLPCI_SB GLIU interface and related logic USBC2 GLIU interface and related logic ATAC GLIU interface and related logic DD GLIU interface and related logic ACC GLIU interface and related logic USBC1 GLIU interface and related logic GLCP GLIU interface and related logic USBC2 Local bus interface and related logic ACC Local bus interface and related logic USBC1 Local bus interface and related logic GLPCI_SB transaction processing GLPCI_SB interface to PCI bus GLCP PCI related logic USBC2 core logic USBC1 core logic System Management Bus core logic UART1 core logic UART2 core logic DD Local bus interface and related logic; Includes PIC LPC Controller core logic Programmable Interval Timer core logic 8237 DMA core logic ACC core logic MFGPT core logic14 MHz clock Power Management Controller Sleep logic Programmable Interval Timer reference clock RTC core logic MFGPT core logic 32 kHz clock MFGPT 32kHz clock source; Standby power domain Power Management Controller Standby logic; Standby power domain GPIO core logic GPIO core logic; Standby power domain JTAG TAP Controller clock source GLCP debug logic The MHZ66_CLK is first inverted and then fed to all these domains. Each domain receives the referenced clock and performs the divide just before the CCU. This clock differs from other clocks in this table in that this clock does not utilize a CCU nor is it subject to GLCP control or power management control. This logic does not have a fixed clock source. During debug it is switched to the clock domain of interest. It does have a CCU. Revision 0.8 57 www.national.com Geode™ CS5535 Global Concepts and Features (Continued) 3.5.2 Clock Controls and Setup Each of the clock domains listed in Table 3-3 is subject to various GLCP controls and status registers except those with “Note 3”. These registers and a brief description of each is provided: • GLCP Clock Active (GLCP_CLKACTIVE), MSR 51700011h: A 1 indicates the corresponding clock is active. This is a read only register. • GLCP Clock Control (GLCP_CLKOFF), MSR 51700010h: A 1 indicates the corresponding clock is to be disabled immediately and unconditionally. Not normally used operationally. Debug only. • GLCP Clock Mask for Debug Clock Stop Action (GLCP_CLKDISABLE), MSR 51700012h: A 1 indicates the corresponding clock is to be disabled by debug logic via a debug event or trigger. Not normally used operationally. Debug only. • GLCP Clock Active Mask for Suspend Acknowledge (GLCP_CLK4ACK), MSR 51700013h: A 1 indicates the corresponding clock is to be monitored during a power management Sleep operation. When all the clocks with associated 1s go inactive, the GLCP sends a Sleep Acknowledge to the Power Management Controller. This register is used during Sleep sequences and requires the CLK_DLY_EN bit in GLCP_GLB_PM (MSR 5170000Bh[1]) to be 0. • GLCP Clock Mask for Sleep Request (GLCP_PMCLKDISABLE), MSR 51700009h: A 1 indicates the corresponding clock is to be disabled unconditionally during a power management Sleep operation. Clocks are disabled when the GLCP completes all of its Sleep Request operations and sends a Sleep Acknowledge to the Power Management Controller. All of the registers above have the same layout, where each bit is associated with a clock domain. The layout and recommended operating values for the registers is provided in Table 5-73 "Clock Mapping / Operational Settings" on page 518. 3.5.2.1 Additional Setup Operations 5170000Bh[1] = 1). This will disable the use of GLCP_CLK4ACK and shut off the clocks in GLCP_PMCLKDISABLE after the GLCP_CLK_DIS_DELAY expires. This delay is measured in PCI clock edges. 3.6 RESET CONSIDERATIONS The elements that effect “reset” within the CS5535 are illustrated in Figure 3-6 on page 59. The following points are significant: • Signals denoted in upper case (i.e., all capitals) are external pins. Signals denoted in lower case are internal signals. • There are separate resets for the Working power domain (RESET_WORK#) and the Standby power domain (RESET_STAND#). • All elements in the figure are within the Standby power domain and operate off the KHZ32_CLK. • The TAP Controller is in the Working power domain, but it may be reset separately from the other Working domain logic. • Any time the CS5535 is in the Standby state, the Working power domain is unconditionally and immediately driven into reset. • Any faulted event or external reset input forces the CS5535 into the Standby state. • External reset (RESET_OUT#) is always asserted immediately with internal working domain reset but is de-asserted subject to a programmable delay. RESET_OUT# asserts without any clocks but requires the KHZ32_CLK for the delay and the PCI_CLK to deassert. • IDE_RESET# is always asserted immediately with internal working domain reset and de-asserts when the ATAC comes out of reset, that is, within a few MHZ66_CLK edges of internal reset de-assert. • LVD monitors VCORE and only asserts power_good_working when VCORE is within normal operating range. • LVD monitors VCORE_VSB and VIO_VSB along with RESET_STAND#. The assertion of power_good_standy only occurs when the voltages are within normal operating range and RESET_STAND# is high, that is, deasserted. When power is applied to the CS5535 from a completely cold start, that is, no Standby or Working power, both RESET_STAND# and RESET_WORK# are applied. Alternatively, one or both of the reset inputs may be tied to Standby I/O power (VIO_VSB), and the LVD circuit will generate internal Power Good Working and internal Power Good Standby. Assuming the LVD circuit is enabled (LVD_EN# pin tied low), Power Good Standby will assert until proper Standby voltages have been achieved and RESET_STAND# has been de-asserted. • GLCP Debug Clock Control (GLCP_DBGCLKCTL), MSR 51700016h: Set all bits to 0. This turns off all clocks to debug features; not needed during normal operation. • GLCP Global Power Management Control (GLCP_GLB_PM), MSR 5170000Bh: Set all bits to 0. This disables the use of the fixed delay in GLCP_CLK_DIS_DELAY and enables the use of GLCP_CLK4ACK. • GLCP Clock Disable Delay Value (GLCP_CLK_DIS_DELAY), MSR 51700008h: Set all bits to 0. Since use of this register is disabled by setting all GLCP_DBGCLKCTL bits to 0, the actual value of this register is a “don’t care”; it is set here for completeness. If use of GLCP_CLK_DIS_DELAY is desired, set the CLK_DLY_EN bit in GLCP_GLB_PM (MSR www.national.com 58 Revision 0.8 Geode™ CS5535 Global Concepts and Features (Continued) RESET_OUT# is de-asserted synchronous with the low-tohigh edge of PCI_CLK. The de-assertion is delayed from internal_reset using a counter in the Power Management Controller. This counter is driven by the 32 kHz clock and is located in the Standby power domain. The value of the counter is programmable but defaults to 0x0_0100 (256 edges). 31.25 µs per edge times 256 equals an 8 ms delay. Note this counter default is established by RESET_STAND# and is not effected by RESET_WORK#. Therefore, the delay value may be changed and then the system can be reset with the new value. Note the special consideration for TAP Controller reset. When boundary scan is being performed, internal component operation is not possible due to the scanning signals on the I/Os. Under this condition, it is desirable to hold the component internals in reset while the boundary scan is being performed by the TAP Controller. However, under normal operation, it is desirable to reset the TAP Controller Normal Software Request for Standby State Fail-safe Power Off Alarm Thermal Alarm Low Power Alarm Shutdown Special Cycle MFGPT WATCHDOG DD Bad Packet GLCP Soft Reset DD Soft Reset Working Power Fail RESET_WORK# 32kHZ_CLK Internal Reset to all Working Domain Logic except TAP Controller RESET_OUT# D Q De-assert Delay ATA Controller IDE_RESET# working work_aux standby_state with the other logic in the Working domain during power management sequences. Achieving these dual goals is accomplished as follows: For boundary scan: • Assert RESET_STAND#, causing internal power_good_standby to go low. This causes the complete component to reset, except for the TAP Controller. Keep this input held low throughout boundary scan operations. • Assert and de-assert RESET_WORK# as needed to reset the TAP Controller. For normal operation: • The internal Power Good Standby will be high, meaning the TAP Controller reset asserts any time the Standby state is active or anytime RESET_WORK# is active. Faulted Event Capture Faulted Event Status unconditionally & immediately enter Standby state Power Manage Standby State Controller PCI_CLK VCORE VCORE_VSB VIO_VSB RESET_STAND# LVD (Low Voltage Detect) Power Good Working Power Good Standby (Standby Domain Reset When Low) standby_state TAP Controller Reset Figure 3-6. Reset Logic Revision 0.8 59 www.national.com Geode™ CS5535 Global Concepts and Features (Continued) 3.7 MEMORY AND I/O MAP OVERVIEW • Bit 14: Reject Secondary IDE. If this bit is set, the GLPCI_SB will not actively decode the secondary IDE addresses of: 0170h/0177h and 0376h. • Bit 15: Reject DMA High Page Active. If this bit is set, the GLPCI_SB will actively decode the following I/O range associated with the DMA High Page registers: 0480h/048Fh. For further details on the GLPCI_MSR_CTL register see Section 5.2.2.1 "Global Control (GLPCI_CTRL)" on page 219. Lastly, there in an “MSR Access Mailbox” located in PCI Configuration register space. It consists of the following 32bit registers: • MSR Address (PCI Index F4h). Full MSR routing path in the upper portion plus 14 device address bits in the lower portion. • MSR Data Low (PCI Index F8h). Bits [31:0]: When read, an MSR cycle is generated. The 64-bit read returns the low 32 bits and saves the upper 32 bits for a read to “Data High”. A write holds the value written as the current “Data Low”. • MSR Data High (PCI Index FCh). Bits [63:32]: Reads return upper 32 bits of the last MSR value read. Writes generate an MSR write cycle using the current value and the “Data Low” value. For further details on the MSR Access Mailbox see Section 5.2.3 "PCI Configuration Registers" on page 225. 3.7.3 GLIU Decoding From reset, the GLIU passes all request packets to the Diverse Device, except for the legacy primary IDE addresses (01F0h/01F7h and 03F6h), these are passed to the IDE device in the ATAC. There is a GLIU IOD_SC descriptor to control this primary IDE behavior and it defaults configured (see Section 5.1.4.2 "IOD Swiss Cheese Descriptors (GLIU_IOD_SC[x])" on page 211). If this descriptor is disabled, all requests pass to the Diverse Device. Using appropriate MSR setup registers (descriptors), the GLIU can be programmed to route selected I/O and memory regions to specific GeodeLink Devices. Any memory or I/O address that does not hit one of these regions, subtractively routes to the Diverse Device. Unlike PCI, there is no performance loss associated with being the subtractive port. Operationally, there are five bus masters within the CS5535: ATAC, ACC, DD, USBC1, and USBC2. These masters only generate requests to access main memory off the GX2. Therefore, all their GLIU requests need to be routed to the GLPCI_SB for presentation to the PCI bus. A set of GLIU P2D_BM descriptors could be used for this purpose. However, the CS5535 GLIU is uniquely modified to route all requests for the listed masters to the GLPCI_SB unconditionally. Therefore, GLIU P2D_BM settings do not 3.7.1 Introduction There are several places in the CS5535 where addresses are decoded and routed: • Physical PCI Bus: The GLPCI_SB decodes PCI bus transactions and claims them with a “DEVSEL#” as appropriate. After claiming a transaction, the GLPCI_SB converts it to a GLIU request packet. It then passes the request to the GLIU. It has no routing control or responsibility beyond this point. • GLIU: The GLIU compares the request addresses against the descriptor settings. It passes the request to the port associated with the compare hit. Each port is connected to a specific GeodeLink Device (see Section 3.1.5 "Topology" on page 52 for port assignment). There are also specific legacy addresses that receive “special” routing beyond the standard descriptor routing mechanisms. • Typical GeodeLink Device: For most GeodeLink Devices, further decoding is minimal. If a device contains only MSRs and a single native block (register group) in I/O or memory space, specific bits within the request packet can be used to easily select between the two. If a device contains more than one register group, a Local Base Address Register (LBAR) for each group is used. Like a PCI Base Address Register (BAR), an LBAR compare and hit operation is used to select the desired group. • Diverse Device: The Diverse Device has the same decoding responsibilities as a typical GeodeLink Device. Beyond this programmable LBAR decoding, it has substantial fixed decoding associated with legacy addresses. 3.7.2 PCI Bus Decoding From reset, the GLPCI_SB does not actively decode anything. However, it will subtractively decode everything. From reset, everything not positively claimed on the PCI bus is converted to a GLIU request and passed to the GLIU. Using appropriate setup registers, the GLPCI_SB can be programmed to actively decode selected I/O and memory regions. Other than actively claiming, the “convert” and “pass” operation is the same. There are also control bits in the GLPCI_MSR_CTL (MSR 51700010h) register to regulate behavior associated with legacy addresses: • Bits [12:11]: Legacy I/O Space Active Decode. These bits control the degree to which the GLPCI_SB will actively claim I/O region 0000h through 03FFh: — 00: Subtractive – Claim on fourth clock. (Default.) — 01: Slow – Claim on third clock. — 10: Medium – Claim on second clock. • Bit 13: Reject Primary IDE. If this bit is set, the GLPCI_SB will not actively decode the primary IDE addresses of: 01F0h/01F7h and 03F6h. www.national.com 60 Revision 0.8 Geode™ CS5535 Global Concepts and Features (Continued) affect packet routing from the listed masters. GLIU descriptors are only used to route requests from the GLPCI_SB and GLCP. 3.7.4 Legacy Keyboard Emulation In the CS5535, there are two USB Controllers and hence two copies of this hardware. The USB control registers are memory mapped. The memory region associated with these registers is relocatable via standard GLIU descriptor MSRs starting at an appropriate base address. The region size is 4 kB (1000h), that is, an offset range of 000h through FFFh. There are four registers called: HceControl, HceInput, HceOutput, and HceStatus. There are no USB control registers above this region. Special consideration is given to the legacy keyboard emulation control registers normally associated with the USB Controller. This “normal” association is due to the fact that “normally”, the keyboard emulation hardware is physically located with the USB hardware, even though there is no logical association between the two at the hardware level. This “normal” association is driven by industry standard device drivers that group the two register sets in the same region. The keyboard emulation registers are located at the USB base address plus 0100h. A single copy of the Keyboard Emulation Logic (KEL) hardware is located in the Diverse Device (DD) module, where it can be closely coordinated with a possible real keyboard controller in any of three locations: in either USB Controller (USBC1 or USBC2), or on the LPC bus. This leaves the problem of the control registers that are physically in the DD, but logically (from the software perspective) in the USB Controller. A descriptor type is incorporated into the CS5535 to deal with this keyboard issue. It is a variant of the standard “P2D Base Mask Descriptor” (P2D_BM) called P2D_BMK (keyboard). A P2D_BMK descriptor does additional decoding based on Address bit 8. If this bit is low, the hit directs to the USB port. If this bit is high, the hit directs to the subtractive port. There are two P2D_BMK descriptors in the CS5535 (see Section 5.1.2.2 "P2D Base Mask KEL Descriptors (GLIU_P2D_BMK[x])" on page 195). 3.7.5 GeodeLink Device Decoding Except Diverse Device Table 3-4 shows the register space map for all CS5535 devices except the Diverse Device. There are no fixed addresses associated with these devices other than the MSRs and the legacy IDE I/O addresses as detailed in Section 3.7.3 "GLIU Decoding". 3.7.6 Diverse Device Decoding Except Legacy I/O The Diverse Device “space” map except legacy I/O is shown in Table 3-5. Table 3-4. CS5535 Register Space Map Except Diverse Device Device GLPCI_SB MSR Space (Note 1) Standard GeodeLink Device MSRs plus GLPCI_SB setup. All MSRs also accessible from PCI Configuration space. Standard GeodeLink Device MSRs plus diagnostic and debug. Standard GeodeLink Device MSRs plus descriptor setup. Standard GeodeLink Device MSRs. I/O Space None. Memory Space None. GLCP GLIU ACC None. Programmable SSMIs. 16-byte codec I/F plus 48byte master interface. All trap registers removed. Generates no SSMIs. None. Programmable SSMIs. The register space can be here also. ATAC Standard GeodeLink Device MSRs plus timing parameters. Bus Master LBAR. Legacy primary addresses. 16-byte master interface. None. None. USBC1 Standard GeodeLink Device MSRs plus PCI configuration emulation. Must set PCI BAR in USB Controller. 4 kB, but less than 256 bytes used. Keyboard emulation registers to Diverse Device. 4 kB, but less than 256 bytes used. Keyboard emulation registers to Diverse Device. USBC2 Standard GeodeLink Device MSRs plus PCI configuration emulation. Must set PCI BAR in USB Controller. None. Note 1. See Section 3.8 "Standard GeodeLink Device MSRs" on page 67 for register descriptions. Revision 0.8 61 www.national.com Geode™ CS5535 Global Concepts and Features (Continued) Table 3-5. Diverse Device Space Map Except Legacy I/O Device DD MSR Space (Note 1) Standard GeodeLink Device MSRs plus: SMB LBAR, ACPI LBAR, PM LBAR, GPIO LBAR, MFGPT LBAR, NAND LBAR, KEL LBAR, KEL LBAR, IRQ Mapper LBAR, Legacy Controls, DMA Mappers, Shadow Registers, LPC Controls, and Memory Mask. NOR Flash address control. I/O Space Located by associated LBAR. Defaults disabled. 008 Bytes SMB, 016 Bytes ACPI, 064 Bytes PM Support, 256 Bytes GPIO and ICFs, 064 Bytes MFGPTs, 016 Bytes NAND Flash, and 032 Bytes IRQ Mapper. All I/O that does not hit one of the items above and does not hit a legacy address, is directed to the LPC bus. Memory Space 16-Byte KEL Host Controller register set at LBAR. Defaults disabled. NOR Flash per LBAR. All other memory accesses are directed to the LPC bus. Note 1. See Section 3.8 "Standard GeodeLink Device MSRs" on page 67 for register descriptions. 3.7.7 Legacy I/O Decoding Table 3-6 details the legacy I/O range for 000h through 4FFh. Each I/O location has a read/write (R/W) capability. Note the following abbreviations: --Yes WO RO Unknown or can not be determined. Read and Write the register at the indicated location. No shadow required. Write only. Value written can not be read back. Reads do not contain any useful information. Read only. Writes have no effect. Shw The value written to the register can not be read back via the same I/O location. Read back is accomplished via a “Shadow” register located in MSR space. Shw@ Shw$ Rec Reads of the location return a constant or meaningless value. Reads of the location return a status or some other meaningful information. Writes to the location are “recorded” and written to the LPC. Reads to the location return the recorded value. The LPC is not read. Table 3-6. Legacy I/O: 000h-4FFh I/O Addr. 000h 001h 002h 003h 004h 005h 006h 007h 008h 009h 00Ah 00Bh 00Ch 00Dh Function Slave DMA Address - Channel 0 Slave DMA Counter - Channel 0 Slave DMA Address - Channel 1 Slave DMA Counter - Channel 1 Slave DMA Address - Channel 2 Slave DMA Counter - Channel 2 Slave DMA Address - Channel 3 Slave DMA Counter - Channel 3 Slave DMA Command/Status - Channels [3:0] Slave DMA Request - Channels [3:0] Slave DMA Mask - Channels [3:0] Slave DMA Mode - Channels [3:0] Slave DMA Clear Pointer - Channels [3:0] Slave DMA Reset - Channels [3:0] Size 8-bit 8-bit 8-bit 8-bit 8-bit 8-bit 8-bit 8-bit 8-bit 8-bit 8-bit 8-bit 8-bit 8-bit R/W Yes Yes Yes Yes Yes Yes Yes Yes Shw$ WO Shw@ Shw@ WO WO Reads return value B2h. Reads return value B2h. Reads return value B2h. Reads return value B2h. Reads return value B2h. Comment 16-bit values in two transfers. 16-bit values in two transfers. 16-bit values in two transfers. 16-bit values in two transfers. 16-bit values in two transfers. 16-bit values in two transfers. 16-bit values in two transfers. 16-bit values in two transfers. www.national.com 62 Revision 0.8 Geode™ CS5535 Global Concepts and Features (Continued) Table 3-6. Legacy I/O: 000h-4FFh (Continued) I/O Addr. 00Eh 00Fh 010h-01Fh 020h 021h 022h-03Fh 040h 041h 042h 043h 044h-05Fh 060h Function Slave DMA Reset Mask - Channels [3:0] Slave DMA General Mask - Channels [3:0] No Specific Usage PIC Master - Command/Status PIC Master - Command/Status No Specific Usage PIT – System Timer PIT – Refresh Timer PIT – Speaker Timer PIT – Control No Specific Usage Keyboard/Mouse - Data Port Size 8-bit 8-bit --8-bit 8-bit --8-bit 8-bit 8-bit 8-bit --8-bit R/W Shw@ Shw@ --Shw$ Shw$ --Shw$ Shw$ Shw$ Shw$ --Yes If KEL Memory Offset 100h[0] = 1 (EmulationEnable bit). If MSR 5140001Fh[0] = 1 (SNOOP bit) and KEL Memory Offset 100h[0] = 0 (EmulationEnable bit). 061h 062h-063h 064h Port B Control No Specific Usage Keyboard/Mouse - Command/ Status 8-bit --8-bit Yes --Yes If KEL Memory Offset 100h[0] = 1 (EmulationEnable bit). If MSR 5140001Fh[0] = 1 (SNOOP bit) and KEL Memory Offset 100h[0] = 0 (EmulationEnable bit). 065h-06Fh 070h-071h 072h-073h 074h-077h 078h-07Fh 080h 081h 082h 083h 084h-086h 087h 088h 089h 08Ah 08B No Specific Usage RTC RAM Address/Data Port High RTC RAM Address/Data Port No Specific Usage No Specific Usage Post Code Display DMA Channel 2 Low Page DMA Channel 3 Low Page DMA Channel 1 Low Page No Specific Usage DMA Channel 0 Low Page No Specific Usage DMA Channel 6 Low Page DMA Channel 7 Low Page DMA Channel 5 Low Page 8-bit 8-bit 8-bit 8-bit Rec Rec Rec Rec Write LPC and DMA. Read only DMA. Upper addr bits [23:16]. Write LPC and DMA. Read only DMA. Write LPC and DMA. Read only DMA. Upper addr bits [23:16]. Write LPC and DMA. Read only DMA. --8-bit 8-bit ----8-bit 8-bit --Yes Yes ----Rec Rec Write LPC and DMA. Read only DMA. Upper addr bits [23:16]. Write LPC and DMA. Read only DMA. Options per MSR 51400014h[0]. (Note 1) Options per MSR 51400014h[1]. Comment Reads return value B2h. Reads return value B2h. Revision 0.8 63 www.national.com Geode™ CS5535 Global Concepts and Features (Continued) Table 3-6. Legacy I/O: 000h-4FFh (Continued) I/O Addr. Function Size 8-bit 8-bit --8-bit --8-bit 8-bit 8-bit 8-bit 8-bit 8-bit 8-bit 8-bit 8-bit 8-bit 8-bit 8-bit 8-bit 8-bit 8-bit 8-bit 8-bit 8-bit 8-bit 8-bit 8-bit 8-bit 8-bit 8-bit 8-bit 8-bit 8-bit 8-bit 8-bit 8-bit 8-bit 8-bit 8-bit R/W Rec Rec --Yes --Shw$ Shw$ --Yes --Yes --Yes Yes --Yes Yes --Yes --Yes --Shw$ --WO --Yes --Shw@ --WO --WO --WO --Shw@ --16-bit values in two transfers. 16-bit values in two transfers. 16-bit values in two transfers. 16-bit values in two transfers. 16-bit values in two transfers. 16-bit values in two transfers. 16-bit values in two transfers. 16-bit values in two transfers. If kel_porta_en is enabled, then access Port A; else access LPC. Comment Write LPC and DMA. Read only DMA. Upper addr bits [23:16] ment at 080h. See com- 08Ch-08Eh No Specific Usage 08Fh 090h-091h 092h 093h-09Fh 0A0h 0A1h DMA C4 Low Page No Specific Usage Port A No Specific Usage PIC Slave - Command/Status PIC Slave - Command/Status 0A2h-0BFh No Specific Usage 0C0h 0C1h 0C2h 0C3h 0C4h 0C6h 0C7h 0C8h 0CAh 0CBh 0CCh 0CDh 0CEh 0CFh 0D0h 0D1h 0D2h 0D3h 0D4h 0D5h 0D6h 0D7h 0D8h 0D9h 0DAh 0DBh 0DCh 0DDh 0DEh 0DFh Master DMA Address - Channel 4 No Specific Usage Master DMA Counter - Channel 4 No Specific Usage Master DMA Address - Channel 5 Master DMA Counter - Channel 5 No Specific Usage Master DMA Address - Channel 6 Master DMA Counter - Channel 6 No Specific Usage Master DMA Address - Channel 7 No Specific Usage Master DMA Counter - Channel 7 No Specific Usage Master DMA Command/Status - Channels [7:4] No Specific Usage Master DMA Request - Channels [7:4] No Specific Usage Master DMA Mask - Channels [7:4] No Specific Usage Master DMA Mode - Channels [7:4] No Specific Usage Master DMA Clear Pointer - Channels [7:4] No Specific Usage Master DMA Reset - Channels [7:4] No Specific Usage Master DMA Reset Mask - Channels [7:4] No Specific Usage Master DMA General Mask - Channels [7:4] No Specific Usage www.national.com 64 Revision 0.8 Geode™ CS5535 Global Concepts and Features (Continued) Table 3-6. Legacy I/O: 000h-4FFh (Continued) I/O Addr. Function Size --8-bit R/W ----MSR bit enables/disables into I/O space.(UART1 MSR 51400014h[18:16], UART2 MSR 51400014h[22:20]). Defaults to LPC. Comment 0E0h-2E7h No Specific Usage 2E8h-2EFh UART/IR - COM4 2F0h-2F7h 2F8h-2FFh No Specific Usage UART/IR - COM2 --8-bit ----MSR bit enables/disables into I/O space.(UART1 MSR 51400014h[18:16], UART2 MSR 51400014h[22:20]). Defaults to LPC. 300h-36Fh 370h 371h 372h 373h 374h 375h 376h 377h 378h-3E7h No Specific Usage Floppy Status R A Floppy Status R B Floppy Digital Out No Specific Usage Floppy Cntrl Status Floppy Data No Specific Usage Floppy Conf Reg No Specific Usage --8-bit 8-bit 8-bit 8-bit 8-bit 8-bit 8-bit 8-bit --8-bit --RO RO Shw@ --RO Yes --Shw$ ----MSR bit enables/disables into I/O space.(UART1 MSR 51400014h[18:16], UART2 MSR 51400014h[22:20]). Defaults to LPC. First Floppy. First Floppy. First Floppy. Second Floppy. Second Floppy. Second Floppy. Second Floppy. Second Floppy. Second Floppy. 3E8h-3EFh UART/IR - COM3 3F0h 3F1h 3F2h 3F3h 3F4h 3F5h 3F6h 3F7h 3F8h-3FFh Floppy Status R A Floppy Status R B Floppy Digital Out No Specific Usage Floppy Cntrl Status Floppy Data No Specific Usage Floppy Conf Reg UART/IR - COM1 8-bit 8-bit 8-bit 8-bit 8-bit 8-bit 8-bit 8-bit 8-bit RO RO Shw@ --RO Yes --Shw$ --- First Floppy. First Floppy. First Floppy. MSR bit enables/disables into I/O space.(UART1 MSR 51400014h[18:16], UART2 MSR 51400014h[22:20]). Defaults to LPC. 400h-47Fh 480h 481h 482h 483h 484h-486h No Specific Usage No Specific Usage DMA Channel 2 High Page DMA Channel 3 High Page DMA Channel 1 High Page No Specific Usage --8-bit 8-bit --WO Rec Write LPC and DMA. Read only DMA. Upper addr bits [31:24]. Write LPC and DMA. Read only DMA. 8-bit WO Write LPC and DMA. Read only DMA. Revision 0.8 65 www.national.com Geode™ CS5535 Global Concepts and Features (Continued) Table 3-6. Legacy I/O: 000h-4FFh (Continued) I/O Addr. 487h 488h 489h 48Ah 48Bh Function DMA Channel 0 High Page No Specific Usage DMA Channel 6 High Page DMA Channel 7 High Page DMA Channel 5 High Page 8-bit 8-bit --8-bit 8-bit --WO Rec --Yes Yes --IRQ0-IRQ 7. IRQ8-IRQ15. Write LPC and DMA. Read only DMA. Upper addr bits [31:24]. Write LPC and DMA. Read only DMA. Size 8-bit 8-bit 8-bit R/W Rec WO Rec Comment Upper addr bits [31:24]. Write LPC and DMA. Read only DMA. Write LPC and DMA. Read only DMA. Upper addr bits [31:24]. Write LPC and DMA. Read only DMA. 48Ch-48Eh No Specific Usage 48Fh 490h-4CFh 4D0h 4D1h DMA Channel 4 High Page No Specific Usage PIC Level/Edge PIC Level/Edge 4D2h-4FFh No Specific Usage Note 1. The Diverse Device snoops writes to this port and maintains the MSB as NMI enable. When low, NMI is enabled. When high, NMI is disabled. This bit defaults high. Reads of this port return bits [6:0] from the on-chip or off-chip target, while bit 7 is returned from the “maintained” value. www.national.com 66 Revision 0.8 Geode™ CS5535 Global Concepts and Features (Continued) 3.8 STANDARD GEODELINK DEVICE MSRS 3.8.2 MSR Address 1: Master Configuration The defined fields in the GeodeLink Device Master Configuration MSR (GLD_MSR_CONF) vary depending upon the device. Refer to the appropriate GeodeLink Device register chapter starting in Section 5.0 "Register Descriptions" on page 184. 3.8.3 MSR Address 2: SMI Control Each GeodeLink Device within the CS5535 incorporates System Management Interrupts (SMIs). These SMIs are controlled via the Standard GLD_MSR_SMI located at MSR Address 2 within each GLD (see Table 3-8). The lower 32 bits of this register contain Enable (EN) bits, while the upper 32 bits contain Flag (FLAG) bits. The EN and FLAG bits are organized in pairs of (n, n+32). For example: (0,32); (1,33); (2,34); etc. The GLD_MSR_SMI is used to control and report events. An event is any action or occurrence within the GeodeLink Device requiring processor attention. The FLAG bits are status bits that record events. The EN bits enable events to be recorded. An EN bit must be 1 for an event to be recorded (with the exception of the GLUI and the GLCP the EN bit must be 0 for an event to be recorded). When an event is recorded, the associated FLAG bit is set to a 1. SMI events are of two types: Asynchronous SMI (ASMI) and Synchronous SMI (SSMI). All GeodeLink Devices have the following Standard MSRs and are always located at the addresses indicated below from the base address given in Table 3-2 "CS5535 MSR Addresses from GX2 Processor" on page 54: • MSR Address 0: GeodeLink Device Capabilities (GLD_MSR_CAP) • MSR Address 1: GeodeLink Device Master Configuration (and GLA Prefetch) (GLD_MSR_CONFIG) • MSR Address 2: GeodeLink Device System Management Interrupt Control (GLD_MSR_SMI) • MSR Address 3: GeodeLink Device Error Control (GLD_MSR_ERROR) • MSR Address 4: GeodeLink Device Power Management (GLD_MSR_PM) • MSR Address 5: GeodeLink Device Diagnostic MSR (GLD_MSR_DIAG) (This register is reserved for internal use by National and should not be written to.) 3.8.1 MSR Address 0: Capabilities The Capabilities MSR (GLD_MSR_CAP) is read only and provides identification information as illustrated Table 3-7. Table 3-7. GLD_MSR_CAP Bit Descriptions Bit 63:24 23:8 7:0 Name RSVD DEV_ID REV_ID Description Reserved. Reads as 0. Device ID. Identifies the module. Revision ID. Identifies the module revision. Table 3-8. Standard GLD_MSR_SMI Format 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 SMI_FLAG SMI_FLAG SMI_FLAG SMI_FLAG SMI_FLAG SMI_FLAG SMI_FLAG SMI_FLAG SMI_FLAG SMI_FLAG SMI_FLAG SMI_FLAG SMI_FLAG SMI_FLAG SMI_FLAG SMI_FLAG SMI_FLAG SMI_FLAG SMI_FLAG SMI_FLAG SMI_FLAG SMI_FLAG SMI_FLAG SMI_FLAG SMI_FLAG SMI_FLAG SMI_FLAG SMI_FLAG SMI_FLAG SMI_FLAG SMI_FLAG 1 SMI_EN SMI_FLAG 0 SMI_EN 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 SMI_EN SMI_EN SMI_EN SMI_EN SMI_EN SMI_EN SMI_EN SMI_EN SMI_EN SMI_EN SMI_EN SMI_EN SMI_EN SMI_EN SMI_EN SMI_EN SMI_EN SMI_EN SMI_EN SMI_EN SMI_EN SMI_EN 9 SMI_EN 8 SMI_EN 7 SMI_EN 6 SMI_EN 5 SMI_EN 4 SMI_EN 3 SMI_EN 2 SMI_EN Revision 0.8 67 www.national.com Geode™ CS5535 Global Concepts and Features (Continued) 3.8.3.1 ASMI ASMIs fall into two classes: direct and in-direct. A behavioral model for a direct class ASMI is illustrated in Figure 3-7. In the model, an event is represented as a short duration (much less than 1 µs) positive pulse that is associated with a given Enable/Event pair n. The Enable/Event pair is represented by a pair of simple “D” flip/flops that can be set (write 1 to Q) or cleared (write 0 to Q) by software. The EN bit can be written high or low, but the FLAG bit can only be cleared. By GeodeLink architecture convention, writing a 1 to a FLAG bit clears it; writing a 0 has no effect. If the EN bit is 1, then the 0-to-1 transition of the event pulse clocks a 1 into the SMI FLAG flip/flop. All of the ASMI bits are ORed together to form the GLD ASMI. The GLD ASMI is routed through the GLIU where it is ORed with all other device ASMIs to form the CS5535 ASMI. SMI MSR A behavioral model for a in-direct class ASMI is illustrated in Figure 3-8 on page 69. An event is represented as before, but it is first applied to some type of Native Event register. Generally, this is an IRQ status register of some kind that records multiple IRQ sources. Alternatively, there might be multiple independent Native Event registers that are at some point ORed together to form a single Native Event Summary Signal (NESS). In general, a NESS can also be an IRQ signal routed to the PIC subsystem. Hence, depending on operational needs, a NESS can be an IRQ or ASMI. The important point is that the NESS 0-to-1 transition clocks a 1 into the SMI FLAG flip/flop. The event only indirectly causes the SMI FLAG bit to be set. Further note that the Event[X] and ASMI[n+1] are independently clearable. ASMI[n+1] can be cleared, while leaving NESS at a 1 state. After such clearing action with NESS high, ASMI[n+1] will not set again. Alternatively, Event[X] could be cleared without effecting the state of ASMI[n+1]. Lastly, it is possible to clear and set ASMI[n+1] while NESS remains at a constant high state. Consider the following sequence: 1) Other ASMI FLAG Bits GLD ASMI 2) 3) 4) ASMI [n+1] 5) 6) Assume EN[n] is high. Event[X] occurs and NESS makes a 0-to-1 transition that sets ASMI[n+1]. Software clears ASMI[n+1] by writing a 1 to it. NESS remains high because Event[X] has not been cleared. EN[n] is cleared to 0. EN[n] is set to a 1 and causes ASMI[n+1] to be set again. Step 5 could also be performed between steps 2 and 3 instead, yielding the same result. The sequence of setting EN[n] to 0 followed by setting EN[n] to 1 is called an Enable Toggle. + D Q CI Clear_By_Software FLAG Bit[n+1] Note: Event [X] Set_By_Software The previous sequence is used when multiple events X, Y, Z, etc. all OR to form a single NESS. The events are sharing a single NESS. Under this arrangement, the following Virtual System Architecture (VSA) software sequence would be typical: 1) Assume EN[n] is high. Event[X] fires and causes a CS5535 ASMI. VSA searches the GX2/CS5535 system looking for the ASMI source and finds ASMI[n+1]. VSA clears EN[n] to 0 and begins to perform the actions associated with Event[X]. While the “actions” are being taken, Event[Y] fires. VSA “actions” ASMI[n+1]. include clearing Event[X] and D Q 2) 3) Clear_By_Software 4) 5) 6) 7) CI EN Bit[n] NESS remains high because Event[Y] has fired. Figure 3-7. Direct ASMI Behavioral Model www.national.com 68 Revision 0.8 Geode™ CS5535 Global Concepts and Features (Continued) 8) 9) VSA sets EN[n] high. This action sets ASMI[n+1] high again and causes another CS5535 ASMI. VSA begins to return to the process interrupted by the original ASMI, but notes SMI into the processor is still asserted and returns to step 3. blocks access to the target register. The actual register write and/or read operation is not performed. Generally, only write operations are trapped, but there are cases of trapping writes and reads. The CS5535 does not support SSMIs, however, the CS5535 supports a mechanism called “Apparent SSMI” using ASMIs. (Hereafter “Apparent SSMI” is referred to as “SSMI”.) The CS5535 insures that the ASMI is taken on the I/O instruction boundary. The ASMI reaches the CPU before a target ready is signaled on the PCI bus. This action creates an SSMI because the I/O instruction will not complete before ASMI reaches the CPU. VSA software then examines the GLPCI_SB GLD_SMI_MSR to determine if an SSMI has occurred from an I/O trap. 10) If there was no Event[Y] at any point above, return to the interrupted process. Note: Step 5 above could occur at any time between step 2 and step 9, or the Event[Y] could come after step 10. Regardless, the same VSA approach is used in order not to miss any events. 3.8.3.2 Apparent SSMI An SSMI event is associated with an I/O space access to a specific address or range of addresses. If SSMIs are enabled for the given address, then the hardware traps or Native Event Register SMI MSR Other FLAG Bits OR ALL Native Event Summary Signal (NESS) Other ASMI FLAG Bits OR ALL GLD ASMI + D Q Event [X] + D Q ASMI [n+1] CI Clear_By_Software FLAG Bit[x] CI Clear_By_Software FLAG Bit[n+1] Event [X] Set_By_Software Set_By_Software D Q D Q CI Clear_By_Software EN Bit[m] CI Clear_By_Software EN Bit[n] Figure 3-8. In-Direct ASMI Behavioral Model Revision 0.8 69 www.national.com Geode™ CS5535 Global Concepts and Features (Continued) SSMIs are primarily used for hardware emulation and extension. From the perspective of the code on which the trap occurred, everything is normal and done in hardware. However, VSA code generally performs a number of operations to achieve the desired result. This can include returning an appropriate read value to the trapped software. The GLIU is often used to implement SSMI traps. Any I/O descriptor can be used for this purpose by setting the Destination ID to 0. On a descriptor hit, the GLIU traps the access and sets the SSMI bit in the response packet. 3.8.3.3 ASMI/SSMI Summary Table 3-9 provides a register summary for the Standard GLD_SMI_MSRs. Table 3-9. GLD_MSR_SMIs Summary Port #, Device Port 0, GLIU (Note 1) FLAG Bit 35 34 33 32 Port 1, GLPCI_SB 22 21 20 19 18 17 16 Port 2, USBC2 Port 3, ATAC Port 4, DD (DIVIL) 33 32 33 1 47 46 45 44 43 41 40 39 38 37 36 35 34 33 32 Port 5, ACC Port 6, USBC1 Port 7, GLCP (Note 1) Note 1. 32 33 32 17 16 EN Bit 3 2 1 0 6 5 4 3 2 1 0 1 0 1 0 15 14 13 12 11 9 8 7 6 5 4 3 2 1 0 0 1 0 1 0 SMI Type ASMI ASMI ASMI SSMI ASMI ASMI ASMI ASMI ASMI ASMI ASMI ASMI ASMI ASMI SSMI SSMI SSMI ASMI SSMI SSMI SSMI SSMI ASMI ASMI ASMI ASMI ASMI ASMI ASMI ASMI SSMI ASMI ASMI ASMI ASMI Description Statistics Counter 2 Event Statistics Counter 1 Event Statistics Counter 0 Event Descriptor Trap and Illegal Accesses Target Abort Signaled Parity Error System Error EXECP Received SSMI Received Target Abort Received Master Abort Received INT by the USB (see PIC for actual source) ASMI for the USB (see USB for actual source) IRQ for IDE (see PIC for actual source) IDE PIO PMC PM1_CNT PMC PM2_CNT KEL A20 Keyboard 8237 DMA Controller access during legacy DMA LPC access during legacy DMA UART 2 access during legacy DMA UART 1 access during legacy DMA KEL INIT Port A KEL A20 Port A KEL INIT Keyboard PMC Event (see PMC for actual source) Extended PIC Mapper (see PIC for actual source) KEL Emulation Event Shutdown Special Cycle Halt Special Cycle IRQ from ACC INT by the USB (see PIC for actual source) ASMI for the USB (see USB for actual source) Debug event Convert CS5535 Global GLIU_Error to ASMI For this device, the listed events are enabled when the EN bit is low. For all other devices, events are enabled when the associated EN bit is high. www.national.com 70 Revision 0.8 Geode™ CS5535 Global Concepts and Features (Continued) 3.8.4 MSR Address 3: Error Control Each GeodeLink Device within the CS5535 can generate errors. Furthermore, these errors are controlled via the Standard GeodeLink Device Error MSR (GLD_MSR_ERROR) located at MSR Address 3 within each GLD. The register is organized just like GLD_MSR_SMI, that is, the lower 32 bits contain Enable (EN) bits, while the upper 32 bits contain Flag (FLAG) bits (see Table 3-8 on page 67). The EN and FLAG bits are organized in pairs of (n, n+32). For example: (0,32); (1,33); (2,34); etc. The Error MSR is used to control and report errors. The SMI concepts of direct asynchronous and synchronous carry over into similar error concepts. However, there is no concept of an in-direct error. At each GeodeLink Device, all of the Error FLAG bits are ORed together to form the Error signal. The Error is routed through the GLIU where it is ORed with all other device Errors to form the CS5535 Error signal. This signal is routed to the GLCP for debug purposes. Only the GLIU is capable of generating synchronous errors that utilize the Exception (EXCEP) bit of the associated response packet. All other CS5535 GeodeLink Devices only generate asynchronous errors. 3.8.5 MSR Address 4: Power Management All the power management MSRs (GLD_MSR_PM) conform to the model illustrated in Table 3-10. The power and I/O mode functions are completely independent other than sharing the same MSR. The GLD_MSR_PM fields have the following definitions: • Power Mode for Clock Domains: — 00: Disable clock gating. Clocks are always on. — 01: Enable active hardware clock gating. Clock goes off whenever this module’s circuits are not busy. — 10: Reserved. — 11: Reserved. • I/O Mode (Applies only to GLPCI_SB and ATAC modules, see Table 3-11 and Table 3-12 for a list of controlled signals): — 00: No gating of I/O cells during a Sleep sequence (Default). — 01: During a power management Sleep sequence, force inputs to their non-asserted state when PM_IN_SLPCTL is enabled. — 10: During a power management Sleep sequence, force inputs to their non-asserted state when PM_IN_SLPCTL is enabled, and park (force) outputs low when PM_OUT_SLPCTL is enabled. — 11: Immediately and unconditionally, force inputs to their not asserted state, and park (force) outputs low. The PMC controls when the PCI/IDE inputs and outputs (listed in Table 3-11 and Table 3-12) are asserted and deasserted. The PM_OUT_SLPCTL (PMS I/O Offset 0Ch) and PM_IN_SLPCTL (PMS I/O Offset 20h) registers provide the global control of the PCI/IDE I/Os. The IO_MODE bits individually control PCI (GLPCI_SB GLD_MSR_PM Table 3-10. MSR Power Management Model 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 IO IO IO IO IO IO IO IO MODE MODE MODE MODE MODE MODE MODE MODE A B C D E F G H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PMODE15 PMODE14 PMODE13 PMODE12 PMODE11 PMODE10 PMODE9 PMODE8 PMODE7 PMODE6 PMODE5 9 PMODE4 RSVD 8 7 PMODE3 6 5 PMODE2 4 3 PMODE1 2 1 PMODE0 0 Table 3-11. Sleep Driven PCI Signals Signal C/BE[3:0]# DEVSEL# FRAME# TRDY# IRDY# STOP# Ball No. R6, T9, U11, U14 R11 U9 T10 R10 T11 Direction Pad driven to 0. Internal logic sees logic 1. Pad driven to 0. Internal logic sees logic 1. Pad driven to 0. Internal logic sees logic 1. Pad driven to 0. Internal logic sees logic 1. Pad driven to 0. Internal logic sees logic 1. Pad driven to 0. Internal logic sees logic 1. Table 3-11. Sleep Driven PCI Signals Signal PAR REQ# GNT# Ball No. U10 T1 R1 Direction Pad driven to 0. Internal logic sees logic 1. Pad driven to 0. Pad TRI-STATE. Internal logic sees logic 0. Revision 0.8 71 www.national.com Geode™ CS5535 Global Concepts and Features (Continued) Table 3-11. Sleep Driven PCI Signals Signal AD[31:0] Ball No. U1, T3, U3, R4, T4, R5, T5, U5, T6, U6, R7, T7, U7, R8, T8, U8, R12, T12, U12, R13, T13, U13, R14, T14, P15, R15, T15, P16, T16, R16, T17, R17 Direction Pad driven to 0. from which the complete power management solution depends on. Basically two methods are supported to manage power during periods of inactivity. The first method, called activity based power management allows the hardware in the Geode I/O companion to monitor activity to certain devices in the system and if a period of inactivity occurs take some form of power conservation action. This method does not require OS support because this support is handled by SMM software. Simple monitoring of external activity is imperfect as well as inefficient. The second method, called passive power management, requires the OS to take an active role in managing power. National supports two application programming interfaces (APIs) to enable power management by the OS: Advanced Power Management (APM) and Advanced Configuration and Power Interface (ACPI). These two methods can be used independent of one another or they can be used together. The extent to which these resources are employed depends on the application and the discretion of the system designer. The GX2 processor and Geode CS5535 I/O companion devices contain advanced power management features for reducing the power consumption of the processor, I/O companion and other devices in the system. 3.9.1 Power Domains In order to support power management in periods of inactivity as well as “off” conditions, the CS5535 is divided into three power domains: • Working Domain - Consists of VCORE and VIO • Standby Domain - Consists of VCORE_VSB and VIO_VSB • RTC Domain - Consists of VBAT When the system is in an operational mode all three of the domains are on. In general the power management techniques used while operating produce power savings without user awareness. The performance and usability of the system is unaffected. When the system is “off” only the standby domain is powered. If desired, the operational design can allow returning the system to the operational point when the system was last “on”. This “instant on” feature is a requirement for many battery powered systems. If the system has been removed from all power sources the Real Time Clock (RTC) can be kept operating with a small button battery. All sections of CS5535 use the Working domain except: Standby Domain • GPIO[31:24] and associated registers. • GPIO Input Conditioning Functions 6 and 7. • GPIO Power Management Events (PMEs) 6 and 7. • MFGPT[7:6]. Table 3-12. Sleep Driven IDE Signals Signal IDE_CS[1:0]# IDE_IOR0# IDE_IOW0# IDE_AD[2:0] IDE_RESET# IDE_RDY0 IDE_DREQ0 IDE_DACK0# IDE_DATA[15:0] Ball No. C10, B10 B13 C13 B11, A12, A11 F15 A13 A14 C12 C14, B15, B16, A17, C17, D16, D17, E17, E16, E15, D15, B17, C16, C15, A15, B14 Direction Pad driven to 0. Pad driven to 0. Pad driven to 0. Pad driven to 0. Pad driven to 0. Pad TRI-STATE. Internal logic sees logic 0. Pad TRI-STATE. Internal logic sees logic 0. Pad driven to 0. Pad driven to 0. 3.9 POWER MANAGEMENT Typically the three greatest power consumers in a computing device are the display, the hard drive (if it has one) and the system electronics. The CPU usually consumes the most power of all the system electronic components. Managing power for the first two is relatively straightforward in the sense that they are simply turned on or off. Managing CPU power is more difficult since effective use clock control technology requires effective detection of inactivity, both at a system level and at a code processing level. Power consumption in a GX2 or other Geode processor based system is managed with the use of both hardware and software. The complete hardware solution is provided for only when the GX2 processor is combined with the CS5535 Geode I/O companion. The processor power consumption is managed primarily through a sophisticated clock stop management technology. The processor also provides the hardware enablers www.national.com 72 Revision 0.8 Geode™ CS5535 Global Concepts and Features (Continued) • Power Management Controller (PMC) Standby Controller and associated I/O consisting of: WORKING, WORK_AUX, and RESET_OUT. • PMC Standby registers starting at PMS I/O Offset 30h. See Table 5-68 "PM Support Registers Summary" on page 478. RTC domain • Real Time Clock 3.9.2 ACPI Power Management ACPI power management is a standardized method to manage power. An overview of the standard is presented here. See Section 4.17 "Power Management Control" on page 159 for a more complete discussion of ACPI support in the CS5535. See ACPI specification v2.0 for complete details on ACPI. A GX2/CS5535 system solution can fully support all the requirements in the ACPI specification. ACPI defines power states from a system perspective down to a device perspective. There are four global system states: G0 through G3. As a subset of the Global system states G0-G2 there are six Sleep states: S0 through S5. Within the sleep states S0-S1 there are five CPU states: C0-C3 and CT, and three Device states: D0-D2. In a GX2/CS5535 system design, the optional Sleep state S2, and the CPU states C3 and CT (CPU Throttling) are not supported. See Table 4-34 "Supported ACPI Power Management States" on page 159“. Table 4-34 shows how the ACPI power states relate to each other. The table also shows the condition of the power domains and the logic within those domains with respect to the ACPI power states. 3.9.3 APM Power Management Some systems rely solely on an APM (Advanced Power Management) driver for enabling the operating system to power-manage the CPU. APM provides several services which enhance the system power management. It is a reasonable approach to power management but APM has some limitations: • APM is an OS-specific driver, and may not be available for some operating systems. • Application support is inconsistent. Some applications in foreground may prevent Idle calls. • APM does not help with Suspend determination or peripheral power management. 3.10 COMPONENT REVISION ID The revision ID number of the CS5535 may be read in any of the following places. All return the same value: 1) 2) 3) GLCP_CHIP_REV_ID register: MSR 51700017h[7:0]. PCI Configuration Space Device Revision ID: PCI Index 08h[15:0]. TAP Controller Revision register: Instruction 8FFFFAh[7:0]. The revision is an 8-bit value. Bits [7:4] indicate major revisions while bits [3:0] indicate minor revisions. For example: 0x11 0x12 0x21 A1 A2 B1 Value assigned to first manufactured silicon of any new product. Minor update to first silicon. Major change to first silicon. For listing of updates, refer to the document entitled Geode CS5535 I/O Companion Device Errata. Revision 0.8 73 www.national.com Geode™ CS5535 4.0 Module Functional Descriptions • Universal Serial Bus 2 Controller with Ports 2-1 and 2-2 • Audio Codec 97 (AC97) Controller • Diverse Device The Low Voltage Detect (LVD) circuit is not a GeodeLink Device (GLD), but is connected to the PMC for voltage monitoring support. This section provides a functional description of each module. Geode™ GX2 Interface PCI GeodeLink™ Interface Unit (GLIU) 33 or 66 MHz GeodeLink™ PCI South Bridge (GLPCI_SB) The modules that make up the Geode CS5535 (shown in gray in Figure 4-1) are: • GeodeLink Interface Unit • GeodeLink PCI South Bridge • GeodeLink Control Processor • ATA-5 Controller (IDE Controller multiplexed with Flash Interface) • Universal Serial Bus 1 Controller with Ports 1-1 and 1-2 Test/Reset Interface External USB Ports 1-1 & 1-2 External USB Ports 2-1 & 2-2 External Audio GeodeLink™ Control Processor (GLCP) USB Controller #1 (USBC1) USB Controller #2 (USBC2) AC97 Controller (ACC) Diverse Integration Logic (DIVIL) 82xx PC Legacy UART (2) & IR (1) SMB Controller Flash Interface LPC Port GPIO Power Mgmnt MFGP Timers External I/O Revision 0.8 External IDE/Flash ATA-5 Controller (ATAC) System Power Voltages Low Voltage Detect (LVD) Power Good for Power On Reset (POR) RTC & CMOS RAM Diverse Device (DD) Figure 4-1. Module Block Diagram www.national.com 74 Geode™ CS5535 4.1 GEODELINK INTERFACE UNIT space. The full 64-bit data space is always read or written when accessed. 4.1.1 GLIU Port Connections Table 4-1 shows the GeodeLink Devices connected to each of the seven GLIU ports on CS5535. Many traditional architectures use buses to connect modules together, usually requiring unique addressing for each register in every module. This requires that some kind of house-keeping be done as new modules are designed and new devices are created from the module set. Module select signals can be used to create the unique addresses, but that can get cumbersome and it requires that the module selects be sourced from some centralized location. To alleviate this issue, National developed an internal bus architecture called GeodeLink. The GeodeLink architecture connects the internal modules of a device using the data channels provided by GeodeLink Interface Units (GLIUs). Using GLIUs, all internal module port addresses are derived from the distinct port that the module is connected to. In this way, a module’s Model Specific Registers (MSRs) do not have unique addresses until a device is defined. Also, as defined by the GeodeLink architecture, a module’s port address depends on the location of the module sourcing the cycle, or source module. The CS5535 incorporates one GLIU into its device architecture. Except for the configuration registers that are required for x86 compatibility, all internal registers are accessed through a Model Specific Register (MSR) set. MSRs have a 32-bit address space and a 64-bit data Table 4-1. GLIU Port Connections Port Number 1 2 3 4 5 6 7 Device GeodeLink PCI South Bridge (GLPCI_SB) USB Controller #2 (USBC2) ATA-5 Controller (ATAC) Diverse Device (DD) AC97 Audio Controller (ACC) USB Controller #1 (USBC1) GeodeLink Control Processor (GLCP) 4.1.2 Descriptor Summary Table 4-2 shows the descriptors reserved for each GeodeLink Device. Table 4-2. GLIU Descriptors Reserved for GeodeLink Devices Device USBC1 USBC2 ATAC Descriptor Type P2D_BMK P2D_BMK IOD_BM IOD_BM IOD_SC DD IOD_BM IOD_BM IOD_SC IOD_SC IOD_SC IOD_SC ACC P2D_BM IOD_BM GLPCI_SB Spares P2D_BM IOD_BM # of Descriptors 1 1 1 1 1 3 1 1 1 3 1 1 1 1 2 Usage Do not hit on keyboard emulation registers. Do not hit on keyboard emulation registers. For IDE master registers. Defaults to 1Fxh. Defaults to 3F6h. COM ports legacy power management. For secondary IDE trapping to 17xh. For secondary IDE trapping to 376h. Keyboard legacy power management. LPC ports legacy power management. Floppy legacy power management. For memory space registers. For I/O space registers. For master requests to GX2 GLPCI. Provides the possibility to virtualize NAND Flash accesses when the IDE/Flash shared pins are in the ‘IDE Position’. For the ‘Flash Position’, already dedicated IDE descriptors can be used to virtualize. IOD_BM IOD_SC P2D_BM 1 1 1 Revision 0.8 75 www.national.com Geode™ CS5535 4.2 GEODELINK PCI SOUTH BRIDGE • Programmable IDSEL selection. • Support active decoding for Legacy I/O space 000h to 3FFh and DMA High Page 480h to 48Fh. • Support subtractive decode for memory and I/O space. • Special performance enhancements for fast IDE PIO data transfers. The GLPCI_SB module is composed of the following major blocks: • GeodeLink Interface The GeodeLink PCI Bus South Bridge (GLPCI_SB) provides a PCI interface for GeodeLink Device based designs. Its three major functions are: 1) 2) 3) Acting as a PCI slave and transforming PCI transactions to GLIU transactions as a GLIU master. Acting as a GLIU slave and transforming GLIU transactions to PCI bus transactions as a PCI master. Providing a CPU serial interface that conveys system information such as interrupts, SSMI, ASMI, etc. Features include: • PCI v2.2 compliance. Optional signals PERR#, SERR#, LOCK#, and CLKRUN are not implemented. • 32-bit, 66 MHz PCI bus operation and 64-bit, 66 MHz GeodeLink Device operation. • Target support for fast back-to-back transactions. • Zero wait state operation within a PCI burst. • MSR access mailbox in PCI configuration space. • Capable of handling in-bound transactions after RESET_OUT# + 2 clock cycles. • Dynamic clock stop/start support for GeodeLink and PCI clock domains via power management features. • FIFO/Synchronization • Transaction Forwarding • PCI Bus Interface • CPU Interface Serial (CIS) The GLIU and PCI bus interfaces provide adaptation to the respective buses. The Transaction Forwarding block provides bridging logic. The CIS block provides serial output to the CPU for any change in SSMI and the selected sideband signals. Little endian byte ordering is used on all signal buses. Figure 4-2 is a block diagram of the GLPCI_SB module. GX2 CIS REQ# / GNT# PCI Bus PCI Bus Interface MSR Transaction Forwarding FIFOs/Synchronization CIS Side-band signals GeodeLink Interface Request Data Request Figure 4-2. GLPCI_SB Block Diagram www.national.com 76 Revision 0.8 Geode™ CS5535 GLPCI_SB Functional Description (Continued) 4.2.1 GeodeLink Interface The GeodeLink Interface block provides a thin protocol conversion layer between the transaction forwarding module and the GLIU. It is responsible for multiplexing in-bound write request data with out-bound read response data on the single GLIU data out bus. 4.2.2 FIFOs/Synchronization The FIFO block consists of a collection of in-bound and out-bound FIFOs. Each FIFO provides simple, synchronous interfaces to the reader and to the writer. The FIFO block also includes synchronization logic for a few non-FIFO related signals and clock gating logic. 4.2.3 Transaction Forwarding The Transaction Forwarding block receives, processes, and forwards transaction requests and responses between the GeodeLink Interface and PCI Bus Interface blocks. It implements the transaction ordering rules. It performs write/read prefetching as needed. It also performs the necessary translation between GLIU and PCI commands. The Transaction Forwarding block also handles the conversion between 64-bit GLIU data paths and 32-bit PCI data paths. Out-bound transactions are handled in a strongly ordered fashion. All out-bound memory writes are posted. The SEND_RESPONSE flag is never expected to be set in a memory write and is ignored. Any queued out-bound requests are flushed prior to handling an in-bound read request. All in-bound memory writes are posted. South bridge master out-bound read request data can pass in-bound writes. Thus, a pending out-bound read request need not be deferred while posted in-bound write data is waiting to be flushed or is in the process of being flushed. The out-bound read request may be performed on the PCI bus at the same time that the in-bound write data is flowing through the GLIU. When handling an in-bound read request, the intended size of the transfer is unknown. In-bound read requests for nonprefetchable addresses will only fetch the data explicitly indicated in the PCI transaction. Thus, all in-bound read requests made to non-prefetchable addresses will return at most a single 32-bit WORD. In-bound read requests made to prefetchable memory may cause more than a 32-bit WORD to be prefetched. The amount of data prefetched is configurable via the read threshold fields of the Global Control (GLPCI_CTRL), MSR 51000010h. Multiple read requests may be generated to satisfy the read threshold value. In-bound read requests may pass posted in-bound write data when there is no address collision between the read request and the address range of the posted write data (different cache lines) and the read address is marked as being prefetchable. Support IDE data port Read Prefetch when MSR Control register (MSR 51000010h[19:18]) is set to IDE prefetch for performance enhancement. I/O reads to address 1F0h can follow a prefetching behavior. When enabled, the GLPCI_SB issues GLIU Read Request Packets for this specific address before receiving a request on the PCI bus for it. All PCI accesses to 1F0h must be DWORDs; that is, 4 bytes. 4.2.4 PCI Bus Interface The PCI Bus Interface block provides a protocol conversion layer between the transaction forwarding module and the PCI bus. The master and target portions of this module operate independently. Thus, out-bound write requests and in-bound read responses are effectively multiplexed onto the PCI bus. It includes address decoding logic to recognize distinct address regions for slave operation. Each address region is defined by a starting address, an address mask, and some attached attributes (i.e., memory and/or I/O space indicator, prefetchable, retry/hold, postable memory write, region enable). The PCIF is responsible for retrying out-bound requests when a slave termination without data is seen on the PCI bus. It also must restart transactions on the PCI that are prematurely ended with a slave termination. This module also always slave terminates in-bound read transactions issued to non-prefetchable regions after a single WORD has been transferred. 4.2.5 CPU Interface Serial The CPU Interface Serial block provides a serial interface to the CPU for side-band signals. From reset, the GLPCI_SB connects only the SUSP# signal to the serial output. All other signals must be added by programming the CIS mode (MSR 51000010h[4:3]). Any change of the signals selected from the 16 side-band signals will start shifting to the CPU all 20 bits of the CIS register including two START bits (00) and two padding STOP bits (11). Three different modes control the selection of the sideband signals to the CIS shift register. 4.2.6 Programmable ID Selection An ID select register, IDSEL[31:0], is used for programmable ID selection. Only one bit in IDSEL[31:12] is set and used as a chip select (i.e., compared with AD[31:12]) during a PCI configuration write/read. The reset value of the IDSEL register is 02000000h. After reset, the first 32-bit I/O write PCI command (i.e., BE# = 0h) with address 00000000h and one bit set in AD[31:0] is assumed to initialize the IDSEL register. Only data with one bit set in AD[31:0] is considered valid. All other values are ignored and will not change the contents of IDSEL. Revision 0.8 77 www.national.com Geode™ CS5535 GLPCI_SB Functional Description (Continued) SSMI and EXCEP Support in GLIU Read/Write Response Packets If the HCD (Hold for CIS Transfer Disable) bit in GLPCI_MSR_CTRL (MSR 51000010h[9]) is set, any inbound memory, I/O, or external MSR read/write response packet will be checked for SSMI and EXCEP bits. If the response packet has the EXCEP bit and/or SSMI bit set, then the GLPCI_SB will not complete the transaction (it will either issue a Retry or Hold PCI bus) until the CIS transfer completes. During an out-bound transaction, when the GLPCI_SB issues a Master Abort, the EXCEP bit in the GLIU response packet is set. 4.2.8 Subtractive Decoding If the SDOFF (Subtractive Decode Off) bit in the GLPCI_MSR_CTRL (MSR 51000010h[10]) is cleared (reset value), any PCI transaction, other than Configuration Read/Write, Interrupt Acknowledge, and Special Cycle transactions, not claimed by any device (i.e., not asserting DEVSEL#) within the default active decode cycles (three cycles immediately after FRAME# being asserted) will be accepted by GLPCI_SB at the fourth clock edge. The Retry condition will be issued for Memory Read, Memory Read Line, Memory Read Multiple (after Initial Latency Timeout), and I/O Read/Write (immediately) and all the required information (command, address and byte enable bits) is stored for the following Delayed Transactions. During Delayed Transactions, the active decode scheme is used. Any address accessed through a subtractive decoding is assumed to be non-prefetchable. 4.2.9 Byte Enable Checking in I/O Address Decoding In any in-bound I/O transaction, the byte enables BE[3:0]# are checked against address bits PCI_AD[1:0] for valid combinations. If an illegal byte enable pattern is asserted, the GLPCI_SB will issue a Target Abort. The only exception is when subtractive decode is used. During a subtractive decode, PCI_AD[1:0] and BE# are passed to the GLIU as is. The IOED (I/O Addressing Error Checking Disable) bit in GLPCI_MSR_CTRL (MSR 51000010h[8]) can be set to disable the I/O addressing error checking, where AD[1:0] is ignored and the byte enables are passed to the GLIU. 4.2.10 IDE Data Port Read Prefetch This algorithm issues multiple four byte reads to the IDE data register (1F0h) at the “beginning” of an IDE “read operation”. The hardware continues to read ahead of software read requests until a sector boundary is about to be crossed. The hardware does not read ahead over a sector boundary. Once a software read crosses a sector boundary, the hardware proceeds to read ahead again. Furthermore, the algorithm does not prefetch the last read of a sector because there is the potential that the last sector read will be the last read of the overall “read operation”. On the last read, the status will change to indicate the operation is complete. By not prefetching the last sector read, the data and status never get out of sync with each other. In PIDE prefetch mode, hardware always makes four byte reads to the IDE data register (1F0h) and supplies the four 4.2.7 bytes of read data to IDE read operations ignoring byte enables of the IDE read operation. 4.2.11 IDE Data Port Write Posting The PPIDE (Post Primary IDE) in GLPCI_MSR_CTRL (MSR 51000010h[17]) controls post/write on confirmation for I/O writes of address 1F0h (part of primary IDE address). If bit 17 is set, a write is completed immediately on the PCI bus as soon as it is accepted by the GLPCI_SB. If bit 17 is cleared, an I/O write is completed only after completing the write in the primary IDE space. Default behavior is write on confirmation. 4.2.12 Other Typical Slave Write Posting For each GLPCI_SB Region Configuration register (0 through 15), if the SPACE bit (bit 32) is programmed for I/O and bit 3 (PF, Prefetchable) is high, post all I/O writes to this region. (See Section 5.2.2.2 "Region 0-15 Configuration MSRs (GLPCI_R[x])" on page 223 for furtherdetails.) Use of this feature is most appropriate for GPIO “bit banging” in the Diverse Device module. Posting writes on the North Bridge side will not increase performance. 4.2.13 Memory Writes with Send Response Normally memory writes are posted independent of region and independent of decode and legacy/non-legacy address. The USB registers are in memory space and can not be moved to I/O space due to driver compatibility issues. In a GX2/CS5535 system a memory write is posted and a possibility exists that a subsequent I/O write will complete before the posted memory write completes. In order to prevent out of order execution, when a memory write is issued to the GLIU in the CS5535, the request packet is issued with the send response bit set to serialize the request. I/O writes are not an issue, since the requests packet always has the send response bit set. www.national.com 78 Revision 0.8 Geode™ CS5535 GLPCI_SB Functional Description (Continued) 4.2.14 CPU Interface Serial (CIS) The CIS provides the system interface between the CS5535 and GX2. The interface supports several modes to send different combinations of 16-bit side-band signals through the CIS signal (ball P3). The sideband signals are synchronized to the PCI clock through 2-stage latching. Whenever at least one of 16 signals is changed, the serial transfer (using the PCI clock) immediately starts to send the information from the South Bridge to the North Bridge. But, if any bit changes within 20 clocks of any previous change, the later change will not be transmitted during the transfer. Another transfer will start immediately after the conclusion of the transfer due to the subsequent change. There are three modes of operation for the CIS signal (ball P3). Note that the transmitted polarity may be different than the “generally defined” polarity state: • Mode A - Non-serialized mode with CIS equivalent to SUSP# (reset mode). Not used in normal operation. • Mode B - Serialized mode with signals SUSP#, NMI, Sleep, and Delayed Sleep. Not used in normal operation. • Mode C - Serialized mode with Mode B signals plus ASMI, and INTR. Used in normal operation. If the GLPCI_MSR_CTRL bit HCD (MSR 51000010h[9]) is set, any in-bound transaction, except in-bound memory writes, will be held for any CIS transfer to complete before claiming completion. Mode selection is programmed in the GLPCI_MSR_CTRL, bits [4:3] (MSR 51000010h). Table 4-3 lists the serial data with corresponding side-band signals. The serial shift register takes the selected sideband signals as inputs. The signal SMI is the ORed result of the SSMI_ASMI_FLAG (SSMI Received Event) bit in GLPCI_SB GLD_MSR_SMI (MSR 51000002h[18]) and the side-band signal ASMI. It also serves as a direct output to the processor. Table 4-3. CIS Serial Bits Assignment and Descriptions Bit Position start_0 start_1 data 00 data 01 data 02 data 03 data 04 data 05 data 06 data 07 data 08 data 09 data 10 data 11 data 12 data 13 data 14 data 15 stop_0 stop_1 Note: Mode B 0 0 1 1 SUSP NMI# Sleep# Delayed Sleep# 1 1 1 1 1 1 1 1 1 1 1 1 Mode C 0 0 1 1 SUSP NMI# Sleep# Delayed Sleep# ASMI# INTR# 1 1 1 1 1 1 1 1 1 1 Comment Start Bit 0 Start Bit 1 Reserved Reserved Sleep Request Non-Maskable Interrupt Power Management Input Disable Power Management Output Disable ASMI or SSMI Maskable Interrupt out Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Stop Bit 0 Stop Bit 1 Mode A is not listed since it is a non-serialized mode with CIS equivalent to SUSP# (reset mode). Revision 0.8 79 www.national.com Geode™ CS5535 GLPCI_SB Functional Description (Continued) 4.2.15 Exception Handling This section describes how various errors are handled by the PCI Bus Interface block. Since PERR# is not implemented on the CS5535 or the GX2 processor, error reporting via this signal is not supported. In a GX2/CS5535 system, other PCI devices that do have the PERR# pin must have a pull-up. 4.2.16 Out-Bound Write Exceptions When performing an out-bound write on PCI, three errors may occur: master abort, target abort, and parity error. When a master or target abort occurs, the PCI Bus Interface block will flush any stored write data. If enabled, an ASMI is generated. ASMI generation is enabled and reported in GLPCI_SB GLD_MSR_SMI (MSR 51000002h). Parity errors are detected and handled by the processor. The failed transaction will not be retried. 4.2.17 Out-Bound Read Exceptions When performing an out-bound read on PCI, three errors may occur: master abort, target abort, and detected parity error. When a master or target abort occurs, the PCI Bus Interface block will return the expected amount of data. If enabled, an ASMI is generated. ASMI generation is enabled and reported in GLPCI_SB GLD_MSR_SMI (MSR 51000002h). Parity errors are detected and handled by the processor. The failed transaction will not be retried. 4.2.18 In-Bound Write Exceptions When performing an in-bound write from PCI, two errors may occur: a detected parity error and a GLIU exception. A GLIU exception cannot be relayed back to the originating PCI bus master, because in-bound PCI writes are always posted. When a parity error is detected, an ASMI is generated if it is enabled. ASMI generation is enabled and reported in GLPCI_SB GLD_MSR_SMI (MSR 51000002h). However, the corrupted write data will be passed along to the GLIU. 4.2.19 In-Bound Read Exceptions When performing an in-bound read from the GLIU, the EXCEP flag may be set on any received bus-WORD of data. This may be due to an address configuration error caused by software or by an error reported by the source of data. The asynchronous ERR and/or SMI bit will be set by the PCI Bus Interface block and the read data, valid or not, will be passed to the PCI Bus Interface block along with the associated exceptions. The PCI Bus Interface block should simply pass the read response data along to the PCI bus. www.national.com 80 Revision 0.8 Geode™ CS5535 4.3 AC97 AUDIO CODEC CONTROLLER • Transport for audio data to and from the system memory and AC97 codec. • Capable of outputting multi-channel 5.1 surround sound (Left, Center, Right, Left Rear, Right Rear, and Low Frequency Effects). Hardware Includes: • GeodeLink Adapter. • Three 32-bit stereo-buffered bus masters (two for output, one for input). • Five 16-bit mono-buffered bus masters (three for output, two for input). • AC Link Control block for interfacing with external AC97 codec(s). The ACC logic controls the traffic to and from the AC97 codec. For input channels, serial data from the codec is buffered and written to system memory using DMA. For output channels, software-processed data is read from system memory and streamed out serially to the codec. The primary purpose of the AC97 Audio Codec Controller (ACC) is to stream data between system memory and an AC97 codec (or codecs) using direct memory access (DMA). The AC97 codec supports several channels of digital audio input and output. Hence, the ACC contains several bus mastering DMA engines to support these channels. This method off-loads the CPU, improving system performance. The ACC is connected to the system through the GLIU and all accesses to and from system memory go through the GLIU. The AC97 codec is connected with a serial interface, and all communication with the codec occurs via that interface (see Figure 4-3). Features include: • AC97 version 2.1 compliant interface to codecs: serial in (x2), serial out, sync out, and bit clock in. • Eight-channel buffered GLIU mastering interface. • Support for industry standard 16-bit pulse code modulated (PCM) audio format. • Support for any AC97 codec with Sample Rate Conversion (SRC). GLIU Data In GLIU Data Out GLCP I/F GeodeLink Adaptor (GLA) Bus Master 0 GL Clock CCU Bus Master 1 LBus Clock AC Link Bit Clock CCU Bus Master 2 Bus Master 3 CCU Bus Master 4 Bus Master 5 Output Data Mux Bus Master 6 Bus Master 7 AC Link Registers / Control Control Signals to Bus Masters To/From Codec Figure 4-3. ACC Block Diagram www.national.com 81 Revision 0.8 Geode™ CS5535 ACC Functional Description (Continued) 4.3.1 Audio Bus Masters The ACC includes eight bus mastering units (three for input, five for output). Each bus master corresponds to one or two slots in the AC Link transfer protocol (see Section 4.3.4.1 "AC Link Serial Interface Protocol" on page 83). Table 4-4 lists the details for each bus master. 4.3.2 Bus Master Audio Configuration Registers The bus masters must be programmed by software to configure how they transfer data. This is done using their configuration registers. These registers determine whether the bus master is active and what parts of memory they have been assigned to transfer. Status registers allow software to read back information on the state of the bus masters. (See Section 5.3.2 "ACC Native Registers" on page 236 for further details on the Bus Master Audio Configuration registers.) 4.3.3 AC Link Overview The AC Link is the interface between the AC97 codec and the ACC. The interface is AC97 v2.1 compliant. Any AC97 codec that supports Sample Rate Conversion (SRC) can be used with the ACC. See Intel Corporation’s “Audio Codec 97” Revision 2.1 component specification for more details. The AC Link protocol defines an input and output frame consisting of 12 “slots” of data. Each slot contains 20 bits, except slot 0, it contains 16 bits. The SYNC signal is generated by the ACC and defines the beginning of an input and an output frame. The serial clock is generated by the AC97 codec. The AC Link is covered in depth in Section 4.3.4.1 "AC Link Serial Interface Protocol" on page 83. It is important to note that the AC97 codec has its own set of configuration registers that are separate from the ACC. These registers are accessible over the serial link. There are registers in the ACC that provide software with an interface to the AC97 codec registers. (See Section 5.3.2 "ACC Native Registers" on page 236 for register descriptions.) Table 4-4. Audio Bus Master Descriptions Bus Master BM0 BM1 BM2 BM3 BM4 BM5 Size 32-bit (16 bits/channel) 32-bit (16 bits/channel) 16-bit 16-bit 16-bit 16-bit Direction Output to codec Input from codec Output to codec Input from codec Output to codec Input from codec AC Link Slot(s) 3 (left) and 4 (right) 3 (left) and 4 (right) 5 5 6 or 11 (configurable) 6 or 11 (configurable) Channel Description Left and Right Stereo Main Playback Left and Right Stereo Recording Modem Line 1 DAC Output Modem Line 1 ADC Input Center Channel Playback (slot 6) or Headset Playback (slot 11) Microphone Record (slot 6) or Headset Record (slot 11) BM6 BM7 32-bit (16 bits/channel) 16-bit Output to codec Output to codec 7 (left) and 8 (right) 9 Left and Right Surround Playback Low Frequency Effects Playback (LFE) www.national.com 82 Revision 0.8 Geode™ CS5535 ACC Functional Description (Continued) 4.3.4 Codec Interface 4.3.4.1 AC Link Serial Interface Protocol The following figures outline the slot definitions and timing scheme of the AC Link serial protocol. Slot # AC_S_SYNC 0 1 2 3 4 5 6 7 8 9 10 11 12 AC_S_OUT (Outgoing Stream) AC_S_IN or AC_S_IN2 (Incoming Stream) TAG CMD ADDR CMD DATA PCM LEFT PCM LINE1 RIGHT DAC PCM CEN PCM PCM L SUR R SUR PCM LFE RSVD HSET DAC GPIO CNTL TAG STATUS STATUS PCM ADDR DATA LEFT PCM LINE1 RIGHT ADC MIC ADC RSVD RSVD RSVD RSVD HSET GPIO ACD STATUS TAG Phase Data Phase Figure 4-4. AC Link Slot Scheme 48 kHz (20.8 µs) Tag Phase Data Phase AC_S_SYNC 12.288 MHz (81.4 ns) AC_CLK AC_S_OUT Valid Frame Slot 1 Slot 2 Slot 12 “0” “0” “0” 19 0 19 0 19 0 19 0 End of Previous Frame Time slot “valid” bits (“1” = Time slot contains valid PCM data) Slot 1 Slot 2 Slot 3 Slot 12 Figure 4-5. AC Link Output Frame 48 kHz (20.8 µs) Tag Phase Data Phase AC_S_SYNC 12.288 MHz (81.4 ns) AC_CLK AC_S_IN or AC_S_IN2 Codec Ready Slot 1 Slot 2 Slot 12 “0” “0” “0” “19” 0 19 0 19 0 19 0 End of Previous Frame Time slot “valid” bits (“1” = Time slot contains valid PCM data) Slot 1 Slot 2 Slot 3 Slot 12 Figure 4-6. AC Link Input Frame www.national.com 83 Revision 0.8 Geode™ CS5535 ACC Functional Description (Continued) 4.3.4.2 AC Link Output Frame (AC_S_OUT) The audio output frame data stream corresponds to the time division multiplexed bundles of all digital output data targeting the AC97 codec’s DAC inputs and control registers. Each audio output frame contains 13, 20-bit outgoing data slots, except for slot 0, it has 16 bits. Slot 0 is a dedicated slot used for the AC Link protocol. An audio output frame begins with a low-to-high transition of the AC_S_SYNC signal. AC_S_SYNC is synchronous to the rising edge of AC_CLK. The AC97 codec samples the AC_S_SYNC on the immediately following falling edge of AC_CLK. AC_S_SYNC is held high for 16 bit clocks. The ACC transmits data on each rising edge of the bit clock, whereas the AC97 codec samples the data on the falling edge of AC_CLK. The serial output stream is MSB justified (MSB first) within each slot, and all non-valid bit positions are stuffed with 0s by the AC Link interface module. Slot 0: TAG This slot is used for AC Link protocol information. The first bit (bit 15) flags the validity of the entire audio frame as a whole. If this bit is 0, all of the remaining bits in the frame should be 0. The next 12 bits indicate the validity of the 12 following slots. The last two bits contain the codec ID for accessing registers of several codecs. When the codec ID is 01, 10, or 11, bits 13 and 14 must always be 0, even if slots 1 and 2 are valid. Slots that are marked invalid by slot 0 should be padded with all 0s (except for slots 1 and 2 while accessing registers of a secondary codec). bit 15 bit 14 bit 13 bits [12:3] Frame Valid Slot 1 Valid (primary codec only) Slot 2 Valid (primary codec only) Slot 3-12 Valid bits (bit[12] -> slot 3, bit[11] -> slot 4, bit[10] -> slot 5, ... , bit[3] -> slot 12) Reserved Codec ID field bits [18:12] Control Register Index (64 16-bit locations, addressed on even byte boundaries) Reserved (Stuffed with 0s) bits [11:0] The first bit (MSB) indicates whether the current control transaction is a read or write operation. The following 7 bit positions communicate the targeted control register address. Slot 2: Command Data The command data slot carries 16-bit control register write data if the current command port operation is a write cycle as indicated by slot 1, bit 19. bits [19:4] Control Register Write Data (Stuffed with 0s if current operation is a read) Reserved (Stuffed with 0s) bits [3:0] If the current command port operation is a read, then the entire slot is stuffed with 0s. Slot 3: PCM Playback Left Channel Outputs the front left audio DAC data (main output) (16-bit resolution, MSB first, unused LSBs = 0). Slot 4: PCM Playback Right Channel Outputs the front right audio DAC data (main output) (16-bit resolution, MSB first, unused LSBs = 0). Slot 5: Modem Line 1 DAC Outputs the modem line 1 DAC data (16-bit resolution, MSB first, unused LSBs = 0). Slot 6: PCM Playback Center Channel Outputs the center channel DAC data (16-bit resolution, MSB first, unused LSBs = 0). Slot 7: PCM Playback Left Surround Channel Outputs the left surround channel DAC data (16-bit resolution, MSB first, unused LSBs = 0). Slot 8: PCM Playback Right Surround Channel Outputs the right surround channel DAC data (16-bit resolution, MSB first, unused LSBs = 0). Slot 9: PCM Playback LFE Channel Outputs the low frequency effects channel DAC data (16-bit resolution, MSB first, unused LSBs = 0). Slot 10: Not used Slots 10 is not used by the ACC. Slot 11: Modem Headset DAC Outputs the headset DAC data (16-bit resolution, MSB first, unused LSBs = 0). bit 2 bits [1:0] Slot 1: Command Address The command address is used to access registers within the AC97 codec. The AC97 registers control features and monitor status for AC97 codec functions, including mixer settings and power management as indicated in the AC97 Codec specifications. The control interface architecture supports up to 64 16-bit read/write registers, addressable on even byte boundaries, and reserves support for 64 odd addresses. Audio output frame slot 1 communicates control register address, and write/read command information to the AC97 codec. bit 19 Read/Write Command (1 = Read, 0 = Write) www.national.com 84 Revision 0.8 Geode™ CS5535 ACC Functional Description (Continued) Slot 12: GPIO Control This slot allows the ACC to set the value of the AC97 codec’s GPIO output pins. bits [19:4] bits [3:0] Value of the GPIO pins (Up to 16 can be implemented) Reserved pendent of the validity of slot 1, and slot 1 will only be tagged valid by the codec if it contains a register index. Table 4-5. SLOTREQ to Output Slot Mapping Bit 11 10 9 8 7 6 5 4 3 2 Slot Request Slot 3 Slot 4 Slot 5 Slot 6 Slot 7 Slot 8 Slot 9 Slot 10 Slot 11 Slot 12 Notes Left Channel Out (BM0) Right Channel Out (BM0) Modem Line 1 Out (BM2) Center Out (BM4 if selected) Left Surround Out (BM6) Right Surround Out (BM6) LFE Out (BM7) Not Supported Handset Out (BM4 if selected) Not Supported 4.3.4.3 AC Link Input Frame (AC_S_IN, AC_S_IN2) The audio input frame data streams correspond to the time division multiplexed bundles of all digital input data coming from the AC97 codec. Each input frame contains 13, 20-bit incoming data slots, except for slot 0; it is 16 bits. Slot 0 is a dedicated slot used for the AC Link protocol. An audio input frame begins with a low-to-high transition of the AC_S_SYNC signal. AC_S_SYNC is synchronous to the rising edge of AC_CLK. The AC97 codec samples the AC_S_SYNC signal on the immediately following falling edge of the bit clock. The AC97 codec transmits data on each following rising edge of AC_CLK. The ACC samples the data on the falling edges of AC_CLK. The serial input stream is MSB justified (MSB first) within each slot, and all non-valid bit positions stuffed with zeroes by the AC97 codec. Slot 0: TAG The first bit of the TAG slot (bit 15) is the Codec_Ready bit. The next 12 bits indicate the validity of the next 12 data slots. Slot 1: Status Address / SLOTREQ Bits The status address is the echo of the register address (index) that was sent to the codec on output slot 1 of the previous output frame. It indicates the address (index) of the register whose data is being returned in slot 2 of the input frame. bit 19 bits [18:12] Reserved (Stuffed with 0s) Control Register Index (Echo of register index for which data is being returned) SLOTREQ bits (For variable sampling rate) Reserved (Stuffed with 0s) Slot 2: Status Data The status data slot delivers 16-bit control register read data. bits [19:4] Control Register Read Data (Stuffed with 0s if slot 2 is tagged “invalid” by slot 0) Reserved (Stuffed with 0s) bits [3:0] Slot 3: PCM Record Left Channel Contains the left channel ADC input data (16-bit resolution, MSB first, unused LSBs = 0). Slot 4: PCM Record Right Channel Contains the right channel ADC input data (16-bit resolution, MSB first, unused LSBs = 0). Slot 5: Modem Line 1 ADC Contains the modem line 1 ADC input data (16-bit resolution, MSB first, unused LSBs = 0). Slot 6: Optional Microphone Record Data Contains the microphone ADC input data (16-bit resolution, MSB first, unused LSBs = 0). Slots 7-10: Not Used Slots 7-10 are reserved. Slot 11: Modem Headset ADC Contains the modem headset ADC input data (16-bit resolution, MSB first, unused LSBs = 0). bits [11:2] bits [1:0] The SLOTREQ bits support the variable sample rate signaling protocol. With normal 48 kHz operation, these bits are always zero. When the AC97 codec is configured for a lower sample rate, some output frames will not contain samples because the AC Link always outputs frames at 48 kHz. The SLOTREQ bits serve as the codec’s instrument to tell the ACC whether it needs a sample for a given slot on the next output frame. For each bit: 0 = Send data; 1 = Do NOT send data. If the codec does not request data for a given slot, the ACC should tag that slot invalid and not send PCM data. The mapping between SLOTREQ bits and output slots is given in Table 4-5. The SLOTREQ bits are indewww.national.com 85 Revision 0.8 Geode™ CS5535 ACC Functional Description (Continued) Slot 12: GPIO Status This slot returns the pin status of the AC97 codec’s GPIO pins (if implemented). bits [19:4] bits [3:1] bit 0 Value of the GPIO pins (Up to 16 can be implemented) Reserved GPIO_INT input pin event interrupt (1 = Event; 0 = No Event) buffer space. A bus master will always do buffer fill/empty requests whenever it can transfer 16 bytes of data. It will attempt to do transfers of 16 bytes on a 16-byte boundary, whenever possible. A bus master may do a transfer of more (if it is just starting, and sufficient buffer space is available) or less than 16 bytes (to bring itself onto a 16-byte boundary). It may also do a transfer of less than 16 bytes if the size of the physical memory region causes it to end on a non-16 byte boundary. Some important details on how a bus master behaves: • When an outgoing bus master is enabled, it begins sending data over the AC Link as soon as data is available in its buffer. The slot valid tag for its slot will be asserted beginning with the first audio sample. • When a bus master is disabled while operating, any data in its buffer is lost. Re-enabling the bus master begins by fetching a PRD. • If the bus master is paused during recording or playback, the data in its buffer remains there in a frozen state. Once resumed, it continues as if nothing has occurred. If the bus master is playing back data, the output slots corresponding to the bus master are tagged invalid while it is in the paused state. • If a buffer underrun occurs on an outgoing bus master, the output slots corresponding to the bus master are tagged invalid until data becomes available. • If a buffer overrun occurs on an incoming bus master, samples coming in on the serial link are tossed away until space becomes available in the bus master’s buffer. 4.3.7 4.3.7.1 ACC Software Programming Bit[0] indicates that there was a transition on one of the unmasked codec GPIO pins (see AC97 Codec Specification v2.1 for details). If the Codec GPIO Interrupt Enable bit is set, then slot 12, bit[0] = 1 will trigger an IRQ and set the Codec GPIO Interrupt Flag bit. 4.3.5 AC Link Power Management 4.3.5.1 AC Link Power-down The AC Link interface signals can be placed in a low power mode by programming the AC97 codec’s Power-down Control/Status register. When this is performed, both the AC_CLK and AC_S_IN are brought to a low voltage level by the AC97 codec. This happens immediately following the write to the AC97 codec’s Power-down Control/Status register, so no data can be transmitted in slots 3-12 for the frame signaling power-down. After powering down the AC Link, the ACC must keep AC_S_SYNC and AC_S_OUT low; hence, all the AC Link signals (input and output) are driven low. AC_CLK is de-asserted at the same time that bit[4] of slot 2 is being transmitted on the AC Link. This is necessary because the precise time when the codec stops AC_CLK is not known. 4.3.5.2 AC Link Wakeup (Warm Reset) A warm reset re-activates the AC Link without altering the registers in the AC97 codec. The ACC signals the warm reset by driving AC_S_SYNC high for a minimum of 1 µs in the absence of the AC_CLK. This must not occur for a minimum of four audio frame periods following power-down (note that no bit clock is available during this time). AC_S_SYNC is normally a synchronous signal to AC_CLK, but when the AC97 codec is powered down, it is treated as an asynchronous wakeup signal. During wakeup, the AC97 codec does not re-activate the bit clock until AC_S_SYNC is driven high (for 1 µs minimum) and then low again by the ACC. Once AC_S_SYNC is driven low, AC_CLK is reasserted. See "Audio Driver Power-up/down Programming Model" on page 90 for additional power management information and programming details. 4.3.6 Bus Mastering Buffer Scheme Because the bus masters must feed data to the codec without interruption, they require a certain amount of data buffering. The 32-bit bus masters (stereo) use 24 bytes of buffer space, and the 16-bit bus masters (mono) use 20 bytes of Physical Region Descriptor (PRD) Table Address Register Before a bus master starts a transfer it must be programmed with a pointer to a Physical Region Descriptor (PRD) table. This is done by writing to the bus master’s PRD Table Address register. This pointer sets the starting memory location of the PRD table. The PRDs in the PRD table describe the areas of memory that are used in the data transfer. The table must be aligned on a 4-byte boundary (DWORD aligned). 4.3.7.2 Physical Region Descriptor Format Each physical memory region to be transferred is described by a PRD as illustrated in Table 4-6 on page 87. The PRD table must be created in memory by software before the bus master can be activated. When the bus master is enabled by setting its Bus Master Enable bit, data transfer begins, with the PRD table serving as the bus master’s “guide” for what to do. The bus master does not cache PRDs. A PRD entry in the PRD table consists of two DWORDs. The first DWORD contains a 32-bit pointer to a buffer to be transferred (Memory Region Base Address). The second DWORD contains control flags and a 16-bit buffer size value. The maximum amount of audio data that can be www.national.com 86 Revision 0.8 Geode™ CS5535 ACC Functional Description (Continued) transferred for a given PRD is 65534 bytes for mono streams and 65532 bytes for stereo streams. For stereo streams (bus masters 0, 1, and 6): Memory Region Base Address and Size should be a multiple of four (DWORD aligned). This ensures an equal number of left and right samples. For mono streams (bus masters 2, 3, 4, 5, and 7): Memory Region Base Address and Size should be a multiple of two (WORD aligned). Descriptions of the control flags are: • End of Transfer (EOT) - If set in a PRD, this bit indicates the last entry in the PRD table. The last entry in a PRD table must have either the EOT bit or the JMP bit set. A PRD can not have both the JMP and EOT bits set. When the bus master reaches an EOT, it stops and clears its Bus Master Enable bit. If software desires an IRQ to be generated with the EOT, it must set the EOP bit and the EOT bit on the last PRD entry. • End of Page (EOP) - If set in a PRD and the bus master has completed the PRD’s transfer, the End of Page bit is set (in the IRQ status register) and an IRQ is generated. If a second EOP is reached due to the completion of another PRD before the End of Page bit is cleared, the Bus Master Error bit is set (in the IRQ status register) and the bus master pauses. In this paused condition, reading the IRQ status register clears both the Bus Master Error and the End of Page bits, and the bus master continues. • Jump (JMP) - This PRD is special. If set, the Memory Region Base Address is now the target address of the JMP. The target address of the JMP must point to another PRD. There is no audio data transfer with this PRD. This PRD allows the creation of a looping mechanism. If a PRD table is created with the JMP bit set in the last PRD, the PRD table does not need a PRD with the EOT bit set. A PRD can not have both the JMP and EOT bits set. 4.3.7.3 PCM Data Format and Byte Order Table 4-7 shows an example of the how PCM audio data is stored in memory (byte order and channel order). Each row represents a byte in memory, with increasing addresses as you go down. The byte order can be configured via the Bus Master Command Register for Intel (little endian) or Motorola (big endian) byte ordering. Changing the byte order ONLY affects how PCM data is interpreted. PRD entries and register contents are always little endian. The two channel format applies to the 32-bit bus masters handling left and right input and output. The single channel format applies to the 16-bit bus masters. The 32-bit bus masters always operate on stereo data, and the 16-bit bus masters always operate on mono data. Since there is no special mode for playing monaural sound through the main channels (left and right), it is the responsibility of the software to create stereo PCM data with identical samples for the left and right channels to effectively output monaural sound. Table 4-6. Physical Region Descriptor (PRD) Format Byte 3 DWORD 0 1 EEJ OOM TPP Byte 2 Byte 1 8 7 6 5 Byte 0 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Reserved Memory Region Base Address [31:0] (Address of Audio Data Buffer) Size [15:0] Table 4-7. PCM Data format (Byte and Channel Ordering) 2 Channel, Little Endian Sample 0 0 0 0 1 1 1 1 Channel Left Left Right Right Left Left Right Right Byte Low High Low High Low High Low High 1 Channel, Little Endian Sample 0 0 1 1 2 2 3 3 Byte Low High Low High Low High Low High Sample 0 0 0 0 1 1 1 1 2 Channel, Big Endian Channel Left Left Right Right Left Left Right Right Byte High Low High Low High Low High Low 1 Channel, Big Endian Sample 0 0 1 1 2 2 3 3 Byte High Low High Low High Low High Low www.national.com 87 Revision 0.8 Geode™ CS5535 ACC Functional Description (Continued) 4.3.7.4 Programming Model The bus master reads the PRD entry pointed to by the PRD Table Address register. Using the address from the PRD, it begins the audio transfer. The PRD Table Address register is incremented by eight. Example - The bus master is now properly programmed to transfer Audio Buffer_1 to a specific slot(s) in the AC97 interface. 5) The bus master transfers data from memory and sends it to the AC97 Codec. At the completion of each PRD, the bus master’s next response depends on the settings of the flags in the PRD. Example - After transferring the data described by PRD_1, an interrupt is generated because the EOP bit is set, and the bus master continues on to PRD_2. The interrupt service routine reads the Second Level Audio IRQ Status register to determine which bus master to service. It refills Audio Buffer_1 and then reads the bus master’s IRQ Status register to clear the End of Page flag and the interrupt. After transferring the data described by PRD_2, another interrupt is generated because the EOP bit is set, and the bus master continues on to PRD_3. The interrupt service routine reads the Second Level Audio IRQ Status register to determine which bus master to service. It refills Audio Buffer_2 and then reads the bus master’s IRQ Status register to clear the End of Page flag and the interrupt. PRD_3 has the JMP bit set. This means the bus master uses the address stored in PRD_3 (Address_3) to locate the next PRD. It does not use the address in the PRD Table Address register to get the next PRD. Since Address_3 is the location of PRD_1, the bus master has looped the PRD table. No interrupt is generated for PRD_3. Address_1 Address_1 EOT = 0 EOP = 1 JMP = 0 Address_2 EOT = 0 EOP = 1 JMP = 0 Address_3 EOT = 0 EOP = 0 JMP = 1 PRD_3 Don’t Care PRD_2 Size_2 Address_2 PRD_1 Size_1 Audio Buffer_1 Size_1 Audio Playback/Record The following discussion explains, in steps, how to initiate and maintain a bus master transfer between memory and an audio slave device. In the steps, the reference to Example refers to Figure 4-7: 1) Software creates a PRD table in system memory. The last PRD entry in a PRD table must have the EOT or JMP bit set. Example - Assume the data is outbound. There are three PRDs in the example PRD table. The first two PRDs (PRD_1, PRD_2) have only the EOP bit set. The last PRD (PRD_3) has only the JMP bit set. This example creates a PRD loop. 2) Software loads the starting address of the PRD table by programming the PRD Table Address register. Example - Program the PRD Table Address register with Address_3. 3) Software must fill the buffers pointed to by the PRDs with audio data. It is not absolutely necessary to fill the buffers; however, the buffer filling process must stay ahead of the buffer emptying. The simplest way to do this is by using the EOP flags to generate an interrupt when an audio buffer is empty. Example - Fill Audio Buffer_1 and Audio Buffer_2. Ensure than an interrupt service routine is assigned to the audio interrupt. 4) Read the IRQ Status register to clear the Bus Master Error and End of Page flags (if set). Program the AC97 codec properly to receive audio data (mixer settings, etc.). Engage the bus master by setting the Bus Master Enable bit. Address_3 Audio Buffer_2 Size_2 Figure 4-7. ACC PRD Table Example www.national.com 88 Revision 0.8 Geode™ CS5535 ACC Functional Description (Continued) Pausing the bus master can be accomplished by setting the Bus Master Pause bit in its control register. The bus master stops immediately on the current sample being processed. Upon resuming, the bus master (clearing the Bus Master Pause bit), resumes on the exact sample where it left off. The bus master can be stopped in the middle of a transfer by clearing the Bus Master Enable bit in its control register. In this case, the bus master will not remember what sample it left off on. If it is re-enabled, it will begin by reading the PRD entry pointed to by its PRD Table Address register. If software does not reinitialize this pointer, it will be pointing to the PRD entry immediately following the PRD entry that was being processed. This may be an invalid condition if the bus master was disabled while processing the last PRD in a PRD table (PRD Table Address register pointing to memory beyond the table). Note that if the Bus Master Error bit is set, the interrupt service routine should refill two buffers instead of one, because a previous interrupt was missed (unless it was intentionally missed). For this to work correctly, the service routine should read the Second Level Audio IRQ Status register, fill the buffer of the bus master needing service, read the bus master’s IRQ Status register, and then fill the next buffer if the Bus Master Error bit was set. Failing to fill the first buffer before reading the IRQ Status register would possibly resume the bus master too early and result in sound being played twice or data being overwritten (if recording). Codec Register Access The ACC provides a set of registers that serve as an interface to the AC97 codec’s registers. The Codec Command register allows software to initiate a read or a write of a codec register. The Codec Status register allows software to read back the data from the codec after a read operation has completed. Since the AC Link runs very slow relative to core CPU speed (and therefore software speed), it is necessary for software to wait between issuing commands to the codec. For register reads, software specifies a command address and sets both the read/write flag and the Codec Command New flag in the Codec Control register. Software must then wait for the Codec Status New bit to be set before using the returned status data in the Codec Status register. Before issuing another read command, software must wait for the Codec Command New flag to be cleared by hardware. (Note: Codec Command New will clear before Codec Status New is set; therefore, a second read can be issued before the result of the current read is returned). For register writes, software specifies a command address and command data using the Codec Control register. At the same time it must set the Codec Command New flag. Before issuing another read or write, software must wait for the Codec Command New flag to clear. See Section 5.3 "AC97 Audio Codec Controller Register Descriptions" for details on the Codec register interface. www.national.com 89 Revision 0.8 Geode™ CS5535 ACC Functional Description (Continued) Audio Driver Power-up/down Programming Model The ACC contains Machine Specific Registers (MSRs) that relate to a very low level power management scheme, but are discrete from the power management features of the codec and the device driver programming model. This section covers the power management features for the device driver. See Section 4.3.5 "AC Link Power Management" on page 86 for power management hardware details. The following sections outline how the device driver should perform power management. Power-down Procedure 1) Disable or pause all bus masters using their bus master command register. 2) It may be necessary to determine if a second codec is being used, and if so, verify that the power-down Semaphore for Secondary Codec bit is set before proceeding (to insure that the modem driver has prepared the second codec for power-down, if necessary). Using the Codec Control register, access the primary codec’s registers and program the codec to powerdown. Also, simultaneously write to the AC Link Shutdown bit in the Codec Control register (ACC I/O Offset 0Ch[18]). The ACC and codec will power-down once the command is received by the codec. All of the contents of the ACC and codec registers are preserved during the power-down state. If you wish to enable the GPIO wakeup interrupt, wait for an additional two audio frame periods (42 µs) before setting the GPIO Wakeup Interrupt Enable bit (ACC I/O Offset 00h[29]). Failure to wait will cause false interrupt events to occur. Power-up Procedure 1) If GPIO Wakeup Interrupt Enable (ACC I/O Offset 00h[29]) was set in the power-down procedure, it will automatically be disabled upon power-up. 2) Set the AC Link Warm Reset bit in the Codec Control register (ACC I/O Offset 0Ch[17]). This will initiate the warm reset sequence. Wait for the Codec Ready bit(s) in the Codec Status register (ACC I/O Offset 08h[23:22]) to be asserted before accessing any codec features or enabling any bus masters. 3) Notes: 1) If the GPIO Wakeup Interrupt Enable (ACC I/O Offset 00h[29]) is set, and an interrupt occurs, it is detected and fired, but the interrupt does not wakeup the codec and ACC. The hardware will only wakeup if the software responds to the interrupt and performs the power-up procedure. Once software has issued a power-down, it must not perform the power-up procedure for at least six audio frame periods (about 0.125 ms or 125 µs). Doing so could lock up the codec or ACC. If the system has cut off power to the codec and restarted it, it is not necessary to initiate a warm reset. The AC Link Shutdown should be cleared manually to restart the operation of the AC Link. 2) 3) 3) 4) 5) www.national.com 90 Revision 0.8 Geode™ CS5535 4.4 ATA-5 CONTROLLER The PIO portion of the IDE registers is enabled through: • Channel 0 Drive 0 PIO (ATAC_CH0D0_PIO) (MSR 51300020h) • Channel 0 Drive 1 PIO (ATAC_CH0D1_PIO) (MSR 51300022h) The IDE channel and devices can be individually programmed to select the proper address setup time, asserted time, and recovery time. The bit formats for these registers are shown in Section 5.4.3 "ATAC Native Registers" on page 258. Note that there are different bit formats for each of the PIO programming registers depending on the operating format selected: Format 0 or Format 1. Channel 0 Drive 0/1 - The DMA register (MSR 51300021h/ 51300023h) sets the format of the PIO register. If bit 31 = 0, Format 0 is used and it selects the slowest PIO mode (bits [19:16]) for commands. If bit 31 = 1, Format 1 is used and it allows independent control of command and data. Also listed in the bit formats are recommended values for the different PIO modes. Note that these values are only recommended settings and are not 100% tested. 4.4.2 Bus Master Mode An IDE bus master is provided to perform the data transfers for the IDE channel. The ATAC off-loads the CPU and improves system performance. The bus master mode programming interface is an extension of the standard IDE programming model. This means that devices can always be dealt with using the standard IDE programming model, with the master mode functionality used when the appropriate driver and devices are present. Master operation is designed to work with any IDE device that supports DMA transfers on the IDE bus. Devices that work in PIO mode can only use the standard IDE programming model. The IDE bus master uses a simple scatter/gather mechanism, allowing large transfer blocks to be scattered to or gathered from memory. This cuts down on the number of interrupts to and interactions with the CPU. 4.4.2.1 Physical Region Descriptor Table Address Before the controller starts a master transfer it is given a pointer to a Physical Region Descriptor Table. This pointer sets the starting memory location of the Physical Region Descriptors (PRDs). The PRDs describe the areas of memory that are used in the data transfer. The PRDs must be aligned on a 4-byte boundary and the table cannot cross a 64 kB boundary in memory. 4.4.2.2 IDE Bus Master Registers The IDE Bus Master registers have an IDE Bus Master Command register and Bus Master Status register. These registers can be accessed by byte, WORD, or DWORD. The hard disk controller is an ATA-5 compatible IDE controller (ATAC). This controller supports UDMA/66, MDMA, and PIO modes. The controller can support one channel (two devices). The IDE interface provides a variety of features to optimize system performance, including 32-bit disk access, post write buffers, bus master, MDMA, look-ahead read buffer, and prefetch mechanism. The IDE interface timing is completely programmable. Timing control covers the command active and recover pulse widths, and command block register accesses. The IDE data-transfer speed for each device on each channel can be independently programmed allowing high-speed IDE peripherals to coexist on the same channel as older, compatible devices. Faster devices must be ATA-5 compatible. The ATAC also provides a software-accessible buffered reset signal to the IDE drive. The IDE_RST# signal is driven low during system reset and can be driven low or high as needed for device power-off conditions. Features include: • ATA5-compliant IDE controller • Supports PIO (mode 0 to 4), MDMA (mode 0 to 2), and UDMA (mode 0 to 4) • Supports one channel, two devices • Allows independent timing programming for each device 4.4.1 PIO Modes The IDE data port transaction latency consists of address latency, asserted latency, and recovery latency. Address latency occurs when a PCI master cycle targeting the IDE data port is decoded, and the IDE_ADDR[2:0] and IDE_CS# lines are not set up. Address latency provides the setup time for the IDE_ADDR[2:0] and IDE_CS# lines prior to IDE_IOR# and IDE_IOW#. Asserted latency consists of the I/O command strobe assertion length and recovery time. Recovery time is provided so that transactions may occur back-to-back on the IDE interface without violating minimum cycle periods for the IDE interface. If IDE_IORDY is asserted when the initial sample point is reached, no wait states are added to the command strobe assertion length. If IDE_IORDY is negated when the initial sample point is reached, additional wait states are added. Recovery latency occurs after the IDE data port transactions have completed. It provides hold time on the IDE_ADDR[2:0] and IDE_CS# lines with respect to the read and write strobes (IDE_IOR# and IDE_IOW#). Revision 0.8 91 www.national.com Geode™ CS5535 ATAC Functional Description (Continued) 4.4.2.3 Physical Region Descriptor Format Each physical memory region to be transferred is described by a Physical Region Descriptor (PRD) as illustrated in Table 4-8. When the bus master is enabled (Command register bit 0 = 1), data transfer proceeds until each PRD in the PRD table has been transferred. The bus master does not cache PRDs. The PRD table consists of two DWORDs. The first DWORD contains a 32-bit pointer to a buffer to be transferred. This pointer must be 4-byte aligned. The second DWORD contains the size (16 bits) of the buffer and the EOT (End Of Table) flag. The size must be in multiples of 1 WORD (2 bytes) or zero (which means a 64 kB transfer). The EOT bit (bit 31) must be set to indicate the last PRD in the PRD table. 4.4.2.4 Programming Model The following steps explain how to initiate and maintain a bus master transfer between memory and an IDE device: 1) Software creates a PRD table in system memory. Each PRD entry is 8 bytes long, consisting of a base address pointer and buffer size. The maximum data that can be transferred from a PRD entry is 64 kB. A PRD table must be aligned on a 4-byte boundary. The last PRD in a PRD table must have the EOT bit set. 2) 3) 4) 5) Software loads the starting address of the PRD table by programming the PRD Table Address register. Software must fill the buffers pointed to by the PRDs with IDE data. Write 1 to the Bus Master Interrupt bit and Bus Master Error (Status register bits 2 and 1) to clear the bits. Set the correct direction to the Read or Write Control bit (Command register bit 3). Engage the bus master by writing a 1 to the Bus Master Control bit (Command register bit 0). The bus master reads the PRD entry pointed to by the PRD Table Address register and increments the address by 08h to point to the next PRD. The transfer begins. 6) The bus master transfers data to/from memory responding to bus master requests from the IDE device until all PRD entries are serviced. The IDE device signals an interrupt once its programmed data count has been transferred. In response to the interrupt, software resets the Bus Master Control bit in the Command register. It then reads the status of the controller and IDE device to determine if the transfer is successful. 7) 8) Table 4-8. Physical Region Descriptor Format Byte 3 DWORD 0 EOT 1 Byte 2 Byte 1 9 8 7 6 5 Byte 0 4 3 2 1 0 0 0 0 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Memory Region Physical Base Address [31:4] (IDE Data Buffer) Reserved Size [15:2] www.national.com 92 Revision 0.8 Geode™ CS5535 ATAC Functional Description (Continued) 4.4.2.5 UDMA/66 Mode The ATAC supports UDMA/66. It utilizes the standard IDE bus master functionality to interface, initiate, and control the transfer. The UDMA/66 definition also incorporates a Cyclic Redundancy Checking (CRC) error checking protocol to detect errors. The UDMA/66 protocol requires no extra signal pins on the IDE connector. The ATAC redefines three standard IDE control signals when in UDMA/66 mode. These definitions are shown in Table 4-9. The data transfer phase continues the burst transfers with the ATAC and the IDE via providing data, toggling STROBE and DMARDY#. IDE_DATA[15:0] is latched by the receiver on each rising and falling edge of STROBE. The transmitter can pause the burst cycle by holding STROBE high or low, and resume the burst cycle by again toggling STROBE. The receiver can pause the burst cycle by negating DMARDY# and resumes the burst cycle by asserting DMARDY#. The current burst cycle can be terminated by either the transmitter or receiver. A burst cycle must first be paused, as described above, before it can be terminated. The ATAC can then stop the burst cycle by asserting STOP, with the IDE device acknowledging by negating IDE_DREQ. The transmitter then drives the STROBE signal to a high level. The ATAC then puts the result of the CRC calculation onto IDE_DATA[15:0] while de-asserting IDE_DACK#. The IDE device latches the CRC value on the rising edge of IDE_DACK#. The CRC value is used for error checking on UDMA/66 transfers. The CRC value is calculated for all data by both the ATAC and the IDE device during the UDMA/66 burst transfer cycles. This result of the CRC calculation is defined as all data transferred with a valid STROBE edge while IDE_DACK# is asserted. At the end of the burst transfer, the ATAC drives the result of the CRC calculation onto IDE_DATA[15:0], which is then strobed by the deassertion of IDE_DACK#. The IDE device compares the CRC result of the ATAC to its own and reports an error if there is a mismatch. The timings for UDMA/66 are programmed into the DMA control registers: • Channel 0 Drive 0 DMA (ATAC_CH0D0_DMA) (MSR 51300021h) • Channel 0 Drive 1 DMA (ATAC_CH0D1_DMA) (MSR 51300023h) The bit formats for these registers are given in Section 5.4.3 "ATAC Native Registers" on page 258. Note that MSR 51300021h[20] is used to select either MDMA or UDMA mode. Bit 20 = 0 selects MDMA mode. If bit 20 = 1, then UDMA/66 mode is selected. Once mode selection is made using this bit, the remaining DMA registers also operate in the selected mode. Also listed in the bit formats are recommended values for both MDMA modes 0-2 and UDMA/66 modes 0-4. Note that these values are only recommended settings and are not 100% tested. Table 4-9. UDMA/66 Signal Definitions IDE Channel Signal IDE_IOW# IDE_IOR# IDE_IORDY UDMA/66 Read Cycle STOP DMARDY# STROBE UDMA/66 Write Cycle STOP STROBE DMARDY# All other signals on the IDE connector retain their functional definitions during the UDMA/66 operation. IDE_IOW# is defined as STOP for both read and write transfers to request to stop a transaction. IDE_IOR# is redefined as DMARDY# for transferring data from the IDE device to the ATAC. It is used by the ATAC to signal when it is ready to transfer data and to add wait states to the current transaction. The IDE_IOR# signal is defined as STROBE for transferring data from the ATAC to the IDE device. It is the data strobe signal driven by the ATAC on which data is transferred during each rising and falling edge transition. IDE_IORDY is redefined as STROBE for transferring data from the IDE device to the ATAC during a read cycle. It is the data strobe signal driven by the IDE device on which data is transferred during each rising and falling edge transition. IDE_IORDY is defined as DMARDY# during a write cycle for transferring data from the ATAC to the IDE device. It is used by the IDE device to signal when it is ready to transfer data and to add wait states to the current transaction. UDMA/66 data transfer consists of three phases: a startup phase, a data transfer phase, and a burst termination phase. The IDE device begins the startup phase by asserting IDE_DREQ. When ready to begin the transfer, the ATAC asserts IDE_DACK#. When IDE_DACK# is asserted, the ATAC drives IDE_CS0# and IDE_CS1# asserted, and IDE_ADDR[2:0] low. For write cycles, the ATAC negates STOP, waits for the IDE device to assert DMARDY#, and then drives the first data word and STROBE signal. For read cycles, the ATAC negates STOP and asserts DMARDY#. The IDE device then sends the first data word and asserts STROBE. Revision 0.8 93 www.national.com Geode™ CS5535 4.5 UNIVERSAL SERIAL BUS CONTROLLER the GLA synchronizes GLIU transactions at the GLIU clock to the slower Local bus transaction at Local bus clock. 4.5.2 PCI Adapter The PCI Adapter translates PCI signals to a specific Local bus transaction that is attached to the GLA, while the PCI signals are connected directly to a compatible PCI device. It also translates the Local bus transactions to PCI transactions. 4.5.3 USB Core The USB Core is a PCI-based implementation of the Universal Serial Bus (USB) v1.1 Specification utilizing the Open Host Controller Interface (OHCI) standard developed by Compaq, Microsoft, and National Semiconductor. The USB Core consists of the following three blocks: • Host Controller • USB Interface • PCI Interface The USB Core block diagram is shown in Figure 4-8. The two Universal Serial Bus Controllers (USBC) each contain a GeodeLink Adapter, PCI Adapter, and USB Core blocks. The functional descriptions of the blocks are described in the following sub-sections. 4.5.1 GeodeLink Adapter The GeodeLink Adapter (GLA) translates GeodeLink transactions to/from Local bus transactions. The GLA interfaces to a 64-bit GLIU (GeodeLink Interface Unit) and a 32-bit Local bus. The GLA supports in-bound memory and I/O requests which are converted by the PCI Adapter (PA) into PCI memory and I/O requests that target the USBC. It also supports in-bound MSR transactions to the MSRs. These are located “between” the GLA and PA. Lastly, there is a special MSR used to pass PCI configuration requests to the PA. The GLA supports out-bound memory requests only. I/O and MSR transactions from the USBC never occur. USBC PCI master requests are converted by the PA into Local bus master requests. These requests may consist of a simple 4-byte read or write. Alternatively, a PCI burst transaction of any length may be converted to an appropriate series of GLIU transactions by the GLA. Lastly, Embedded PCI Bus PCI Config PCI Interface PCI Slave PCI Master PCI I/O List Processor Host Controller Bus Master Frame Mgmnt USB Core Interrupts Data Buffer Root Hub Control SIE Clock Generator USB Interface Port 1 Port 2 USB Port 1 USB Port 2 Figure 4-8. USB Core Block Diagram www.national.com 94 Revision 0.8 Geode™ CS5535 USBC Functional Description (Continued) 4.5.4 Host Controller The USB host interacts with USB devices through the Host Controller. The host is responsible for: • Detecting the attachment and removal of USB devices. • Managing control flow between the host and USB devices. • Managing data flow between the host and USB devices. • Collecting status and activity statistics. • Providing power to attached USB devices. The USB system software on the host manages interactions between USB devices and host-based device software. There are five areas of interactions between the USB system software and device software: 1) 2) 3) 4) 5) Device enumeration and configuration. Isochronous data transfers. Asynchronous data transfers. Power management. Device and bus management information. sal Serial Bus, which in turn is described by the Universal Serial Bus specification. OHCI allows multiple host controller vendors to design and sell host controllers with a common software interface, freeing them from the burden of writing and distributing software drivers. The design goal has been to balance the complexity of the hardware and software so that OHCI is more than the simplest possible host controller for USB yet not the most complex possible. The Host Controller has four USB states visible to the host controller driver via the operational registers: USBOPERATIONAL, USBRESET, USBSUSPEND, and USBRESUME. These states define the Host Controller responsibilities relating to USB signaling and bus states. The USB states are reflected in the HostControllerFunctionalState field of the HcControl register. The Host Controller may only perform a single state transition. During a remote wakeup event, the Host Controller may transition from USBSUSPEND to USBRESUME. The Host Controller interface registers are PCI memory mapped I/O. The functional state machine (FSM) is shown in Figure 4-9. 4.5.5 USB Interface The USB Interface includes the integrated Root Hub with two external ports, Port 1 and Port 2, as well as the Serial Interface Engine (SIE) and USB clock generator. The interface combines responsibility for executing bus transactions requested by the Host Controller as well as the hub and port management specified by USB. Whenever possible, the USB system software uses existing host system interfaces to manage the above interactions. The OHCI specification for the Universal Serial Bus is a register-level description of a host controller for the Univer- USBOPERATIONAL USBRESET WRITE USBOPERATIONAL WRITE USBOPERATIONAL WRITE USBSUSPEND WRITE USBRESUME USBRESET WRITE USBRESET USBRESUME WRITE or REMOTE WAKEUP USBRESET WRITE HARDWARE RESET USBSUSPEND SOFTWARE RESET Figure 4-9. USB Host Controller FSM Revision 0.8 95 www.national.com Geode™ CS5535 4.6 DIVERSE INTEGRATION LOGIC • Address Decode - Decodes the upper Local bus address bits to select a target slave. Most of the legacy devices have fixed addresses or are selectable between a small number of selectable I/O addresses. However, many of the functions are relocatable via a Local Base Address Register (LBAR); established via an MSR. Address Decode also detects special GLIU cycles, such as Shutdown, and takes appropriate action. DO RO The Diverse Integration Logic (DIVIL) connects a series of Local bus devices to the GeodeLink architecture. Figure 410 illustrates how the DIVIL (within the dashed lines) interfaces with the other devices of the Diverse Device. The main blocks of the DIVIL are: Address Decode, Standard MSRs, Local BARs, and Dataout Mux (DOM). RI DI GLIU Interface Local Bus Interface GeodeLink Adapter Data Out RO Packet Arguments from MSR Data In Slave Addr & Byte Enables * 8254 & Port B (2) 8259A & IRQ Map Kybd Emu & Port A System Mgmt Bus Control External I/O Req/Ack (2) UART & IR External I/O Master Addr & Byte Enables Local Bus Handshake Chip Selects (2) 8237 & DMA Map Address LPC Bus Control RTC & CMOS RAM External I/O External I/O Address Decode and Legacy Decode MSRs Address Hits Standard MSRs GPIO & ICF MFGP Timers DIVIL Local BARs, Compares, and Miscellaneous Pwr Mgmnt *Data Out Mux not shown. Figure 4-10. Diverse Logic Block Diagram NOR & NAND Flash Interfaces and Control External I/O www.national.com 96 Revision 0.8 Geode™ CS5535 DIVIL Functional Description (Continued) • Standard MSRs - Includes the Standard GeodeLink Device MSRs found in all GeodeLink Devices: Capabilities, Master Configuration, SMI Control, Error Control, Power Management, and Diagnostics. • Local BARs - Local Base Address Registers (LBARs) establish the location of non-legacy functions within the Diverse Device. The module also includes logic to compare the current bus cycle address to the LBAR to detect a hit. For the I/O LBARs, the I/O address space 000h-4FFh is off limits. No I/O LBAR is allowed to point to this space. • Data Out Mux (DOM) - This mux is not explicitly illustrated. Each function above produces a single output to the DIVIL. The DIVIL DOM has a port for each of the functions and is responsible for selecting between them. 4.6.1 LBARs and Comparators The LBARs are used to establish the address and hence, chip select location of all functions that do not have fixed legacy addresses. This block also has comparators to establish when a current bus cycle address hits an LBAR. A hit is passed to the address decode block and results in a chip select to the target device if there are no conflicts. The mask and base address values are established via an MSR. 4.6.1.1 Fixed Target Size I/O LBARs This discussion applies to the following LBARs: • MSR 51400008h: IRQ Mapper (MSR_LBAR_IRQ) • MSR 5140000Bh: SMB (MSR_LBAR_SMB) • MSR 5140000Ch: GPIO and ICFs (MSR_LBAR_GPIO) • MSR 5140000Dh: MFGPTs (MSR_LBAR_MFGPT) • MSR 5140000Eh: ACPI (MSR_LBAR_ACPI) • MSR 5140000Fh: Power Management Support (MSR_LBAR_PMS) The IO_MASK only applies to the upper bits [15:12] (see Figure 4-11). Normally, one would set all the mask bits (i.e., no mask on upper bits). One should only mask or clear bits if address wrapping or aliasing is desired. • Rule. When a mask bit is cleared, the associated bit in the base address must also be cleared. Otherwise, the compare will not be equal on these bits. This rule applies to both memory and I/O LBARs. The base size is fixed based on the target. For example, the GPIO takes 256 bytes of address space. Therefore, the base only applies to bits [15:8]. Base bits [7:0] are always cleared by the hardware. Therefore, the base is always forced by hardware to be on a boundary the size of the target. ADDR[15:12] I/O_MASK [15:12] Compare [15:n] BASE_ADDR Hit Notes: 1) The I/O mask is always 4 bits. 2) The I/O base address is variable ([15:n]). The value of “n” depends on the I/O space requirements of the target. For example, a device needing 4, 8, 16, 32, 64, 128, or 256 bytes of I/O space has “n” = 2, 3, 4, 5, 6, 7, 8, respectively. The value “n” for various functions is: MSR_LBAR_IRQ MSR_LBAR_GPIO MSR_LBAR_ACPI MSR_LBAR_FLASH_IO n=5 n=8 n=5 n=4 MSR_LBAR_SMB MSR_LBAR_MFGPT MSR_LBAR_PMS n=3 n=6 n=7 Figure 4-11. I/O Space LBAR - Fixed Target Size Revision 0.8 97 www.national.com Geode™ CS5535 DIVIL Functional Description (Continued) 4.6.1.2 Variable Target Size I/O LBARs This discussion applies to the following LBARs: • MSR 51400010h: Flash Chip Select 0 (MSR_LBAR_FLSH0) with bit 34 = 0 (I/O mapped) • MSR 51400011h: Flash Chip Select 1 (MSR_LBAR_FLSH1) with bit 34 = 0 (I/O mapped) • MSR 51400012h: Flash Chip Select 2 (MSR_LBAR_FLSH2) with bit 34 = 0 (I/O mapped) • MSR 51400013h: Flash Chip Select 3 (MSR_LBAR_FLSH3) with bit 34 = 0 (I/O mapped) Note: Flash Chip Selects [3:0] can be programmed for I/O or a memory space. See Section 4.6.1.3 "Memory LBARs". 4.6.1.3 Memory LBARs This discussion applies to the following LBARs: • MSR 51400009h: KEL from USB Host Controller 1 (MSR_LBAR_KEL1) • MSR 51400010h: Flash Chip Select 0 (MSR_LBAR_FLSH0) with bit 34 = 1 (memory mapped) • MSR 51400011h: Flash Chip Select 1 (MSR_LBAR_FLSH1) with bit 34 = 1 (memory mapped) • MSR 51400012h: Flash Chip Select 2 (MSR_LBAR_FLSH2) with bit 34 = 1 (memory mapped) • MSR 51400013h: Flash Chip Select 3 (MSR_LBAR_FLSH3) with bit 34 = 1 (memory mapped) • MSR 5140000Ah: KEL from USB Host Controller 2 (MSR_LBAR_KEL2) Note: The Flash Chip Selects [3:0] can be programmed for an I/O space or a Memory space. The I/O LBAR works just like the Fixed style, except the size of the IO_MASK has been expanded to cover the entire address range (see Figure 4-12). In the Fixed style, the IO_MASK applies to bits [15:12] but for Variable style, the IO_MASK applies to bits [15:4]. If all bits are set, then the target size is 16 bytes and base address bits [15:4] determine the base. Base bits [3:0] are a “don't care” and are effectively forced to zero by the hardware. Thus, the smallest I/O target is 16 bytes. As the LSBs of IO_MASK are cleared, the “target space” expands. For example, assume a 64-byte device is desired in I/O space. The IO_MASK = FFCh, base address bits [15:6] are programmed to the desired base, and base address bits [5:4] are cleared (see Rule on page 97). For memory space, the LBAR works exactly like the Variable style (see Figure 4-13), except that clearing the LSBs of the MEM_MASK begins to make sense. For example, assume there is a 64 kB external ROM that is going to be connected to Flash Chip Select 0. Such a device needs address bits [15:0]. The MEM_MASK would normally be programmed to FFFF0h and base address bits [31:16] would be programmed to the desired base. The values in base address [15:12] would be cleared because the associated mask bits are cleared (see Rule on page 97). Lastly, the memory target can not be smaller than 4 kB. ADDR[15:4] I/O_MASK [15:4] Compare [15:4] BASE_ADDR Hit Figure 4-12. I/O Space LBAR - Variable Target Size ADDR[31:12] MEM_MASK [31:12] Compare [31:12] BASE_ADDR Note: Hit The memory mask is always 20 bits, which is equal to the number of memory base address bits. Figure 4-13. Memory Space LBAR www.national.com 98 Revision 0.8 Geode™ CS5535 DIVIL Functional Description (Continued) 4.6.1.4 Miscellaneous Block Special cycles are sent to the Miscellaneous block. They are decoded as given in Table 4-10. Note that the Halt special cycle depends on the value of the SPEC_CYC_MD bit in MSR_LEG_IO (MSR 51400014h[28]). Soft IRQ and Soft Reset MSRs are decoded within the Miscellaneous block. Each block in the Diverse Device generates an output to the DIVIL. The DIVIL DOM has a port for each of the functions and is responsible for selecting between them. 4.6.2 Standard MSRs This block contains the Standard GeodeLink Device MSRs and their associated logic. These standard MSRs are: Capabilities, Master Configuration, SMI Control, Error Control, Power Management, and Diagnostics. The Capabilities, Master Configuration, and Diagnostic MSRs are “passive” in that they contain values that have an effect elsewhere. The other MSRs have various “active” bits that are set and cleared via hardware/software interactions. Table 4-10. Special Cycle Decodes Cycle Type Write Address 00h Function Shutdown Action Send shutdown pulse to MSR_ERROR. Send shutdown pulse to MSR_SMI. If RESET_SHUT_EN (MSR 51400014h[31]) is high, send reset pulse to power management indicating shutdown reset. SPEC_CYC_MD (MSR 51400014h[28]) = 0 Write 01h Halt Send halt pulse to MSR_SMI. SPEC_CYC_MD (MSR 51400014h[28]) = 1 Write 02h All other values All other values Read 00h Halt x86 Special Not Defined Interrupt Ack Send halt pulse to MSR_SMI. Discard with no side effects. Discard with no side effects. Send cycle to PIC. GeodeLink Adapter generates back-to-back bus cycles. All other values Not Defined Return zero with no side effects. Revision 0.8 99 www.national.com Geode™ CS5535 4.7 PROGRAMMABLE INTERVAL TIMER Each counter has its output signal, whose shape is dependent upon the counter’s operational mode. The Control register loads the counters and controls the various modes of operation. This Control register controls the operation mode of the control logic (counter state machine), which in turn controls the counter, the high-order and low-order output latches. A status latch is also present in the 8254 and is used to output status information. Features include: • Comprised of three 16-bit wide counters. • Supports read-back and counter latch commands. • Supports six modes of counting. • Allows several counter latch commands in parallel with the read-back command. The Programmable Interval Timer (PIT) generates programmable time intervals from the divided clock of an external clock signal of a crystal oscillator. The PIT (8254) has six modes of operation. Figure 4-14 shows the block diagram of the PIT and its connectivity to the Local bus. The 8254 is comprised of three independently programmable counters. Each counter is 16 bits wide. A 14.318 MHz external clock signal (from a crystal oscillator or an external clock chip) is divided by 12 to generate 1.19 MHz, which is used as a clocking reference for these three counters. Each counter is enabled or triggered with its GATE signal. Based on the counting mode, the counter concerned is activated by a high level or a low-to-high transition of its GATE signal. CPU GeodeLink Adapter Local Bus 14 MHz Control Register PIT Shadow Register Divide By 12 c Timer 0 Timer 1 Timer 2 Figure 4-14. PIT Block Diagram www.national.com 100 c Revision 0.8 Geode™ CS5535 PIT Functional Description (Continued) 4.7.1 Programming the 8254 PIT Programming of the 8254 PIT is initiated by first writing one control word via I/O Address 043h into the PIT Mode Control Word register. It is followed by writing one or two data bytes via the I/O address of the intended counter. If the Control register is loaded once, the counters may be overwritten with different values without accessing the Control register again. Table 4-11 lists the I/O addresses of the various registers. 0 of the Control Word register defines the binary or BCD counting format. The maximum loadable count value is not FFFFh (binary counting) or 9999 (BCD counting), but 0. On the next CLK pulse the counter concerned jumps to FFFFh or 9999. Once the value is decreased to 0 again, it outputs a signal according to the programmed mode. Therefore, the value 0 corresponds to 2^16 for binary counting and 10^4 for BCD counting. Read from the Counters There are three options for reading a counter in the 8254 PIT: 1) 2) 3) Counter Latch command Read-back (read-status) command Direct Read Table 4-11. 8254 PIT Register Ports I/O Address 040h 041h 042h 043h Register Counter 0 Counter 1 Counter 2 Control Word Access Type Read/ Write Read / Write Read / Write Write The Control register in the 8254 PIT is write-only, but certain control information can be determined by the readback (read-status) command. 4.7.1.1 Write to the Counters To load a counter with new values, a control word needs to output that defines the intended counter, number and type of bytes to write, the counting mode and the counting format. Bits [5:4] of the Control Word register (see Section 5.8.2.7 on page 329) indicate whether low-order or highorder or both are going to be written. If low-order or highorder counter byte only is specified to be written, then only that byte can be read during a read access. According to bits [5:4] of the Control Word register, one needs to write either the low-order or the high-order or both into the counter after passing the control word. If bits [5:4] of the Control Word register is 11, then a low-order byte needs to be written first, followed by a high-order byte. For small counting values or counting values that are multiples of 256, it is sufficient to pass the low-order or high-order counter byte. Bits [3:1] of the Control Word register define the counting mode of the counter selected by bits [5:4]. Bit 7 6 5 0 4 0 To read a counter, the third option (Direct Read) should not be used. The Counter Latch command or Read-back command should be used to transfer the current state of the counter into its output latches. One or two successive read counter instructions for the port address of the counter concerned reads these latches. If only the low-order or highorder byte was written when the counter was loaded with the initial counting value, then read the current counting value of the initially written byte by a single read counter instruction. If both the low-order and high-order counter bytes are written previously, then to read the current counter value, two read counter instructions are needed. The 8254 PIT returns the low-order byte of the 16-bit counter with the first read counter instruction, and then the high-order byte with the second read counter instruction. If the content of the counter has been transferred once by a counter latch command into the output latches, then this value is held there until the CPU executes one or two counter read instructions, or until the corresponding counter is reprogrammed. Successive counter latch commands are ignored if the output latches haven’t been read before. Figure 4-15 shows the format of the control word for the counter latch command. 3 x 2 x 1 x 0 x Bits [7:6] = Select counter to latch Figure 4-15. PIT Counter Latch Command Format Revision 0.8 101 www.national.com Geode™ CS5535 PIT Functional Description (Continued) The read-back command present in the 8254 PIT is used to determine the current counter value and its status like counting format, the counting mode, the low-order or highorder byte or both being read or written, and the status of its output. Figure 4-16 shows the format of the read-back command. The two most significant bits define the readback command with their value 11b. CT and ST indicate that the value and the status of the counter are to be determined respectively. The C0-C2 bits define the counter whose value or status is to be determined. With the readback command, several counter latch commands can be issued in parallel by indicating several counters simultaneously with the C0-C2 bits. The 8254 then behaves as if several counter latch commands have been issued individually, and transfers the individual count values into the output latches of each counter. All successive counter latch 7 1 6 1 5 CT 4 ST commands, whether issued by its own counter or a next read-back command, are ignored if the counter concerned has not been read by counter read instructions. To determine the programmed mode of a particular counter, set CT = 1 and ST = 0. The read-back command latches the current mode and provides a status byte (see Figure 4-17) at the port address of the counter concerned. This status byte is fetched by a counter read instruction. The PIN bit indicates the current status of the concerned counter’s output pin. If PIN = 1, then the counter output is at logic 1, else at logic 0. Bit 0 shows whether the last written counter value has already been transferred to the counter. Not before zero = 0 is it meaningful to read back the counter value. 3 C2 2 C1 1 C0 0 x CT: Determine count value of selected counter. 0 = Determine count value. 1 = Do not determine count value. ST: Determine status of selected counter. 0 = Determine count status. 1 = Do not determine count status. C2, C1, C0: Counter selection. 0 = Counter not selected. 1 = Counter selected. Figure 4-16. PIT Read-Back Command Format 7 PIN 6 LOAD 5 LH 4 3 2 MODE 1 0 BCD PIN: Status of counter output pin: 0 = Output pin low. 1 = Output pin high. LOAD: Is counter loaded with a start value? 0 = Counter loaded, count value can be read. 1 = Counter not yet loaded, count value cannot be read. LH: Corresponds to bits [5:4] of the Control Word register. MODE: Corresponds to bits [3:1] of the Control Word register. BCD: Corresponds to bit 0 of the Control Word register. Figure 4-17. PIT Status Byte Format www.national.com 102 Revision 0.8 Geode™ CS5535 4.8 PROGRAMMABLE INTERRUPT CONTROL 4.8.1 Mapper and Masks This block maps and masks up to 62 interrupt sources to 60 discrete Extended PIC (XPIC) inputs. The sources are organized into four groups: 1) 2) 3) 4) 15 Primary pre-defined inputs (see Table 4-12) 15 LPC inputs pre-defined (see Table 4-12) 16 Unrestricted Y inputs (see Table 4-13) 16 Unrestricted Z inputs (see Table 4-14) The Programmable Interrupt Control subsystem (PIC) is illustrated in Figure 4-18. The major modules are the Mapper and Masks (MM), Extended PIC (XPIC), and Legacy 8259A PIC (LPIC). Features • Two x86 compatible 8259As • 15-Level Priority Controller • Programmable Interrupt Modes • Individual Request Mask Capability • Individual Edge/Level Controls • Complete 8259A state read back via shadow registers • Mapper routes 62 inputs to 15 legacy interrupts and one Asynchronous System Management Interrupt (ASMI) • All 62 inputs individually maskable and status readable (MSRs 51400020h-51400027h or PIC I/O Offsets 00h1Ch, see Section 5.9.1 on page 333) The outputs are organized into 16 groups of four signals each, except groups 0 and 2; they have two signals each. Each group is called an Interrupt Group (IG). Each predefined input is mapped to a specific IG. Each unrestricted input can be mapped to any IG except IG0. Regardless of mapping, any interrupt source can be masked to prevent participation in the interrupt process. Once the input to output map is established along with the mask values, signal flow from input to output is always completely combinational. Primary Input 0 Primary Input 1 Primary Input 3 Primary Input 4 : Primary Input 15 LPC Input 0 LPC Input 1 LPC Input 3 LPC Input 4 : LPC Input 15 Unrestricted Y Input 0 Unrestricted Y Input 1 Unrestricted Y Input 2 Unrestricted Y Input 3 : Unrestricted Y Input 15 Unrestricted Z Input 0 Unrestricted Z Input 1 Unrestricted Z Input 2 Unrestricted Z Input 3 : Unrestricted Z Input 15 IG0 (Note) IG1 IG2 (Note) IG3 IG4 IG5 IG6 Mapper and Masks (MM) IG7 IG8 IG9 IG10 IG11 IG12 IG13 IG14 IG15 Extended PIC (XPIC) IRQ0 IRQ1 (IRQ2) IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 Legacy 8259A PICs (LPIC) INTR ASMI Note: The outputs are organized into 16 groups of four signals each, except IG0 and IG2; they have two signals each. Figure 4-18. PIC Subsystem Revision 0.8 103 www.national.com Geode™ CS5535 PIC Functional Description (Continued) Table 4-12. IRQ Map - Primary and LPC Input # Input 0 Input 1 N/A Input 3 Input 4 Input 5 Input 6 Input 7 Input 8 Input 9 Input 10 Input 11 Input 12 Input 13 Input 14 Input 15 Primary Sources 8254 Timer IRQ KEL IRQ1 None (Slave Controller) Reserved - Grounded Reserved - Grounded Reserved - Grounded Reserved - Grounded Reserved - Grounded RTC Periodic IRQ Reserved - Grounded Reserved - Grounded Reserved - Grounded KEL IRQ12 Float Point Error IRQ Primary IDE Channel IRQ Reserved - Grounded LPC Sources LPC IRQ0 LPC IRQ1 None LPC IRQ3 LPC IRQ4 LPC IRQ5 LPC IRQ6 LPC IRQ7 LPC IRQ8 LPC IRQ9 LPC IRQ10 LPC IRQ11 LPC IRQ12 LPC IRQ13 LPC IRQ14 LPC IRQ15 Legacy IRQ 8254 Timer Keyboard None UART UART Parallel Port 2 Floppy Parallel Port1 RTC Undefined Undefined Undefined Mouse FPU Primary IDE Secondary IDE Table 4-13. IRQ Map - Unrestricted Sources Y Unrestricted Y Input 0 Input 1 Input 2 Input 3 Input 4 Input 5 Input 6 Input 7 Input 8 Input 9 Input 10 Input 11 Input 12 Input 13 Input 14 Input 15 Source Software Generated IRQ USB1 IRQ USB2 IRQ RTC Alarm Audio IRQ Power Management SCI NAND Flash Ready NAND Flash Distraction Reserved, Grounded Reserved, Grounded Reserved, Grounded Reserved, Grounded SMB Controller IRQ KEL Emulation IRQ UART 1 IRQ UART 2 IRQ This is a pulse from the RTC. Must use edge triggered interrupt, that is, level interrupt will not work. OR of all audio codec interrupts and master interrupts. OR of all possible power management System Control Interrupts (SCIs). Ready to perform NAND write or read. NOR access occurred during NAND operation causing a NAND abort or distraction. Comment www.national.com 104 Revision 0.8 Geode™ CS5535 PIC Functional Description (Continued) Table 4-14. IRQ Map - Unrestricted Sources Z Unrestricted Z Input 0 Input 1 Input 2 Input 3 Input 4 Input 5 Input 6 Input 7 Input 8 Input 9 Input 10 Input 11 Input 12 Input 13 Input 14 Input 15 Source MFGPT_Comp_1A MFGPT_Comp_1B MFGPT_Comp_1C MFGPT_Comp_1D MFGPT_Comp_2A MFGPT_Comp_2B MFGPT_Comp_2C MFGPT_Comp_2D GPIO Interrupt 0 GPIO Interrupt 1 GPIO Interrupt 2 GPIO Interrupt 3 GPIO Interrupt 4 GPIO Interrupt 5 GPIO Interrupt 6 GPIO Interrupt 7 Comment OR of MFGPT_Comp_1 0 and 4. OR of MFGPT_Comp_1 1 and 5. OR of MFGPT_Comp_1 2 and 6. OR of MFGPT_Comp_1 3 and 7. OR of MFGPT_Comp_2 0 and 4. OR of MFGPT_Comp_2 1 and 5. OR of MFGPT_Comp_2 2 and 6. OR of MFGPT_Comp_2 3 and 7. From GPIO Interrupt/PME Mapper. From GPIO Interrupt/PME Mapper. From GPIO Interrupt/PME Mapper. From GPIO Interrupt/PME Mapper. From GPIO Interrupt/PME Mapper. From GPIO Interrupt/PME Mapper. From GPIO Interrupt/PME Mapper. From GPIO Interrupt/PME Mapper. 4.8.2 Extended PIC (XPIC) For each of 16 input IGs of four signals each (except IG0 and IG2 with two signals each), XPIC provides a four input “OR”. Thus, 16 outputs are formed. A software readable XPIC Input Request Register (XIRR) is available to read the status of the 64 inputs. Outputs [0:1] and [3:15] are connected directly to the corresponding inputs on LPIC. Output 2 can be used as an ASMI. 4.8.3 Legacy PIC (LPIC) The LPIC consists of two 8259A compatible Programmable Interrupt Controllers (PICs) connected in Cascade mode through interrupt signal two (see Figure 4-19). LPIC contains mechanisms to: 1) Mask any of the 15 inputs via an Interrupt Mask Register (IMR). 2) 3) 4) Determine the input request status via an Interrupt Request Register (IRR). Generate an interrupt request (INTR) to the processor when any of the unmasked requests are asserted. Provide an interrupt vector to the processor as part of an interrupt acknowledge operation based on request priorities. Determine which requests are acknowledged but not yet fully serviced, via an In-Service Register (ISR). 5) In addition to the above 8259A features, there are two registers to control edge/level mode for each of the interrupt inputs as well as shadow registers to obtain the values of legacy 8259A registers that have not been historically readable. D0-D7 8259A Slave INTA INT D0-D7 INTA 8259A Master INT IR0 IR1 IR2 IR3 IR4 IR5 IR6 IR7 IR0 IR1 IR2 IR3 IR4 IR5 IR6 IR7 IRQ8 IRQ10 IRQ12 IRQ14 IRQ9 IRQ11 IRQ13 IRQ15 IRQ0 IRQ2 IRQ4 IRQ6 IRQ1 IRQ3 IRQ5 IRQ7 Note: Cascading the 8259A PICs. The INT output of the slave is connected to the IRQ2 input of the master. Figure 4-19. Cascading 8259As for LPIC Revision 0.8 105 www.national.com Geode™ CS5535 PIC Functional Description (Continued) As illustrated in Figure 4-20, the blocks that make up the 8259A PIC are: • Read/Write Control Logic • Interrupt Request Register (IRR) • In-Service Register (ISR) • Interrupt Mask Register (IMR) • Priority Resolver • Interrupt Sequence • Data Bus Buffer • Cascade Buffer/Comparator Read/Write Control Logic The function of this block is to accept commands from the CPU. It contains the four Initialization Command Word registers, ICW1-ICW4, and three Operation Command Word registers, OCW1-OCW3, that can be programmed to operate in various modes. IRR, ISR, and IMR Three registers are available to handle interrupts in the PIC: Interrupt Request Register (IRR), In-Service Register (ISR), and Interrupt Mask Register (IMR). Each of the three registers is eight bits wide, where every bit corresponds to one of the IR0-IR7 input lines. Priority Resolver The priority resolver block manages the hardware requests according to their priority. As several bits may be set in the IRR simultaneously, the priority encoder passes only the highest priority bit; ordered in priority 0 through 7 (0 being the highest). Interrupt Sequence The INT output goes directly to the CPU interrupt input. When an INT signal is activated, the CPU responds with an Interrupt Acknowledge access that is translated to two pulses on the INTA input of the PIC. At the first INTA pulse the highest priority IRR bit is loaded into the corresponding ISR bit, and that IRR bit is reset. The second INTA pulse instructs the PIC to present the 8-bit vector of the interrupt handler onto the data bus. Data Bus Buffer Control words and status information are transferred through the data bus buffer. Cascade Buffer/Comparator This functional block stores and compares the IDs of the PICs. INTA INT D7-D0 Data Bus Buffer Control Logic RD WR A0 CS Read/ Write Logic In-Service Register (ISR) Priority Resolver Interrupt Request Register (IRR) IR0 IR1 IR2 IR3 IR4 IR5 IR6 IR7 CAS0 CAS1 CAS2 SP/EN Internal Bus Cascade Buffer/ Comparator Interrupt Mask Register (IMR) Figure 4-20. PIC 8259A Block Diagram www.national.com 106 Revision 0.8 Geode™ CS5535 PIC Functional Description (Continued) 4.8.3.1 Interrupt Sequence There are three registers in the PIC that control the interrupt requests: Interrupt Request Register (IRR), Interrupt Service Register (ISR), and Interrupt Mask Register (IMR). The eight interrupt lines IR0-IR7 are connected to the IRR. The peripheral that requests an interrupt raises the signal at the corresponding IR0-IR7 inputs, which sets the corresponding bit in the IRR. Several peripheral devices can issue interrupt requests at the same time. The PIC gates these requests under the Interrupt Mask register and under the priority of any interrupt service routine already entered (using the ISR), and activates the PIC’s output INTR to the CPU. The CPU acknowledges the INTR, generating two INTA pulses. On the first, the priority encoder transfers (clears) the highest-priority enabled bit in the IRR to the corresponding bit in the ISR (sets). Also, the two PICs use their Cascade connections to decide which one will be selected to respond further. On the second INTA pulse, the selected PIC presents the 8-bit pointer (called as vector data) onto the data bus. The CPU reads this pointer as the number of the interrupt handler to call. Software writes a command (EOI) at the end of the interrupt subroutine, which clears the appropriate ISR bit. Initialization and Programming Two types of command words are generated by the CPU to program the PIC: 1) Initialization Command Word (ICW): The PIC is first initialized by four ICWs (ICW1-ICW4) before any normal operation begins. The sequence is started by writing Initialization Command Word 1 (CW1). After ICW1 has been written, the controller expects the next writes to follow in the sequence ICW2, ICW3, and ICW4 if it is needed. Operation Command Word (OCW): Using these three OCWs (OCW1-OCW3), the PIC is instructed to operate in various interrupt modes. These registers can be written after the initialization above. Table 4-15. 8259A PIC I/O Addresses and I/O Data I/O Address IRQ0-IRQ7 (Master) 020h I/O Address IRQ8-IRQ15 (Slave) 0A0h Read Data IRR ISR Write Data ICW1 OCW2 OCW3 021h 0A1h IMR ICW2 ICW3 ICW4 OCW1 (IMR) 4.8.3.2 Interrupt Modes Fully Nested Mode The interrupt requests are ordered in priority from 0 through 7. The highest priority request is processed and its vector data placed on the bus. The corresponding ISR bit is set until the trailing edge of the last INTA. While the ISR bit is set, all other interrupts of the same or lower priority are inhibited, while higher levels will be acknowledged only if the CPU’s internal interrupt enable flip-flop has been re-enabled through software. End of Interrupt (EOI) Mode The ISR bit can be reset by a command word that must be issued to the PIC before returning from a service routine. EOI must be issued twice if in cascade mode, once for the master and once for the slave. There are two forms of EOI: Specific and Non-Specific. When a non-specific EOI is issued, the PIC automatically resets the ISR bit corresponding to the highest priority level in service. A non-specific EOI can be issued with OCW2 (EOI = 1, SL = 0, R = 0). A specific EOI is issued when a mode is used that may disturb the fully nested structure and the PIC might not be able to determine the last interrupt level acknowledged. A specific EOI can be issued with OCW2 (EOI = 1, SL = 1, R = 0, and L0-L2 is the binary level of the ISR bit to be reset). Automatic End of Interrupt (AEOI) Mode The PIC automatically performs a non-specific EOI at the trailing edge of the last INTA pulse. This mode is not supported in the CS5535. 2) ICWs and OCWs must be programmed before operation begins. Since both the PICs are cascaded, the ICW3 of the master PIC should be programmed with the value 04h, indicating that the IRQ2 input of the master PIC is connected to the INT output of the slave PIC, rather than the I/O device. This is part of the system initialization code. Also, ICW3 of the slave PIC should be programmed with the value 02h (slave ID) as that corresponds to the input on the master PIC. For accessing the PIC’s registers, two ports are available for the master and slave. Table 4-15 lists the addresses and read/write data for these registers. Revision 0.8 107 www.national.com Geode™ CS5535 PIC Functional Description (Continued) Automatic Rotation Mode In cases where a number of IRQs have equal priority, the device that has been serviced, will receive the lowest priority. So now that device, if requesting another interrupt, must wait until the other seven devices have been serviced. There are two ways to accomplish automatic rotation using OCW2: • Rotation on the non-specific EOI command (R = 1, SL = 0, EOI = 1). • Rotation in automatic EOI mode, which is set by (R = 1, SL = 0, EOI = 0) and cleared by (R = 0, SL = 0, EOI = 0). Specific Rotation Mode Priorities can be changed by programming the bottom priority, which fixes all other priorities. For example, if IR5 is programmed as the bottom priority device, then IR6 will have the highest priority. The command is issued to OCW2 (R = 1, SL = 1, and L0-L2 is the binary priority level code of the bottom priority device). Special Mask Mode In this mode, when a mask bit is set in OCW1, it inhibits further interrupts at that level and enables interrupts from all other levels (lower as well as higher) that are not masked. The special mask mode is set (SSMM = 1, SMM = 1) and cleared (SSMM = 1, SMM = 0) by OCW3. 4.8.4 PIC Subsystem Operation From reset, the PIC subsystem comes up in legacy mode. The “Primary” mapper and mask inputs connect directly to LPIC and all other interrupt sources are masked off. While there are a number of different ways to use the PIC Subsystem, the discussions that follow assume a mix of “level” and “edge” interrupt inputs. The first discussion assumes the OS schedules the “work” of the interrupt service after a brief interrupt service routine. The second discussion assumes the OS performs the “work” real-time in the interrupt service routine. Assume the mapper and masks have been established as desired. “Level” interrupts can be shared, but “edge” interrupts cannot. This means an XPIC “level” output can be driven by up to four mapper and masks inputs. Further, this means an XPIC “edge” output can only be driven by one mapper and mask input. Assume all edge interrupts generate a low-to-high edge to indicate an interrupt. Assume active low interrupts are inverted outside the PIC subsystem as needed; that is, all MM inputs are active high. An external PCI bus uses active low interrupts that can be shared in an open-collector wired “OR” fashion. This is OK. On-chip, the interrupt sense is inverted. Lastly, note that for the edge interrupts the edge must remain high until the interrupt acknowledge action. Assume LPIC is initialized as follows: ;Set Initialization Command Words (ICWs) ;All values are in hex ;PIC #1 (Master) out 20, 11 ; ICW1 - Edge, Master, ICW4 needed out 21, 8 ; ICW2 - Interrupt vector table offset is 8 out 21, 4 ; ICW3 - Master level 2 out 21, 1 ; ICW4 - Master, 8086 mode out 21, ff ; mask all IRQs ;PIC #2 (Slave) out a0, 11 ; ICW1 - Edge, Slave ICW4 needed out a1, 70 ; ICW2 - Interrupt vector table offset 70 out a1, 2 ; ICW3 - Slave Level 2 out a1, 1 ; ICW4 - Slave, 8086 mode out a1, ff ; mask all IRQs ;Use Operation Control Words (OCWs) during interrupt service Thus, the LPIC 8259As all start in edge mode. This is followed by writes to the individual edge level registers at 4D0h (interrupts 0-7) and 4D1h (interrupts 8-15) to establish level mode for all level inputs. Note that IRQ0 and IRQ2 can not be put in level mode. Writing 0FFh to 4D0h will read back 0FAh. Scheduled Interrupts Approach The following set of events would be typical. Assume the processor has maskable interrupts enabled: 1) One or more interrupts are generated in the system. These set the associated bits in the LPIC Interrupt Request Register (IRR). The maskable interrupt signal (INTR) is asserted by the LPIC and interrupts the processor. INTR is an active high level. The processor generates an interrupt acknowledge bus cycle that flows through the GeodeLink system as a single BIZZARO packet. When it reaches the Diverse Logic, it is converted to the two cycle interrupt acknowledge sequence expected by the LPIC. The acknowledge operation returns an interrupt vector to the processor that is used to call the appropriate interrupt service routine. Processor interrupts are now disabled at the processor. The acknowledge operation also selects the highest priority interrupt from the IRR and uses it to set one bit in the LPIC Interrupt Service Register (ISR). Each acknowledge operation always sets a single ISR bit. 2) 3) 4) 5) www.national.com 108 Revision 0.8 Geode™ CS5535 PIC Functional Description (Continued) 6) The acknowledge operation generally de-asserts INTR if there are no higher priority interrupts. However, it is possible that another interrupt is generated in the system anytime after the acknowledge. Any new interrupts will appear in the IRR. If they are higher priority than the current interrupt, then the INTR is reasserted. Since interrupts are disabled at the processor, INTR remaining high or going high during the interrupt service routine has no effect until interrupts are explicitly enabled again at the processor by the interrupt service routine or implicitly enabled when a return-from-interrupt is executed. The interrupt service routine masks off the interrupt in the LPIC Interrupt Mask Register (IMR). The interrupt service routine interacts with the OS to schedule calls to the drivers associated with the interrupt. If level, one or more drivers could be associated. If edge, only one driver could be associated. The service executes a return-from-interrupt. The OS calls the drivers associated with the interrupt as scheduled. Each driver checks its associated device to determine service needs. If no “need”, the driver returns to the OS without any action. If “need”, the driver performs the interrupt action, clears the interrupt source, and returns to the OS. When all the scheduled drivers have been called, the OS un-masks the interrupt at LPIC. Note that the individual drivers do not directly interact with LPIC. 10) The interrupt service routine disables interrupts at the processor and prepares to return to a lower priority service routine or the initially interrupted process. It writes an end-of-interrupt (EOI) command (020h) to the LPIC OCW2 register. This clears the highest priority ISR bit. One EOI always clears one ISR bit. The service routine executes a return-from-interrupt that enables interrupts again at the processor. 11) It is possible for INTR to assert from the same interrupt as soon as EOI is written. The initial interrupt acknowledge action copies the bit to the ISR. For edge mode, the initial interrupt acknowledge action also clears the bit in the IRR. For level, IRR always reflects the level of the signal on the interrupt port. After the interrupt acknowledge for edge mode, another edge could set the bit in the IRR before the EOI. If in level mode, another shared interrupt could be keeping the input high or potentially the initial interrupt has occurred again, since the driver cleared the source but before the EOI. At any rate, if IRR is high at EOI, INTR will immediately assert again. Hence, the need to disable interrupts at the processor in step 10 above before writing the EOI. 12) Eventually, all system events are serviced and control returns to the originally interrupted program. Note that the above procedure did not use the Interrupt Mask Register (IMR), but variations on the above could have. Lastly note, as in the first discussion, drivers do not directly interact with the LPIC. 7) 8) Note in the above procedure that there is not a need to handle “level” and “edge” types separately as long as “edge” types are not shared. Real-Time Interrupts Approach The following discussion assumes the “work” associated with the interrupt is performed in the interrupt service routine. The setup and steps 1 through 6 are the same: 7) If there is only one driver associated with the interrupt, it is called at this point. If more than one driver (shared), then they could be called in order to determine “need”. Alternately, the XIRR could be read to directly identify the source. Depending on the event being serviced and the OS policies, the processor will enable interrupts again at some point. Potentially, this will generate another higher priority interrupt causing the current service routine to nest with another interrupt acknowledge cycle. For a nest operation, an additional bit will be set in the ISR. Eventually, the highest priority service routine is running and INTR is de-asserted. The service calls the driver(s) associated with the interrupt. The driver completes the interrupt “work”, clears the interrupt at its system source, and returns to the interrupt service routine. 8) 9) Revision 0.8 109 www.national.com Geode™ CS5535 4.9 KEYBOARD EMULATION LOGIC • Produces IRQ and ASMI outputs. • Employs a clock control logic for power management purposes. • No USB controller required for KEL to operate. 4.9.1 Keyboard Emulation and Port A The Keyboard Emulation Logic (KEL) with Port A is illustrated in Figure 4-21. Strictly speaking, these are separate functions. However, since they both effect the FA20# (Force processor Address bit 20 to zero when low), the two functions are implemented together. The Keyboard Emulation Logic is the most complex and is discussed first. The Keyboard Emulation Logic (KEL) provides a virtual 8042 keyboard controller interface that is used to map nonlegacy keyboard and mouse sources to this traditional interface. For example, Universal Serial Bus (USB) sources are “connected” to this interface via System Management Mode (SMM) software. It also allows mixed environments with one LPC legacy device and multiple new (USB) devices. It produces IRQ and ASMI outputs. Features • Provides a virtual 8042 keyboard controller interface. • Allows mixed environments. 14 MHz Reset Local Bus Clock USB1_SOF USB2_SOF 1 kHz Clock LPC_IRQ1 LPC_IRQ12 14 MHz to 1 kHz KEL X Control Keyboard Emulator Logic (KEL) IRQ 1 (to PIC Subsystem) IRQ 12 (to PIC Subsystem) EmulationInterrupt ASMI EmulationEnable SnoopEnable FA20# INIT Keyboard A20 Keyboard INIT Port A A20 Port A Port A Enable Port A Write & Read * HCE Control Port 060h and Port 064h Write * HCE Input Port 060h Read * HCE Output Port 064h Read * 32 32 * Read-Back Multiplexer is not shown IN OUT OUT IN HCE Status 8 8 * * Local Bus Data Local Bus Data Figure 4-21. KEL Block Diagram www.national.com 110 Revision 0.8 Geode™ CS5535 KEL Functional Description (Continued) 4.9.2 Keyboard Emulation Overview The purpose of the KEL is to model the legacy 8042 keyboard/mouse controller interfaced via legacy I/O Addresses 060h and 064h (also known as Ports 60 and 64). This hardware and supporting processor System Management Mode (SMM) software are designed to support systems that do not have a true PS/2-compatible keyboard and/or mouse interface, but those that have alternative devices performing the equivalent function. Generally, the alternative device is a keyboard or mouse off a USB (Universal Serial Bus) port, but it need not be. Due to the origins of the hardware to be explained shortly, this discussion generally assumes a USB alternative device, but this is not a requirement from a hardware perspective. The KEL closely models the keyboard emulation hardware detailed in the USB OpenHost Controller Interface specification (OHCI). It is specifically designed to be software compatible with this model. In the USB model, it is part of the USB “Host Controller”, but is logically separate from it. The discussion and description that follows is taken from the OHCI specification, but with modifications to reflect the Geode CS5535 specific implementation. To support applications and drivers in non-USB-aware environments (e.g., DOS), a peripheral subsystem needs to provide some hardware support for the emulation of a PS/2 keyboard and/or mouse by their USB equivalents (alternative devices). For OHCI, this emulation support is provided by a set of registers that are controlled by code running in SMM. Working in conjunction, this hardware and software produces approximately the same behavior-toapplication code as would be produced by a PS/2-compatible keyboard and/or mouse interface. When data is received from the alternative device, the emulation code is notified and becomes responsible for translating the alternative device keyboard/mouse data into a data sequence that is equivalent to what would be produced by a PS/2-compatible keyboard/mouse interface. The translated data is made available to the system through the legacy keyboard interface I/O Addresses 060h and 064h. Likewise, when data/control is to be sent to the alternative device (as indicated by the system writing to the legacy keyboard interface), the emulation code is notified and becomes responsible for translating the information into appropriate data to be sent to the alternative device. On the PS/2 keyboard/mouse interface, a read of I/O Address 060h returns the current contents of the keyboard output buffer; a read of I/O Address 064h returns the contents of the keyboard status register. An I/O write to I/O Addresses 060h and 064h puts data into the keyboard input buffer (data is being input into the keyboard subsystem). When emulation is enabled, reads and writes of I/O Addresses 060h and 064h are captured in the KEL HceOutput, HceStatus, and/or HceInput operational registers. The KEL described here supports a mixed environment in which either the keyboard or mouse is implemented as an alternative device and the other device is attached to a standard PS/2 interface. The following sub-sections use the term “alternate device interrupt”. This is an ASMI or IRQ as appropriate for the device; for example the USB can generate either an ASMI or IRQ. The KEL generates a separate ASMI or IRQ. 4.9.3 Theory - Keyboard / Mouse Input When data is received from the alternative device, the emulation code is notified with an alternate device interrupt and translates the keyboard/mouse data into an equivalent PS/2-compatible sequence for presentation to the application software. For each byte of PS/2-compatible data that is to be presented to the applications software, the emulation code writes to the HCE_Output register. The emulation code then sets the appropriate bits in the HCE_Status register (normally, OutputFull is set for keyboard data and OutputFull plus AuxOutputFull for mouse data). If keyboard/mouse interrupts are enabled, setting the HCE_Status register bits causes the generation of an IRQ1 for keyboard data and IRQ12 for mouse data. The emulation code then exits and waits for the next alternate device interrupt. When the host CPU exits from SMM, it can service the pending IRQ1/IRQ12. This normally results in a read from I/O Address 060h. When I/O Address 060h is read, the KEL intercepts the access and returns the current contents of HCE_Output. The KEL also clears the OutputFull bit in HCE_Status and de-asserts IRQ1/IRQ12. If the emulation software has multiple characters to send to the application software, it sets the CharacterPending bit in the HCE_Control register. This causes the KEL to generate an ASMI at the beginning of the next frame a time after the application read from I/O Address 060h (HCE_Output.). 4.9.4 Theory - Keyboard Output Keyboard output is indicated by application software writing data to either I/O Address 060h or 064h. Upon a write to either address, the KEL captures the data in the HCE_Input register and, except in the case of a FA20# (Force processor Address bit 20 to zero when low) sequence, updates the HCE_Status register’s InputFull and CmdData bits. When the InputFull bit is set, a KEL ASMI is generated at the beginning of the next frame. Upon receipt of the KEL ASMI, the emulation software reads HCE_Control and HCE_Status to determine the cause of the emulation interrupt and performs the operation indicated by the data. Generally, this means putting out data to the alternate device. 4.9.5 Emulation Events Emulation Events (EEs) are caused by reads and writes of the emulation registers. EEs generated by the emulation hardware are steered by the KEL to either an ASMI or an Emulation Interrupt. Steering is determined by the EE Routing (EER) bit of the Keyboard Emulation Logic Control Register (KELX_CTL) (MSR 5140001Fh[1]). Historically, EEs for data coming from the keyboard/mouse are generated on USB frame boundaries. The KEL is independent of the USB logic, but uses USB frame boundaries for backward compatibility. Alternately, an independent 1 Revision 0.8 111 www.national.com Geode™ CS5535 KEL Functional Description (Continued) ms counter can be used (MSR 5140001Fh[3:2]). At the beginning of each frame, the conditions that define asynchronous EEs are checked and, if an EE condition exists, the EE is signaled to the host. This has the effect of reducing the number of EEs that are generated for legacy input to no more than 1,000 per second. The number of emulation interrupts is limited because the maximum rate of data delivery to an application cannot be more than 1,000 bytes per second. A benefit of this rule is that, for normal keyboard and mouse operations, only one EE is required for each data byte sent to the application. Additionally, delay of the EE until the next Start of Frame causes data persistence for keyboard input data that is equivalent to that provided by an 8042. 4.9.6 Theory - KEL EEs There are three EEs that produce the signal KEL ASMI. These three EEs are: Character Pending, Input Full, and External IRQ. An A20 sequence is a possible Input Full EE. The A20Sequence bit in the HCE_Control register (KEL Memory Offset 100h[5]) will be set in this case. The signal KEL ASMI is an active high pulse one Local bus clock in width and sent to the Diverse Integration Logic (DIVIL). This signal is only asserted when the EmulationEnable bit in HCE_Control is high (KEL Memory Offset 100h[0] = 1), that is, emulation is enabled. For an EE, KEL also optionally produces an Emulation IRQ (KEL_EMU_IRQ). This signal is a level and is only asserted when the EE Routing (EER) bit in MSR_KELX_CTL (MSR 5140001Fh[1]) is low. De-asserting KEL_EMU_IRQ requires clearing the appropriate bit in the HCE_Control or KEL HCE_Status registers (KEL Memory Offset 100h and 10Ch). For the keyboard A20Sequence, KEL sets KEL_A20_ASMI_FLAG if enabled in the DIVIL. the A20Sequence will set the KEL_INIT_ASMI_FLAG if enabled. If a write to Port A changes the value of bit 1, the KEL sets the PORTA_A20_ASMI_FLAG if enabled in the DIVIL. If bit 0 of Port A is written to a 1, KEL sets the PORTA_INIT_ASMI_FLAG if enabled in the DIVIL. It also sets Port A to the value 2; that is, only bit 1 is high. The A20State bit in HCE_Control (KEL Memory Offset 100h[8]) is not effected. The rate of application software reading of I/O Address 060h is dependent on the alternate device interrupt rate or SOFEVENT (Start of Frame Event, MSR 5140001Fh[3:2]) when the CharacterPending bit is used in the HCE_Control register (KEL Memory Offset 100h[2]). There is one KEL EE per application software read of I/O Address 060h when CharacterPending is set. The rate of application software writing of I/O Addresses 060h and 064h is no greater than SOFEVENT. Generally, there is one KEL EE per application write to I/O Address 060h. SOFEVENT is used to emulate normal delays associated with a real 8042 controller and PS/2 device. Its source is established via MSR 5140001Fh[3:2]. Its value is 1 ms frame interval. 4.9.7 Theory - Mixed Environment A mixed environment is one in which an alternate device and a PS/2 device are supported simultaneously (e.g., a USB keyboard and a PS/2 mouse). The mixed environment is supported by allowing the emulation software to control the PS/2 interface. Control of this interface includes capturing I/O accesses to I/O Addresses 060h and 064h and also includes capture of interrupts from the PS/2 keyboard controller off the LPC. IRQ1 and IRQ12 from the LPC keyboard controller are routed through the KEL. When ExternalIRQEn in HCE_Control (KEL Memory Offset 100h[4]) is set, IRQ1 and IRQ12 from the legacy keyboard controller are blocked at the KEL and an ASMI is generated instead. This allows the emulation software to capture data coming from the legacy controller and presents it to the application through the emulated interface. The behavior of IRQ1 and IRQ12 with respect to ExternalIRQEn and IRQEN bits is summarized in Table 4-16. Keyboard INIT and A20 are generated as appropriate when emulation is enabled or snoop is enabled in MSR_KELX_CTL. KEL ASMI is generated as appropriate when emulation is enabled. KEL ASMI is not generated when emulation is disabled and snoop is enabled. Keyboard A20 under snoop does not require service beyond the DIVIL GLD_MSR_SMI (MSR 51400002h); that is, KEL does not need to be manipulated. The InputFull bit in HCE_Status (KEL Memory Offset 10Ch[1]) will set, but does not require service. Each new keyboard Table 4-16. KEL Mixed Environment Emulation Enable 1 1 x x ExternalIRQEn 0 0 1 1 IRQEN 1 1 0 0 LPC_IRQ1 0 0 0 1 LPC_IRQ12 0 0 1 0 OutputFull 1 0 0 0 OutputFull Aux 0 1 0 0 IRQ1 Active 0 0 0 1 IRQ12 Active 0 0 1 0 Action IRQ1 IRQ12 EE EE www.national.com 112 Revision 0.8 Geode™ CS5535 KEL Functional Description (Continued) 4.9.8 Theory - Force A20 Low Sequence The FA20 sequence occurs frequently in DOS applications. Mostly, the sequence is to set FA20 high; that is, do not force address bit 20 to a 0. High is the default state of this signal. To reduce the number of ASMIs caused by the A20 sequence, KEL generates an ASMI only if the GateA20 sequence would change the state of A20. The A20 sequence is initiated with a write of D1h to I/O Address 064h. On detecting this write, the KEL sets the A20Sequence bit in HCE_Control (KEL Memory Offset 100h[5]). It captures the data byte in HCE_Input (KEL Memory Offset 104h[7:0]), but does not set the InputFull bit in HCE_Status (KEL Memory Offset 10Ch[1]). When A20Sequence is set, a write of a value to I/O Address 060h that has bit 1 set to a value different than A20State in HCE_Control (KEL Memory Offset 100h[8]) causes InputFull to be set and causes an ASMI. An ASMI with both InputFull and A20Sequence set indicates that the application is trying to change the setting of FA20 on the keyboard controller. However, when A20Sequence is set, and a write of a value to I/O Address 060h that has bit 1 set to the same value as A20State in HCE_Control is detected, then no ASMI will occur. As mentioned above, a write to I/O Address 064h of any value other than D1h causes A20Sequence to be cleared. If A20Sequence is active and a value of FFh is written to I/O Address 064h, A20Sequence is cleared but InputFull is not set. A write of any value other than D1h or FFh causes InputFull to be set, which then causes an ASMI. A write of FFh to I/O Address 064h when A20Sequence is not set causes InputFull to be set. The current value of the A20_Mask is maintained in two unconnected places. The A20State bit in HCE_Control and bit 1 in Port A. The value of A20State is only changed via a software write to HCE_Control. It is set to 0 at reset. The value of bit 1 in Port A changes on any write to Port A. From reset PortA[1] is 1. 4.9.9 Theory - Processor Initialize Sequence The processor initialization sequence is possible if either of the following cases is true: • A write of a value fed to I/O Address 064h indicates processor initialization (INIT) or warm reset. This sets KEL_INIT_ASMI_FLAG if enabled in the DIVIL. All HCE registers and Port A are not effected. • Port A initialization, INIT will respond to: Write 01h to I/O Address 092h. (Refer to Section 4.9.10 "Port A".) 4.9.10 Port A This register is at I/O Address 092h. It can also be used to change the state of A20 or to cause an INIT. When 8-bit data that has its bit 0 set to 1 is written, it causes an INIT. However, if bit 1 of the 8-bit data is set to 1, it causes a change in the state of A20 (A20 gets asserted). As above, an ASMI is only generated on an INIT or A20 event. The INIT operation always forces A20 high. Writes to bits 2 and higher are a “don’t care”. Reads to Port A always return 00h or 02h depending on the state of the bit 1 of Port A. Note that A20 can be changed with Port A or the GateA20 sequence. Another important point is that A20State in HCE_Control and bit 1 in Port A are independent from each other. Writing a 1 to Port A bit 1 does not effect the A20State bit. Changing the state of the A20State bit does not effect the bit 1 of Port A. Note that when A20 has a value of 0, it means that the second MB wraps to the first MB. However, a value of 1 means that A20 is not modified. The following statements summarize the above INIT and A20 sequences : INIT will respond to: Write 01h to I/O Address 092h or FEh to I/O Address 064h. A20 toggle will respond to: Write 02h to Address 092h or Write 00h to Address 092h (bit 1 toggles, bit 0 held at 0), and Write D1h to I/O Address 064h then write a value to I/O Address 060h that has bit 1 set to a value different than the A20State in HceControl register. Trapping will insure the SMI is taken on the instruction boundary. A Keyboard INIT will not respond to: Write D1h to I/O Address 064h followed by a write 02h to I/O Address 060h (set bit 0 to 0). 4.9.11 Keyboard Emulation Logic MSRs In addition to HCE_Control (KEL Memory Offset 100h), there is a KEL Extended Control MSR, MSR_KELX_CTL (MSR 5140001Fh), to provide additional features. A “snoop” feature is used when an external LPC based keyboard controller is used (while the KEL is not enabled). All I/O accesses to I/O Addresses 060h and 064h proceed to the LPC, but the KEL snoops or watches for the A20 and INIT sequences. If these occur, KEL sets KEL_A20_ASMI_FLAG or KEL_INIT_ASMI_FLAG in the DIVIL if enabled. EEs may be routed such that they generate an IRQ or ASMI. In the case of Emulation IRQ, the clearing is done by an operation on the appropriate HCE_Control or HCE_Status registers. Reading the EE routing bit is not required for emulation processing via IRQ. This bit does not effect ASMIs associated with A20 and INIT operations. All ASMI signals are a single clock pulse wide. SOFEVENT (Start of Frame Event) is established with bits [3:2] of MSR 5140001Fh. These bits provide alternative sources for SOFEVENT. The SOFEVENT can be sourced from USB1, USB2, or the PIT. A 00 value selects the test mode. The Port A enable bit is a mask bit for Port A and its default state is high. Revision 0.8 113 www.national.com Geode™ CS5535 KEL Functional Description (Continued) 4.9.12 Related Diverse Device Functions FA20# and INIT are not passed directly to the processor. SSM code manipulates equivalent functions in the processor. The HCE registers are considered part of the USB operational register set for some software and hence share the same memory mapped register space. The GLIU descriptor for the USBs, MSR_LBAR_KEL1, and MSR_LBAR_KEL2 must all be set to the same base. The GLIU will route accesses at memory offset 100h and above to the Diverse Device and accesses below 100h to the USB. The address decoder in the DIVIL routes accesses to I/O Addresses 060h and 064h to the KEL or LPC based on the value of EmulationEnable in HCE_Control (KEL Memory Offset 100h). If snoop mode is enabled and the EmulationEnable bit is not set, writes are made directly to both the KEL and LPC. The LPC IRQ1 and IRQ12 outputs are connected to both KEL and the PIC subsystem. Masking logic in the subsystem allows the LPC interrupts to be used directly or the KEL set can be used. The KEL ASMI is routed through the Diverse Device’s Standard GLD_MSR_SMI (MSR 51400002h). It may be masked off there, but it is only cleared via MSR_KELX_CTL (MSR 5140001Fh). 4.9.13 Emulation Event Decode Emulation Events are of two types: frame synchronous and asynchronous. The conditions for a frame synchronous interrupt are sampled by the KEL at each SOF interval and, if an event condition exists, it is signaled at that time. For asynchronous events, the event is signaled as soon as the condition exists. The equation for the synchronous Emulation Event condition is: synchronousEvent = HCE_Control.EmulationEnable (KEL Memory Offset 100h[0]) and HCE_Control.CharacterPending (KEL Memory Offset 100h[2]) and not HCE_Status.OutputFull (KEL Memory Offset 10Ch[0]). When this decode is true, an Emulation Event is generated at the next SOF. The Event condition is latched until the decode becomes false. The equation for the asynchronous Emulation Event condition is: asynchronousEvent = HCE_Control.EmulationEnable (KEL Memory Offset 100h[0]) and HCE_Status.InputFull (KEL Memory Offset 10Ch[1]), or HCE_Control.ExternlIRQEn (KEL Memory Offset 100h[4]) and HCE_Control.IRQ1Active (KEL Memory Offset 100h[6]) or HCE_Control.IRQ12Active (KEL Memory Offset 100h[7]). www.national.com 114 Revision 0.8 Geode™ CS5535 4.10 SYSTEM MANAGEMENT BUS CONTROLLER The System Management Bus (SMB) Controller is a twowire synchronous serial interface compatible with the System Management Bus physical layer. The SMB Controller is also compatible with Intel's SMBus and Philips’ I2C. The SMB Controller can be configured as a bus master or slave, and can maintain bidirectional communication with both multiple master and slave devices. As a slave device, the SMB Controller may issue a request to become the bus master. The SMB Controller allows easy interfacing to a wide range of low-cost memories and I/O devices, including: EEPROMs, SRAMs, timers, ADC, DAC, clock chips, and peripheral drivers. This chapter describes the general SMB Controller functional block. A device may include a different implementation. A block diagram of the System Management Bus (SMB) Controller is shown Figure 4-22. The SMB Controller is upward compatible with previous industry standard two-wire interfaces as detailed in Table 417 on page 116. The SMB Controller’s protocol uses a two-wire interface for bidirectional communication between the ICs connected to the bus. The two interface lines are the Serial Data Line (SDL) and the Serial Clock Line (SCL). These lines should be connected to a positive supply via an internal or external pull-up resistor, and remain high even when the bus is idle. Each IC has a unique address and can operate as a transmitter or a receiver (though some peripherals are only receivers). During data transactions, the master device initiates the transaction, generates the clock signal, and terminates the transaction. For example, when the SMB Controller initiates a data transaction with an attached SMB compliant peripheral, the SMB Controller becomes the master. When the peripheral responds and transmits data to the SMB Controller, their master/slave (data transaction initiator and clock generator) relationship is unchanged, even though their transmitter/receiver functions are reversed. CCU PIC Local Bus Interface Clock Busy IRQ Data In Data In SMB Controller I/O Enable Data Out Clock Out Figure 4-22. SMB Block Diagram Revision 0.8 115 www.national.com Geode™ CS5535 SMB Controller Functional Description (Continued) Table 4-17. Comparison of SMB, I2C, and ACCESS.bus SMB Symbol F TBUF THD:STA Parameter Operating frequency Bus free time between STOP and START condition Hold time after (repeated) START condition. After this period the first clock is generated Repeated START condition setup time STOP condition setup time Data hold time Data setup time Detect clock low time-out Clock low period Clock high period Cumulative clock low extend period (slave) Cumulative clock low extend period (master) Clock/data fall time Clock/data rise time Time that device must be operational after power-on reset SMBus signal input low voltage SMBus signal input high voltage SMBus signal output low voltage Input leakage per bus segment Input leakage per device pin Nominal bus voltage Current sinking, VOL = 0.4V (SMBus) Capacitive load per bus segment Capacitance for SMBDAT or SMBCLK pin Signal noise immunity from 10 to 100 MHz 300 mV p-p 2.7V 4.0 mA 400 pF 10 pF 10 pF 2.1V Min 10 kHz 4.7 µs 4.0 µs Max 100 kHz Min 0 kHz 4.7 µs 4.0 µs I2C Max 100 kHz ACCESS.bus Min 10 kHz 4.7 µs 4.0 µs Max 100 kHz TSU:STA TSU:STO THD:DAT TSU:DAT TTimeout TLOW THIGH TLOW:SEXT TLOW:MEXT TF TR TPOR VIL VIH VOL ILEAK_BUS ILEAK_PIN VDD IPULLUP CBUS CI VNOISE 4.7 µs 4.0 µs 300 ns 250 ns 25 ms 4.7 µs 4.0 µs 50 µs 25 ms 10 ms 300 ns 1000 ns 500 ms 0.8V VDD 0.4V +-200uA +-10 µA 5.5V 35 ms 4.7us 4.0us 0 µs 250 ns 3.45 µs 4.7 µs 4.0 µs 300 ns 250 ns 25 ms 35 ms 4.7 µs 4.0 µs 4.7 µs 4.0 µs 50 µs 25 ms 10 ms 300 ns 1000 ns 300 ns 1000 ns -0.5V 3.0V 0V 1.5V -0.5V 1.4V 0.6V 5.5V 0.4V 0.4V 0V -10 µA +10 µA 2.0V 100 µA 10 µA 5.0V 350 µA www.national.com 116 Revision 0.8 Geode™ CS5535 SMB Controller Functional Description (Continued) 4.10.1 Data Transactions One data bit is transferred during each clock pulse. Data is sampled during the high state of the serial clock (SCL). Consequently, throughout the clock’s high period, the data should remain stable (see Figure 4-23). Any changes on the SDA line during the high state of SCL and in the middle of a transaction aborts the current transaction. New data should be sent during the low SCL state. This protocol permits a single data line to transfer both command/control information and data, using the synchronous serial clock. Each data transaction is composed of a START condition, a number of byte transfers (set by the software), and a STOP condition to terminate the transaction. Each byte is transferred with the most significant bit first, and after each byte (8 bits), an Acknowledge signal must follow. The following subsections provide further details of this process. During each clock cycle, the slave can stall the master while it handles the previous data or prepares new data. This can be done for each bit transferred, or on a byte boundary, by the slave holding SCL low to extend the clocklow period. Typically, slaves extend the first clock cycle of a transfer if a byte read has not yet been stored, or if the next byte to be transmitted is not yet ready. Some microcontrollers, with limited hardware support for SMB, extend the SMB after each bit, thus allowing the software to handle this bit. 4.10.1.1 START and STOP Conditions The SMB master generates START and STOP conditions (control codes). After a START condition is generated, the bus is considered busy and retains this status for a certain time after a STOP condition is generated. A high-to-low transition of the data line (SDA) while the clock (SCL) is high indicates a START condition. A low-to-high transition of the SDA line while the SCL is high indicates a STOP condition (see Figure 4-24). In addition to the first START condition, a repeated START condition can be generated in the middle of a transaction. This allows another device to arbitrate the bus, or a change in the direction of data transfer. SDA SCL S P STOP Condition START Condition Figure 4-24. SMB START and STOP Conditions 4.10.1.2 Acknowledge (ACK) Cycle The ACK cycle consists of two signals: the ACK clock pulse sent by the master with each byte transferred, and the ACK signal sent by the receiving device (see Figure 4-25). The master generates the ACK clock pulse on the ninth clock pulse of the byte transfer. The transmitter releases the SDA line (permits it to go high) to allow the receiver to send the ACK signal. The receiver must pull down the SDA line during the ACK clock pulse, signalling that it has correctly received the last data byte and is ready to receive the next byte. Figure 4-26 illustrates the ACK cycle. SDA SCL Data Line Change Stable: of Data Data Valid Allowed Figure 4-23. SMB Bit Transfer Acknowledge Signal From Receiver SDA MSB SCL 1 2 3-6 7 8 9 ACK 1 2 3-8 9 ACK S START Condition P STOP Condition Byte Complete Interrupt Within Receiver Clock Line Held Low by Receiver While Interrupt is Serviced Figure 4-25. SMB Data Transaction Revision 0.8 117 www.national.com Geode™ CS5535 SMB Controller Functional Description (Continued) Data Output by Transmitter Data Output by Receiver Transmitter Stays Off Bus During Acknowledge Clock Acknowledge Signal From Receiver SCL S START Condition 1 2 3-6 7 8 9 Figure 4-26. SMB Acknowledge Cycle 4.10.1.3 Acknowledge After Every Byte Rule According to this rule, the master generates an acknowledge clock pulse after each byte transfer, and the receiver sends an acknowledge signal after every byte received. There are two exceptions to this rule: • When the master is the receiver, it must indicate to the transmitter the end of data by not acknowledging (negative acknowledge) the last byte clocked out of the slave. This negative acknowledge still includes the acknowledge clock pulse (generated by the master), but the SDA line is not pulled down. • When the receiver is full, otherwise occupied, or a problem has occurred, it sends a negative acknowledge to indicate that it cannot accept additional data bytes. 4.10.1.4 Addressing Transfer Formats Each device on the bus has a unique address. Before any data is transmitted, the master transmits the address of the slave being addressed. The slave device should send an acknowledge signal on the SDA line, once it recognizes its address. The address consists of the first seven bits after a START condition. The direction of the data transfer (R/W) depends on the bit sent after the address, the eighth bit. A low-tohigh transition during an SCL high period indicates the STOP condition, and ends the transaction of SDA (see Figure 4-27). When the address is sent, each device in the system compares this address with its own. If there is a match, the device considers itself addressed and sends an acknowledge signal. Depending on the state of the R/W bit (1 = Read, 0 = Write), the device acts either as a transmitter or a receiver. The SMB protocol allows a general call address to be sent to all slaves connected to the bus. The first byte sent specifies the general call address (00h) and the second byte specifies the meaning of the general call (for example, write slave address by software only). Those slaves that require data acknowledge the call, and become slave receivers; other slaves ignore the call. SDA SCL 89 1-7 S START Condition Address R/W ACK 1-7 Data 8 9 ACK 1-7 Data 8 9 ACK P STOP Condition Figure 4-27. SMB Complete Data Transaction www.national.com 118 Revision 0.8 Geode™ CS5535 SMB Controller Functional Description (Continued) 4.10.1.5 Arbitration on the Bus Multiple master devices on the bus require arbitration between their conflicting bus SMB demands. Control of the bus is initially determined according to address bits and clock cycle. If the masters are trying to address the same slave, data comparisons determine the outcome of this arbitration. In master mode, the device immediately aborts a transaction if the value sampled on the SDA line differs from the value driven by the device. (An exception to this rule is SDA while receiving data. The lines may be driven low by the slave without causing an abort.) The SCL signal is monitored for clock synchronization and to allow the slave to stall the bus. The actual clock period is set by the master with the longest clock period, or by the slave stall period. The clock high period is determined by the master with the shortest clock high period. When an abort occurs during the address transmission, a master that identifies the conflict should give up the bus, switch to slave mode, and continue to sample SDA to check if it is being addressed by the winning master on the bus. 4.10.1.6 Master Mode This discussion and Section 4.10.1.7 "Slave Mode" reference several bits in the SMB Native register set (e.g., SMBCTL1.STASTRE, SMBST.MASTER, etc.). Table 4-18 provides the bit map for the SMB Native registers for the reader’s convenience. For full bit descriptions, refer to Section 5.11.1 "SMB Native Registers" on page 354. Requesting Bus Mastership An SMB transaction starts with a master device requesting bus mastership. It asserts a START condition, followed by the address of the device that wants the bus. If this transaction is successfully completed, the software may assume that the device has become the bus master. For the device to become the bus master, the software should perform the following steps: 1) Configure SMBCTL1.INTEN to the desired operation mode (Polling = 0 or Interrupt = 1) and set SMBCTL1.START. This causes the SMB Controller to issue a START condition on the bus when the bus becomes free (SMBCST.BB is cleared, or other conditions that can delay START). It then stalls the bus by holding SCL low. If a bus conflict is detected (i.e., another device pulls down the SCL signal), SMBST.BER is set. If there is no bus conflict, SMBST.SDAST and SMBST.MASTER are set. If SMBCTL1.INTEN is set and either SMBST.BER or SMBST.SDAST is set, an interrupt is issued. 2) 3) 4) Sending the Address Byte When the device is the active master of the bus (SMBST.MASTER is set), it can send the address on the bus. The address sent should not be the device’s own address, as defined by the ADDR bits of the SMBADDR register if the SMBADDR.SAEN is set, nor should it be the global call address if the SMBCST.GCMTCH is set. To send the address byte, use the following sequence: 1) For a receive transaction, where the software wants only one byte of data, it should set SMBCTL1.ACK. If only an address needs to be sent or if the device requires stall for some other reason, set the SMBCTL1.STASTRE. Write the address byte (7-bit target device address) and the direction bit to SMBSDA. This causes the SMB Controller to generate a transaction. At the end of this transaction, the acknowledge bit received is copied to SMBST.NEGACK. During the transaction, the SDA and SCL lines are continuously checked for conflict with other devices. If a conflict is detected, the transaction is aborted, SMBST.BER is set, and SMBST.MASTER is cleared. 2) Table 4-18. SMB Native Registers Map SMB I/O Offset 00h 01h 02h 03h 04h 05h 06h Name SMBSDA SMBST SMBCST SMBCTL1 SMBADDR SMBCTL2 SMBCTL3 SLVSTP SDAST BER TGSCL GCMEN 7 6 5 4 SMBSDA NEGACK TSDA ACK STASTR GCMTCH RSVD SMBADDR EN EN NMATCH MATCH INTEN MASTER BB STOP XMIT BUSY START 3 2 1 0 RSVD STASTRE SAEN SCLFRQ SCLFRQ NMINTE Revision 0.8 119 www.national.com Geode™ CS5535 SMB Controller Functional Description (Continued) 3) If SMBCTL1.STASTRE is set and the transaction was successfully completed (i.e., both SMBST.BER and SMBST.NEGACK are cleared), the STASTR bit is set. In this case, the SMB Controller stalls any further bus operations (i.e., holds SCL low). If SMBCTL1.INTEN is set, it also sends an interrupt request to the host. If the requested direction is transmit and the START transaction was completed successfully (i.e., neither SMBST.NEGACK nor SMBST.BER is set, and no other master has arbitrated the bus), SMBST.SDAST is set to indicate that the SMB Controller awaits attention. If the requested direction is receive, the START transaction was completed successfully and SMBCTL1.STASTRE is cleared, the SMB Controller starts receiving the first byte automatically. Check that both SMBST.BER and SMBST.NEGACK are cleared. If SMBCTL1.INTEN is set, an interrupt is generated when either SMBST.BER or SMBST.NEGACK is set. Master STOP To end a transaction, set SMBCTL1.STOP before clearing the current stall flag (i.e., the SDAST, NEGACK, or STASTR bit of SMBST). This causes the SMB to send a STOP condition immediately, and to clear SMBCTL1.STOP. A STOP condition may be issued only when the device is the active bus master (SMBST.MASTER is set). Master Bus Stall The SMB Controller can stall the bus between transfers while waiting for the host response. The bus is stalled by holding the SCL signal low after the acknowledge cycle. Note that this is interpreted as the beginning of the following bus operation. The user must make sure that the next operation is prepared before the flag that causes the bus stall is cleared. The flags that can cause a bus stall in master mode are: • Negative acknowledge after sending a byte (SMBST.NEGACK = 1). • SMBST.SDAST bit is set. Master Transmit After becoming the bus master, the device can start transmitting data on the bus. To transmit a byte in an interrupt or polling controlled operation, the software should: 1) Check that both SMBST.BER and SMBST.NEGACK are cleared, and that SMBST.SDAST is set. If SMBCTL1.STASTRE is set, also check that the SMBST.STASTR is cleared (and clear it if required). Write the data byte to be transmitted to SMBSDA. • SMBCTL1.STASTRE = 1, after a successful START (SMBST.STASTR = 1). Repeated START A repeated START is performed when the device is already the bus master (SMBST.MASTER is set). In this case, the bus is stalled and the SMB Controller awaits host handling due to: negative acknowledge (SMBST.NEGACK = 1), empty buffer (SMBST.SDAST = 1), and/or a stall after START (SMBST.STASTR = 1). For a repeated START: 1) 2) 3) Master Receive After becoming the bus master, the device can start receiving data on the bus. To receive a byte in an interrupt or polling operation, the software should: 1) Check that SMBST.SDAST is set and that SMBST.BER is cleared. If SMBCTL1.STASTRE is set, also check that SMBST.STASTR is cleared (and clear it if required). Set SMBCTL1.ACK, if the next byte is the last byte that should be read. This causes a negative acknowledge to be sent. Read the data byte from SMBSDA. Set (1) SMBCTL1.START. In master receive mode, read the last data item from SMBSDA. Follow the address send sequence, as described in “Write the address byte (7-bit target device address) and the direction bit to SMBSDA. This causes the SMB Controller to generate a transaction. At the end of this transaction, the acknowledge bit received is copied to SMBST.NEGACK. During the transaction, the SDA and SCL lines are continuously checked for conflict with other devices. If a conflict is detected, the transaction is aborted, SMBST.BER is set, and SMBST.MASTER is cleared. If the SMB Controller was awaiting handling due to SMBST.STASTR = 1, clear it only after writing the requested address and direction to SMBSDA. 4) 5) 6) 2) When either SMBST.NEGACK or SMBST.BER is set, an interrupt is generated. When the slave responds with a negative acknowledge, SMBST.NEGACK is set and SMBST.SDAST remains cleared. In this case, if SMBCTL1.INTEN is set, an interrupt is issued. 4) 2) 3) Before receiving the last byte of data, set SMBCTL1.ACK. Before generating a STOP condition or generating a repeated START condition, it is necessary to perform an SDA read and clear the SMBST.SDAST bit. Master Error Detection The SMB Controller detects illegal START or STOP conditions (i.e., a START or STOP condition within the data transfer, or the acknowledge cycle) and a conflict on the data lines of the bus. If an illegal condition is detected, SMBST.BER is set and master mode is exited (SMBST.MASTER is cleared). 120 Revision 0.8 www.national.com Geode™ CS5535 SMB Controller Functional Description (Continued) Bus Idle Error Recovery When a request to become the active bus master or a restart operation fails, SMBST.BER is set to indicate the error. In some cases, both the device and the other device may identify the failure and leave the bus idle. In this case, the START sequence may be incomplete and the bus may remain deadlocked. To recover from deadlock, use the following sequence: 1) 2) Clear SMBST.BER and SMBCST.BB. Wait for a time-out period to check that there is no other active master on the bus (i.e., SMBCST.BB remains cleared). Disable, and re-enable the SMB Controller to put it in the non-addressed slave mode. This completely resets the functional block. Slave Receive and Transmit Slave receive and transmit are performed after a match is detected and the data transfer direction is identified. After a byte transfer, the SMB Controller extends the acknowledge clock until the software reads or writes the SMBSDA register. The receive and transmit sequences are identical to those used in the master routine. Slave Bus Stall When operating as a slave, the device stalls the bus by extending the first clock cycle of a transaction in the following cases: • SMBST.SDAST is set. • SMBST.NMATCH and SMBCTL1.NMINTE are set. Slave Error Detection The SMB Controller detects an illegal START and STOP conditions on the bus (i.e., a START or STOP condition within the data transfer or the acknowledge cycle). When this occurs, SMBST.BER is set and SMBCST.MATCH and SMBCST.GMATCH are cleared, setting the SMB Controller as an unaddressed slave. 3) At this point, some of the slaves may not identify the bus error. To recover, the SMB Controller becomes the bus master: it asserts a START condition, sends an address byte, then asserts a STOP condition that synchronizes all the slaves. 4.10.1.7 Slave Mode A slave device waits in Idle mode for a master to initiate a bus transaction. Whenever the SMB Controller is enabled and it is not acting as a master (i.e., SMBST.MASTER is cleared), it acts as a slave device. Once a START condition on the bus is detected, the device checks whether the address sent by the current master matches either: • The SMBADDR.ADDR value if SMBADDR.SAEN = 1, or • The general call address if SMBCTL1.GCMEN = 1. This match is checked even when SMBST.MASTER is set. If a bus conflict (on SDA or SCL) is detected, SMBST.BER is set, SMBST.MASTER is cleared and the device continues to search the received message for a match. If an address match or a global match is detected: 1) 2) The device asserts its SDA line during the acknowledge cycle. SMBCST.MATCH and SMBST.NMATCH are set. If SMBST.XMIT = 1 (i.e., slave transmit mode) SMBST.SDAST is set to indicate that the buffer is empty. If SMBCTL1.INTEN is set, an interrupt is generated if both SMBCTL1.INTEN and SMBCTL1.NMINTE are set. The software then reads SMBST.XMIT to identify the direction requested by the master device. It clears SMBST.NMATCH so future byte transfers are identified as data bytes. 3) 4) Revision 0.8 121 www.national.com Geode™ CS5535 SMB Controller Functional Description (Continued) 4.10.1.8 Configuration SDA and SCL Signals The SDA and SCL are open-drain signals. The device permits the user to define whether to enable or disable the internal pull-up of each of these signals. SMB Clock Frequency The SMB permits the user to set the clock frequency for the System Management Bus clock. The clock is set by the SMBCTL2.SCLFRQ field and the SMBCTL3 register, which determines the SCL clock period used by the device. This clock low period may be extended by stall periods initiated by the SMB or by another System Management Bus device. In case of a conflict with another bus master, a shorter clock high period may be forced by the other bus master until the conflict is resolved. 4.10.1.9 Transaction Types Byte Write Sequence of events (see Figure 4-28): 1) 2) 3) 4) 5) 6) 7) 8) START Address phase Acknowledge Word address Acknowledge Data Acknowledge STOP START Device Address Word Address Data SDA Line MSB MSB LSB R/W ACK LSB ACK ACK Figure 4-28. SMB Byte Write www.national.com 122 STOP Write Revision 0.8 Geode™ CS5535 SMB Controller Functional Description (Continued) Page Write Sequence of Events (see Figure 4-29): 1) 2) 3) 4) 5) 6) 7) 8) 9) START Address Acknowledge Word Address Acknowledge Data1 Acknowledge Data(n) Acknowledge Current Address Read Sequence of Events (see Figure 4-30): 1) 2) 3) 4) 5) 6) START Device Address - 8 bit Acknowledge Data No Acknowledge STOP 10) Data(n+1) 11) Acknowledge 12) Data(n+x) 13) Acknowledge 14) STOP START STOP ACK www.national.com Write Device Address Word Address (n) Data (n) Data (n + 1) Data (n + x) SDA Line MSB MSB LSB R/W ACK LSB ACK ACK ACK No ACK STOP Figure 4-29. SMB Page Write START Device Address Read Data SDA Line MSB LSB R/W ACK 123 Figure 4-30. SMB Current Address Read Revision 0.8 Geode™ CS5535 SMB Controller Functional Description (Continued) Random Read Sequence of Events (see Figure 4-31): 1) 2) 3) 4) 5) 6) 7) 8) 9) START Device Address Acknowledge Word Address(n) Acknowledge START Device Address Acknowledge Data(n) Sequential Reads Sequence of Events (see Figure 4-32): 1) 2) 3) 4) 5) 6) 7) 8) 9) START Device Address Acknowledge Data(n) Acknowledge Data(n+1) Acknowledge Data(n+2) Acknowledge 10) No Acknowledge 11) STOP 10) Data(n+x) 11) No Acknowledge 12) STOP START START Device Address Word Address (n) Device Address Data (n) SDA Line MSB MSB MSB LSB ACK LSB R/W ACK LSB No ACK ACK Dummy Write Figure 4-31. SMB Random Read START STOP Read Write Device Address Data (n) Data (n+1) Data (n+2) Data (n + x) SDA Line MSB LSB R/W ACK No ACK Revision 0.8 ACK ACK ACK Figure 4-32. SMB Sequential Reads www.national.com 124 STOP Read Geode™ CS5535 4.11 UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER AND IR PORT CONTROLLER The Universal Asynchronous Receiver Transmitter and IR Port (UART/IR Controller) is an enhanced serial port with fast IR (infrared). The UART/IR Controller provides advanced, versatile serial communications features with IR capabilities and supports: • UART (Section 4.11.1.1 "UART Mode" on page 127) • Sharp-IR (Section 4.11.1.2 "Sharp-IR Mode" on page 128) • IrDA 1.0 SIR (Section 4.11.1.3 "SIR Mode" on page 128) • Consumer Electronic IR (CEIR); also called TV Remote or Consumer remote control (Section 4.11.1.4 "CEIR Mode" on page 128) In UART mode, the functional block can act as a standard 16450 or 16550, or in extended mode. Existing 16550-based legacy software is completely and transparently supported. Organization and specific fallback mechanisms switch the functional block to 16550 compatibility mode upon reset, or when initialized by 16550 software. This functional block has two DMA channels, of which the device can use one or both. One channel is required for IRbased applications, since IR communication works in halfduplex fashion. Two channels are normally needed to handle high-speed, full duplex, UART-based applications. Figure 4-33 shows the serial port connections to the peripheral devices and host, as well as the device configuration. Features • Fully compatible with 16550 and 16450 devices (except modem) • Extended UART mode • Sharp-IR • IrDA 1.0 SIR with up to 115.2 kbaud data rate • Consumer-IR mode • UART mode data rates up to 1.5 Mbps • Full duplex infrared frame transmission and reception • Transmit deferral • Automatic fallback to 16550 compatibility mode • Selectable 16 and 32 level FIFOs • 12-bit timer for infrared protocol support • DMA handshake signal routing for either 1 or 2 channels • Support for power management • Virtual dongle interface Microprocessor MHZ48_CLK Master Bus Interrupt Controller Local Bus Interface IRQ BUSY CCU UART/IR Controller Local Bus to SuperI/O Bus Converter and Control Logic ID[3:0] IRSL0_DS IRSL[2:0] Tx and Rx UART/IR Logic Modem/Control Signals IR Interface UART Interface Register Bank SuperI/O Bus and DMA Interface Virtual Dongle Interface MSR_MOD MSR_DON MSR_CONFIG MSR_RSVD DMA Controller IRTX IRRX1 SOUT SIN Figure 4-33. UART/IR Overview Diagram Revision 0.8 125 www.national.com Geode™ CS5535 UART/IR Controller Functional Description (Continued) 4.11.1 Operational Modes This section describes the operation modes of the UART/IR Controller. Although each mode is unique, certain system resources and features are common. This discussion references several bits in the UART/IR Controller Native register set. Table 4-19 provides the bit map for the UART/IR Controller Native registers for the reader’s convenience. For full bit descriptions, refer to Section 5.12.2 on page 366. Table 4-19. UART/IR Controller Native Register Bit Map I/O Offset Name Bank 0 00h 00h 01h RXD TXD IER (Note 1) IER (Note 2) 02h EIR (Note 1) EIR (Note 2) FCR 03h 04h LCR BSR MCR (Note 1) MCR (Note 2) 05h 06h 07h LSR MSR SPR (Note 1) ASCR (Note 2) Bank 1 00h 01h 02h 03h LBGD_L LBGD_H RSVD LCR BSR 04-07h RSVD Bank 2 00h 01h 02h 03h 04h 05h 06h 07h Bank 3 00h 01h MRID SH_LCR RSVD MID[3:0] SBRK STKP EPS PEN STB RID[3:0] WLS1 WLS0 BGD_L BGD_H EXCR1 BSR EXCR2 RSVD TXFLV RXFLV RSVD RSVD BKSE LOCK RSVD PRESL[1:0] RSVD TFL[5:0] RFL[5:0] RSVD EDTLBK BGD[7:0] BGD[15:8] LOOP DMASWP BSR[6:0] RF_SIZ[1:0] TF_SIZ1[1:0] DMATH DMANF EXT_SL BKSE BKSE SBRK STKP EPS RSVD LBGD[7:0] LBGD[15:8] RSVD PEN BSR[6:0] STB WLS1 WLS0 CTE TXUR RXACT ER_INF DCD BKSE BKSE RSVD MDSL[2:0] TXEMP RI TXRDY DSR LOOP IR_PLS BRK CTS RSVD FEN[1:0] RSVD RXFTH[1:0] SBRK RXD7 TXD7 RXD6 TXD6 RSVD TXEMP_IE DMA_IE RXD5 TXD5 RXD4 TXD4 RXD3 TXD3 MS_IE MS_IE RXFT MS_EV RSVD PEN BSR[6:0] ISEN or DCDLP TX_DFR FE DDCD RILP DMA_EN PE TERI RTS RTS OE DDSR DTR DTR RXDA DCTS RXD2 TXD2 LS_IE LS_IE RXD1 TXD1 TXLDL_IE TXLDL_IE IPR[1:0] LS_EV/ TXHLT_EV TXSR STB TXLDL_EV RXSR RXD0 TXD0 RXHDL_IE RXHDL_IE IPF RXHDL_IE FIFO_EN 7 6 5 4 3 2 1 0 RSVD TXEMP_EV DMA_EV TXFTH[1:0] STKP EPS WLS[1:0] Scratch Data RXWDG RSVD S_OET RSVD RXF_TOUT www.national.com 126 Revision 0.8 Geode™ CS5535 UART/IR Controller Functional Description (Continued) Table 4-19. UART/IR Controller Native Register Bit Map (Continued) I/O Offset Name 02h 03h 04h07h Bank 4 00h01h 02h 03h 04h07h Bank 5 00h02h 03h 04h 05h07h Bank 6 00h 01h 02h 03h 04h07h Bank 7 00h 01h 02h 03h 04h 05h06h 07h IRRXDC IRTXMC RCCFG BSR IRCFG1 RSVD IRCFG4 RSVD IRSL0_DS RXINV R_LEN BKSE STRV_MS RSVD SET_IRTX IRRX1_LV RSVD IRSL21_DS RSVD DBW[2:0] MCPW[2:0] T_OV RXHSC RCDM_DS RSVD BSR[6:0] RSVD IRIC[2:0] DFR[4:0] MCFR[4:0] TXHSC RC_MMD[1:0] IRCR3 RSVD SIR_PW BSR RSVD BKSE RSVD RSVD SHDM_DS SHMD_DS RSVD SPW3 BSR[6:0] SPW2 SPW1 SPW0 RSVD RSVD BSR IRCR2 RSVD BKSE RSVD RSVD RSVD AUX_IRRX RSVD RSVD BSR[6:0] RSVD RSVD IRMSSL IR_FDPLX RSVD IRCR1 BSR RSVD BKSE RSVD RSVD RSVD IR_SL[1:0] BSR[6:0] RSVD SH_FCR BSR RSVD 7 RXFTH[1:0] BKSE 6 5 TXFTH[1:0] RSVD 4 3 RSVD BSR[6:0] 2 TXSR 1 RXSR 0 FIFO_EN Note 1. Non-Extended Mode. Note 2. Extended Mode. 4.11.1.1 UART Mode UART mode supports serial data communication with a remote peripheral device using a wired interface. This functional block provides receive and transmit channels that can operate concurrently in full-duplex mode. This functional block performs all functions required to conduct parallel data interchange with the system and composite serial data exchange with the external data channel. START -LSB- It performs parallel-to-serial conversion on data characters received from the processor or a DMA controller, and serial-to-parallel conversion on data characters received from the serial interface. Figure 4-34 shows the serial data stream. A data character contains five to eight data bits. It is preceded by a START bit and is followed by an optional PARITY bit and a STOP bit. Data is transferred in Little Endian order (LSB first). STOP DATA[5:8] -MSB- PARITY Figure 4-34. UART Serial Data Stream Format Revision 0.8 127 www.national.com Geode™ CS5535 UART/IR Controller Functional Description (Continued) UART mode can be implemented in standard 16450 and 16550 compatibility (non-extended) and extended mode. UART 16450 compatibility mode is the default after powerup or reset. When extended mode is selected, the functional block architecture changes slightly and a variety of additional features are made available. The interrupt sources are no longer prioritized, and an Auxiliary Status and Control Register (ASCR) replaces the Scratch Pad Register (SPR). The additional features include: transmitter FIFO (TX_FIFO) thresholding, DMA capability, and interrupts on transmitter empty states and DMA events. The clock for both transmit and receive channels is provided by an internal baud generator that divides its input clock by any divisor value from 1 to 216-1. The output clock frequency of the baud generator must be programmed to be 16 times the baud rate value. The baud generator input clock is derived from a 24 MHz clock through a programmable prescaler. The prescaler value is determined by the PRESL bits in the EXCR2 register. Its default value is 13. This allows all the standard baud rates, up to 115.2 kbaud, to be obtained. Smaller prescaler values allow baud rates up to 921.6 kbaud (standard) and 1.5 Mbaud (non-standard). Before operation can begin, both the communication format and baud rate must be programmed by the software. The communication format is programmed by loading a control byte into the LCR (Link Control Register), while the baud rate is selected by loading an appropriate value into the Baud Generator Divisor Register. The software can read the status of the functional block at any time during operation. The status information includes Full/Empty states for both transmit and receive channels, and any other condition detected on the received data stream, such as a parity error, framing error, data overrun, or break event. 4.11.1.2 Sharp-IR Mode This mode supports bidirectional data communication with a remote device, using IR radiation as the transmission medium. Sharp-IR uses Digital Amplitude Shift Keying (DASK) and allows serial communication at baud rates up to 38.4 kbaud. The format of the serial data is similar to that of the UART data format. Each data word is sent serially, beginning with a 0 value START bit, followed by up to eight data bits (LSB first), an optional parity bit, and ending with at least one STOP bit, with a binary value of 1. A logical 0 is signalled by sending a 500 kHz continuous pulse train of IR radiation. A logical 1 is signalled by the absence of an IR signal. This functional block can perform the modulation and demodulation operations internally, or can rely on the external optical module to perform them. Sharp-IR device operation is similar to operation in UART mode. The difference being that data transfer operations are normally performed in half-duplex fashion, and the modem control and status signals are not used. Selection of the Sharp-IR mode is controlled by the Mode Select (MDSL) bits in the MCR when the functional block is in extended mode, or by the IR_SL bits in the IRCR1 register when the functional block is in non-extended mode.) This prevents legacy software, running in non-extended mode, from spuriously switching the functional block to UART mode when the software writes to the MCR. 4.11.1.3 SIR Mode SIR mode supports bidirectional data communication with a remote device, using IR radiation as the transmit medium. SIR allows serial communication at baud rates up to 115.2 kbaud. The serial data format is similar to that of the UART data format. Each data word is sent serially, beginning with a 0 value START bit, followed by eight data bits (LSB first), an optional PARITY bit, and ending with at least one STOP bit, with a binary value of 1. A 0 value is signalled by sending a single IR pulse. A 1 value is signalled by the absence of a pulse. The width of each pulse can be either 1.6 µs (3/16 the time required to transmit a single bit at 115.2 kbps). This way, each word begins with a pulse at the START bit. Operation in SIR is similar to that of the UART mode. The difference being that data transfer operations are normally performed in half-duplex fashion. Selection of the IrDA 1.0 SIR mode is controlled by the MDSL bits in the MCR when the UART is in extended mode, or by the IR_SL bits in the IRCR1 register when the UART is in non-extended mode. This prevents legacy software, running in non-extended mode, from spuriously switching the functional block to UART mode when the software writes to the MCR. 4.11.1.4 CEIR Mode The Consumer Electronics IR circuitry is designed to optimally support all major protocols presently used in the following remote-controlled home entertainment equipment: RC-5, RC-6, RECS 80, NEC, and RCA. This module, in conjunction with an external optical device, provides the physical layer functions necessary to support these protocols. Such functions include: modulation, demodulation, serialization, de-serialization, data buffering, status reporting, interrupt generation, etc. The software is responsible for the generation of IR code transmitted, and the interpretation of received code. CEIR Transmit Operation The transmitted code consists of a sequence of bytes that represents either a bit string or a set of run-length codes. The number of bits or run-length codes needed to represent each IR code bit depends on the IR protocol used. The RC-5 protocol, for example, needs two bits or between one and two run-length codes to represent each IR code bit. Transmission is initiated when the processor or DMA controller writes code bytes into the empty TX_FIFO. Transmission is completed when the processor sets the S_EOT bit of the ASCR, before writing the last byte, or when the DMA controller activates the terminal count (TC). Transmission also terminates if the processor simply stops transferring data and the transmitter becomes empty. In this case, however, a transmitter-underrun condition is generated that must be cleared in order to begin the next transmission. www.national.com 128 Revision 0.8 Geode™ CS5535 UART/IR Controller Functional Description (Continued) The transmission bytes are either de-serialized or runlength encoded, and the resulting bit-string modulates a carrier signal that is sent to the transmitter LED. The transfer rate of this bit-string, like in UART mode, is determined by the value programmed in the Baud Generator Divisor Register. Unlike a UART transmission, START, STOP, and PARITY bits are not included in the transmitted data stream. A logic 1 in the bit-string keeps the LED off, so no IR signal is transmitted. A logic 0 generates a sequence of modulating pulses that turn on the transmitter LED. Frequency and pulse width of the modulating pulses are programmed by the MCFR and MCPW fields in the IRTXMC register, as well as the TXHSC bit of the RCCFG register. The RC_MMD field of RCCFG selects the transmitter modulation mode. If the C_PLS mode is selected, modulating pulses are generated continuously for the entire logic 0 bit time. If 6_PLS or 8_PLS mode is selected, six or eight pulses are generated each time a logic 0 bit is transmitted following a logic 1 bit. C_PLS modulation mode is used for RC-5, RC-6, NEC, and RCA protocols. 8_PLS or 6_PLS modulation mode is used for the RECS 80 protocol. The 8_PLS or 6_PLS mode allows minimization of the number of bits needed to represent the RECS 80 IR code sequence. The current transmitter implementation supports only the modulated modes of the RECS 80 protocol; it does not support the Flash mode. Note: The total transmission time for the logic 0 bits must be equal to or greater than six or eight times the period of the modulation subcarrier, otherwise fewer pulses will be transmitted. The receiver also sets the RXWDG bit of the ASCR each time an IR pulse signal is detected. This bit is automatically cleared when the ASCR is read. It is intended to assist the software in determining when the IR link has been Idle for a period of time. The software can then stop data from being received by writing a 1 into the RXACT bit to clear it, and return the receiver to the inactive state. The frequency bandwidth for the incoming modulated IR signal is selected by the DFR and DBW fields in the IRRXDC register. There are two CEIR receive data modes: Oversampled and Programmed T Period. For either mode, the sampling rate is determined by the setting of the Baud Generator Divisor Registers. Oversampled mode can be used with the receiver demodulator either enabled or disabled. It should be used with the demodulator disabled when a detailed snapshot of the incoming signal is needed; for example, to determine the period of the carrier signal. If the demodulator is enabled, the stream of samples can be used to reconstruct the incoming bit-string. To obtain good resolution, a fairly high sampling rate should be selected. Programmed T Period mode should be used with the receiver demodulator enabled. The T Period represents one-half bit time for protocols using biphase encoding or the basic unit of pulse distance for protocols using pulse distance encoding. The baud is usually programmed to match the T Period. For long periods of logic low or high, the receiver samples the demodulated signal at the programmed sampling rate. When a new IR energy pulse is detected, the receiver synchronizes the sampling process to the incoming signal timing. This reduces timing-related errors and eliminates the possibility of missing short IR pulse sequences, especially with the RECS 80 protocol. In addition, the Programmed T Period sampling minimizes the amount of data used to represent the incoming IR signal, therefore reducing the processing overhead in the host CPU. 4.11.1.5 FIFO Timeouts Timeout mechanisms are provided to prevent received data from remaining in the RX_FIFO indefinitely, in case the programmed interrupt or DMA thresholds are not reached. An RX_FIFO timeout generates a Receiver Data Ready interrupt and/or a receiver DMA request if bit 0 of the IER register and/or bit 2 of the MCR register (in Extended mode) are set to 1, respectively. An RX_FIFO timeout also sets bit 0 of the ASCR register to 1 if the RX_FIFO is below the threshold. When a Receiver Data Ready interrupt occurs, this bit is tested by the software to determine whether a number of bytes indicated by the RX_FIFO threshold can be read without checking bit 0 of the LSR register. The conditions that must exist for a timeout to occur in the modes of operation are described below. When a timeout has occurred, it can only be reset when the FIFO is read by the processor or DMA controller. CEIR Receive Operation The CEIR receiver is significantly different from a UART receiver. The incoming IR signals are DASK modulated; therefore, demodulation may be necessary. Also, there are no START bits in the incoming data stream. The operations performed by the receiver, whenever an IR signal is detected, are slightly different, depending on whether or not receiver demodulation is enabled. If demodulation is disabled, the receiver immediately becomes active. If demodulation is enabled, the receiver checks the carrier frequency of the incoming signal and becomes active only if the frequency is within the programmed range. Otherwise, the signal is ignored and no other action is taken. When the receiver enters the Active state, the RXACT bit of the ASCR is set to 1. Once in the Active state, the receiver keeps sampling the IR input signal and generates a bitstring, where a logic 1 indicates an Idle condition and a logic 0 indicates the presence of IR energy. The IR input is sampled regardless of the presence of IR pulses at a rate determined by the value loaded into the Baud Generator Divisor Registers. The received bit-string is either de-serialized and assembled into 8-bit characters, or is converted to run-length encoded values. The resulting data bytes are then transferred into the receiver FIFO (RX_FIFO). Revision 0.8 129 www.national.com Geode™ CS5535 UART/IR Controller Functional Description (Continued) Timeout Conditions for UART, SIR, and Sharp-IR Modes RX_FIFO timeout conditions: • At least one byte is in the RX_FIFO. • More than four character times have elapsed since the last byte was loaded into the RX_FIFO from the receiver logic. • More than four character times have elapsed since the last byte was read from the RX_FIFO by the processor or DMA controller. Timeout Conditions for CEIR Mode The RX_FIFO timeout in CEIR mode is disabled while the receiver is active. The conditions for this timeout to occur are as follows: • At least one byte has been in the RX_FIFO for 64 µs or more. • The receiver has been inactive (RXACT = 0) for 64 µs or more. • More than 64 µs have elapsed since the last byte was read from the RX_FIFO by the processor or DMA controller. 4.11.1.6 Transmit Deferral This feature allows software to send short, high-speed data frames in PIO mode without the risk of generating a transmitter underrun. Transmit deferral is available only in extended mode and when the TX_FIFO is enabled. When transmit deferral is enabled (TX_DFR bit of the MCR register set to 1) and the transmitter becomes empty, an internal flag is set and locks the transmitter. If the processor now writes data into the TX_FIFO, the transmitter does not start sending the data until the TX_FIFO level reaches either 14 for a 16-level TX_FIFO or 30 for a 32-level TX_FIFO, at which time the internal flag is cleared. The internal flag is also cleared and the transmitter starts transmitting when a timeout condition is reached. This prevents some bytes from being in the TX_FIFO indefinitely if the threshold is not reached. The timeout mechanism is implemented by a timer that is enabled when the internal flag is set and there is at least one byte in the TX_FIFO. Whenever a byte is loaded into the TX_FIFO, the timer is reloaded with the initial value. If no byte is loaded for a 64 µs time, the timer times out and the internal flag is cleared, thus enabling the transmitter. 4.11.1.7 Automatic Fallback to 16550 Compatibility Mode This feature is designed to support existing legacy software packages, using the 16550 serial port. For proper operation, many of these software packages require that the module look identical to a plain 16550, since they access the serial port registers directly. Because several extended features and new operational modes are provided, make sure the module is in the proper state before executing a legacy program. The fallback mechanism eliminates the need to change the state when a legacy program is executed following completion of a program that used extended features. It automatically switches the module to 16550 compatibility mode and turns off any extended features whenever the Baud Generator Divisor Register is accessed through the LBGD_L or LBGD_H ports in register Bank 1. In order to avoid spurious fallbacks, baud generator divisor ports are provided in Bank 2. Baud generator divisor access through these ports changes the baud rate setting but does not cause fallback. New programs designed to take advantage of the extended features should not use LBGD_L and LBGD_H to change the baud rate. Instead, they should use BGD_L and BGD_H. A fallback can occur in either extended or non-extended modes. If extended mode is selected, fallback is always enabled. In this case, when a fallback occurs, the following happens: • TX_FIFO and RX_FIFO switch to 16 levels. • A value of 13 is selected for the baud generator prescaler. • ETDLBK and BTEST of the EXCR1 register are cleared. • UART mode is selected. • The functional block switches to non-extended mode. When fallback occurs from non-extended mode, only the first three of the above actions occur. If either Sharp-IR or SIR infrared modes were selected, no switching to UART mode occurs. This prevents spurious switching to UART mode when a legacy program, running in Infrared mode, accesses the Baud Generator Divisor Register from Bank 1. Fallback from non-extended mode can be disabled by setting LOCK in the EXCR2 register to 1. When LOCK is set and the functional block is in non-extended mode, two scratch pad registers overlaid with LBGD_L and LBGD_H are enabled. Any attempted processor access of the Baud Generator Divisor Register through LBGD_L and LBGD_H accesses the scratch pad registers, without affecting the baud rate setting. This feature allows existing legacy programs to run faster than 115.2 kbaud, without realizing they are running at this speed. 4.11.2 Modem Support An MSR (MSR_UART[x]_MOD) (UART1 MSR 51400038h and UART2 MSR 5140003Ch) mimics modem input signals for making it compatible with the software having modem support. The hardware of this module has all the required functionality for modem compatibility. www.national.com 130 Revision 0.8 Geode™ CS5535 UART/IR Controller Functional Description (Continued) 4.11.3 Dongle Interface The dongle interface on the CS5535 is not a fully hardware compatible interface. The real dongle interface requires six external interface signals and the CS5535 only supports three. With only three signals, the dongle interface supports a subset of the real dongle interface through virtualization. 4.11.3.1 Real Dongle The real dongle interface uses six multiplexed pins for dongle identification, data transfer, and transceiver configuration. Figure 4-35 illustrates the real dongle interface and Table 4-20 provides the interface signals and their descriptions. Only three signals (IRTX, IRRX, and ID0/IRSL0/IRRX2) are used for the IR interface. It has three phases: Phase 1: Change the ID0-ID3 bits to input mode, and read the status to complete primary identification of the dongle. Phase 2: Change ID1 and ID2 as output and read the status of ID0 and ID3 to complete the secondary dongle identification phase. This phase provides information about the connected dongle. ID1/IRSL1 ID2/IRSL2 ID3 I/O I/O I/O Phase 3: Configure mode: Change IRSL[2:0] as an output and configure the transceiver for the required mode. If two infrared inputs are required, change IRSL0 to an input to give the second receiver channel IRRX2. The IRSL2 and IRSL1 are configured as outputs to keep the transceiver in the required mode. Table 4-20. Real Dongle Interface Signals Signal Name IRTX IRRX ID0/IRSL0/IRRX2 Type O I I/O Description Infrared transmit data Infrared receive data Identification signal 0 Infrared mode select 0 Infrared receive data for transceivers with two RX channels Identification signal 1 Infrared mode select 1 Identification signal 2 Infrared mode select 2 Identification signal 2 IRTX IRRXI ID0/IRSL0/IRRX2 ID1/IRSL1 IR Controller ID2/IRSL2 ID3 Pull-up Resistance VCC ASIC Boundary Shielded Cable Transceiver Select Logic RX-B RX-A TX IrDa-Data Transceiver with Receive Channels Figure 4-35. Real Dongle Interface Revision 0.8 131 www.national.com Geode™ CS5535 UART/IR Controller Functional Description (Continued) 4.11.3.2 Virtual Dongle The virtual dongle interface is used due to the unavailability of pins for dongle identification and configuration (see Figure 4-36). The virtual dongle interface is a method used to run legacy software on the UART/IR Controller. The virtual dongle interface uses dedicated UART/IR MSRs. (See Section 5.12.1 "UART/IR Controller Specific MSRs" on page 363 for complete register and bit formats.) The virtual dongle imitates the real dongle as far as legacy software is concerned, and there are no plug-and-play requirements for IR transceivers. • The software inputs the dongle's ID to the ID[0:3] bits of MSR_UART[x]_MOD (UART1 MSR 51400038h and UART2 MSR 5140003Ch) as the primary ID encoding. • For dongles that use a non-serial transceiver, it identifies the Consumer IR capabilities. The software should switch ID1 and ID2 to output mode (so they become IRSL1 and IRSL2), IRSL1 and IRSL2 will or will not behave differently (i.e., INV [invert] or NCH [no change]) from the previous step and the software should respond by driving the appropriate level on ID0 and ID3 in the MSR_UART[x]_DONG register. The operational mode of an infrared dongle that uses a non_serial transceiver is selected by the driving the IRSL[2:0] signals. Features • Uses only three pins to connect to IR transceiver. • Fully supports legacy software written for real dongle, with some manual intervention. • All real dongle modes can be supported by changing the MSR. Limitations • No Plug-and-Play features available. • IRSL1 and IRSL2 pins need to be tied in the IR transceiver for the required mode. • MSR contents must be changed when changing the transceiver mode. If BIOS is used to change the MSR contents, it must be a factory setting. • If the legacy software supports IR transceiver configuration, the contents of IRSL[2:0] are to be read from the MSR and the required bit tieing needs to be done in the transceiver board. UART/IR Controller MSR_UART[x]_MOD ID1 ID2 ID0 ID3 MSR_UART[x]_DONG ID0_SEC ID3_SEC IRSL0 IRSL1 IRSL2 Mux ID1 ID2 ID0 ID3 IR Controller IRRX1 IRTX ASIC Boundary IRSL1 IR Transceiver IRSL2 Tie IRSL1 and IRSL2 Figure 4-36. Virtual Dongle Interface www.national.com 132 Revision 0.8 Geode™ CS5535 4.12 DIRECT MEMORY ACCESS MODULE The Direct Memory Access (DMA) module supports industry standard DMA architecture using two 8237-compatible DMA controllers in cascaded configuration. Figure 4-37 shows the DMA module partitioning. It consists of two standard 8237 DMA controllers, a bus interface, address mapper, and source mapper. Features • 32-bit address range support via high page registers. • Supports the standard 7-channel DMA configuration, out of which the four 8-bit channels are used. • DMA mapper to route DMA sources to the four 8-bit DMA channels. • DMA sources to come from the LPC bus, and come from transmit and receive from the two UARTs. • Allow the data bus to be released in between DMA transfers during demand or bulk mode to allow transfers to the DMA module or the module doing DMA transfers. 4.12.1 DMA Mapper Source Selection For each 8-bit DMA channel, the DMA mapper allows the DMA request to come from a number of sources. Table 421 shows how the DMA mapper register select field selects the appropriate DMA source. When LPC is selected as the DMA source for DMA Channel 0, the source is LPC DMA Channel 0. Similarly, when LPC is selected as the source for DMA Channel 1, 2, or 3, then the DMA sources for those three DMA channels are respectively LPC DMA Channels 1, 2, and 3. Therefore, LPC DMA Channel 0 can only be mapped to DMA Channel 0, LPC DMA Channel 1 can only be mapped to DMA Channel 1, etc. Table 4-21. DMA Source Selection Source Selector Value from DMA Mapper 0 1 2 3 4 5 6 7 DMA Source None (DMA channel off) UART1 Transmit UART1 Receive UART2 Transmit UART2 Receive Reserved (not active) Reserved (not active) LPC 8237 LPC and DMA Interfaces with DMA mapper 8237 LPC I/F DMA R/W Controls DMA Requests DMA Acks Data LBus I/F Bus Interface and Registers Figure 4-37. DMA Module Block Diagram Revision 0.8 133 www.national.com Geode™ CS5535 4.13 LOW PIN COUNT PORT The Low Pin Count port is based on Intel’s Low Pin Count (LPC) Interface Specification v1.0. In addition to the required pins, the CS5535 also supports two optional pins: LDRQ# and SERIRQ. The LPC interface supports memory, I/O, DMA, and Intel’s Firmware Hub Interface. Figure 4-38 shows the block diagram of the LPC port. Features • Based on Intel’s Low Pin Count (LPC) Specification v1.0. • Serial IRQ support. • Supports memory, I/O, and DMA cycle types. • Bus master cycles not supported. • CLKRUN# and LPCPD# not supported. SMI# and PME# supported via GPIOs. • On-chip DMA transfers through LPC. • Supports Intel’s FirmWare Hub (FWH) Interface: — 5 Signal communication interface supporting byte-ata-time reads and writes. — LAD[3:0] called as FWH0-FWH3 and LFRAME# as FWH4. GeodeLink Adapter Local Bus LPC to/from Local Bus Local Bus Slave Local Bus Master From DMA LPC Master Busy LPC Reg DRQ To DMA To PIC SIRQ LDRQ SERIRQ LPC Master Local Bus Master Local Bus Slave SIRQ LDRQ DRQ LPC Reg LPC to/from Local Bus Busy LFRAME# LAD[3:0] LDRQ# Initiates all transactions on LPC bus, takes/issues requests from Local bus. Takes request from LPC master and DMA. Issues request to LPC master from Local bus. Decodes SERIRQ into IRQ to be passed on to PIC. Decodes LDRQ# into DRQ sets and clears. Combines multiple LDRQ# outputs and passes results to DMA. Contains all the LPC I/O registers. LPC to Local bus interface module. Generates busy signal for clock controls. Figure 4-38. LPC Block Diagram www.national.com 134 Revision 0.8 Geode™ CS5535 LPC Port Functional Description (Continued) 4.13.1 LPC Protocol LPC supports memory read/write, I/O read/write, DMA read/write, and Firmware Hub Interface (see Table 4-22). Data transfers on the LPC bus are serialized over a 4-bit bus. CYCTYP: The Cycle Type field is driven by the host when it is performing DMA or target accesses. Bits [3:2] are used for cycle type and bit 1 is used for direction. Bit 0 is reserved. SIZE: This field is one clock. It is driven by the host on memory and DMA transfers to determine how many bytes are to be transferred. Bits [1:0] are used to determine size and bits [3:2] are reserved. TAR: The Turn Around field is two clocks, and is driven by the host when it is turning control over to a peripheral and vice versa. In the first clock a host or a peripheral drives the LAD[3:0] lines to 1111b, on the second cycle the host or peripheral TRI-STATES the LAD[3:0] lines. These lines have weak pull-ups so they will remain at a logical high state. ADDR: The Address field is four clocks for I/O cycles and eight clocks for memory cycles. It is driven by the host on target accesses. This field is not driven on DMA cycles. The most significant nibble is driven first. CHANNEL/Terminal Count: The Channel field is one clock and driven by the host on DMA cycles to indicate the DMA channel. Only 8-bit channels are supported (0, 1, 2, 3). DMA channel is communicated on LAD[2:0] and Terminal Count (TC) is communicated through LAD3. TC indicates the last byte of transfer, based upon the size of the transfer. If an 8-bit transfer and TC is set, then this is the last byte. DATA: This field is two clocks, representing one byte data. It is driven by the host on target and DMA cycles when data is flowing to the peripheral, and by the peripheral when data is flowing to the host. The lower nibble is driven first. SYNC: This field can be several clocks in length and is used to add wait states. Driven by the peripheral on target or DMA cycles. SYNC Timeout: 1) The host starts a cycle, but no device ever drives SYNC valid. If the host observes three consecutive clocks without a valid SYNC, it can abort the cycle. 2) The host starts a cycle, a device drives a SYNC valid to insert wait states (LAD[3:0] = 0101b or 0110b), but never completes it. This could happen if the peripheral locks up for some reason. The peripheral should be designed to prevent this case: – If the SYNC pattern is 0101b, then the maximum number of SYNC clocks is eight. If the host sees more than eight, it may abort the cycle. – If the SYNC pattern is 0110b, then no maximum number of SYNC clocks took place, the peripheral must have protection mechanisms to complete the cycle. Table 4-22. Cycle Types Supported Cycle Type Intel FWH Read Intel FWH Write Memory Read Memory Write I/O Read I/O Write DMA Read DMA Write Bus Master Mem Read Bus Master Mem Write Bus Master I/O Read Bus Master I/O Write Size 1 Byte 1 Byte 1 Byte 1 Byte 1 Byte 1 Byte 1, 2, 4 Bytes 1, 2, 4 Bytes 1, 2, 4 Bytes 1, 2, 4 Bytes 1, 2, 4 Bytes 1, 2, 4 Bytes Size Supported Yes Yes Yes Yes Yes Yes 1 Byte Only 1 Byte Only No No No No LFRAME# is used by the host to start or stop transfers. No peripherals drive this signal. A cycle is started by the host when it drives LFRAME# active and puts information related to the cycle on the LAD[3:0] signals. The host drives information such as address or DMA channel number. For DMA and target cycles, the host drives cycle type (memory or I/O), read/write direction, and size of the transfer. The host optionally drives data, and turns around to monitor peripherals for completion of the cycle. The peripheral indicates the completion of the cycle by driving appropriate values on the LAD[3:0] signals. The LAD[3:0] signals communicate address, control, and data information over the LPC bus between the host and the peripheral. The information carried on the LAD signals are: start, stop (abort a cycle), transfer type (memory, I/O, DMA), transfer direction (read/write), address, data, wait states, and DMA channel number. The following sections give an overview of fields used. Detailed field descriptions are provided in Table 4-23 on page 136. START: This field indicates the start or stop of a transaction. The START field is valid on the last clock that LFRAME# is active. It is used to indicate a device number, or start/stop indication. Revision 0.8 135 www.national.com Geode™ CS5535 LPC Port Functional Description (Continued) When the host is driving SYNC, it may insert a very large number of wait-states depending on PCI latencies. The peripheral must not assume any timeouts. SYNC Error Indication: A peripheral can report an error via the LAD[3:0] = 1010b encoding. If the host was reading data from a peripheral, the data will still be transferred in the next two nibbles, even though this data is invalid, the peripheral must transfer it. If the host was writing, data had already been transferred. In DMA if it was a multiple byte cycle, an error SYNC terminates the cycle. For more info on SYNC timeout and SYNC error details, refer to the LPC Specification. Table 4-23. Cycle Field Definitions: Target Memory, I/O, and DMA Field START CYCTYP # Clocks 1 1 Comment Start of Cycle. 0000b indicates a start of a cycle. Cycle Type. Indicates the type of cycle. Bits [3:0] 000x 001x 010x 011x 100x 101x 1100 1101 1110 1111 CHANNEL 1 Definition I/O Read I/O Write Memory Read Memory Write DMA Read DMA Write Reserved FWH Read FWH Write Reserved Channel #. Used only for DMA cycles to indicate channel number being granted. The LAD[2:0] bits indicate the channel number being granted, and LAD[3] indicates the TC bit. The encoding on LAD[2:0] for channel number is as follows: LAD[2:0] 000 001 010 011 100-111 Definition I/O Read I/O Write Memory Read Memory Write Reserved Only 8-bit channels are supported. TAR SIZE 2 1 Turn-Around. The last component driving LAD[3:0] will drive it high during the first clock and TRI-STATE during the second clock. Size of Transfer. Used only for DMA cycles. Bits [3:0] are reserved and must be ignored by the peripheral. LAD[1:0] 00 01-11 DATA 1 Byte DMA: 1 Byte ADDR 8 for Memory, 4 for I/O Definition 8-Bit Reserved Only 8-bit is supported for all transfers. Data Phase. The data byte is transferred with the least significant nibble first (D[3:0] on LAD[3:0], then D[7:4] on LAD[3:0]). DMA. The data byte is transferred with the least significant nibble first (D[3:0] on LAD[3:0], then D[7:4] on LAD[3:0]). Only one byte data transfer is supported. Address Phase. Address is 32-bit for memory, 16-bit for I/O. It is transferred most significant nibble first. DMA cycles do not use the ADDR field. www.national.com 136 Revision 0.8 Geode™ CS5535 LPC Port Functional Description (Continued) Table 4-23. Cycle Field Definitions: Target Memory, I/O, and DMA (Continued) Field SYNC # Clocks 1-N Comment Sync: Allows peripheral or host to synchronize (add wait-states). Generally, the peripheral or host drives 0101 or 0110 until no more wait-states are needed. At that point it will drive 0000. All other combinations are reserved. 0000 Sync achieved with no error. DMA. Sync achieved with no error. Also indicates no more transfer desired for that channel, and DMA request is de-asserted. 0101 Indicates that Sync not achieved yet, but the part is driving the bus. DMA. Part indicating wait states. 0110 Indicates that Sync not achieved yet, but the part is driving the bus, and expect long Sync. DMA. Part indicating wait states, and many wait states will be added. 1010 Special case. Peripheral indicating errors, see sync section in protocol overview. DMA. Sync achieved with error. Also indicates no more transfers desired for that channel, and DMA request is de-asserted. 1001 DMA (only). Sync achieved with no error and more DMA transfer desired to continue after this transfer. 4.13.2 Cycle Protocol Start of Cycle (see Figure 4-39): The host asserts LFRAME# for one or more clocks and drives a START value on LAD[3:0], all peripherals stop driving the LAD[3:0] signals even if in the middle of a transfer. The peripheral must always use the last START value when LFRAME# was active. On the clock after the START value, the host de-asserts LFRAME#. Abort Mechanism (see Figure 4-40): The host can cause an abort on the LPC interface by driving LFRAME# active with a START value of 1111b. The host must keep LFRAME# active for at least four consecutive clocks and drive LAD[3:0] to 1111b no later than the fourth clock after LFRAME# goes active. The host must drive LFRAME# inactive for at least one clock after an abort. An abort typically occurs on SYNC timeouts. LCLK LFRAME# LAD[3:0]# START CYCTYP ADDR 1 1 1-8 TAR 2 SYNC 1-n DATA 2 TAR 2 START 1 Figure 4-39. Start of Cycle Timing Diagram LCLK LFRAME# LAD[3:0]# START CYCTYP 1 1 ADDR 1-8 TAR 2 SYNC Peripheral must Stop driving Chip set will drive high Too many Syncs causes Timeout Figure 4-40. Abort Mechanism Timing Diagram Revision 0.8 137 www.national.com Geode™ CS5535 LPC Port Functional Description (Continued) 4.13.2.1 Host Initiated Cycles Memory Cycles: Memory read or write cycles are intended for memory-mapped devices. The ADDR field is a full 32 bits, and transmitted with most significant nibble first. Typically a memory device supports much less addressing and ignores address bits above which it is capable of decoding. I/O Cycles: I/O read or write cycles are intended for peripherals. These cycles are generally used for register or FIFO accesses and have minimal Sync times. Data transfers are assumed to be exactly 1 byte. The host is responsible for breaking up larger data transfers into 8-bit cycles. The minimum number of wait states between bytes is 1. The host initiated cycles are shown in Table 4-24. requested channel is active or not. The case where the ACT is low (inactive) will be rare, and is only used to indicate that a previous request for that channel is being abandoned. After indication, LDRQ# should go high for at least one clock. After that one clock LDRQ# can be brought low for next encoding sequence (see Figure 4-41.) DMA Transfer: Arbitration for DMA channels is performed through the 8237 within the host. Once the host won the arbitration, it asserts LFRAME# on the LPC bus. The host starts a transfer by asserting 0000b on LAD[3:0] with LFRAME# asserted. The host’s assert “cycle type” and direction is based on the DMA transfer. In the next cycle it asserts channel number and in the following cycle it indicates the size of the transfer. DMA Reads: The host drives 8 bits of data and turns the bus around, then the peripheral acknowledges the data with a valid SYNC. DMA Writes: The host turns the bus around and waits for data, then the peripheral indicates data is ready through valid SYNC and transfer of the data. The DMA initiated cycles are shown in Table 4-25. Table 4-24. Host Initiated Cycles Driven By Memory or I/O START CYCTYP + DIR ADDR TAR SYNC DATA TAR Read Cycle Host Host Host Host Peripheral Peripheral Peripheral Write Cycle Host Host Host Host Peripheral Host Peripheral Table 4-25. DMA Initiated Cycles Driven By Read Cycle (Host to Peripheral) Host Host Host Host Host Host Peripheral Peripheral Write Cycle (Peripheral to Host) Host Host Host Host Host Peripheral Peripheral Peripheral DMA START 4.13.2.2 DMA Initiated Cycles DMA on LPC is handled through the LDRQ# line from peripherals and special encoding on LAD[3:0] for the host. Single, demand, verify, and increment mode are supported on the LPC interface. Block, decrement, and cascade are not supported. Channels 0 through 3 are 8-bit channels. Only 8-bit channels are supported. Asserting DMA Requests: Peripherals need the DMA service to encode their request channel number on the LDRQ# signal. LDRQ# is synchronous with LCLK. Peripherals start the sequence by asserting LDRQ# low. The next 3 bits contain the encoded DMA channel number with the MSB first. And the next bit (ACT) indicates whether the CYCTYP CHANNEL SIZE DATA TAR SYNC TAR LCLK LDRQ# START MSB LSB ACT START Figure 4-41. DMA Cycle Timing Diagram www.national.com 138 Revision 0.8 Geode™ CS5535 LPC Port Functional Description (Continued) 4.13.3 Serial IRQ The LPC supports a serial IRQ scheme. This allows a single signal to be used to report ISA-style interrupt requests. Because more than one device may need to share the single serial IRQ signal, an Open Collector signaling scheme is used. Serial interrupt information is transferred using three types of frames: a Start frame, one or more IRQ Data frames, and one Stop frame (see Figure Figure 4-42, Figure 4-43, and Figure 4-44 on page 140). There are also two modes of operation. Quiet mode, initiated by the peripheral, and Continuous mode, initiated by the host: 1) Quiet (Active) Mode: To indicate an interrupt, the peripheral brings the SERIRQ signal active for one clock, and then places the signal in TRI-STATE mode. This brings all the state machines from the Idle state to the Active state. The host then takes control of the SERIRQ signal by driving it low on the next clock, and continues driving it low for 3-7 clocks more (programmable). Thus, the total number of clocks low will be 4-8. After those clocks, the host drives SERIRQ high for one clock and then places SERIRQ into the TRI-STATE mode. 2) Continuous (Idle) Mode: In this mode, the host initiates the Start frame, rather than the peripherals. Typically, this is done to update IRQ status (acknowledges). The host drives SERIRQ low for 4-8 clocks. This is the default mode after reset; it can be used to enter the Quiet Mode. Stop Frame After all of the Data frames, a Stop frame is performed by the host. This is accomplished by driving SERIRQ low for two to three clocks. The number of clocks determines the next mode: • If the SERIRQ is low for two clocks, the next mode is the Quiet mode. Any device may initiate a Start frame in the second clock (or more) after the rising edge of the Stop frame. • If SERIRQ is low for three clocks, the next cycle is the Continuous mode. Only the host may initiate a Start frame in the second clock (or more) after the rising edge of the Stop frame. Table 4-26. IRQ Data Frames Date Frame Number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 31-21 Usage IRQ0 IRQ1 SMI# (Not Supported) IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 IOCHK# INTA# INTB# INTC# INTD# Unassigned Data Frame Once the Start frame has been initiated, all of the serial interrupt peripherals must start counting frames based on the rising edge of the SERIRQ. Each of the IRQ/DATA frames has exactly three phases of one clock each: a Sample phase, a Recovery phase, and a Turn Around phase. During the sample phase, the device drives SERIRQ low if the corresponding interrupt signals should be active. If the corresponding interrupt is inactive, then the devices should not drive the SERIRQ signal. It will remain high due to pullup registers. During the other two phases (Turn Around and Recovery), no device should drive the SERIRQ signal. The IRQ/DATA frames have a specific order and usage as shown in Table 4-26. Revision 0.8 139 www.national.com Geode™ CS5535 LPC Port Functional Description (Continued) LCLK SERIRQ Drivers Host or Slave START REC TAR None Host Controller START: Start pulse width can be from 4-8 cycles, the width is determined by the value of START width. REC: Recover, host actively drives SERIRQ high. TAR: Turn Around Cycle. Dead cycle to prevent bus contention. Figure 4-42. Start Frame Waveform IRQ Set: LCLK SERIRQ Driver IRQ Clear: SERIRQ Driver SAMP REC None TAR SAMP IRQX REC TAR None SAMP: Sample, slave drives low or leaves high. REC: Recover, slave actively drives SERIRQ high if driven low during sample. TAR: Turn Around Cycle. Dead cycle to prevent bus contention. Figure 4-43. IRQ Frame Waveform Continues Mode: LCLK SERIRQ Drivers Quiet Mode: SERIRQ Drivers STOP Host Controller REC TAR None STOP Host Controller REC TAR None REC: TAR: Recover, host actively drives SERIRQ high. Turn Around Cycle. Dead cycle to prevent bus contention. Figure 4-44. Stop Frame Waveform www.national.com 140 Revision 0.8 Geode™ CS5535 LPC Port Functional Description (Continued) 4.13.4 Firmware Hub Interface The Firmware Hub (FWH) relies on the Intel Firmware Hub interface to communicate with the outside world. This interface consists of four bidirectional signals and one “control” input. The timing and the electrical parameters of the FWH interface are similar to those of the LPC interface. The Intel FWH interface is designed to use an LPC-compatible Start cycle, with a reserved cycle type code. This ensures that all LPC devices present on the shared interface will ignore cycles destined for the FWH, without becoming “confused” by the different protocols. When the FWH interface is active, information is transferred to and from the FWH by a series of “fields” where each field contains four bits of data. Many fields are one clock cycle in length but can be of variable length, depending upon the nature of the field. Field sequences and contents are strictly defined for read and write operations. 4.13.4.1 FWH Cycles A cycle is started on the rising edge of LCLK when LFRAME# is asserted and a valid cycle type is driven on LAD[3:0] by the host. Valid cycle types for the FWH are 1101b (read) and 1110b (write). FWH Read Cycles: A read cycle is initiated by asserting 1101b on LAD[3:0] with LFRAME# low. All data transfers are valid on the rising edge of the LCLK. The cycle is illustrated in Figure 4-45 and described in Table 4-27. FWH Write Cycles: A write cycle is initiated by asserting 1110b on LAD[3:0] with LFRAME# low. All data transfers are valid on the rising edge of the LCLK. The cycle is illustrated in Figure 4-46 and described in Table 4-28. Abort Operation: LFRAME# (FWH4) active (low) indicates either that a Start cycle will eventually occur or that an abort is in progress. In either case, if LFRAME# (FWH4) is asserted, the Intel FWH will “immediately” TRI-STATE its outputs and the FWH state machine will reset. During a write cycle, there is a possibility that an internal Flash write or erase operation is in progress (or has just been initiated). If LFRAME# (FWH4) is asserted during this frame, the internal operation will not abort. The software must send an explicit Flash command to terminate or Suspend the operation. The internal FWH state machine will not initiate a Flash write or erase operation until it has received the last data nibble from the chip set. This means that LFRAME (FWH4) can be asserted as late as this cycle (“cycle 12") and no internal Flash operation will be attempted. However, since the Intel FWH will start “processing” incoming data before it generates its SYNC field, it should be considered a nonbuffered peripheral device. LCLK LFRAME (FWH4) LAD[3:0] (FWH3-FWH0) Number of Clock Cycles START 1 IDSEL 1 ADDR 7 MSIZE 1 TAR 2 SYNC 3 DATA 2 TAR 2 Figure 4-45. FWH Read Cycle Revision 0.8 141 www.national.com Geode™ CS5535 LPC Port Functional Description (Continued) Table 4-27. FWH Read Cycle Signal START IDSEL Clock Cycle 1 1 LAD[3:0] 1101b 0000 Peripheral I/O I I Description On the rising edge of CLK with LFRAME# low, the contents of LAD[3:0] indicate the start of an FWH cycle. Indicates which FWH peripheral is selected. The value on the LAD[3:0] is compared to the IDSEL strapping on the FWH device pins to select which device is being addressed. Note: From Intel 82802 Specification - the boot device must have an ID (determined by ID strapping pins ID[3:0]) of 0. It is advisable that subsequent devices use incremental numbering. ADDR MSIZE TAR TAR WSYNC RSYNC DATA TAR TAR 7 1 1 1 2 1 2 1 1 xxxx 0000b 1111b 1111b (float) 0101b 0000b xxxx 1111b 1111b (float) I I I O O O O O N/A A 28-bit address phase is transferred starting with the most significant nibble first. Always 0000b (single byte transfer). The LPC host drives LAD[3:0] to 1111b to indicate a turnaround cycle. The FWH device takes control of LAD[3:0] during this cycle. The FWH device drives LAD[3:0] to 0101b (short wait-sync) for two clock cycles, indicating that the data is not yet available. The FWH device drives LAD[3:0] to 0000b, indicating that data will be available during the next clock cycle. Data transfer is two cycles, starting with least significant nibble. The FWH device drives LAD[3:0] to 1111b, to indicate a turnaround cycle. The FWH device floats its output and the LPC host takes control of LAD[3:0]. LCLK LFRAME# (FWH4) LAD[3:0] (FWH0-FWH3) Number of Clock Cycles START IDSEL 1 1 ADDR 7 MSIZE 1 DATA 2 TAR 2 SYNC 1 TAR 2 Figure 4-46. FWH Write Cycle www.national.com 142 Revision 0.8 Geode™ CS5535 LPC Port Functional Description (Continued) Table 4-28. FWH Write Cycle Signal START IDSEL Clock Cycle 1 1 LAD[3:0] 1110b 0000 Peripheral I/O I I Description On the rising edge of CLK with LFRAME# Low, the contents of LAD[3:0] indicate the start of an FWH cycle. Indicates which FWH peripheral is selected. The value on the LAD[3:0] is compared to the IDSEL strapping on the FWH device pins to select which device is being addressed. Note: From Intel(R) 82802 spec - the boot device must have an ID (determined by ID strapping Pins ID[3:0]) of 0. It is advisable that subsequent devices use incremental numbering. ADDR MSIZE DATA TAR TAR SYNC TAR TAR 7 1 2 1 1 1 1 1 xxxx 0000b xxxx 1111b 1111b (float) 0000b 1111b 1111b (float) I I I I O O O N/A A 28-bit address phase is transferred starting with the most significant nibble first. Always 0000b (single byte transfer). Data transfer is two cycles, starting with least significant nibble. The LPC host drives LAD[3:0] to 1111b to indicate a turnaround cycle. The FWH device takes control of LAD[3:0] during this cycle. The FWH device drives LAD[3:0] to 0000b to indicate it has received data or a command. The FWH device drives LAD[3:0] to 1111b, indicating a turnaround cycle. The FWH device floats its output and the LPC host takes control of LAD[3:0]. Revision 0.8 143 www.national.com Geode™ CS5535 4.14 REAL-TIME CLOCK FEATURES The Real-Time Clock (RTC) consists of three main blocks: the digital section, the analog section, and the level-shifter block (see Figure 4-47). The digital section contains the bus interface, RAM, voltage control, time generator, and the time keeper. The analog section contains the voltage switch and low power crystal oscillator. Finally, the level shifter block provides the appropriate voltage level translation of signals to and from the RTC block. Level shifters are needed because the RTC is powered by the VPP (output of the analog section), which is different from the VCORE and VCORE_VSB power domains. Features • Accurate timekeeping and calendar management • Alarm at a predetermined time and/or date • Three programmable interrupt sources Local Bus Level Shifter Data & Ctrls rtc_seconds rtc_minutes Index_Reg Ctrl_Reg A, B, C, D RAM I/F Gated Clocks rtc_hours rtc_weekday rtc_monthday rtc_months Bus Interface Index Read Data Write Data rtc_years Time Keeper • Valid timekeeping during power-down, by utilizing external battery backup • 242 bytes of battery-backed RAM • RAM lock schemes to protect its content • Internal oscillator circuit (the crystal itself is off-chip), or external clock supply for the 32.768 kHz clock • A century counter • Additional low-power features such as: — Automatic switching from battery to VSB — Internal power monitoring on the VRT bit — Oscillator disabling to save battery during storage • Software compatible with the DS1287 and MC146818 242x8 Bit RAM Update Clock Voltage Control Voltage Sense VIO_VSB VBAT KHZ32_XCI KHZ32_XCO Voltage Select Voltage Switch q Low Power Osc. 32 kHz Clock #0 #1 #14 Time Generator q q VPP Figure 4-47. RTC Block Diagram www.national.com 144 Revision 0.8 Geode™ CS5535 RTC Functional Description (Continued) 4.14.1 External Use Recommendations It is recommended that the external components for the oscillator be connected as illustrated in Figure 4-48. The recommended specifications for those external components are listed in Table 4-29. Capacitors C1 and C2 should be chosen to match the crystal’s load capacitance. The load capacitance CL “seen” by the crystal Y is comprised of C1 in series with C2 in parallel with the parasitic capacitance of the circuit. The parasitic capacitance is caused by the chip package, board layout, and socket (if any). The rule of thumb in choosing these capacitors is: CL = (C1 * C2)/(C1 + C2) + CPARASITIC C1 can be trimmed to achieve precisely 32.768 kHz. To achieve high time accuracy, use crystal and capacitors with low tolerance and temperature coefficients. Y C1 C2 To other modules Internal External KHZ32_XCI R1 KHZ32_XCO Figure 4-48. Recommended External Component Connections Table 4-29. External Component Recommended Specifications Component Crystal Parameters Resonance Type Serial Resistance Q Factor Shunt Capacitance Load Capacitance, CL Temperature Coefficient Resistor, R1 Capacitor, C1 Capacitor, C2 Resistor Capacitor Capacitor Values 32.768 kHz Parallel Mode N-Cut or XY-bar 40 kΩ 35000 2 pF 9-13 pF User-defined 20 MΩ (Note 1) 22 pF 22 pF 5% 5% 5% Max Min Max Tolerance User-defined Note 1. A single 20 MΩ resistor may be difficult to acquire. Substituting two 10 MΩ resistors in series is acceptable. Revision 0.8 145 www.national.com Geode™ CS5535 4.15 GENERAL PURPOSE INPUT/OUTPUT Proper use and understanding of the General Purpose Input/Output (GPIO) subsystem is the key to applying the CS5535 in a custom system design. By totalizing the optional features of the CS5535 GPIOs, system functions such as soft buttons, DDC monitoring, timers, system interrupts, and others, may be implemented. The system designer should pay careful attention to the suite of features available through the GPIO subsystem and, because the GPIOs are multiplexed with other on-chip functions, must make careful trade-offs to obtain the features desired in the system. The register space for control of the GPIO subsystem contains space for control of 32 GPIOs. Since only 28 GPIOs are realized, the control bits for the non-existent GPIO[31:29], and GPIO[23] are marked “Reserved”. GPIO[22:16] are multiplexed with the LPC bus; therefore, if the system requires an LPC bus, GPIO[22:16] are not available as GPIOs. Likewise, GPIO[15:14] are multiplexed with the SMB (System Management Bus); if the system requires the SMB, GPIO[15:14] will be dedicated to this function and not available as GPIOs. Other GPIOs are multiplexed with individual functions as indicated in Table 2-8 "GPIO Options" on page 42. Features • Input Features: — Each of the available GPIOs may be configured as an input. A block of eight Input Conditioning Functions, providing edge detection, event counting, and input filtering, may be configured for use by any eight of the 28 GPIOs, though all 28 may have edge detection. The optionally-conditioned input may then be fed to steering logic that can connect it to an interrupt, or power-management input event (PME). • Output Features: — Each of the available 28 GPIOs has a configurable output cell. The output cell for each GPIO may be independently configured to provide a variety of interface options. The cell may be enabled or disabled, configured as a totem-pole or open-drain type, have internal pull-up or pull-down resistors applied, or be inverted. — As indicated in Table 2-8 "GPIO Options" on page 42, the GPIOs have differing output driver types and reset defaults. When choosing a GPIO for a given function, choose one with a compatible output driver type, and one that the use of, does not make another desired function inaccessible. Careful study of this table will assist the system designer in making proper selections of the desired functionality of the suite of GPIOs. • Auxiliary Functions — Most of the 28 GPIOs have additional hard-wired internally-connected functions that may be selected by choosing either the AUX_1 or AUX_2 outputs. Use of these allows internal functions to be accessed at the device pins. Table 2-8 "GPIO Options" on page 42 identifies these auxiliary functions, including access to the UARTS and multi-function timers, as well as certain power-management controls. www.national.com 146 Revision 0.8 • Output Mapping: — After passing through the optional input conditioning circuits, any GPIO may be mapped (connected) to one of eight PIC-level interrupts, or to one of eight Power Management Event (PME) inputs. A given GPIO may not be simultaneously mapped to both an interrupt and a PME. The PIC subsystem interrupt inputs may be configured to cause the generation of an ASMI-type interrupt from any or all of the mapped GPIO signals. • Power Domains: — The GPIO circuits are distributed into the Working and Standby power domains. Those circuits in the Standby power domain may be used for system wakeup events, since they remain powered when the Working power is removed. As indicated in Table 2-8 "GPIO Options" on page 42, GPIO[28:24] are located in the Standby power domain; all others are in the Working power domain. Event/Filter pairs 6 and 7 are located in the Standby domain; pairs [5:0] are in the Working power domain. • Auto-Sense: — GPIO5 and GPIO6 have a feature called Auto-sense. When reset is applied to the system, a weak internal pull-up is applied to the pad. When reset is deasserted, the auto-sense value is used to establish the pull-up/down state on the de-assertion edge. If nothing pulls down the pad, then the weak pull-up continues to be applied. If the pad is pulled down, then pull-up is set to “no” and pull-down is set to “yes”. The output driver does not actively drive the pad, that is, it remains in TRI-STATE mode. If an auto-sensed pull-down is desired, a diode between the reset signal and the GPIO pin will pull it down during the Auto-Sense operation but will have no effect during normal operation. • Recommended Functions: — System designers at National Semiconductor have created a list of recommended uses for selected GPIOs, see Table 2-8 "GPIO Options" on page 42. The desired functions were matched up with GPIOs by selecting appropriate buffer types and multiplexing options to create an optimal list of recommended uses for the GPIOs. Designers may use these recommended functions as a starting point and make modifications to the list as needed to fit the particulars of their system. Geode™ CS5535 GPIO Subsystem Functional Description (Continued) 4.15.1 Programming for Recommended Functions Table 2-8 "GPIO Options" on page 42 includes an “Recommended Use” column. Shown below are the register settings to achieve the example. Example Use Getting Example Use Note --------------------------------------------------------------------------------------PCI_INTA# INPUT_ENABLE =1 Setup GPIO Interrupt Mapper AC_BEEP OUT_ENABLE =1 OUT_AUX1_SELECT =1 IDE_IRQ0 INPUT_ENABLE =1 IN_AUX1_SELECT =1 DDC_SCL OUT_ENABLE =1 Software write OUT_VALUE DDC_SDA OUT_ENABLE =1 Software write OUT_VALUE MFGPT0 OUT_ENABLE =1 OUT_AUX1_SELECT =1 MFGPT1 OUT_ENABLE =1 OUT_AUX1_SELECT =1 PCI_INTB# INPUT_ENABLE =1 Setup GPIO Interrupt Mapper UART1_TX OUT_ENABLE =1 OUT_AUX1_SELECT =1 UART1_RX INPUT_ENABLE =1 IN_AUX1_SELECT =1 THRM_ALRM# INPUT_ENABLE =1 IN_AUX1_SELECT =1 INPUT_INVERT =1 SLP_CLK# OUT_ENABLE =1 OUT_AUX1_SELECT =1 GPIO IN INPUT_ENABLE =1 Software read READ_BACK GPIO IN INPUT_ENABLE =1 Software read READ_BACK SMB_CLK INPUT_ENABLE =1 IN_AUX1_SELECT =1 OUT_AUX1_SELECT =1 SMB_DATA INPUT_ENABLE =1 IN_AUX1_SELECT =1 OUT_AUX1_SELECT =1 LPC_AD0 Hardware default Table 2-6 "DIVIL_BALL_OPT" on page 29 LPC_AD1 Hardware default Table 2-6 "DIVIL_BALL_OPT" on page 29 LPC_AD2 Hardware default Table 2-6 "DIVIL_BALL_OPT" on page 29 LPC_AD3 Hardware default Table 2-6 "DIVIL_BALL_OPT" on page 29 LPC_DRQ# Hardware default Table 2-6 "DIVIL_BALL_OPT" on page 29 LPC_SERIRQ Hardware default Table 2-6 "DIVIL_BALL_OPT" on page 29 LPC_FRAME# Hardware default Table 2-6 "DIVIL_BALL_OPT" on page 29 WORK_AUX OUT_ENABLE =1 OUT_AUX1_SELECT =1 LOW_BAT# INPUT_ENABLE =1 IN_AUX1_SELECT =1 PME# INPUT_ENABLE =1 Setup GPIO PME Mapper MFGPT7 OUT_ENABLE =1 OUT_AUX1_SELECT =1 PWR_BUT# INPUT_ENABLE =1 IN_AUX1_SELECT =1 Revision 0.8 147 www.national.com Geode™ CS5535 GPIO Subsystem Functional Description (Continued) 4.15.2 Register Strategy The register set for the GPIO subsystem has been arranged in such a way as to eliminate the need for readmodify-write operations. Individual GPIO control bits may be directly and immediately altered without requiring knowledge of any other GPIO states or bit settings. Previous systems required the current settings for all GPIOs to be read, selected pins changed, and the result written back. If this read-modify-write operation was interrupted by another process that also used the GPIOs, then erroneous operation could result. To avoid the read-modify-write operation, two data bits are used to control each GPIO feature bit, wherein a feature is enabled or disabled. One register bit is used to establish a logic 1, while a second register bit is used to establish a logic 0. A 1 in a register bit changes the feature bit’s value, while a 0 does nothing. Since there are two register bits for each feature bit, for each GPIO, there are four combinations of register bits possible. The two control bits operate in an exclusive-OR pattern, as illustrated in Table 4-30. GPIO5 has a 0 in the logic 0 bit position (register bit 13), and a 1 in the logic 1 bit position (register bit 5), so the GPIO5 feature bit would become a 1. GPIO4 has a 1 in the logic 0 bit position (register bit 13), and a 0 in the logic 1 bit position (register bit 5), so the GPIO4 feature bit would become a 0. GPIO7 has a 1 in both bit positions 15 and 7. Writing a 1 to both the logic 1 and logic 0 bit positions causes no change to the GPIO7 feature bit. GPIO6 has a 0 in both bit positions 14 and 6. Writing a 0 to both the logic 1 and logic 0 bit positions causes no change to the GPIO6 control bit. GPIO[3:0], also have 0s in both bit positions, so they experience no change. Reads produce a normal and an inverted value. For example, assume the Output Enable is set only for GPIO4 in the above register. A read would return the value EF10h. Actual GPIO registers associated with feature bit settings are 32 bits wide and each handle 16 GPIOs. They are organized into low and high banks. The low bank deals with GPIO[15:0], while the high bank deals with GPIO[28:24] and GPIO[22:16]. In addition to these “bit registers”, there are value registers for the Input Conditioning Functions. 4.15.3 Lock Bits Many GPIO registers are protected against accidental changes by Lock Enable registers that prevent further changes. Once a LOCK bit is set, the associated register can not be changed until the corresponding LOCK bit is cleared. There are two Lock Bit registers, one for the high bank (GPIOH_LOCK_EN, GPIO I/O Offset 8Ch) and one for the low bank (GPIOH_LOCK_EN, GPIO I/O Offset 3Ch). All GPIO registers are protected by LOCK bits except the High and Low Bank Read Back registers, (GPIO[x]_READ_BACK), High and Low Bank Positive Edge Status registers (GPIO[x]POSEDGE_STS), the High Low Bank Negative Edge Status registers (GPIO[x]NEGEDGE_STS), and of course the Lock Enable registers themselves. Table 4-30. Effect on Feature Bit Logic 0 Bit Position 0 1 0 1 Logic 1 Bit Position 0 0 1 1 Effect on Feature Bit No change Feature bit is cleared to 0 Feature bit is set to 1 No change An example 16-bit register controlling a feature bit for eight GPIOs is illustrated in Table 4-31. Note that the real registers are 32 bits; 16 bits are used here as an illustrative example. Assume that the register in Table 4-31 allows setting and clearing of an unspecified “feature bit” for GPIO[7:0]. Assume that the 16-bit value given in the example has just been written into the register. In this example, all four possible bit combinations fromTable 4-30 are examined. Table 4-31. 16-Bit GPIO Control Register Example “1” Sets Control Bit to 0 Bit No. Value GPIO # 15 1 7 14 0 6 13 0 5 12 1 4 11 0 3 10 0 2 9 0 1 8 0 0 7 1 7 6 0 6 “1” Sets Control Bit to 1 5 1 5 4 0 4 3 0 3 2 0 2 1 0 1 0 0 0 www.national.com 148 Revision 0.8 Geode™ CS5535 GPIO Subsystem Functional Description (Continued) 4.15.4 GPIO Basic I/O Configuration The General Purpose Input and Output (GPIO) Interface is illustrated in Figure 4-49. The figure represents one of twenty-eight GPIOs potentially available. Note the GPIOs [31:29] and [23] are non-existent. Table 2-8 "GPIO Options" on page 42 provides a complete list of features for each GPIO and should be consulted when configuring a system. Each GPIO has basic configuration options used to set up the characteristics of the GPIO for either input or output. Each of the functions in the list below follows the GPIO register strategy outlined inSection 4.15.2 "Register Strategy" on page 148 unless otherwise noted. This strategy allows individual GPIOs to be modified without accidentally changing the characteristics of unrelated GPIOs, and without requiring ‘read-modify-write’ cycles. All values are active high. • OUT_EN. When high, enables this GPIO for output. A pad may be configured for output, input, or both. • IN_EN. Enables this GPIO for input. A pad may be configured for input, output, or both. • OUT_VAL. This will establish the value driven to the pad when it is selected as an Output, unless either OUT_AUX1 or OUT_AUX2 are selected. The value driven to the GPIO pad is subject to an optional inversion. Event Event Count Enable Count Positive Edge Enable • OUT_INVRT_EN. When high, inverts the Output Value. • IN_INVRT_EN. Inverts the signal applied to the ball, and presents the inverted value to all follow-up circuitry (i.e., input conditioning functions). • OUT_OD_EN. Configures this GPIO for open-drain operation. When the output pad is to be driven low, the pad is driven low. When the output pad is to be driven high, the pad is allowed to float and is not driven. • OUT_AUX1_SEL and OUT_AUX2_SEL. Selects an internal auxiliary source for the Output Value. Table 2-8 "GPIO Options" on page 42 identifies all the possible internal connections for these two auxiliary sources. • IN_AUX1_SEL. Selects an internal source as an input instead of the ball. Table 2-8 "GPIO Options" on page 42 lists all the functions that may be connected in this manner. • PU_EN. Applies a weak pull-up to the pad. The effect of this control is independent of all other settings except PD_EN. If PU_EN is set by software, PD_EN is automatically cleared. • PD_EN. Applies a weak pull-down to the pad. The effect of this control is independent of all other settings except PU_EN. If PD_EN is set by software, PU_EN is automatically cleared. Filter Amount Filter Enable Input Enable Input Invert Enable Pull-Up Enable Event Counter Digital Filter Read Status Input Conditioning Functions (1 of 8) Negative Edge Enable Event Enable X,Y,Z,W Interrupt Mapping Registers Interrupts Ball AUX1 AUX2 Output Value [7:0] PME Open-Drain Output Output Invert Enable Enable Enable [7:0] X,Y,Z,W PME Mapping Registers Pull-Down Enable Figure 4-49. GPIO Configuration Revision 0.8 149 www.national.com Geode™ CS5535 GPIO Subsystem Functional Description (Continued) 4.15.5 Input Conditioning Functions GPIOs in the CS5535 may have their inputs conditioned by configurable circuitry as illustrated in Figure 4-49 on page 149. Any GPIO may be connected to one of eight Input Conditioning functions, each consisting of a Digital Filter and an Event Counter (known as an Event/Filter pair). Each GPIO is followed by an edge detection function that may be set for either positive or negative going edges. As shown in Figure 4-49, the edge detection function may be used to monitor the output of the Event/Filter pair that has been associated with that particular GPIO, or it may be used independently of the Event /Filter pair. These functions are enabled as follows: • IN_FLTR_EN. Enables the input filter function of the associated GPIO. • EVNTCNT_EN. Enables the event counter function of the associated GPIO. • IN_POSEDGE_EN and IN_NEGEDGE_EN. Enables the edge detection function and mode. The final input value may be read back by a software accessible register (GPIO[x]_READ_BACK). It may also be used as an Interrupt or a Power Management Event. There are a total of eight Digital Filter/Event Counter pairs that are shared by 28 GPIOs. There is a selection function to associate a given Filter/Counter pair with a given GPIO. All GPIOs incorporate edge detection. 4.15.5.1 Input Filter Conditioning Function The digital filter is one-half of a Filter/Event conditioning circuit. (The other half is the Event Counter.) The filter is used to produce a stable output from an unstable input. Mechanical switch de-bounce is a typical use. To use one of the eight digital filters, it must first be assigned to one of the GPIO inputs using one of the GPIO_FE[x]_SEL registers (GPIO I/O Offsets F0h-F7h); where “x” is the number of the Filter/Event pair, 0 to 7. Then the filter function must be enabled through either the GPIOL_IN_FLTR_EN (GPIO I/O Offset 28h) or the GPIOH_IN_FLTR_EN (GPIO I/O Offset A8h) registers, depending on whether the selected GPIO is in the high [28:16] or low [15:0] bank. Finally, a GPIO_FLTR[x]_AMNT (GPIO I/O Offsets 50h, 58h, 60h, 68h, 70h, 78h, D0h, and D8h) must be determined and then programmed to establish the filter’s stability period. The associated GPIO input must ultimately remain stable for a FLTR_AMNT number of 32 kHz clock edges in order for the output to change. A FLTR_AMNT of 0 effectively disables the filtering function, because the counter will not roll over from 0 to all 1s. The maximum FLTR_AMNT is FFFFh. The digital filter is based upon a 16-bit programmable down-counter. An initial count is loaded into the counter via the GPIO_FLTR[x]_AMNT register. When the associated GPIO input changes, the counter begins counting down from FLTR_AMNT towards 0. If the associated GPIO input remains stable for the length of the count-down period, then the counter reaches 0 and produces an output pulse to whatever the GPIO is internally connected to. If the associated GPIO input changes during the count-down period, then the counter reloads the initial count from the GPIO_FLTR[x]_AMNT register and begins counting down towards 0 again. Direct access to the counter’s state is provided by the R/W register GPIO_FLTR[x]_CNT, that may be read at any time to determine the current value of the counter. The GPIO_FLTR[x]_CNT register may also be written to at any time, thereby jamming the counter state forward or backward from the current count. Reads and writes of the GPIO_FLTR[x]_CNT register are internally synchronized to avoid false read values and corrupted writes, that is, reads and writes may occur to a filter circuit without concern of the phasing or timing of the 32 kHz clock edges. When GPIO[x]_IN_FLTR_EN is low the filter circuit is not clocked. The filter circuit is used to produce a stable output from an unstable input. Mechanical switch de-bounce is a typical use. The default value for all flip-flops, the Down Counter, and the Filter Amount Register is zero. Software establishes the filter amount. As long as the preliminary input on the left matches the filtered input on the right, the circuit is stable and the counter continuously loads the filter amount value. When the preliminary input changes, the counter begins to count. If the input remains steady, then the counter reaches zero and enables loading the value flipflop. This brings the circuit back to the stable point. If the input does not remain steady, then the counter reloads. The preliminary input on the left must remain steady the “filter amount” number of clock edges for the final input on the right to change. A filter amount of zero effectively disables the filtering function because the Down Counter will not roll over backwards to all ones. The maximum filter amount is FFFFh 4.15.5.2 Input Event Counter Conditioning Function The event counter is one half of a filter/event conditioning circuit, and is in series with its associated filter. (The other half is the digital filter.) It counts events and can produce an output when a predefined count is reached. The event counter may be down-counted by writing to a particular address. It may be used as a rate counter that may be periodically read, and that produces no output at all. To use one of the eight event counters, it must first be assigned to one of the GPIO inputs using one of the GPIO_FE[x]_SEL registers (where X is the number of the Filter/Event pair, 0 to 7). Then the associated digital filter must be enabled, through either the GPIOL_IN_FLTR_EN or GPIOH_IN_FLTR_EN registers, depending on whether the selected GPIO is in the high [28:16] or low [15:0] bank. If digital filtering is not required, program the associated GPIO_FLTR[x]_AMNT registers to 0000h. Finally, the desired “compare value” (GPIO_EVNTCNT[x] _COMPARE) must be determined and then programmed to establish the number of events that will produce an output when that count has been reached. www.national.com 150 Revision 0.8 Geode™ CS5535 GPIO Subsystem Functional Description (Continued) The event counter is based upon a 16-bit programmable up/down counter. The up-down counter counts positive edges of the selected GPIO input and produces a constant or level output when the GPIO_EVNTCNT[x] (counter value) exceeds the CPIO_EVNTCNT[x]_COMPARE (compare value). The output can be read as the GPIO and/or used to drive an auxiliary input. The counter may be counted down one count by writing to one of two addresses, depending on which bank (High or Low) the associated GPIO resides in. Knowledge of which GPIO is associated with the event counter is required, since these two decrementer registers have a dedicated bit for each GPIO. When counted down, this counter, unlike the counter in the digital filter, will roll over from 0000h to FFFFh. Typically, decrementing is used to clear an interrupt or power management event as part of the associated service routine. 4.15.5.3 Uses of the Event Counter Such an auxiliary input could be used to drive an ASMI or maskable interrupt. Assume the compare value is set to 0. The service routine clears the ASMI by decrementing the counter via the mechanism illustrated. If additional events have occurred, the count does not decrement to 0 and the ASMI remains asserted. The count up and down inputs are synchronized such that false values are not created if up and down pulses occur at or near the same instant in time. The counter will not decrement through 0. Alternatively, the compare value could be set to a higher value to trigger an ASMI or interrupt when a certain number of events has occurred. In this case, the ASMI or interrupt is cleared by writing the counter to 0. Lastly, the input value may be ignored and the event counter used as a rate indicator. If software reads the counter at a fixed periodic interval, an input pulse rate may be measured. Such an approach may be used to implement a tachometer function. The counter will increment past all Fs back to 0. As suggested above, the counter may be read or written under software control. The read and write operations are synchronized such that false values are not created if count up pulses occur at or near the same instant in time. 4.15.5.4 Input Edge Conditioning Function The Edge Detection function is illustrated as part of Figure 4-49 on page 149. It is normally used to generate an ASMI or maskable interrupt on each positive and/or negative edge of an input signal. Use of this function simultaneously with the event counter function is somewhat logically mutually exclusive, but is not prevented in hardware. Each GPIO has the optional edge detection function. The reset default for the detection circuit establishes a 0 level on GPIO[x]_POSEDGE_EN and GPIO[x]_NEGEDGE_EN. When both are set to 0, the edge detection function is disabled. If either a positive or negative edge detection is enabled, an active high output is produced when the appropriate edge occurs. This level must be cleared by writing to either the GPIO[x]_POSEDGE_STS or the GPIO[x]NEGEDGE_STS registers, whichever is appropriate. If another edge occurs before clearing, the active high output is not affected. If the clear action occurs at the “same time” as another edge, the result is not defined. Each edge detection function is controlled by four registers as follows: • Positive Edge Enable (GPIO[x]_POSEDGE_EN). Enabled if feature bit is high. • Negative Edge Enable (GPIO[x]_NEGEDGE_EN). Enabled if feature bit is high. • Positive Edge Status (GPIO[x]_POSEDGE_STS). Set indicates edge. Write 1 to clear. • Negative Edge Status (GPIO[x]_POSEDGE_STS). Set indicates edge. Write 1 to clear. 4.15.5.5 Output Steering (Mapping) Outputs from the internal GPIO circuits, driven by inputs to the CS5535 from the system, may be steered (or ‘mapped’) to either interrupts, or power management events (PME). Sufficient steering logic exists in the CS5535 to provide for eight independent interrupts and simultaneously for eight independent PMEs. The eight GPIO interrupts are all in Working power domain; of the eight PMEs, [7:6] are in Standby power domain and [5:0] are in Working domain. Those in the Standby power domain are intended to be used to awaken the system when the Working power domain is off, however, they may also be used when the Working power domain is on. The interrupts are connected to the PIC subsystem, and the PMEs are connected to the Power Management subsystem. Four 32-bit steering registers control the routing of the GPIOs’ internal output (that produced by an input to the chip from an external source, or from one of the internallyconnected AUX inputs) to either an interrupt or PME. The set of four registers taken together, contain a nibble for each GPIO. The upper bit of each nibble selects either a PME (if high) or an interrupt (if low). The remaining three bits of each nibble select which of the eight possible interrupts or PMEs the GPIO will be steered to. The four registers are identified as GPIO Mapper X, Y, Z, and W. Their GPIO associations are as follows: • GPIO_MAP_X = GPIO[7:0] • GPIO_MAP_Y = GPIO[15:8] • GPIO_MAP_Z = GPIO[23:16] • GPIO_MAP_W = GPIO[31:24] The steering logic does not prohibit mapping of two or more GPIOs to the same output, but it is impossible to create a single GPIO that functions simultaneously as both an interrupt and a PME. Registers X, Y, Z, and W default to all 0s, as do both the High and Low EVNT_EN registers. Thus, all GPIOs are mapped to INT[0] after a reset, but none are enabled. Revision 0.8 151 www.national.com Geode™ CS5535 GPIO Subsystem Functional Description (Continued) 4.15.5.6 Auto Sense Two GPIOs (GPIO5 and GPIO6) have a function called “Auto-sense”. Auto-sense is a method of automatically determining whether or not to apply a pull-up or pull-down to the corresponding GPIO input. Auto-sensed inputs behave as follows: when reset is applied to the system, a weak pull-up is applied to the pad. When reset is de-asserted, the sensed value is used to establish the pull-up/down state on the de-assertion edge. If nothing pulls down the pad, then the pull-up continues to be applied. If the pad is pulled down, then the pull-up is cleared to 0 and the pull-down is set to 1. If a pull-down is desired, a diode between the reset signal and the GPIO pin will pull it down during the Auto-Sense operation but have no effect during normal operation. www.national.com 152 Revision 0.8 Geode™ CS5535 4.16 MULTI-FUNCTION GENERAL PURPOSE TIMER The Multi-Function General Purpose Timer module contains eight multi-function general purpose timers (MFGPTs). Six of the eight MFGPTs are in the Working power domain running off a 32 kHz clock or a 14.318 MHz clock, while the other two are in the Standby power domain running off a 32 kHz clock. The Working power domain contains the following blocks: • Six MFGPTs each split into three blocks, one containing I/O registers, one containing the clock switch, and one containing the timer logic. • 15-bit prescaler to divide down the 14.318 MHz clock and generate 15 carry-out signals. • 15-bit prescaler to divide down the 32 kHz clock and generate 15 carry-out signals. Bus Interface 32 kHz Prescaler Working Domain Control and MSR Registers 14.318 MHz Prescaler MFGPT0 I/O Reg Clock Timer Switch MFGPT1 I/O Reg Clock Timer Switch MFGPT2 I/O Reg Clock Timer Switch MFGPT3 I/O Reg Clock Timer Switch MFGPT4 I/O Reg Clock Timer Switch MFGPT5 I/O Reg Clock Timer Switch MFGPT6 I/O Reg I/F MFGPT7 I/O Reg I/F • Logic to implement Local Bus Interface, Control Logic, MSR Registers, and NMI, IRQ, and Reset Output Events. • Two blocks containing I/O registers to write into the two MFGPTs in the Standby power domain. The Standby power domain contains the following blocks: • Two MFGPTs. • 15-bit prescaler to divide down the 32 kHz clock and generate 15 carry-out signals. • Interface for signals going between Standby and Working power domains. Figure 4-50 shows the top level block diagram of the MultiFunction General Purpose Timer module. Features Each MFGPT operates independently and can have the following features: • 32 kHz or 14.318 MHz clock selectable by software (MFGPT0 to MFGPT5 only; MFGPT6 and MFGPT7 use 32 kHz clock). • Programmable input clock prescaler divisor to divide input clock by 2i, where i = 0 to 15. • Watchdog timer (trigger GPIO output, interrupt, or reset). • Pulse Width Modulation (PWM). • Pulse Density Modulation (PDM). • Blink (low frequency pulse for LED). • General Purpose Timer. • Generate GPIO outputs. • Provide outputs for generating reset (limited to MFGPT0 to MFGPT5), IRQs, NMI, and ASMI (indirectly through PIC). Power Domain Crossing I/F MFGPT6 Timer MFGPT7 Timer 32kHz Prescaler Standby Domain Figure 4-50. MFGPT System Top Level Block Diagram Revision 0.8 153 Reset and Interrupt Generation www.national.com Geode™ CS5535 MFGPT Functional Description (Continued) 4.16.1 Prescaler The 15-bit prescaler is a binary down counter, dividing down the incoming clock, and provides 15 outputs for the MFGPTs. The frequency of these outputs ranges from 2-1 to 2-15 of the input frequency and each pulse is one incoming clock high, so these outputs function as increment enables for the MFGPTs. The prescaler resets to 000016 and starts decrementing after reset. The prescaler output vector, psclr_out[14:0], is based on prescaler counter psclr_cnt[14:0], where psclr_out[i] = &(~psclr_cnt[i:0]) (i.e., prescaler output bit i is asserted if the prescaler counter from bit i down to bit 0 are all low). When the prescaler reaches 000016, all prescaler outputs are asserted at that time. The external clock for the prescaler is activated if there is one or more MFGPTs activated using it as its clock source; it is also activated for MFGPT I/O register writes and synchronous counter reads (only for 14.318 MHz) when the MFGPT being written has already selected the 14.318 MHz clock as its clock source. Whenever the external clock is activated, the prescaler counts. Therefore, multiple MFGPTs and register access can affect the prescaler counting. From the point of view of the MFGPT, once the MFGPT is disabled and then re-enabled, it cannot be determined exactly when the prescaler carry-out occurs as it does not know how long the prescaler has been stopped, if at all. 4.16.2 I/O Registers Block The I/O register write data is first stored in I/O register submodules before being transferred over to the MFGPTs. There are two types of I/O register sub-modules, one for the Working power domain and one for the Standby power domain. The main difference is that for the Working power domain, except for the counter register, the register values here and the register values in the timer are the same. For the Standby power domain, the register values in the I/O register sub-module cannot be relied upon except during write, as this logic could have been powered down in Standby mode and the register data is therefore invalid. For the Standby power domain, the read always comes from the timer directly. 4.16.2.1 MFGPT Register Set There are four software accessible I/O registers per MFGPT: Up Counter, Comparator 1 Value, Comparator 2 Value, and Setup registers. (See Section 5.17 "Multi-Function General Purpose Timer Register Descriptions" on page 466 for register details.) Writes to these registers are first stored here and then transferred to a separate copy of the register in the timer. For MFGPT0 to MFGPT5, read of these registers, except for the counter, comes from the registers here, while read of the counter register comes from the timer. For MFGPT6 and MFGPT7, reads of these registers comes from the copy inside the timer. (TW Note: Restate reason or be more precise in reference.) 4.16.2.2 Setup Register The Setup Register contains the following control fields that control the MFGPT operation: • Counter Enable. Enables the Up Counter to count (it does not enable/disable other MFGPT functions). • Clock Select. Instructs the clock switch logic to use the 32 kHz clock as the MFGPT clock if low or the 14.318 MHz clock if high, once this register has been written (only for MFGPT0 to MFGPT5). • Scale Factor. Selects the prescaler divide scale factor for Up Counter to increment. • Stop Enable. Enables the Up Counter to stop counting during a system power management Sleep mode (for MFGPT0 to MFGPT5) or Standby mode (for MFGPT6 and MFGPT7). • External Enable. Enables the Up Counter to be cleared and restarted rather than performing the next increment each time there is a low to high transition detected on the GPIO input associated with the timer. An asynchronous edge-detector catches the transition; the signal is then synchronized and sent to clear the counter synchronously. Therefore, the clear does not occur immediately on the transition. • Reverse Enable. Flips the order of the Up Counter outputs going to the Compare 1 circuit so that bit 0 becomes bit 15, bit 1 becomes bit 14, etc. This allows the timer logic to generate a PDM signal instead of a PWM signal. To properly generate a PDM signal, the Compare 2 Value should be set to FFFF16 to allow the Compare 1 Value to establish the density. • Compare 1 Mode. Controls the Compare 1 output. There are four cases: 00: Disabled. Output is low. 01: Compare on Equal. The compare output goes high when the Up Counter value, after going through Bit Reverse logic, is the same value as the Compare 1 Value. 10: Compare on GE. The compare output goes high when the Up Counter value, after going through Bit Reverse logic, is greater than or equal to the Compare 1 Value. 11: Event. Same as “Compare on GE”, but an event is also created. This event can be read and cleared via the MFGPT Setup Register and is used to generate interrupt and reset. • Compare 2 Mode. Same as Compare 1 Mode, except this controls the Compare 2 output. The Up Counter is directly compared against the Compare 2 Value (i.e., without going through Bit Reverse logic). All of the above fields, except Count Enable, are write-once only. www.national.com 154 Revision 0.8 Geode™ CS5535 MFGPT Functional Description (Continued) Compare Status/Event Bits The Setup register also contains two status bits: one from Compare 1 and one from Compare 2. If Event mode is selected, then these two status bits represent the events from the two Compare circuits, and writing a 1 to one of the bits would clear that particular event. If Event mode is not selected, then the status bits read back the compare outputs, and writing to those bits has no effect. Note that since this logic is in the Working power domain, MFGPT6 and MFGPT7 would lose these events when VCORE is powered off. In order for events to be captured again, the chip has to have VCORE powered up out of Standby mode and then come out of reset. The Compare 1 and Compare 2 outputs may change simultaneously on the same MFGPT clock edge. However, when checking the outputs through the two status bits after this occurred, on rare occasions the read may find only one of the two outputs changed to the new value. This could occur when the two outputs change at about the same time they are synchronized, by separate synchronizers to the local bus clock domain, and one synchronizer captured the new value in time while the other one does not. A subsequent read can show that both outputs did change states. 4.16.2.3 Register Initialization Sequence for Event Mode If the Setup register is written before the other three I/O registers, and if Event mode is selected for Compare 1 mode or Compare 2 mode, then events will be triggered immediately. This is because the compare outputs will look for a Compare register value greater than or equal to the counter, and the result will be true as those registers are all 0. To avoid triggering these events on Setup register initialization, first initialize the Compare 1 Value and Compare 2 Value registers before initializing the Setup register. 4.16.2.4 Register Data Transfer to/from MFGPT Only WORD writes and DWORD writes are accepted for I/O register accesses; BYTE writes to I/O registers are ignored. The DWORD write would cause the two I/O registers located within the DWORD boundaries to be written in parallel. If Up Counter, Compare 1 Value, or Compare 2 Value registers are written while the MFGPT is running, it could cause the compare outputs to change in the middle of a prescaler period (i.e., not at a clock cycle where the prescaler signals a counter increment). For MFGPT0 to MFGPT5, the clock switch circuitry disables all clocks to MFGPT until the Setup register has been written. Therefore, even if the Up Counter, Compare 1 Value, and/or Compare 2 Value registers are written before the Setup register; these register values would get transferred to the timer at the same time as the Setup register values. All reads and writes to MFGPT registers can be done by software at any time and are completed without requiring any additional software operation and without affecting the proper operation of the MFGPT as long as a clock to the MFGPT has been selected by writing to the Setup register. On a write, the write transfer on the bus is considered complete when the write to the register in the I/O register submodule is complete. This occurs before the register data is transferred to the timer. However, a subsequent read or write to the same register will be held up until that first write transfer to the timer is complete. The Setup register, except for bits 13 and 14, are handled in the same way as the Compare 1 Value and Compare 2 Value registers. Bits 13 and 14 write and read were discussed earlier, where the entire logic is in the Working power domain. 4.16.2.5 Register Re-initialization If it is necessary to re-initialize the Up Counter, Compare 1 Value, or Compare 2 Value, the following sequence should be followed to prevent any spurious reset, interrupt, or output pulses from being created: 1) 2) 3) 4) 5) Clear Counter Enable bit to 0. Clear Interrupt Enable, NMI Enable, and Reset Enable bits in MSRs; disable GPIO inputs and outputs. Update Up Counter, Compare 1 Value, and Compare 2 Value registers as desired. When updates are completed, clear any event bits that are set. Set up Interrupt Enable, NMI Enable, and Reset Enable bits in MSRs; enable desired GPIO inputs and outputs. Set Counter Enable bit to 1. 6) 4.16.3 Clock Switch The clock switch output is disabled at reset and selection can only be done one time after reset, at the first write to Setup register. Restriction on Register Read/Write Sequence Due to Clock Switch Note that because the timer clock is stopped until the first write to the Setup register, a write to one of the other three I/O registers during this time could not complete its transfer to the timer. As a result, a second access, read or write, to the same register will cause the bus interface to hang, as the second access waits for the first access (the initial write) to complete before completing its own operation. But since the first access cannot complete without a clock, the second access is in limbo. This means no more accesses can occur, so there is no way to write to the Setup register to enable the timer clock. Care should be taken to see that this situation does not occur. Revision 0.8 155 www.national.com Geode™ CS5535 MFGPT Functional Description (Continued) 4.16.4 Single MFGPT Figure 4-51 shows the functionality of one of these timers. There are two types of timers, one for the Working power domain and one for the Standby power domain. 4 0 15 Scale Factor VCORE 14 MHz/32 kHz Prescaler_Carry_Outs Count_Enable Stop Enable Count 16 Bit Sync Up Counter Standby State/ Sleep State Clear & Re-start GPIO Clear GPIO Input Value External Enable 32 kHz/14 MHz Little Endian Big Endian Bit Reverse Reverse Enable Compare 1 Mode Compare 1 Output Compare 1 Compare 1 Event Compare 1 Value Compare 2 Mode ≥ Compare 2 Compare 2 Output Compare 2 Event Compare 2 Value Figure 4-51. MFGPT Block Diagram www.national.com 156 Revision 0.8 Geode™ CS5535 MFGPT Functional Description (Continued) 4.16.4.1 Clock Selection and Counter Increment The MFGPT can use either the 32 kHz clock or 14.318 MHz clock as the clock source (MFGPT6 and MFGPT7 in Standby power domain are limited to the 32 kHz clock). When the Counter Enable bit is high, the MFGPT is activated and capable of counting. An actual increment is performed when the selected prescaler divide-by signals the increment; this is done through the Scale Factor selecting one of 16 signals. Table 4-32 shows how the Scale Factor effectively divides down the incoming clock. 4.16.4.2 Compare 1 and Compare 2 Outputs When the Up Counter reaches the Compare 1 Value, the Compare 1 Output is asserted. When the Compare 2 Value is reached, the Compare 2 Output is asserted, and the Up Counter then synchronously clears and restarts. The MFGPT outputs coming from Compare 1 and Compare 2 are all glitch-free outputs. The compare outputs and events may change in the middle of a prescaler period if new values are written to the Up Counter, Compare 1 Value, or Compare 2 Value registers. These compare outputs can be used to trigger their respective events and drive GPIO outputs. The events are used to trigger interrupts, NMI, and reset. 4.16.4.3 GPIO Input The Up Counter could also be software selected to have a GPIO input positive edge as another source for the counter to clear and restart. The GPIO input signal is asynchronous to the timer and the timer uses a flip-flop to capture the GPIO rising edge. It takes up to one prescaler clock period plus two MFGPT clock periods from the GPIO rising edge for the clear to take effect. Once the counter is cleared, this edge detect circuit can then accept a new GPIO edge. Each individual pulse can be as short as a few nanoseconds wide for the rising edge to be captured. If this feature is not selected or the counter is disabled, the clear counter output and the edge detector are kept de-asserted. 4.16.4.4 Bit Reverse and Pulse Density Modulation Figure 4-52 shows how the Little Endian/Big Endian Bit Reverse functions. Table 4-33 on page 158 shows a 3-bit example of pulse density modulation; note that the MFGPT has a 16-bit implementation. If the desired pulse train is of the opposite polarity, this can be inverted in the GPIO or generated with a different Compare 1 value. Table 4-32. MFGPT Prescaler Clock Divider Scale Factor 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Input Clock Divide-By 1 2 4 8 16 32 64 128 256 512 1024 2048 4096 8192 16384 32768 Input Word from Up Counter 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Output Word to Compare Circuit Figure 4-52. MFGPT Bit Reverse Logic Revision 0.8 157 www.national.com Geode™ CS5535 MFGPT Functional Description (Continued) Table 4-33. MFGPT Pulse Density Modulation Example Pulse Train Output for Given Compare 1 Value (Note 1) Up Counter Output 000 001 010 011 100 101 110 111 Bit Reverse Output 000 100 010 110 001 101 011 111 1 0 1 1 1 1 1 1 1 2 0 1 1 1 0 1 1 1 4 0 1 0 1 0 1 0 1 5 0 0 0 1 0 1 0 1 6 0 0 0 1 0 0 0 1 Note 1. Compare 2 Value must be set to all 1s for pulse density modulation. 4.16.5 Working Power Domain Logic The Working power domain logic consists of the Local Bus Interface, Control Logic, MSRs, and NMI, IRQ, and Reset Output Events. When Event mode is enabled, the NMI, IRQ, and Reset Output Events logic gathers the event outputs of all eight MFGPTs and then generates the interrupt and resets outputs based on MSR settings. The interrupt outputs go to the PIC that can then trigger an IRQ or ASMI. Note that MFGPT6 and MFGPT7 cannot trigger reset. These outputs are controlled by MSR bits, and the NMI output can be further controlled by the MSB of I/O Address 070h. 4.16.6 Power Domain Crossing Interface Logic The asynchronous internal Standby State signal will disable/enable the Working power domain interface immediately. Therefore, any bus operation active at that time will have an indeterminate result. www.national.com 158 Revision 0.8 Geode™ CS5535 4.17 POWER MANAGEMENT CONTROL The Power Management Control (PMC) module is a GeodeLink Device whose function is to control all aspects of power management. Power management is event driven meaning that, in general, any action that the PMC performs is predicated on some event. These events can come from other GeodeLink Devices, including the CPU module inside the GX2 for example, or events coming from other off-chip sources. The PMC is compatible with the industry standard power management capabilities as defined in the Advanced Configuration and Power Interface (ACPI) v2.0 specification. An OS that conforms to ACPI can take advantage of the CS5535 ACPI support hardware. Advanced Power Management (APM) is another power management approach that the PMC supports. APM is a subset of ACPI and therefore will not be directly discussed. Components in a GeodeLink architecture based system have hardware and software means of performing power management which the PMC controls. A high performance computing system consumes multiple watts of power when fully on. However, with GeodeLink architecture, system power consumption is significantly lower on average through the use of power states that reduce power needs when the system is idle. 4.17.1 Power Domains The PMC module consists of three blocks: Working Standby and RTC. • The Working block contains all circuits and functions associated with the Working power domain. It includes the Working state machine, Local bus interface, ACPI power management registers, and power management supporting logic (i.e., counters, timer, CCU, etc.). The main function of the Working block is to put the system into Sleep, that is, turn off clocks to the system and disable I/Os to reduce power consumption. • The Standby block contains all circuits and functions associated with the Standby power domain. It includes the Standby state machine, ACPI registers, and power management supporting logic (i.e., counters, reset, CCU, etc.). The function of the Standby logic is to control power to the Working power domain. The PMC disables all interfaces between the Standby and Working domains while the Working power is off. • The RTC block contains the timing circuits for keeping real time. These circuits are powered by VBAT (ball A3). It is not a device requirement that the RTC block be powered during Mechanical Off. If a system design does not require that real time be kept, then VBAT should be tied to ground. 4.17.2 Power States Table 4-34 shows the supported ACPI power states and how they relate to the CS55335/GX2. ACPI power states not described are not supported. Table 4-34. Supported ACPI Power Management States ACPI States Hardware States CS5535 Working Logic FO AHCG AHCG Sleep Off Off Off Off System Main Memory FO AHCG AHCG Auto-refresh Auto-refresh Off Off Off Standby Off On (Sleep) Standby CS5535 Standby Logic On Global System State G0: Working Sleep State S0 C State C0 GX2 State FO AHCG C1 G1: Idle S1: Sleeping S3: Save-to-RAM S4: Save-to-Disk G2: Soft Off G3: Mechanical Off S5 Off C2 Off Off Off Off Suspend on Halt Sleep Off Off Off Off Revision 0.8 159 www.national.com Geode™ CS5535 PMC Functional Description (Continued) 4.17.2.1 ACPI System Power States • G0/S0: Not Sleeping. Software is executing code or could be halted waiting for a system event. • G1/S1: Requires explicit software action to enter this state. All GX2, CS5535, and main memory states maintained. All system clocks may be turned off except 32 kHz or selected additional clocks may be left on as required. The PMC provides generic controls SLEEP_X and SLEEP_Y that may be used to control the “D” states of external system devices (not described in this datasheet, see ACPI specification for details). Two additional internal signals control PCI and IDE input and outputs. A wakeup event brings the system back to the opcode following the one that initiated entry into S1. Context restore operation is not required on the GX2, CS5535, or main memory. • G1/S3: Save-to-RAM state. Requires explicit software action to enter this state. The CS5535 and other system context are lost. System state is saved in the main memory. To properly support this state, main memory power must be controlled by WORKING power while the CS5535, GX2, and all other system components power must be controlled by WORK_AUX power. Note that this applies only to the Working domain of the CS5535. The Standby domain must be continuously supplied from Standby power. • G1/S4: Suspend-to-Disk state. Requires explicit software action to enter this state. Same as S3 state, but the system state is “saved” on the hard drive or other mass storage device. Only Standby power is on while in this state. • G2/S5: Requires explicit software action to enter this state. All system context is lost and not saved. Operating system re-boot is required. The 32 kHz clock is kept running for Standby PMC and selected GPIO and MFGPT circuits. • G3: Software action is not required to enter this state. Working power and Standby power are removed. The only domain that may be powered is the RTC. It is not a requirement that the RTC be powered. 4.17.2.2 CPU Power States • G0/S0/C0: Processor actively executing instructions and clock running. Cache snoops supported. • G0/S0/C1: HLT instruction executed. Usually occurs in the Operating System’s idle loop. Operating System waiting for Power Management Event (PME), interrupt, or ASMI. Cache snoops are supported while in this state, so bus mastering activity can safely occur. • G1/S1/C2: Processor is in the lowest power state that maintains context in a software invisible fashion. Entered as part of the S1 sequence. The SUSP#/SUSPA# signaling protocol indicates entry. SUSP# is not an explicit external signal, it is part of the CIS packet. (See Section 4.2.14 "CPU Interface Serial (CIS)" on page 79 for further details.) No explicit software action required. However, this state can be entered by explicit software action by reading the ACPI P_LVL2 register provided by the GX2 GLCP. 4.17.2.3 Hardware Power States • FO (Full On): From a hardware reset, all clocks come up Full On or always running. Generally, the system should not be left in this state. The AHCG state should be used. • AHCG (Active Hardware Clock Gating): This is the desired mode of operation; it utilizes automatic hardware clock gating. Latency to turn on a clock is near 0. This hardware state should be established at system initialization by BIOS code; after initialization it needs no additional support. AHCG is invisible to the Operating System, ACPI, or other software based power management facilities. • Suspend on Halt: See CPU power state G0/S0/C1. • Sleep: See CPU power state G1/S1/C2. • Auto-refresh: The memory controller issues an autorefresh command to the DRAMs. In this state, the DRAMs perform refresh cycles on their own without any additional commands or activity from the memory controller or the interface. As long as power to the DRAMs is maintained, the memory contents are retained. 4.17.2.4 PMC Control Under S3, S4, and S5 power management states, all Working domain circuits, as well as the GX2, are turned off to conserve power. Under S3, the system memory is powered by VIO_VSB in Standby Auto-refresh mode but otherwise, all other system components are also turned off. The PMC is used to establish overall system power states. Normally, the Standby domain voltages are present anytime the system is plugged into the wall; if portable, anytime the battery is plugged in. Generally, G3 Mechanical Off (see Table 4-34 on page 159) only applies during storage or maintenance. Therefore, operationally speaking, the PMC Standby controller is always available to manage power. There is a class of system designs that do not require G1 and G2 global power states. These systems usually power-up WORKING and STANDBY power domains simultaneously when power is applied. For supporting “Save-to-RAM” (G1/S3) the WORKING output is used to switch off/on the Working domain sources for system memory while the WORK_AUX output is used to switch off/on the Working domain sources for everything else. Thus, the PMC can completely control the system power states via these outputs. www.national.com 160 Revision 0.8 Geode™ CS5535 PMC Functional Description (Continued) 4.17.3 Software Power Management Actions The hardware comes up from hardware system reset in the Full On (FO) state. As part of system initialization, the power management MSRs (see Section 5.18.1 on page 479) are written to establish the Active Hardware Clock Gating (AHCG) state. The AHCG state is the nominal operational state. 4.17.3.1 Sleep/Standby Sequence Entering the states under G1 and G2 requires explicit software action. That action starts a hardware chain of events in which some of the chain is determined by registers that must be programmed previous to the start of the sequence. The block diagram of the hardware involved in this sequence is illustrated in Figure 4-53. Figure 4-54 and Figure 4-55 graphically show the Sleep/Standby sequence. The sequence is as follows: 1) The “explicit software action” begins with a write to PM1_CNT (ACPI I/O Offset 08h) starting the Sleep/Standby sequence. The PMC issues a Sleep Request to the CS5535 GLCP and it passes the request as SUSP# to the GX2 GLCP. The GX2 GLCP issues a suspend request to the processor. After the processor has shutdown operation it provides a suspend acknowledge back to the GX2 GLCP. The GX2 GLCP processes a sleep sequence similar to that described in step 5 while issuing a SUSPA# to the CS5535 GLCP. 2) 3) 4) GLIU Processor Activity Counters DSMI, SMI, NMI, IRQ SUSP# (CIS packet) SUSPA# GeodeLink Device (1 of n) Clock Control GLCP PM MSR Turn Off PCI/IDE Outputs Turn Off PCI/IDE Inputs Sleep Request Sleep Acknowledge External I/O System Reset if Wakeup from Standby Power Low Indicator PML & Reset (with Standby power) Internal Wakeup Events External Wakeup and Thermal Events including Buttons SLEEP_X, SLEEP_Y, SLP_CLK_EN#, WORKING, and WORK_AUX Notes: *At least one per GeodeLink Device. #Global signal, one per system. Figure 4-53. PMC Power Management Elements Revision 0.8 161 www.national.com Geode™ CS5535 PMC Functional Description (Continued) 5) The CS5535 GLCP processes a Sleep sequence. This is done in one of the three ways: a) If the CLK_DLY_EN bit in GLCP_GLB_PM (MSR 5170000Bh[1]) is 0 and the CLK_DELAY value in the GLCP_CLK_DIS_DELAY (MSR 51700008h[23:0]) is 0, then wait until the CLK_ACTIVE flags specified in GLCP_CLK4ACK (MSR 51700013h[33:0]) have gone to 0. b) If the CLK_DLY_EN bit is 1 and the CLK_DELAY value is non-zero, then wait the amount of time of the CLK_DELAY value. c) If the CLK_DLY_EN is 0 and the CLK_DELAY value is non-zero, then wait as in (a) but no longer than (b). 6) At the completion of the wait above, de-assert the CLK_DIS bits specified in GLCP_PMCLKDISABLE (MSR 51700009h[33:0]) and assert Sleep Acknowledge to the PMC. 9) 7) When the Sleep Acknowledge is received, the PMC can optionally issue additional external generic controls SLEEP_X and SLEEP_Y as well as SLP_CLK#to turn off external clocks. The completion of this step takes the system to S1. The system is now in Sleep. If the Sleep Request was to enter S3 (Save-to-RAM) then the PMC moves beyond S1 and removes main power by de-asserting WORK_AUX and leaving WORKING asserted. WORKING is used to power main memory, while WORK_AUX is used for everything else in the system. If the Sleep Request was to enter S4 (Save-to-Disk) or S5 (Soft Off) then the PMC moves beyond S1 and removes main power by de-asserting both WORK_AUX and WORKING. 8) 10) An external or internal wakeup event reverses the events above to bring the system back to the S0 state. Sleep Request SUSP# SUSPA# GL Device Clock Control Sleep Acknowledge PCI/IDE Input Control SLEEP_X/SLEEP_Y PCI/IDE Output Control SLP_CLK_EN# Indicates a variable delay. SLP_CLK_EN# signal must be the last control to assert because it turns off all system clocks. NOTE: External signals are not necessarily active high. Shown as active high for clarity. Figure 4-54. PMC System Sleep Sequence www.national.com 162 Revision 0.8 Geode™ CS5535 PMC Functional Description (Continued) Sleep Request SUSP# SUSPA# GL Device Clock Control Sleep Acknowledge PCI/IDE Input Control SLEEP_X/SLEEP_Y PCI/IDE Output Control SLP_CLK_EN# Indicates a variable delay. SLP_CLK_EN# de-asserts at wakeup event and turns on system clocks. SLEEP_X/SLEEP_Y Controls should de-assert between PCI/IDE input and output controls. Wakeup sequence begins with a Sleep wakeup event. NOTE: External signals are not necessarily active high. Shown as active high for clarity. Figure 4-55. PMC System Wakeup Sequence 4.17.3.2 Sleep Controls Sleep Request/Sleep Acknowledge handshake (see Figure 4-53 on page 161) between the GLCP and PMC controls the transitions into and out of the Sleep and Standby states. The PMC starts the Sleep sequence by asserting Sleep Request to the GLCP. The GLCP requests the processor to enter C2 by asserting the SUSP# signal. When SUSPA# from the processor is received, the GLCP informs the internal GeodeLink Devices of a pending shutdown and waits until the GeodeLink Devices’ clock control indicates that they are ready. The length of time it takes for each device to respond is programmable (GLCP MSR 51700008h, 51700013h, and 5170000Bh). After all designated GeodeLink Devices have responded, the GLCP asserts Sleep Acknowledge to the PMC. The PM_IN_SLPCTL (PMS I/O Offset 20h) register and the PM_OUT_SLPCTL (PMS I/O Offset 0Ch) are used to disable PCI/IDE inputs and outputs respectively during Sleep. Generally, they are asserted at the end of a Sleep sequence and de-asserted at the beginning of a Wakeup sequence. When “disabled”, some of the outputs are forced to TRI-STATE with an active internal pull-down resistor while the rest are simply pulled low. See Section 3.8.5 "MSR Address 4: Power Management" on page 71 for specific details on PCI/IDE I/O controls during Sleep. 4.17.3.3 Power Controls In response to Sleep Acknowledge from the GLCP, the PMC can assert five controls/enables: SLEEP_X, SLEEP_Y, SLP_CLK_EN#, WORKING, and WORK_AUX. These can control external electronic power switches and enables. Each control’s assertion and de-assertion is subject to an enable and a programmable delay (PMS I/O Offset 04h to 3Ch). Controls SLEEP_X and SLEEP_Y are generic and have no specific use. Asserting control SLP_CLK_EN# is assumed to turn off the system (board) clocks. It is always deasserted by the wakeup event. The following conditions apply to the timing of selected output control (see Section 4.17.3.2 "Sleep Controls"), SLEEP_X, SLEEP_Y and SLP_CLK_EN#. When going to sleep: a) If not enabled, SLEEP_X and SLEEP_Y do not assert at all. If they are enabled, the delay should be set to occur between the delays programmed in the PM_IN_SLPCTL and PM_OUT_SLPCTL registers. b) If SLP_CLK_EN# is enabled, any delays associated with the PM_OUT_SLPCTL, SLEEP_X, and SLEEP_Y registers must be less than the SLP_CLK_EN# delay. c) If SLP_CLK_EN# is enabled, then Sleep wakeup is possible only after SLP_CLK_EN# asserts. Revision 0.8 163 www.national.com Geode™ CS5535 PMC Functional Description (Continued) d) If SLP_CLK_EN# is not enabled, and if at least one of the following PM_OUT_SLPCTL, SLEEP_X, or SLEEP_Y registers is enabled, then Sleep wakeup is possible only after the longest delay of the three. The delays could be zero. e) If SLP_CLK_EN# is not enabled, and the PM_OUT_SLPCTL, SLEEP_X, or SLEEP_Y registers are not enabled, then Sleep wakeup is possible immediately. f) If SLP_CLK_EN# is enabled and the delay associated with the PM_OUT_SLPCTL register is longer than or equal to the delay associated with SLP_CLK_EN#, then the PCI/IDE outputs will not be disabled. If enabled, the de-assertion of WORKING is assumed to remove Working power and all clock sources except 32 kHz; that is, the Standby state is entered. In this state, the PMC, disables its interface to all circuits connected to Working power and asserts RESET_OUT# before deassertion of WORKING. RESET_OUT# remains asserted throughout Standby. WORK_AUX is an auxiliary control for the Standby state with no specific use. It can be de-asserted any time before or after WORKING. WORKING and WORK_AUX are independent controls, but the use of either implies that Standby state is to be entered. In both cases, the PMC disables all circuits connected to Working power and asserts reset. However, since they are independent, one may be left on while the other is deasserted. 4.17.3.4 Wakeup Events If the system has been put to Sleep, only preprogrammed wakeup events can get the system running again. The PMC contains the controls that allow the system to respond to the selected wakeup events. On wakeup from Sleep (not Standby, but Sleep Wakeup) (see Figure 4-53 on page 161), the PMC immediately deasserts SLP_CLK_EN# to turn system clocks back on. It also re-enables PCI/IDE outputs to allow output drivers to return to their operational levels. Next it de-asserts SLEEP_X and SLEEP_Y based on programmable delays. Alternate SLEEP_X and SLEEP_Y interactions are shown as dotted lines. Lastly, the PMC, re-enables PCI/IDE inputs after a programmable delay and de-asserts Sleep Request. The GLCP starts any on-chip PLLs and waits for them to become stable. Then the GLCP de-asserts SUSP# to the processor. When the processor de-asserts SUSPA#, the GLCP de-asserts Sleep Acknowledge. The PMC allows the wakeup event to assert a System Control Interrupt (SCI). After a wakeup event: a) PCI/IDE outputs are re-enabled after SLP_CLK_EN# is de-asserted. b) PCI/IDE inputs are re-enabled at Sleep wakeup or after a programmable delay. Generally, PCI/IDE inputs are normally used with a delay and that delay is longer than any de-assertion delay associated with SLEEP_X and/or SLEEP_Y. Re-enabling PCI/IDE inputs is generally not useful at the beginning of a wakeup sequence. c) Sleep Request is de-asserted at Sleep wakeup or after a programmable delay. Sleep Request is kept de-asserted until the PCI/IDE inputs are re-enabled. Generally, the enable and delay values in PM_SED (PMS I/O Offset 14h) and PM_IN_SLPCTL (PMS I/O Offset 20h) should always be the same. d) If used, SLEEP_X/SLEEP_Y delay should be set to occur between the delays programmed in PM_OUT_SLPCTL (PMS I/O Offset 0Ch) and PM_IN_SLPCTL (PMS I/O Offset 20h). If the delays for SLEEP_X/SLEEP_Y are longer than the PM_IN_SLPCTL delay, then SLEEP_X/SLEEP_Y de-assert at the same time as the PCI/IDE inputs are re-enabled. On wakeup from Standby (not Sleep, but Standby Wakeup) the PMC asserts WORKING and performs a system reset. RESET_OUT# is de-asserted after a programmable delay and the normal software start-up sequence begins. However, early in the sequence, the software checks the PMC state to determine if waking from Standby (PMS I/O Offset 54h[0]). If yes, then the system state is potentially restored from non-volatile storage. If enabled, WORK_AUX may be asserted before or after RESET_OUT# is de-asserted. 4.17.3.5 Fail-Safe Power Off The PMC provides the support logic to implement an ACPI compliant fail-safe power off button. This logic unconditionally de-asserts the WORKING and WORK_AUX signals if the On/Off button is held down for a programmable delay. For ACPI compliance, this delay should be set to four seconds. 4.17.3.6 Wake Events Status and SCI When enabled, a wake event from the general wake events register (see Section 5.16.4 "GPIO Interrupt and PME Registers" on page 462) set its status bit and the "WAK_STS" bit and causes a system control interrupt (SCI). The Sleep button, RTC alarm, and power button when asserted, always set their status bit. They set the "WAK_STS" bit and generate an SCI only when their enable bit is set. When overflowed, the PM timer sets its status bit. This overflow condition does not cause a wakeup event but if enabled, it generates an SCI. The event’s status is cleared by writing a one to it. www.national.com 164 Revision 0.8 Geode™ CS5535 PMC Functional Description (Continued) 4.17.4 PMC Power Management States The PMC state machines support the fundamental hardware states: Power Off, Reset Standby, Working, Sleep, and Controlled Standby. • Reset Standby State: From Power Off, reset is applied to the Standby domain by the external input pin RESET_STAND#. Once reset, the Reset Standby state de-asserts WORKING and WORK_AUX outputs and waits for a Reset Standby wakeup event. • Working State: The Working state can be entered from Reset Standby, Sleep, or Controlled Standby states. Working state is established when Working power is applied and all system clocks are enabled. Once in this state, registers and functions in the PMC can be initialized, programmed, enabled/disabled, and the potential exists for the system to proceed to the Sleep state or Standby state. • Sleep State: The system initiates the entry to the Sleep state with a Sleep sequence. Under the Sleep state, Working and Standby power are maintained. PCI/IDE inputs are disabled when Sleep Acknowledge asserts. PCI/IDE outputs are disabled when Sleep Acknowledge asserts or after a programmable delay. SLEEP_X, SLEEP_Y, and SLP_CLK_EN# may be asserted if enabled. A Sleep wakeup event returns the system to Working state. • Controlled Standby State: Can be entered “normally”, “fault condition”, or by a “restart”. A normal entry is by way of a system initiated sequence as in the Sleep case. This method of entry requires the Standby state machine to monitor SLP_CLK_EN# and look for an enable of the “Working De-assert Delay and Enable” register (PM_WKD, PMS I/O Offset 30h[30]) or the Work_aux De-assert Delay and Enable register (PM_WKXD, PMS I/O Offset 34h[30]). This signals the Controlled Standby state normal entry. A Standby wakeup event returns the system to Working state after a programmable delay (PM_NWKD, PMS I/O Offset 4Ch). If enabled, a faulted entry can be initiated by a low power off, thermal off, or fail-safe off. It can also be initiated by Working power fail asserted. A default wakeup event returns the system to the Working state after a programmable delay (PM_FWKD, PMS I/O Offset 50h). A re-start can be initiated by any of these resets: GLCP soft reset, soft reset, shutdown reset, watchdog reset, or bad packet type reset. The system returns to the Working state when reset is de-asserted and the faulted_to_work delay (PM_FWKD) expired. WORKING and WORK_AUX are not de-asserted. When a Controlled Standby state is entered by a faulted condition or restart event, software control is assumed lost and the software established state is assumed to be potentially wrong. Therefore, the Standby domain returns to the state associated with “Standby State Entry from Power Off”; that is, Standby domain reset defaults are used. The only exceptions are registers from the following list; these are locked and not subject to change by software: Revision 0.8 165 PM_RD PM_WKXA PM_FSD PM_TSD PM_PSD PM_NWKD PM_FWKD De-assert Reset Delay from Standby (PMS I/O Offset 38h) WORK_AUX Assert Delay from Standby (PMS I/O Offset 3Ch) Fail-Safe Delay and Enable (PMS I/O Offset 40h) Thermal Safe Delay and Enable (PMS I/O Offset 44h) Power Safe Delay and Enable (PMS I/O Offset 48h) Normal to Work Delay and Enable (PMS I/O Offset 4Ch) Faulted to Work Delay and Enable (PMS I/O Offset 50h) The Faulted to Work Delay and Enable (PM_FWKD) register is the only one of the above registers that potentially applies during a re-start entry. Lastly, note that any normal entry operation in process is aborted. Wakeup from faulted entry is the same as that associated with Standby State Entry from Power Off; that is, it acts as if the power button has been pushed. Other possible wakeup events such as RTC Alarm and PMEs are ignored. However, the system can be held in the Standby state for the following reasons: 1) 2) If enabled and locked, the low power indicator is still asserted. If LVD_EN# is tied to ground and VCORE is not at a valid voltage, or if RESET_WORK # is asserted. If enabled and locked, the thermal alarm does not keep the system in the Standby state if it is asserted. The thermal alarm circuitry resides in the Working domain, and its state is ignored by the Standby state. Once out of Standby, the thermal alarm again comes into play. If it is still asserted, its timer would start again. Note: The Power Management Control (PMC) has two state machines: • Working State Machine: Operates under Working power and runs on a 14 MHz clock from the CCU. Its function is to generate control signals used to turn off/on systems clocks and I/Os based on events coming from on or off the chip. • Standby State Machine: Operates under Standby power and runs on the 32 kHz clock. Its function is to power-up and down the Working power to the Working domain based on events coming from on or off the chip. www.national.com Geode™ CS5535 PMC Functional Description (Continued) 4.17.5 PMC Power Management Events A large number of inputs to the PMC are used to monitor and create system power managements events. Some of these inputs apply the Working state machine while the remainder apply to the Standby state machine. 4.17.5.1 PM Sleep Events • Sleep: — Sleep sequence initiated by software • Wakeup: — Assertion of the Sleep Button (SLEEP_BUT) — Assertion of the Power Button (PWR_BUT#) — RTC alarm — Working power domain PMEs — Standby power domain PMEs 4.17.5.2 PM Standby Events • Standby: — Sleep sequence initiated by software — LVD detection of low voltage on VCORE (system fault) — Assertion of the Power Button for 4 seconds (PWR_BUT#, system fault) — Thermal Alarm (THRM_ALRM#, system fault) — Low battery (LOW_BAT#, system fault) — Hardware reset (system restart) — Software initiated reset (system restart) — Shutdown initiated reset, CPU triple fault (system restart) — Watchdog initiated reset (system restart) — GLCP software initiated reset (system restart) — Bad packet type reset (system restart) — Reset Standby state machine RESET_STAND# (Standby) • Wakeup: — Assertion of the Power Button (PWR_BUT#) — RTC Alarm — Standby power domain PMEs Table 4-35 provides a complete list of the power management inputs and describes their function. The system can only be in one of three states: Working, Sleep, or Standby. The activity of the inputs is to move the system from one state to another. Table 4-35. PM Events and Functions Event Current State Function The following events are Sleep and/or Standby wakeup events (except for ACPI Timer). PWR_BTN# (also serves as a Standby event) Working Sets the status bit (PWRBTN_STS) in PM1_STS (ACPI I/O Offset 00h[8] = 1). If PWRBTN_EN is enabled (ACPI I/O Offset 02h[8] = 1), an SCI is generated. Sleep Sets the status bit (PWRBTN_STS) in PM1_STS (ACPI I/O Offset 00h[8] = 1). If PWRBTN_EN is enabled (ACPI I/O Offset 02h[8] = 1), SCI generation and wakeup from this event is enabled (i.e., sets the WAK_STS bit, ACPI I/O Offset 00h[15] = 1). Standby Sets the status bit (PWRBTN_STS) in PM1_STS (ACPI I/O Offset 00h[8] = 1). If PWRBTN_EN is enabled (ACPI I/O Offset 02h[8] = 1), SCI generation and wakeup from this event is enabled (i.e., sets the WAK_STS bit, ACPI I/O Offset 00h[15] = 1). SLP_BTN Working Sets the status bit (SLPBTN_STS) in PM1_STS (ACPI I/O Offset 00h[9] = 1). If SLPBTN_EN is enabled (ACPI I/O Offset 02h[9] = 1), an SCI is generated. Sleep Sets the status bit (SLPBTN_STS) in PM1_STS (ACPI I/O Offset 00h[9] = 1). If SLPBTN_EN is enabled (ACPI I/O Offset 02h[9] = 1), SCI generation and wakeup from this event is enabled (i.e., sets the WAK_STS bit, ACPI I/O Offset 00h[15] = 1). RTC Alarm Working Sets the status bit (RTC_STS) in PM1_STS (ACPI I/O Offset 00h[10] = 1). If RTC_EN is enabled (ACPI I/O Offset 02h[10] = 1), an SCI is generated. Sleep Sets the status bit (RTC_STS) in PM1_STS (ACPI I/O Offset 00h[10] = 1). If RTC_EN is enabled (ACPI I/O Offset 02h[10] = 1), SCI generation and wakeup from this event is enabled (i.e., sets the WAK_STS bit, ACPI I/O Offset 00h[15] = 1). Standby Sets the status bit (RTC_STS) in PM1_STS (ACPI I/O Offset 00h[10] = 1). If RTC_EN is enabled (ACPI I/O Offset 02h[10] = 1), SCI generation and wakeup from this event is enabled (i.e., sets the WAK_STS bit, ACPI I/O Offset 00h[15] = 1). ACPI Timer (internal timer) Working Sets the status bit (TMR_STS) in PM1_STS (ACPI I/O Offset 00h[0] = 1). If TMR_EN is enabled (ACPI I/O Offset 02h[0] = 1), an SCI is generated. www.national.com 166 Revision 0.8 Geode™ CS5535 PMC Functional Description (Continued) Table 4-35. PM Events and Functions (Continued) Event GPE[23:0] (General Purpose Power Management Events in Working Domain) Current State Working Function If GPE_EN[23:0] are enabled (ACPI I/O Offset 1Ch[23:0] = 1), the corresponding status bit (GPE_STS[23:0]) in GPE0_STS (ACPI I/O Offset 18h[23:0]) is set and an SCI is generated. If GPE_EN[23:0] are enabled (ACPI I/O Offset 1Ch[23:0] = 1), SCI generation and wakeup from the event is enabled (i.e., sets the WAK_STS bit, ACPI I/O Offset 00h[15] = 1). If GPE_EN[31:24] are enabled (ACPI I/O Offset 1Ch[31:24] = 1), the corresponding status bit (GPE_STS[31:24]) in GPE0_STS (ACPI I/O Offset 18h[23:0]) is set and an SCI is generated. If GPE_EN[31:24] are enabled (ACPI I/O Offset 1Ch[23:0] = 1), SCI generation and wakeup from the event is enabled (i.e., sets the WAK_STS bit, ACPI I/O Offset 00h[15] = 1). If GPE_EN[31:24] are enabled (ACPI I/O Offset 1Ch[31:24] = 1), the corresponding status bit (GPE_STS[31:24]) in GPE0_STS (ACPI I/O Offset 18h[23:0]) is set, and SCI generation and wakeup from the event is enabled (i.e., sets the WAK_STS bit, ACPI I/O Offset 00h[15] = 1). Sleep GPE[31:24] (General Purpose Power Management Events in Standby Domain) Working Sleep Standby The following events caused a Standby state entry. RESET_STAND# Working If asserted, the corresponding status bit (OFF_FLAG) in PM_SSC (PMS I/O Offset 54h[0]) is set and causes a Reset Standby state entry. No Working or Standby power. If asserted, the corresponding status bit (OFF_FLAG) in PM_SSC (PMS I/O Offset 54h[0]) is set and causes a Reset Standby state entry. No Working or Standby power. If asserted in Restart, or Normal or Faulted Standby state, the corresponding status bit (OFF_FLAG) in PM_SSC (PMS I/O Offset 54h[0]) is set and causes a Reset Standby state entry. If de-asserted, the status bit (LVD_FLAG) in PM_SSC (PMS I/O Offset 54h[2]) is set and causes an Faulted Standby state entry. Working power is turned-off. If de-asserted, the status bit (LVD_FLAG) in PM_SSC (PMS I/O Offset 54h[2]) is set and causes an Faulted Standby state entry. Working power is turned-off. If de-asserted in Restart state, the status bit (LVD_FLAG) in PM_SSC (PMS I/O Offset 54h[2]) is set and causes an Faulted Standby state entry. If enabled and asserted for four seconds (fail-safe), the status bit (PWRBUT_FLAG) in PM_SSC (PMS I/O Offset 54h[3]) is set and causes an Faulted Standby state entry. Working power is turned-off. If enabled and asserted for four seconds (fail-safe), the status bit (PWRBUT_FLAG) in PM_SSC (PMS I/O Offset 54h[3]) is set and causes an Faulted Standby state entry. Working power is turned-off. If enabled and asserted for four seconds (fail-safe) while in Normal or Restart state, the status bit (PWRBUT_FLAG) in PM_SSC (PMS I/O Offset 54h[3]) is set and causes a Faulted Standby state entry. If enabled and asserted for a programmable amount of time, the status bit (THRM_FLAG) in PM_SSC (PMS I/O Offset 54h[4]) is set and causes an Faulted Standby state entry. Working power is turned-off. If enabled and asserted for a programmable amount of time, the status bit (THRM_FLAG) in PM_SSC (PMS I/O Offset 54h[4]) is set and causes an Faulted Standby state entry. Working power is turned-off. If asserted in Normal or Re-start state, the status bit (THRM_FLAG) in PM_SSC (PMS I/O Offset 54h[4]) is set and causes a Faulted state entry. Sleep Standby LVD circuit detects low voltage on VCORE Working Sleep Standby PWR_BTN# Working Sleep Standby THRM_ALRM# Working Sleep Standby Revision 0.8 167 www.national.com Geode™ CS5535 PMC Functional Description (Continued) Table 4-35. PM Events and Functions (Continued) Event LOW_BAT# Current State Working Function If enabled and asserted for a programmable amount of time, the status bit (LOWBAT_FLAG) in PM_SSC (PMS I/O Offset 54h[5]) is set and causes an Faulted Standby state entry. Working power is turned-off. If enabled and asserted for a programmable amount of time, the status bit (LOWBAT_FLAG) in PM_SSC (PMS I/O Offset 54h[5]) is set and causes an Faulted Standby state entry. Working power is turned-off. If asserted in Normal or Re-start state, the status bit (LOWBAT_FLAG) in PM_SSC (PMS I/O Offset 54h[5]) is set and causes a Faulted state entry. If asserted, the status bit (HRD_RST_FLAG) in PM_SSC (PMS I/O Offset 54h[6]) is set and causes a Restart state entry. Working power is not turned-off. If asserted, the status bit (HRD_RST_FLAG) in PM_SSC (PMS I/O Offset 54h[6]) is set and causes a Restart state entry. Working power is not turned-off. If asserted, the status bit (SFT_RST_FLAG) in PM_SSC (PMS I/O Offset 54h[8]) is set and causes a Restart state entry. Working power is not turned-off. If asserted, the status bit (SFT_RST_FLAG) in PM_SSC (PMS I/O Offset 54h[8]) is set and causes a Restart state entry. Working power is not turned-off. If asserted, the status bit (SHTDWN_RST_FLAG) in PM_SSC (PMS I/O Offset 54h[9]) is set and causes a Re-start state entry. Working power is not turned-off. If asserted, the status bit (SHTDWN_RST_FLAG) in PM_SSC (PMS I/O Offset 54h[9]) is set and causes a Restart state entry. Working power is not turned-off. If asserted, the status bit (WATCHDOG_RST_FLAG) in PM_SSC (PMS I/O Offset 54h[10]) is set and causes a Restart state entry. Working power is not turned-off. If asserted, the status bit (WATCHDOG_RST_FLAG) in PM_SSC (PMS I/O Offset 54h[10]) is set and causes a Restart state entry. Working power is not turned-off. If asserted, the status bit (GLCP_SFT_RST_FLAG) in PM_SSC (PMS I/O Offset 54h[11]) is set and causes a Restart state entry. Working power is not turned-off. If asserted, the status bit (GLCP_SFT_RST_FLAG) in PM_SSC (PMS I/O Offset 54h[11]) is set and causes a Restart state entry. Working power is not turned-off. If asserted, the status bit (BADPACK_RST_FLAG) in PM_SSC (PMS I/O Offset 54h[12]) is set and causes a Restart state entry. Working power is not turned-off. If asserted, the status bit (BADPACK_RST_FLAG) in PM_SSC (PMS I/O Offset 54h[12]) is set and causes a Restart state entry. Working power is not turned-off. Sleep Standby RESET_WORK# Working Sleep Software initiated reset Working Sleep Shutdown initiated reset (CPU triple fault) Working Sleep Working Sleep GLCP Soft Reset Working Sleep Bad packet type reset Working Sleep Watchdog initiated reset www.national.com 168 Revision 0.8 Geode™ CS5535 4.18 FLASH CONTROLLER The CS5535 has a Flash device interface that supports popular NOR Flash and inexpensive NAND Flash devices. This interface is shared with the IDE interface (ATA-5 Controller (ATAC)), using the same balls. NOR or NAND Flash may co-exist with IDE devices using PIO (Programmed I/O) mode. The 8-bit interface supports up to four “lanes” of byte-wide Flash devices through use of four independent chip selects, and allows for booting from the array. Hardware support is present for SmartMedia-type ECC (Error Correction Code) calculations, off-loading software from having to support this task. Features • Supports popular NOR Flash and inexpensive NAND Flash devices on IDE interface. No extra pins needed. • NOR Flash and NAND Flash co-exist with IDE devices with PIO (Programmed I/O) only mode. • General purpose chip select pins support on-board ISAlike slave devices. • Programmable timing supports a variety of Flash devices. • Supports up to four byte-wide NOR Flash devices. — Address up to 256 kB boot ROMs using an external octal latch. — Address up to 256 MB linear Flash memory arrays using external latches. — Boot ROM capability. — Burst mode capability (DWORD read/write on PCI bus). • Supports up to four byte-wide NAND Flash devices. — Hardware support for SmartMedia-type ECC (Error Correction Code) calculation off-loading software effort. • Supports four programmable chip select pins with memory or I/O addressable. — Up to 1 kB of address space without external latch. 4.18.1 NAND Flash Controller To understand the functioning of the NAND Flash Controller, an initialization sequence and a read sequence is provided in the following sub-sections. The NAND Flash Controller’s registers can be mapped to memory or I/O space. The following example is based on memory mapped registers. 4.18.1.1 Initialization 1) Program MSR_LBAR_FLSH0 (MSR 51400010h) to establish a base address (NAND_START) and whether in memory or I/O space. The NAND Controller is memory mapped in this example and always occupies 4 kB of memory space. 2) Set the NAND timing MSRs to the appropriate values (MSRs 5140001Bh and 5140001Ch). 4) 4.18.1.2 Read 1) Allocate a memory buffer. Start at address BAh in system memory. 2) Fill the buffer with the following values: – – – – – – – – – – – 3) BA: 02h (Assert CE#, CLE) BA + 1: 00h (Command: Read mode) BA + 2: 04h (Assert CE#, ALE, De-assert CLE) BA + 3: CA (Start column address) BA + 4: 04h BA + 5: PA0 (Page address byte 0) BA + 6: 04h BA + 7: PA1 (Page address byte 1) BA + 8: 04h BA + 9: PA2 (Page address byte 2) BA + 10: 08h (Assert CE#, De-assert ALE, Enable Interrupt) For (i = 0; i < 11; i++), write the data in buffer [BA+i] to memory location [NAND_START + 800h + i]. Generate the command and address phase on the NAND Flash interface. NAND Flash device may pull down the RDY/BUSY# signal at this point. Software sets the EN_INT bit and waits for the interrupt. Memory byte writes 03h to memory location [NAND_START + 815h] to clear ECC parity and Enable ECC engine. For (i = 0; i < 256; i++), read data from [NAND_START + i] to buffer [BA + i] (read data from NAND Flash to memory buffer. Can use DWORD read to save time). Memory DWORD Reads [NAND_START + 810h] to get ECC parity [ECC0] of first 256 byte data. Memory byte writes 03h to memory location [NAND_START + 815h] to clear ECC parity and enable ECC engine. For (i = 256; i < 512; i++), read data from [NAND_START + i] to buffer [BA + i] (read data from NAND Flash to memory buffer. Can use DWORD read to save time). 5) 6) 7) 8) 9) 10) Memory DWORD reads [NAND_START + 810h] to get ECC parity [ECC1] of second 256 byte data. 11) For (i = 512; i < 528; i++), read data from [NAND_START + i] to buffer [BA + i] (read data from NAND Flash redundant data to memory buffer. Can use DWORD read to save time). 12) Write 01h to memory location [NAND_START + 800h] (de-assert CE#, NAND Flash enters to Idle state). 13) Retrieve ECC parity data from redundant data area and compare them to ECC0 and ECC1. 14) Correct data if data error is detected and can be fixed. Figure 4-56 on page 170 shows a basic NAND read cycle. Revision 0.8 169 www.national.com Geode™ CS5535 Flash Controller Functional Description (Continued) CLE CE# WE# ALE RE# I/O R/B# 00h CA PA0 PA1 PA2 D0 D1 D2 D (n-1) Figure 4-56. Flash Controller NAND Read Cycle 4.18.1.3 NAND ECC Control Module The NAND ECC Control Module is part of the NAND Flash Controller. It calculates 22-bit ECC parity for each of the 256 bytes of the NAND Flash’s data transferred on the Local bus. The ECC calculation algorithm follows the SmartMedia Physical Format Specification. The ECC algorithm is capable of single-bit correction and 2-bit randomerror detection. ECCs are generated only for data areas and no ECC is generated for page-data redundant areas containing ECCs as the page-data redundant area is duplicated for reliability. For ECC calculations, 256 bytes are handled as a stream of 2048-bit serial data. In the event of an error, the error-correction feature can detect the bit location of the error based on the results of a parity check and correct the data. Hardware Operation The ECC engine treats 256-byte data as a block. Each byte has an 8-bit address called a Line Address (LA). Each bit in a byte has a 3-bit address called a Column Address (CA). Combining these two address fields forms an 11-bit unique address for every single bit in the 256-byte data block. The address uses the notation: LLLL_LLLL, CCC. This module contains an 8-bit counter to keep track of the LA of each byte. Each ECC parity bit calculation in the ECC engine produces even parity of half of the data bits in the block. Different parity bits use different sets of the bits. For example, CP0 is the even parity bit of the bits with Column Address bit 0 equals 0. CP1 is the even parity bit of the bits with Column Address bit 0 equals 1. Both odd and even parity are supported for ECC. The ECC parity available in the NAND ECC column, LSB line, and MSB line parity registers is the inverted output of the ECC parity from the ECC engine in the case of odd ECC parity and the non-inverted output in the case of even parity. Table 4-36 lists the relationship between the parity bits and the corresponding bit addresses. The hardware ECC engine calculates 22-bit ECC parity whenever there is a data write or data read to/from the NAND Flash device. On power-up, the ECC engine is configured to be odd parity. Even or odd ECC parity is controlled by bit 2 of NAND ECC Control register (Flash Memory Offset 815h). www.national.com 170 Revision 0.8 Geode™ CS5535 Flash Controller Functional Description (Continued) Table 4-36. ECC Parity and Bit Address Relationship Parity CP0 CP2 CP4 LP00 LP02 LP04 LP06 LP08 LP10 LP12 LP14 Bit Address xxxx_xxxx, xx0 xxxx_xxxx, x0x xxxx_xxxx, 0xx xxxx_xxx0, xxx xxxx_xx0x, xxx xxxx_x0xx, xxx xxxx_0xxx, xxx xxx0_xxxx, xxx xx0x_xxxx, xxx x0xx_xxxx, xxx 0xxx_xxxx, xxx Parity CP1 CP3 CP5 LP01 LP03 LP05 LP07 LP09 LP11 LP13 LP15 Bit Address xxxx_xxxx, xx1 xxxx_xxxx, x1x xxxx_xxxx, 1xx xxxx_xxx1, xxx xxxx_xx1x, xxx xxxx_x1xx, xxx xxxx_1xxx, xxx xxx1_xxxx, xxx xx1x_xxxx, xxx x1xx_xxxx, xxx 1xxx_xxxx, xxx Software Operation The NAND Flash contains a redundant data area containing ECC fields. While writing to the NAND Flash, the hardware ECC engine calculates ECC parity, if it is enabled properly. Software can write the ECC parity bits to the ECC field after writing the data area. When software reads the data from NAND Flash, the hardware ECC engine calculates ECC parity. After the data is read from the NAND Flash, software can compare the ECC parity in the hardware ECC engine and the ECC parity in the ECC field of the NAND Flash to determine if the data block is correct. Each data bit has 11 corresponding parity bits, which can be determined by the bit address. If one data bit is different from its original value, 11 ECC parity bits are changed from the original ECC parity bits. Take the ECC parity from the hardware ECC engine and perform bit-wise exclusive OR with it and the ECC parity field in NAND Flash. The result can be as follows. 1) 2) 3) 4) All bits are 0. The data is correct. Eleven bits are 1. One bit error has been detected. Use the eleven bits to identify the error bit position. One bit is 1. One bit in ECC field is corrupt. Data area should be OK. Otherwise, two or more data bits are corrupt. Cannot be corrected. 4.18.2 NOR Flash Controller/General Purpose Chip Select The NOR Flash Controller supports up to four independent chip selects that can be used for NOR Flash devices or General Purpose Chip Selects (GPCS). Up to 28 bits of address is supported for each chip select, allowing bytewide linear arrays up to 256 MB in memory space. Chips selects may also be located in I/O space, but the usable address bits are limited by the over all limits of I/O space. Each chip select is independently programmable: • Address Setup: Defaults to seven Local bus clocks • Read/Write Strobe Width: Defaults to seven Local bus clocks • Address Hold: Defaults to seven Local bus clocks cycles • Optional Wait State Insertion: Defaults off, driven by an external input (FLASH_IOCHRDY) to be used by General Purpose devices. • Optional Write Protect: Defaults protected These settings are located in MSR space and on hard reset default to the settings listed above. Hence, virtually any NOR device can be used immediately out of reset for first instruction fetch. After booting, delays can be programmed as appropriate. Revision 0.8 171 www.national.com Geode™ CS5535 Flash Controller Functional Description (Continued) Special considerations must be made for NOR Flash write operations. Depending on the manufacturer and write mode, each write can take from a few microseconds to a few hundred microseconds. Specifically, the software performing the write must observe the following procedure: 1) 2) 3) Write to device. Wait an amount of time dependent on manufacturer’s specifications. Repeat from #1 until all writes are completed. 4.18.3 Flash Controller Interface Timing Diagrams 4.18.3.1 NOR/GPCS The NOR/GPCS timing has two phases: address phase and data phase. In the address phase, the address bus and data bus present a higher address, ADD[27:10]. Board designers can use external latches, such as 74x373, to latch the address bits. In the data phase, the address bus presents ADD[9:0], and the data bus is for data read or write. The Flash Controller is running off internal Local bus clock , which is at the highest frequency of 33 MHz. The address phase is always two clock periods. The ALE signal asserts high in the first-half clock period and de-asserts in the second clock period. A 74LCX373 only needs 4 ns setup time and 2 ns hold time (worst case). This timing provides a lot of flexibility for the designing of the board. In the data phase, the address bus and write data bus are available in the first clock period. In the second clock period of the data phase, chip select goes low. After the required hold time, chip select goes high, and write data bus change. After one Local bus clock from chip select change (going high), address bus changes. The setup time, strobe pulse width, and hold time are programmable through the NOR timing registers. See Section 5.19.1.2 "NOR Flash Timing MSRs" on page 504. Figure 4-57 and Figure 4-58 provides some NOR Flash timing examples. 0 1 2 Address Phase ADD[9:0] 3 4 X Y Y+1 Y+2 Z Z+1 Z+2 The “wait” in step two is implemented using an appropriate time base reference. There is no reference within the Flash Controller subsystem. Some NOR devices provide a ready line that de-asserts during the “wait” in step two. Direct use of this signal is not supported by the Flash Controller. The NOR write software should use an appropriate time base reference to determine when the device is ready, that is, determine how long to wait for the current write to complete before starting another write. Alternatively, the NOR device internal status may be read to determine when the write operation is complete. Refer to NOR Flash manufactures data sheets for additional write operation details. Data Phase Higher Address Lower Address » » » » » » » » » » » » tP tH ALE CS# tS WE#, RE# » tS Higher Address » » » » Data DATA (write) DATA (read) Higher Address » » » » » » Data tH » Figure 4-57. NOR Flash Basic Timing www.national.com 172 Revision 0.8 Geode™ CS5535 Flash Controller Functional Description (Continued) 0 1 2 Address Phase 3 4 X Y Y+1 Y+2 Z Z+1 Z+2 Data Phase Lower Address ADD[9:0] Higher Address » » » » » » » » » » » » Wait States tH ALE CS# tS tP WE#, RE# » Don’t Care » » » Don’t Care IOCHRDY » » tS tH DATA (write) Higher Address DATA (read) Higher Address » » » » » » » Data » » Data » Figure 4-58. NOR Flash with Wait States Timing Revision 0.8 173 www.national.com Geode™ CS5535 Flash Controller Functional Description (Continued) 4.18.3.2 NAND The NAND Flash interface has three external timings that are controlled by nine timing registers. The timing parameters are described in Table 4-37 and illustrated in Figures 4-59 through 4-61. Table 4-37. NAND Flash External Timing Parameters Symbol tCS tCP Description Control Setup Time: The setup time from the toggle of the control signals to the falling edge of WE#. Control Pulse Width: The WE# active pulse width in the Command/Address phase. Note that the command/address byte is put on the I/O bus at the same time that the WE# is asserted. tCH Control Hold Time: The hold time from the rising edge of WE# to the toggle of the control signals. Note that the I/O bus is turned off when the tCH expires. tWS Data Write Setup Time: This timing is just for the internal state machine; no external reference point. Can be set to 0 if the setup time is not needed. tWP Data Write Pulse Width: The WE# active pulse width in the data write phase. Note that the data byte is put on the I/O bus at the same time that WE# is asserted; no external reference point. Can be set to 0 if the hold time is not needed. tRP tRH Data Read Pulse Width: The RE# active pulse width in the data read phase. Data Read Hold Time: This timing is just for the internal state machine; no external reference point. Can be set to 0 if the hold time is not needed. 0 CTLR_BUSY 1 2 3 4 X X+1 Y Z Z+1 Z+2 tCS WE# tCH » » tCP » tCH I/O[7:0] » » Command / Address » » » » Note: CTLR_BUSY is bit 2 of the NAND Status register (Flash Memory Offset 810h or Flash I/O Offset 06h). Figure 4-59. NAND Flash Command/Address Timing www.national.com 174 Revision 0.8 Geode™ CS5535 Flash Controller Functional Description (Continued) 0 1 2 3 X Y Y+1 Z Z+1 Z+2 WE# / RE# » » tWS / tRS tWP / tRP » tWH / tRP I/O [7:0] (write) I/O [7:0] (read) » » » » » » » » » » Figure 4-60. NAND Data Timing with No Wait States and No Prefetch (for the first data read) 0 1 2 3 X Y Y+1 Z Z+1 Z+2 FLASH_RDY/BUSY# WE# / RE# Wait State » » » » » » » » » tWS / tRS tWP / tRP tWH / tRH I/O [7:0] (write) I/O [7:0] (read) » » » » » » » » » » Figure 4-61. NAND Data Timing with Wait States Revision 0.8 175 www.national.com Geode™ CS5535 4.19 GEODELINK CONTROL PROCESSOR The GeodeLink Control Processor (GLCP) functionality is illustrated in Figure 4-62 and is summarized as: • Serial to GeodeLink conversion to facilitate JTAG accesses to GeodeLink Devices • Power management support (reset and clock control) • MSRs Together with a JTAG controller, the GLCP provides complete visibility of the register state that the chip is in. All registers are accessible via the JTAG interface. How the JTAG controller interfaces with the GLCP is beyond the scope of this document and is not explained here. The GLCP also works with the CCU (Clock Control Unit) blocks of other GeodeLink Devices to provide clock control via its relevant MSRs. The GLCP supplies the clock enable signals to all the CCUs, which allows clocks to be shut off if the power management logic generates a Sleep request or if a debug event triggers a clock disable situation. 4.19.1 GeodeLink Power Management Support The main power management functions are performed by the Power Management Logic, with the GLCP playing a supporting role. (See Section 4.17 "Power Management Control" on page 159 for a complete understanding of power management.) 4.19.1.1 Soft Reset This is one of the active high soft reset sources going to the Power Management Logic. It resides in the GLCP_SYS_RST register. When active, all circuitry in the CS5535 chip is reset (including the GLCP_SYS_RST register itself). 4.19.1.2 Clock Control The GLCP provides a mechanism to shut off clocks. The busy signal from a module can control the clock gating in its CCU, however, clocks can also be enabled or disabled by the functional clock enable signals coming from the GLCP. These enable signals are asynchronous to the modules and need to be synchronized in the CCU blocks before being used to enable or disable the functional clocks. The clocks can be disabled in one or a combination of the three ways below. All the MSRs mentioned can be found in Section 5.18 "Power Management Controller Register Descriptions" on page 477 and Section 5.20 "GeodeLink Control Processor Register Descriptions" on page 513. PCI Clock 1) The power management circuitry disables the clocks when going into Sleep. The Sleep sequence is started by the assertion of Sleep Request from the Power Management Logic. The GLCP asserts Sleep Request and waits for the assertion of Sleep Acknowledge, which indicates that the clocks should be disabled. There are two ways to do this: – If Sleep Acknowledge is asserted and the clock disable delay period has expired, disable the clocks specified in GLCP_PMCLKDISABLE (MSR 51700009h). Each bit in GLCP_PMCLKDISABLE corresponds to a CCU, and when set, indicates that the clock going to that CCU should be disabled during a Sleep sequence. The clock disable delay period is specified by the CLK_DELAY bits in GLCP_CLK_DIS_DELAY (MSR 51700008h), and is enabled by the CLK_DLY_EN bit in GLCP_GLB_PM (MSR 5170000Bh). It is clocked by the PCI functional clock. TAP Controller Serial to GL Conversion PCI Interface Power Management Support MSR Registers GeodeLink Interface Req Out Req In Data Data Out In Figure 4-62. GLCP Block Diagram www.national.com 176 Revision 0.8 Geode™ CS5535 GLCP Functional Description (Continued) – If Sleep Acknowledge is asserted and the clock disable delay period is not enabled, check to see if all clocks specified by GLCP_CLK4ACK (MSR 51700013h) have become inactive. If GLCP_CLKACTIVE (MSR 51700011h) shows that those clocks are indeed inactive, disable the clocks specified in GLCP_PMCLKDISABLE (MSR 51700009h). Sleep Acknowledge is asserted after the clocks have been disabled. The wakeup sequence is triggered by the de-assertion of the Sleep Request, which turns on all the clocks. 2) If a debug event in the debug circuitry triggers a clock disable, disable all the clocks specified in GLCP_CLKDISABLE. Each GLCP_CLKDISABLE bit corresponds to a CCU, and when set, indicates that the clock going to that CCU should be disabled. Each bit in GLCP_CLKOFF (MSR 51700010h) corresponds to a CCU. When set, the bit indicates that the clock going to that CCU should be disabled. This is the simplest case. 4.19.2 GLCP Clocks The GLCP has multiple clock domains, namely the GeodeLink clock and PCI clock. The GeodeLink clock is the clock source for the MSRs, the serial interface, and the GeodeLink interface. The PCI clock is used in the power management support for the clock disable delay timer. Both the GeodeLink and PCI functional clocks come from primary inputs. All these clocks are handled by a CCU. Even though the PCI clock is always running in functional mode, a CCU is needed to be able to perform reset synchronization and to turn off the internal clock to support TAPSCAN. The CCUs used by the GLCP are the asynchronous versions, since the GLCP outputs asynchronous busy signals. 3) Revision 0.8 177 www.national.com Geode™ CS5535 4.20 TAP CONTROLLER The TAP Controller is IEEE 1149.1 compliant. A block diagram of the TAP, boundary scan and Internal scan is shown in Figure 4-63. The JTAG pins TCK, TDI, TDO, TMS, and RESET_STAND# are directly supported. The TAP is programmable by means of TAP control instructions. The meanings of the various instructions are shown in Table 438 on page 179 along with the length of the DR (Data register) that can be accessed once the instruction is entered. All Data registers shift in and out data LSB first. The Instruction register and all Data registers are shift registers, so if more bits are shifted in than the register can hold, only the last bits shifted in - the MSBs - will be used. This can be useful on systems that always shift in a multiple of 8 bits to the Data or Instruction registers. The Instruction register is 24 bits wide and defined in Table 4-39 on page 180. The TAP Controller can be initialized synchronously or asynchronously. For a synchronous reset, holding TMS high and clocking TCK a minimum of five times will put the TAP state machine into the Test-Logic-Reset state. Asynchronous reset is available too by asserting RESET_STAND# (Tap Controller Reset) (see Section 3.6 "Reset Considerations" on page 58). From RESET_STAND#, the TAP state machine will immediately enter the Test-Logic-Reset state. The TAP has specific pre-assigned meanings to the bits in the 24-bit IR register. The meanings are summarized in Table 4-39. Note that the bits only affect the chip once the “Update-IR” JTAG state occurs in the JTAG Controller shifting through these bits will not change the state of internal signals (e.g., test_mode). The details on JTAG Controller states are covered in the IEEE 1149.1 standard. Features TAP control/access to the following: • Shift/capture of CCU scan chain • GLIU access via Request-in, Request-out packets • TAPSCAN access • TRI-STATE mode control • Memory BIST control • ID code • Configures component for JTAG bypass mode Boundary Scan Registers Internal Scan Registers To Bscan To Iscan From Iscan From Bscan TDI TDO TCK TMS RESET_STAND# or LVD Standby Reset Memory BIST Interface Serial Interface with GLCP TAP Figure 4-63. TAP Controller, Boundary Scan Block Diagram www.national.com 178 Revision 0.8 Geode™ CS5535 TAP Controller Functional Description (Continued) Table 4-38. TAP Controller Instructions Instruction 000000h and FFFFE8h 01FFFAh through 1DFFFAh 01FFFFh through 1DFFFFh 81FFFAh 83FFFAh 85FFFAh 87FFFAh 8BFFFAh DR Length 240 Variable IR Name EXTEST TAPSCAN[0:28] Description Boundary Scan Ring. IEEE 1149.1 specification compliant. (Mapped twice in IR address space.) TAP Scan Chain 0 through Chain 28. These are parts of the internal scan chain subdivided according to a common CCU clock. TAP Function Chain 0 through Chain 28. One capture cycle applied to the individual CCU scan chain clocked by the functional clock. GeodeLink Address. Access GeodeLink request packet and data packet control bits. GeodeLink Data. Access GeodeLink data. Pad Access. Padtestmode for access to analog and memory BIST signals. Program instruction. This instruction provides direct access to an MSR used for the ROM memory BIST test. Not supported. GeodeLink Address Action. Same data register as GL_ADDR, but no GeodeLink transactions are triggered by the access only by GLCP debug action. Test IDDQ. Put chip in a mode for running IDDQ tests. Revision ID. The TAP instruction used to access the current revision code (8 bits) for the chip. TRI-STATE. Put chip into TRI-STATE and comparison mode. Parallel RAM BIST. Internal data register (for chip test). ID Code. 0FE1101Fh for CS5535. MSB ID[31:28] Version FFFFFFh 1 BYPASS ID27 Part Number ID[12:11] Manuf. ID LSB ID[1:0] 1 1 TAPFUNC[0:28] 70 66 4 24 70 GL_ADDR GL_DATA PADACC PROGMISR GL_ADDR_ACT 8DFFFAh 8FFFFAh FFFFDFh FFFFFDh FFFFFEh -8 1 21 32 TST_IDDQ REVID TRISTATE BISTDR IDCODE Bypass. IEEE 1149.1 specification requires all 1s to be bypassed. Revision 0.8 179 www.national.com Geode™ CS5535 TAP Controller Functional Description (Continued) Table 4-39. TAP Controller Instruction Bits Bit 23 22:17 16 15:10 9:7 Name TAPSCAN USER[5:0] bistEnable[3] RSVD bistEnable[2:0] Description TAP Scan. (Also USER[6].) This is a user bit added by National. Low indicates that an internal scan chain will be accessed by the TAP. User Bits 5 through 0. User bits used to identify an internal scan chain or, if bit 23 is high, to access a special internal DR. BIST Enable Bit 3. Works in conjunction with bits [9:7]. See bits [9:7] description for decode. Reserved. Should always be high. BIST Enable Bits 2 through 0. Works in conjunction with bit 16. 0000: 0010: 0100: 0110: 0001: 0011: 0101: 0111: 1000: 1010: 1100: 1110: 1011: 1001: 1101: 1111: 6 5 4 3 2:0 RSVD forceDis selectJtagOut selectJtagIn OP[2:0] bistEn12 bistEn11 bistEn10 bistEn9 bistEn8 bistEn7 bistEn6 bistEn5 bistEn4 bistEn3 bistEn2 bistEn1 bistEn0 Does nothing [normally used for logic BIST] Parallel scan Scan through TAP Reserved. Should always be high. Force Disable. Active low bit that places all output pins in TRI-STATE mode. See TRISTATE for details. Select JTAG Output. Active low bit that allows boundary scan cells to control pads. Select JTAG Output. Active low bit that allows boundary scan cells to drive data into core logic of chip. Operation Bits 2 through 0. Selects for how the JTAG chains are wired together. 000: 001: 010: 011: 100: 101: 110: 111: TDI -> Boundary Scan -> TDO TDI -> Boundary Scan -> Internal Scan -> Device ID -> Bypass -> TDO TDI -> Internal Scan -> TDO TDI -> Boundary Scan -> Internal Scan -> Device ID -> Bypass -> TDO TDI -> Internal Scan -> TDO TDI -> Internal Data Register -> TDO TDI -> Device ID -> TDO TDI -> Bypass -> TDO www.national.com 180 Revision 0.8 Geode™ CS5535 TAP Controller Functional Description (Continued) 4.20.1 EXTEST The EXTEST instruction accesses the boundary scan chain around the chip and controls the pad logic such that the boundary scan data will control the data and enable signals for the pads. IEEE 1149.1 requires that an all-zero instruction access the boundary scan chain. 4.20.2 TAPSCAN These instructions enable JTAG access to the internal scan associated with a particular CCU clock. TCK will then provide the Scan clock to the CCU so that shifting occurs correctly during the Shift-DR state of the TAP. (See Figure 464 and Figure 4-65.) 4.20.3 TAPFUNC These instructions connect TDI and TDO to the 1-bit bypass register during DR access. They are useful in that during the Capture-DR state, one functional clock can be applied to the specific CCU clock indicated by the instruction. This mode works well with the FS2 JTAG control software available with CS5535. The Scan Enable signal to the block will be inactive during this clock. Scan In Scan Out Pad Pad GeodeLink™ Device Scan In TAP Pad Test Mode = 1 Figure 4-64. TAP Controller and Parallel Scan Mode Revision 0.8 181 www.national.com Geode™ CS5535 TAP Controller Functional Description (Continued) Scan In[0] Scan Out[0] Scan In[1] GeodeLink™ Device Scan Out[1] TAP TDI Pad Test Mode = 0 TDO TAP_INST[23] = 0 TDO Pad Select Figure 4-65. TAP Controller and TAPSCAN Mode www.national.com 182 Revision 0.8 Geode™ CS5535 TAP Controller Functional Description (Continued) 4.20.4 GL_ADDR This register contains 53 bits for a GeodeLink control packet and the 17 bits for a GeodeLink data packet. The 17 bits from the data packet are updated if a GeodeLink read is requested and is available for shifting out. The GL_DATA description discusses the various conditions under which a valid request packet is posted to the internal GeodeLink. Note that since only one GL_ADDR request packet can be sequenced in with JTAG, the special “read with byte enable” 2-packet requests that GeodeLink supports cannot be triggered. Of course, 8, 16, 32, and 64-bit reads can still be performed and reads of less than 64-bit sizes will generate the appropriate byte enables at the device. As with GeodeLink traffic, reads of less than 64 bits must be to an aligned address, but the data will return in the GL_DATA adjusted to 64-bit alignment (i.e., a 16-bit read to address 102h should have address bit 1 set and data will return in bits [31:16] of the 64-bit response). Writes of less than 64 bits must always have 64-bit aligned addresses and should use the byte enables in the data packet (part of the GL_ADDR data register) to identify which specific bytes are to be written. 4.20.5 GL_DATA The data transfer rate in and out of the JTAG port is limited to about 90% of the TCK frequency by the GLCP design. The GLCP is designed for up to 50 MHz TCKs, but typical TCK rates for industry interfaces are about 15 MHz. As such, the GLCP JTAG data rate is 14 Mbits/sec or 1.6 Mbytes/sec. Again, however, industry interface boxes will limit this rate to about 500 kbytes/sec. GeodeLink requests packets are triggered at these specific moments: • If GL_ADDR has been accessed more recently than GL_ADDR_ACT and... — the TYPE of the request is a read and the Update-DR JTAG state is entered after loading the GL_ADDR register. — the TYPE of the request is a write and the UpdateDR JTAG state is entered after loading the GL_DATA register. — the TYPE of the request is a read and the second TCK in the Shift-DR state for shifting out the GL_DATA register is received and the first two bits shifted in (GL_DATA DR bits 1 and 0) are non-zero and the first bit shifted out was non-zero. • If GL_ADDR_ACT register has been accessed more recently than GL_ADDR and... — the GLCP debug logic triggers the GeodeLink_action due to a debug event occurring. Note that if both MSR accesses from the GLIU and JTAG accesses are interfacing to these registers, the results will be non-deterministic. 4.20.6 PADACC Provides a test mode whereby USB interface signals or memory BIST signals can be accessed by input/output pads. This access is accomplished by writing to the Auxiliary Test Register. 4.20.7 PROGMISR This instruction provides direct access to an MSR used for the ROM memory BIST test. At the conclusion of the test, the resulting signature is then checked. A correct test will result in MBIST_GO being logic-high. 4.20.8 MB_ADDR_ACT This is the same data register as GL_ADDR, but it disables any GeodeLink transaction from occurring either on this access or a following access to the GL_DATA register. Only the GLCP debug action that triggers a GeodeLink cycle will cause these bits to be used. 4.20.9 TST_IDDQ Places the chip in a mode for running IDDQ tests (i.e., generates an internal signal to disable pull-ups and pull downs). Also the transceiver is powered off. 4.20.10 REVID The TAP instruction used to access the current 8-bit revision code of the chip. 4.20.11 TRISTATE This instruction will TRI-STATE all of the tri-statable primary outputs. The DR accessed is the BYPASS register. 4.20.12 BISTDR Can be used to run all memory BIST controllers in parallel. 4.20.13 IDCODE This instruction accesses the 32-bit IDCODE register during DR access. 4.20.14 BYPASS In the IEEE 1149.1 specification, shifting all 1s into the IR must connect the 1-bit BYPASS register. The register has no function except as a storage flip-flop. This instruction can also allow relatively easy connection of multiple GLCP JTAG interface chips. On a board with two GLCP chips, TMS and TCK of each chip should be wired together and TDO of one chip should connect to TDI of the other chip. Note: In parallel scan mode, “input” pads provide data into the boundary scan cells (the boundary scan cells provide data into the core). “Cowrie” pads will behave as dictated by the internal core flops that normally control the pad; the output data and enable state will be latched into the boundary scan cells. “Cheroot” pads will drive out data as dictated by the internal core flop associated with the pad. Revision 0.8 183 www.national.com Geode™ CS5535 5.0 Register Descriptions Floppy Port • Standard GeodeLink Device MSRs: Accessed via RDMSR and WRMSR instructions. (Shared with DIVIL.) • Floppy Port Specific MSRs: Accessed via RDMSR and WRMSR instructions. Programmable Interval Timer (PIT) • Standard GeodeLink Device MSRs: Accessed via RDMSR and WRMSR instructions. (Shared with DIVIL.) • PIT Specific MSRs: Accessed via RDMSR and WRMSR instructions. • PIT Native Registers: Accessed as I/O addresses. Programmable Interrupt Controller (PIC) • Standard GeodeLink Device MSRs: Accessed via RDMSR and WRMSR instructions. (Shared with DIVIL.) • PIC Specific MSRs: Accessed via RDMSR and WRMSR instructions. • PIC Native Registers: Accessed as I/O addresses. Keyboard Emulation Logic (KEL) • Standard GeodeLink Device MSRs: Accessed via RDMSR and WRMSR instructions. (Shared with DIVIL.) • KEL Specific MSRs: Accessed via RDMSR and WRMSR instructions. • KEL Native Registers: Accessed via a base address register, MSR_LBAR_KEL1 (MSR 51400009h) and/or MSR_LBAR_KEL2 (MSR 5140000Ah), as memory offsets. System Management Bus (SMB) • Standard GeodeLink Device MSRs: Accessed via RDMSR and WRMSR instructions. (Shared with DIVIL.) • SMB Native Registers: Accessed via a base address register, MSR_LBAR_SMB (MSR 5140000Bh), as I/O offsets. Universal Asynchronous Receiver-Transmitter (UART) • Standard GeodeLink Device MSRs: Accessed via RDMSR and WRMSR instructions. (Shared with DIVIL.) • UART/IR Controller Specific MSRs: Accessed via RDMSR and WRMSR instructions. • UART/IR Controller Native Registers: Accessed via Banks 0 through 7 as I/O offsets. See MSR_LEG_IO (MSR 51400014h) bits [22:20] and bits [18:16] for setting base address. This chapter provides detailed information regarding the registers of the CS5535. The register descriptions are documented at the module-level and briefly summarized below. GeodeLink Interface Unit (GLIU) • Standard GeodeLink Device MSRs: Accessed via RDMSR and WRMSR instructions. • P2D Descriptor MSRs: Accessed via RDMSR and WRMSR instructions. (Memory base descriptor.) • GLIU Specific MSRs: Accessed via RDMSR and WRMSR instructions. • IOD Descriptor MSRs: Accessed via RDMSR and WRMSR instructions. (I/O base descriptor.) GeodeLink PCI South Bridge (GLPCI_SB) • Standard GeodeLink Device MSRs: Accessed via RDMSR and WRMSR instructions. • GLPCI_SB Specific MSRs: Accessed via RDMSR and WRMSR instructions. • PCI Configuration Registers: Index accessed via PCI configuration cycle. Audio Codec 97 Controller (ACC) • Standard GeodeLink Device MSRs: Accessed via RDMSR and WRMSR instructions. • ACC Native Registers: Accessed as I/O offsets from a GLIU IOD descriptor. ATA5 Controller (ATAC) • Standard GeodeLink Device MSRs: Accessed via RDMSR and WRMSR instructions. • ATAC Specific MSRs: Accessed via RDMSR and WRMSR instructions. • ATAC Native Registers: Accessed as I/O offsets from a GLIU IOD descriptor. Universal Serial Bus Controllers (USBC1, USBC2) • Standard GeodeLink Device MSRs: Accessed via RDMSR and WRMSR instructions. • USB Specific MSRs: Accessed via RDMSR and WRMSR instructions. • USB Embedded PCI Configuration Registers: Accessed via RDMSR and WRMSR instructions. Also requires GLIU P2D descriptor. • Host Controller Native Registers: Accessed via a base address register at USB PCI Index 10h as memory offsets. Diverse Integration Logic (DIVIL) • Standard GeodeLink Device MSRs: Accessed via RDMSR and WRMSR instructions. • DIVIL Specific MSRs: Accessed via RDMSR and WRMSR instructions. www.national.com 184 Revision 0.8 Geode™ CS5535 Register Descriptions (Continued) Direct Memory Access (DMA) • Standard GeodeLink Device MSRs: Accessed via RDMSR and WRMSR instructions. (Shared with DIVIL.) • DMA Specific MSRs: Accessed via RDMSR and WRMSR instructions. • DMA Native Registers: Accessed as I/O Addresses. Low Pin Count (LPC) • Standard GeodeLink Device MSRs: Accessed via RDMSR and WRMSR instructions. (Shared with DIVIL.) • LPC Specific MSRs: Accessed via RDMSR and WRMSR instructions. Real-Time Clock (RTC) • Standard GeodeLink Device MSRs: Accessed via RDMSR and WRMSR instructions. (Shared with DIVIL.) • RTC Specific MSRs: Accessed via RDMSR and WRMSR instructions. • RTC Native Registers: Accessed as I/O addresses. General Purpose Input Output (GPIO) • Standard GeodeLink Device MSRs: Accessed via RDMSR and WRMSR instructions. (Shared with DIVIL.) • GPIO Native Registers: Accessed via a base address register, MSR_LBAR_GPIO (MSR 5140000Ch), as I/O offsets. – GPIO Low/High Bank Feature Bit Registers – GPIO Input Conditioning Function Registers – GPIO Interrupt and PME Registers Multi-Function General Purpose Timer (MFGPT) • Standard GeodeLink Device MSRs: Accessed via RDMSR and WRMSR instructions. (Shared with DIVIL.) • MFGPT Specific MSRs: Accessed via RDMSR and WRMSR instructions. • MFGPT Native Registers: Accessed via a base address register, MSR_LBAR_MFGPT (MSR 5140000Dh), as I/O offsets. Power Management Controller (PMC) • Standard GeodeLink Device MSRs: Accessed via RDMSR and WRMSR instructions. (Shared with DIVIL.) • PMC Specific MSRs: Accessed via RDMSR and WRMSR instructions. • ACPI Registers: Accessed via a base address register, MSR_LBAR_ACPI (MSR 5140000Eh), as I/O offsets. • PM Support Registers: Accessed via a base address register, MSR_LBAR_PMS (MSR 5140000Fh), as I/O offsets. Flash Controller • Standard GeodeLink Device MSRs: Accessed via RDMSR and WRMSR instructions. (Shared with DIVIL.) • Flash Controller Specific MSRs: Accessed via RDMSR and WRMSR instructions. • Flash Controller Native Registers: Accessed via a base address register as either memory or I/O offsets: — MSR_LBAR_FLSH0 (MSR 51400010h) for use with FLASH_CS0#. — MSR_LBAR_FLSH1 (MSR 51400011h) for use with FLASH_CS1#. — MSR_LBAR_FLSH2 (MSR 51400012h) for use with FLASH_CS2#. — MSR_LBAR_FLSH3 (MSR 51400013h) for use with FLASH_CS3#. GeodeLink Control Processor (GLCP) • Standard GeodeLink Device MSRs: Accessed via RDMSR and WRMSR instructions. • GLCP Specific MSRs: Accessed via RDMSR and WRMSR instructions. Note that MSRs for the Floppy Port, PIT, PIC, KEL, SMB, UART, DMA, LPC, RTC, GPIO, MFGPT, and Flash Controller modules are part of the DIVIL (i.e., MSR 51400000h514000FFh). Hence, the Standard GeodeLink Device MSRs (MSR 51400000h-51400007h) are documented in the DIVIL register description and the device Specific MSRs are documented in their appropriate register description chapter. The tables in this chapter use the following abbreviations: Type R/W R Description Read/Write. Read from a specific address returns the value of a specific register. Write to the same address is to a different register. W RO WO R/W1C Write. Read Only. Write Only. Read/Write 1 to clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect. Revision 0.8 185 www.national.com Geode™ CS5535 5.1 GEODELINK INTERFACE UNIT REGISTER DESCRIPTIONS • P2D Descriptor MSRs • GLIU Specific MSRs • IOD Descriptor MSRs Tables 5-1 through 5-4 are GLIU register summary tables that include reset values and page references where the bit descriptions are provided. Reserved (RSVD) fields do not have any meaningful storage elements. They always return 0. The GeodeLink Interface Unit (GLIU) registers are Model Specific Registers (MSRs) and are accessed through the RDMSR and WRMSR instructions. The MSR address is derived from the perspective of the CPU Core. See Section 3.2 "CS5535 MSR Addressing" on page 53 for more details on MSR addressing. The MSRs are split into the following groups: • Standard GeodeLink Device MSRs Table 5-1. Standard GeodeLink Device MSRs Summary MSR Address 51010000h 51010001h 51010002h 51010003h 51010004h 51010005h 51010006h5101000Fh Type RO R/W R/W R/W R/W R/W R/W Register Name GeodeLink Device Capabilities MSR (GLIU_GLD_MSR_CAP) GeodeLink Device Master Configuration MSR (GLIU_GLD_MSR_CONFIG) GeodeLink Device SMI MSR (GLIU_GLD_MSR_SMI) GeodeLink Device Error MSR (GLIU_GLD_MSR_ERROR) GeodeLink Device Power Management MSR (GLIU_GLD_MSR_PM) GeodeLink Device Diagnostic MSR (GLIU_GLD_MSR_DIAG) GLIU Reserved MSRs (GLD_MSRs_RSVD) Reset Value 00000000_000010xxh 0000000_00000004h 00000000_00000001h 00000000_00000001h 00000000_00000000h 00000000_00000000h 00000000_00000000h Reference Page 189 Page 189 Page 190 Page 191 Page 193 Page 193 --- Table 5-2. P2D Descriptor MSRs Summary MSR Address 51010020h 51010021h 51010022h 51010023h 51010024h 51010025h5101003Fh Type R/W R/W R/W R/W R/W R/W Register Name P2D Base Mask Descriptor 0 (GLIU_P2D_BM0) P2D Base Mask Descriptor 1 (GLIU_P2D_BM1) P2D Base Mask Descriptor 2 (GLIU_P2D_BM2) P2D Base Mask KEL Descriptor 0 (GLIU_P2D_BMK0) P2D Base Mask KEL Descriptor 1 (GLIU_P2D_BMK1) P2D Reserved Descriptors (P2D_RSVD) Reset Value 000000FF_FFF00000h 000000FF_FFF00000h 000000FF_FFF00000h 000000FF_FFF00000h 000000FF_FFF00000h 00000000_00000000h Reference Page 194 Page 194 Page 194 Page 195 Page 195 --- www.national.com 186 Revision 0.8 Geode™ CS5535 GLIU Register Descriptions (Continued) Table 5-3. GLIU Specific MSRs Summary MSR Address 51010080h 51010081h 51010082h 51010083h 51010084h 51010085h 51010086h 51010087h 51010088h 51010089h5101008Ah 5101008Bh 5101008Ch 5101008Dh5101008Fh 510100A0h 510100A1h 510100A2h 510100A3h 510100A4h 510100A5h 510100A6h 510100A7h 510100A8h 510100A9h 510100AAh 510100ABh510100BFh 510100C0h 510100C1h Type R/W R/W R/W R/W R/W R/W RO RO RO R/W RO R/W R/W WO R/W R/W R/W WO R/W R/W R/W WO R/W R/W R/W R/W R/W Register Name Coherency (GLIU_COH) Port Active Enable (GLIU_PAE) Arbitration (GLIU_ARB) Asynchronous SMI (GLIU_ASMI) Asynchronous Error (GLIU_AERR) Debug (GLIU_DEBUG) Physical Capabilities (GLIU_PHY_CAP) N Outstanding Response (GLIU_NOUT_RESP) Number of Outstanding Write Data (GLIU_NOUT_WDATA) Reserved (RSVD) WHO AM I (GLIU_WHOAMI) Slave Disable (GLIU_SLV_DIS) Reserved (RSVD) Descriptor Statistic Counter 0 (GLIU_STATISTIC_CNT0) Descriptor Statistic Mask 0 (GLIU_STATISTIC_MASK0) Descriptor Statistic Action 0 (GLIU_STATISTIC_ACTION0) Reserved (RSVD) Descriptor Statistic Counter 1 (GLIU_STATISTIC_CNT1) Descriptor Statistic Mask 1 (GLIU_STATISTIC_MASK1) Descriptor Statistic Action 1 (GLIU_STATISTIC_ACTION1) Reserved (RSVD) Descriptor Statistic Counter 2 (GLIU_STATISTIC_CNT2) Descriptor Statistic Mask 2 (GLIU_STATISTIC_MASK2) Descriptor Statistic Action 2 (GLIU_STATISTIC_ACTION2) Reserved (RSVD) Request Compare Value (GLIU_RQ_COMP_VAL) Request Compare Mask (GLIU_RQ_COMP_MASK) Reset Value 00000000_00000000h 00000000_0000FFFFh 00000000_00000000h 00000000_00000000h 00000000_00000000h 00000000_00000004h 327920A0_80000003h 00000000_00000000h 00000000_00000000h 00000000_00000000h Configuration Dependent 00000000_00000000h 00000000_00000000h 00000000_00000000h 00000000_00000000h 00000000_00000000h 00000000_00000000h 00000000_00000000h 00000000_00000000h 00000000_00000000h 00000000_00000000h 00000000_00000000h 00000000_00000000h 00000000_00000000h 00000000_00000000h 001FFFFF_FFFFFFFFh 00000000_00000000h Reference Page 196 Page 196 Page 197 Page 197 Page 198 Page 199 Page 200 Page 201 Page 201 --Page 201 Page 202 --Page 203 Page 204 Page 205 --Page 203 Page 204 Page 205 --Page 203 Page 204 Page 205 --Page 206 Page 207 Revision 0.8 187 www.national.com Geode™ CS5535 GLIU Register Descriptions (Continued) Table 5-3. GLIU Specific MSRs Summary (Continued) MSR Address 510100C2h510100CFh 510100D0h 510100D1h 510100D2h 510100D3h 510100D4h510100DFh Type R/W R/W R/W R/W R/W R/W Register Name Reserved (RSVD) Data Compare Value Low (GLIU_DA_COMP_VAL_LO) Data Compare Value High (GLIU_DA_COMP_VAL_HI) Data Compare Mask Low (GLIU_DA_COMP_MASK_LO) Data Compare Mask High (GLIU_DA_COMP_MASK_HI) Reserved (RSVD) Reset Value 00000000_00000000h 00001FFF_FFFFFFFFh 0000000F_FFFFFFFFh 00000000_00000000h 00000000_00000000h 00000000_00000000h Reference --Page 207 Page 208 Page 208 Page 209 --- Table 5-4. IOD Descriptor MSRs Summary MSR Address 510100E0h 510100E1h 510100E2h 510100E3h 510100E4h 510100E5h 510100E6h 510100E7h 510100E8h 510100E9h 510100EAh 510100EAh 510100EBh 510100ECh 510100EDh 510100EEh 510100EFh 510100F0h 510100F1h 510100F2h510100FFh Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Register Name IOD Base Mask 0 (GLIU_IOD_BM0); Reserved for ATA-5; Defaults to 1Fx16. IOD Base Mask 1 (GLIU_IOD_BM1) IOD Base Mask 2 (GLIU_IOD_BM2) IOD Base Mask 3 (GLIU_IOD_BM3) IOD Base Mask 4 (GLIU_IOD_BM4) IOD Base Mask 5 (GLIU_IOD_BM5) IOD Base Mask 6 (GLIU_IOD_BM6) IOD Base Mask 7 (GLIU_IOD_BM7) IOD Base Mask 8 (GLIU_IOD_BM8) IOD Base Mask 9 (GLIU_IOD_BM9) IOD Swiss Cheese 0 (GLIU_IOD_SC0) IOD Swiss Cheese 0 (GLIU_IOD_SC0); Reserved for ATA-5; Defaults to 3F616. IOD Swiss Cheese 1 (GLIU_IOD_SC1) IOD Swiss Cheese 2 (GLIU_IOD_SC2) IOD Swiss Cheese 3 (GLIU_IOD_SC3) IOD Swiss Cheese 4 (GLIU_IOD_SC4) IOD Swiss Cheese 5 (GLIU_IOD_SC5) IOD Swiss Cheese 6 (GLIU_IOD_SC6) IOD Swiss Cheese 7 (GLIU_IOD_SC7) Reserved (RSVD) Reset Value 60000000_1F0FFFF0h 000000FF_FFF00000h 000000FF_FFF00000h 000000FF_FFF00000h 000000FF_FFF00000h 000000FF_FFF00000h 000000FF_FFF00000h 000000FF_FFF00000h 000000FF_FFF00000h 000000FF_FFF00000h 60000000_403003F0h 60000000_403003F0h 00000000_00000000h 00000000_00000000h 00000000_00000000h 00000000_00000000h 00000000_00000000h 00000000_00000000h 00000000_00000000h 00000000_00000000h Reference Page 210 Page 210 Page 210 Page 210 Page 210 Page 210 Page 210 Page 210 Page 210 Page 210 Page 211 Page 211 Page 211 Page 211 Page 211 Page 211 Page 211 Page 211 Page 211 --- www.national.com 188 Revision 0.8 Geode™ CS5535 GLIU Register Descriptions (Continued) 5.1.1 Standard GeodeLink Device MSRs 5.1.1.1 GeodeLink Device Capabilities MSR (GLIU_GLD_MSR_CAP) MSR Address 51010000h Type RO Reset Value 00000000_000010xxh GLIU_GLD_MSR_CAP Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RSVD DEV_ID 9 8 7 6 5 4 3 2 1 0 REV_ID GLIU_GLD_MSR_CAP Bit Descriptions Bit 63:24 23:8 7:0 Name RSVD DEV_ID REV_ID Description Reserved. Reads return 0. Device ID. Identifies module (0010h). Revision ID. Identifies module revision. See CS5535 I/O Companion Device Errata document for value. 5.1.1.2 GeodeLink Device Master Configuration MSR (GLIU_GLD_MSR_CONFIG) MSR Address 51010001h Type R/W Reset Value 0000000_00000004h GLIU_GLD_MSR_CONFIG Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RSVD 9 8 7 6 5 4 3 2 1 SUBP 0 GLD_MSR_CONFIG Bit Descriptions Bit 63:3 2:0 Name RSVD SUBP Description Reserved. Write as read. Subtractive Port. For all negative decode requests. 000: Port 0 (GLIU) 001: Port 1 (GLPCI_SB) 010: Port 2 (USBC2) 011: Port 3 (ATAC) Note: 100: Port 4 (DD) 101: Port 5 (ACC) 110: Port 6 (USBC1) 111: Port 7 (GLCP) The reset value of this register should not be changed. Revision 0.8 189 www.national.com Geode™ CS5535 GLIU Register Descriptions (Continued) 5.1.1.3 GeodeLink Device SMI MSR (GLIU_GLD_MSR_SMI) MSR Address 51010002h Type R/W Reset Value 00000000_00000001h The flags are set by internal conditions. The internal conditions are enabled if the EN bit is 0. Reading the FLAG bit returns the value; writing 1 clears the flag; writing 0 has no effect. (See Section 3.8.3 "MSR Address 2: SMI Control" on page 67 for further SMI and ASMI generation details.) GLIU_GLD_MSR_SMI Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 STATCNT2_ASMI_FLAG STATCNT1_ASMI_FLAG RSVD STATCNT0_ASMI_FLAG 1 STATCNT0_ASMI_EN 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RSVD 9 8 7 6 5 4 3 STATCNT2_ASMI_EN 2 STATCNT1_ASMI_EN GLIU_GLD_MSR_SMI Bit Descriptions Bit 63:36 35 Name RSVD STATCNT2_ ASMI_FLAG STATCNT1_ ASMI_FLAG STATCNT0_ ASMI_FLAG SSMI_FLAG Description Reserved. Write as read. Statistic Counter 2 ASMI Flag. If high, records that an ASMI was generated due to a Statistic Counter 2 (MSR 510100A8h) event. Write 1 to clear; writing 0 has no effect. STATCNT2_ASMI_EN (bit 3) must be low to generate ASMI and set flag. Statistic Counter 1 ASMI Flag. If high, records that an ASMI was generated due to a Statistic Counter 1 (MSR 510100A4h) event. Write 1 to clear; writing 0 has no effect. STATCNT1_ASMI_EN (bit 2) must be low to generate ASMI and set flag. Statistic Counter 0 SMI Flag. If high, records that an ASMI was generated due to a Statistic Counter 0 (MSR 510100A0h) event. Write 1 to clear; writing 0 has no effect. STATCNT0_ASMI_EN (bit 1) must be low to generate ASMI and set flag. SSMI Flag. If high, records that an SSMI was generated due to a received event. Event sources are: • Illegal request type to GLIU (Port 0), meaning anything other than MSR read/write, debug request, and null. • A self-referencing packet (i.e., a packet sent to the GLIU that finds its destination port is the source port). • The destination of the packet is to a port where the GLIU slave for that port has been disabled. • Trap on a descriptor with device port set to 0. This is the typical operational use of this bit. The data returned with such a trap is the value 0. Write 1 to clear; writing 0 has no effect. SSMI_EN (bit 0) must be low to generate SSMI and set flag. 31:4 RSVD Reserved. Write as read. 34 33 32 www.national.com 190 Revision 0.8 SSMI_EN SSMI_FLAG 0 Geode™ CS5535 GLIU Register Descriptions (Continued) GLIU_GLD_MSR_SMI Bit Descriptions (Continued) Bit 3 2 1 0 Name STATCNT2_ ASMI_EN STATCNT1_ ASMI_EN STATCNT0_ ASMI_EN SSMI_EN Description Statistic Counter 2 ASMI Enable. Write 0 to enable STATCNT2_ASMI_FLAG (bit 35) and to allow a Statistic Counter 2 (MSR 510100A8h) event to generate an ASMI. Statistic Counter 1 ASMI Enable. Write 0 to enable STATCNT1_ASMI_FLAG (bit 34) and to allow a Statistic Counter 1 (MSR 510100A4h) event to generate an ASMI. Statistic Counter 0 ASMI Enable. Write 0 to enable STATCNT0_ASMI_FLAG (bit 33) and to allow a Statistic Counter 0 (MSR 510100A0h) event to generate an ASMI. SSMI Enable. Write 0 to enable SSMI_FLAG (bit 32) and to allow a received SSMI event to generate an SSMI. (See bit 32 description for SSMI event sources.) 5.1.1.4 GeodeLink Device Error MSR (GLIU_GLD_MSR_ERROR) MSR Address 51010003h Type R/W Reset Value 00000000_00000001h The flags are set by internal conditions. The internal conditions are enabled if the EN bit is 0. Reading the FLAG bit returns the value; writing 1 clears the flag; writing 0 has no effect. (See Section 3.8.4 "MSR Address 3: Error Control" on page 71 for further details.) GLIU_GLD_MSR_ERROR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 STATCNT2_ERR_FLAG STATCNT1_ERR_FLAG STATCNT0_ERR_FLAG RQCOMP_ERR_FLAG RSVD DACMP_ERR_FLAG RSVD UNEXP_TYPE_ERR_FLAG 0 UNEXP_TYPE_ERR_EN UNEXP_ADD_ERR_FLAG 1 UNEXP_ADD_ERR_EN 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RSVD DACMP_ERR_EN 9 8 7 RQCOMP_ERR_EN 6 5 STATCNT2_ERR_EN 4 STATCNT1_ERR_EN 3 STATCNT0_ERR_EN RSVD GLIU_GLD_MSR_ERROR Bit Descriptions Bit 63:44 43 Name RSVD DACOMP_ ERR_FLAG Description Reserved. Write as read. Data Comparator Error Flag. If high, records that an ERR was generated due to a Data Comparator (DA_COMP_VAL_LO / DA_COMP_VAL_HI, MSR 510100D0h / 510100D1h) event. Write 1 to clear; writing 0 has no effect. DACOMP_ERR_EN (bit 11) must be low to generate ERR and set flag. Reserved. Write as read. 42:40 RSVD Revision 0.8 191 www.national.com SSMI_ERR_EN RSVD SSMI_ERR_FLAG 2 RSVD Geode™ CS5535 GLIU Register Descriptions (Continued) GLIU_GLD_MSR_ERROR Bit Descriptions (Continued) Bit 39 Name RQCOMP_ ERR_FLAG RSVD STATCNT2_ ERR_FLAG STATCNT1_ ERR_FLAG STATCNT0_ ERR_FLAG SSMI_ERR_ FLAG UNEXP_ADD_ ERR_FLAG UNEXP_TYPE _ERR_FLAG RSVD DACOMP_ ERR_EN RSVD RQCOMP_ ERR_EN RSVD STATCNT2_ ERR_EN STATCNT1_ ERR_EN STATCNT0_ ERR_EN SSMI_ERR_ EN UNEXP_ADD_ ERR_EN UNEXP_TYPE _ERR_EN Description Request Comparator Error Flag. If high, records that an ERR was generated due to a Request Comparator 0 (RQ_COMP_VAL, MSR 510100C0h) event. Write 1 to clear; writing 0 has no effect. RQCOMP_ERR_EN (bit 7) must be low to generate ERR and set flag. Reserved. Write as read. Statistic Counter 2 Error Flag. If high, records that an ERR was generated due to a Statistic Counter 2 (MSR 510100A8h) event. Write 1 to clear; writing 0 has no effect. STATCNT2_ERR_EN (bit 5) must be low to generate ERR and set flag. Statistic Counter 1 Error Flag. If high, records that an ERR was generated due to a Statistic Counter 1 (MSR 510100A4h) event. Write 1 to clear; writing 0 has no effect. STATCNT2_ERR_EN (bit 4) must be low to generate ERR and set flag. Statistic Counter 0 Error Flag. If high, records that an ERR was generated due to a Statistic Counter 0 (MSR 510100A4h) event. Write 1 to clear; writing 0 has no effect. STATCNT0_ERR_EN (bit 3) must be low to generate ERR and set flag. SSMI Error Flag. If high, records that an ERR was generated due an unhandled SSMI (synchronous error). Write 1 to clear; writing 0 has no effect. SSMI_ERR_EN (bit 2) must be low to generate ERR and set flag. (Note 1) Unexpected Address Error Flag. If high, records that an ERR was generated due an unexpected address (synchronous error). Write 1 to clear; writing 0 has no effect. UNEXP_ADD_ERR_EN (bit 1) must be low to generate ERR and set flag. (Note 1) Unexpected Type Error Flag. If high, records that an ERR was generated due an unexpected type (synchronous error). Write 1 to clear; writing 0 has no effect. UNEXP_TYPE_ERR_EN (bit 0) must be low to generate ERR and set flag. (Note 1) Reserved. Write as read. Data Comparator Error Enable. Write 0 to enable DACOMP_ERR_FLAG (bit 43) and to allow a Data Comparator (DA_COMP_VAL_LO / DA_COMP_VAL_HI, MSR 510100D0h / 510100D1h) event to generate an ERR and set flag. Reserved. Write as read. Request Comparator Error Enable. Write 0 to enable RQCOMP_ERR_FLAG (bit 39) and to allow a Request Comparator (RQ_COMP_VAL, MSR 510100C0h) event to generate an ERR. Reserved. Write as read. Statistic Counter 2 Error Enable. Write 0 to enable STATCNT2_ERR_FLAG (bit 37) and to allow a Statistic Counter 2 (MSR 510100A8h) event to generate an ERR. Statistic Counter 1 Error Enable. Write 0 to enable STATCNT1_ERR_FLAG (bit 36) and to allow a Statistic Counter 1 (MSR 510100A4h) event to generate an ERR. Statistic Counter 0 Error Enable. Write 0 to enable STATCNT0_ERR_FLAG (bit 35) and to allow a Statistic Counter 0 (MSR 510100A0h) event to generate an ERR. SSMI Error Enable. Write 0 to enable SSMI_ERR_FLAG (bit 34) and to allow the unhandled SSMI (synchronous error) event to generate an ERR. Unexpected Address Error Enable. Write 0 to enable UNEXP_ADD_ERR_FLAG (bit 33) and to allow the unexpected address (synchronous error) event to generate an ERR. Unexpected Type Error Enable. Write 0 to enable UNEXP_TYPE_ERR_FLAG (bit 32) and to allow the unexpected type (synchronous error) event to generate an ERR. 38 37 36 35 34 33 32 31:12 11 10:8 7 6 5 4 3 2 1 0 Note 1. These are synchronous errors, that is, they do not result in the assertion of the GL Error signal but instead set the Exception bit in the response packet. www.national.com 192 Revision 0.8 Geode™ CS5535 GLIU Register Descriptions (Continued) 5.1.1.5 GeodeLink Device Power Management MSR (GLIU_GLD_MSR_PM) MSR Address 51010004h Type R/W Reset Value 00000000_00000000h GLIU_GLD_MSR_PM Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RSVD 9 8 7 6 5 4 3 PMODE1 2 1 PMODE0 0 GLIU_GLD_MSR_PM Bit Descriptions Bit 63:4 3:2 Name RSVD PMODE1 Description Reserved. Write as read. Power Mode 1. Statistics and Time Slice Counters. 00: Disable clock gating. Clocks are always on. 01: Enable active hardware clock gating. Clock goes off whenever this module’s circuits are not busy. 10: Reserved. 11: Reserved. 1:0 PMODE0 Power Mode 0. Online GLIU logic. 00: Disable clock gating. Clocks are always on. 01: Enable active hardware clock gating. Clock goes off whenever this module’s circuits are not busy. 10: Reserved. 11: Reserved. 5.1.1.6 GeodeLink Device Diagnostic MSR (GLIU_GLD_MSR_DIAG) MSR Address 51010005h Type R/W Reset Value 00000000_00000000h This register is reserved for internal use by National and should not be written to. Revision 0.8 193 www.national.com Geode™ CS5535 GLIU Register Descriptions (Continued) 5.1.2 5.1.2.1 P2D Descriptor MSRs P2D Base Mask Descriptors (GLIU_P2D_BM[x]) P2D Base Mask Descriptor 0 (GLIU_P2D_BM0) MSR Address 51010020h Type R/W Reset Value 000000FF_FFF00000h P2D Base Mask Descriptor 1 (GLIU_P2D_BM1) MSR Address 51010021h Type R/W Reset Value 000000FF_FFF00000h P2D Base Mask Descriptor 2 (GLIU_P2D_BM2) MSR Address 51010022h Type R/W Reset Value 000000FF_FFF00000h These registers set up the Physical To Device Base Mask descriptors for determining an address hit. GLIU_P2D_BM[x] Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 PCMP_BIZ_BM PDID1_BM RSVD PBASE 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PBASE_BM 9 8 7 6 5 4 3 2 1 0 PMASK_BM GLIU_P2D_BM[x] Bit Descriptions Bit 63:61 Name PDID_BM Description Physical Descriptor Destination ID. These bits define which port to route the request to if it is a hit based on the other settings in this register. 000: Port 0 (GLIU) 001: Port 1 (GLPCI_SB) 010: Port 2 (USBC2) 011: Port 3 (ATAC) 60 PCMP_BIZ_BM Physical Compare BIZZARO Flag. 0: Consider only transactions whose BIZZARO flag is low as a potentially valid address hit. A low BIZZARO flag indicates a normal transaction cycle such as a memory or I/O. 1: Consider only transactions whose BIZZARO flag is high as a potentially valid address hit. A high BIZZARO flag indicates a ‘special’ transaction, such as a PCI Shutdown or Halt cycle 59:40 39:20 RSVD PBASE_BM Reserved. Write as read. Physical Memory Address Base. These bits form the matching value against which the masked value of the physical address bits [31:12] are directly compared. If a match is found, then a hit is declared, depending on the setting of the BIZZARO flag comparator. Physical Memory Address Mask. These bits are used to mask physical address bits [31:12] for the purposes of this hit detection. 100: Port 4 (DD) 101: Port 5 (ACC) 110: Port 6 (USBC1) 111: Port 7 (GLCP) 19:0 PMASK_BM www.national.com 194 Revision 0.8 Geode™ CS5535 GLIU Register Descriptions (Continued) 5.1.2.2 P2D Base Mask KEL Descriptors (GLIU_P2D_BMK[x]) P2D Base Mask KEL Descriptor 0 (GLIU_P2D_BMK0) MSR Address 51010023h Type R/W Reset Value 000000FF_FFF00000h P2D Base Mask KEL Descriptor 1 (GLIU_P2D_BMK1) MSR Address 51010024h Type R/W Reset Value 000000FF_FFF00000h This is a special version of a P2D_BM descriptor to support routing the USB Keyboard Emulation Logic (KEL) native registers to the default port. The default port device on the CS5535 contains the KEL. GLIU_P2D_BMK[x] Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 PCMP_BIZ_BMK PDID1_BM K RSVD PBASE_BMK 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PBASE_BMK 9 8 7 6 5 4 3 2 1 0 PMASK_BMK GLIU_P2D_BMK[x] Bit Descriptions Bit 63:61 Name PDID1_BMK Description Physical Descriptor Destination ID. Descriptor Destination ID. These bits define which port to route the request to if it is a hit based on the other settings in this register. 000: Port 0 (GLIU) 001: Port 1 (GLPCI_SB) 010: Port 2 (USBC2) 011: Port 3 (ATAC) 60 59:40 39:20 PCMP_BIZ_BMK RSVD PBASE_BMK 100: Port 4 (DD) 101: Port 5 (ACC) 110: Port 6 (USBC1) 111: Port 7 (GLCP) Physical Compare BIZZARO Flag. If set, bit 8 of the address must be low for a hit on this descriptor. Reserved. Write as read. Physical Memory Address Base.These bits form the matching value against which the masked value of the physical address bits [31:12] are directly compared. If a match is found, then a hit is declared, depending on the setting of the BIZZARO flag comparator. Physical Memory Address Mask.These bits are used to mask physical address bits [31:12] for the purposes of this hit detection. 19:0 PMASK_BMK Revision 0.8 195 www.national.com Geode™ CS5535 GLIU Register Descriptions (Continued) 5.1.3 GLIU Specific MSRs 5.1.3.1 Coherency (GLIU_COH) MSR Address 51010080h Type R/W Reset Value 00000000_00000000h GLIU_COH Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RSVD 9 8 7 6 5 4 3 2 1 COHP 0 GLIU_COH Bit Descriptions Bit 63:3 2:0 Name RSVD COHP Description Reserved. Write as read. Coherent Device Port. The port that coherent snoops are routed to. If the coherent device is on the other side of a bridge, the COHP points to the bridge. 000: Port 0 (GLIU) 001: Port 1 (GLPCI_SB) 010: Port 2 (USBC2) 011: Port 3 (ATAC) 100: Port 4 (DD) 101: Port 5 (ACC) 110: Port 6 (USBC1) 111: Port 7 (GLCP) 5.1.3.2 Port Active Enable (GLIU_PAE) MSR Address 51010081h Type R/W Reset Value 00000000_0000FFFFh GLIU_PAE Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RSVD PAE0 PAE7 PAE6 9 8 7 6 5 4 3 2 1 0 PAE5 PAE4 PAE3 PAE2 PAE1 GLIU_PAE Bit Descriptions Bit 63:16 15:14 Name RSVD PAE0 Description Reserved. Write as read. Port Active Enable for Port 0 (GLIU). 00: OFF - Master transactions are disabled. 01: LOW - Master transactions limited to one outstanding transaction. 10: Reserved. 11: ON - Master transactions enabled with no limitations. 13:12 11:10 9:8 7:6 PAE7 PAE6 PAE5 PAE4 Port Active Enable for Port 7 (GLCP).See bits [15:14] for decode. Port Active Enable for Port 6 (USBC1). See bits [15:14] for decode. Port Active Enable for Port 5 (ACC). See bits [15:14] for decode. Port Active Enable for Port 4 (DD). See bits [15:14] for decode. www.national.com 196 Revision 0.8 Geode™ CS5535 GLIU Register Descriptions (Continued) GLIU_PAE Bit Descriptions (Continued) Bit 5:4 3:2 1:0 Name PAE3 PAE2 PAE1 Description Port Active Enable for Port 3 (ATAC). See bits [15:14] for decode. Port Active Enable for Port 2 (USBC2). See bits [15:14] for decode. Port Active Enable for Port 1 (GLPCI_SB). 5.1.3.3 Arbitration (GLIU_ARB) MSR Address 51010082h Type R/W Reset Value 00000000_00000000h GLIU_ARB Register 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 PIPE_DIS RSVD RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RSVD 9 8 7 6 5 4 3 2 1 0 GLIU_ARB Bit Descriptions Bit 63 62 Name RSVD PIPE_DIS Description Reserved. Write as read. Pipelined Arbitration Disabled. 0: Pipelined arbitration enabled and the GLIU is not limited to one outstanding transaction. 1: Limit the entire GLIU to one outstanding transaction. 61:0 RSVD Reserved. Write as read. 5.1.3.4 Asynchronous SMI (GLIU_ASMI) MSR Address 51010083h Type R/W Reset Value 00000000_00000000h ASMI is a condensed version of the Port ASMI signals. The EN bits ([15:8]) can be used to prevent a device from issuing an ASMI. A write of 1 to the EN bit disables the device’s ASMI. The FLAG bits ([7:0]) are status bits. If high, an ASMI was generated due to the associated device. (See Section 3.1.4 "ASMI and Error" on page 51 for further details.) GLIU_ASMI Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 P7_ASMI_EN P6_ASMI_EN P5_ASMI_EN P4_ASMI_EN P3_ASMI_EN P2_ASMI_EN RSVD 9 P1_ASMI_EN 8 P0_ASMI_EN 7 P7_ASMI_FLAG 6 P6_ASMI_FLAG 5 P5_ASMI_FLAG 4 P4_ASMI_FLAG 3 P3_ASMI_FLAG 2 P2_ASMI_FLAG 1 P1_ASMI_FLAG 0 P0_ASMI_FLAG Revision 0.8 197 www.national.com Geode™ CS5535 GLIU Register Descriptions (Continued) GLIU_ASMI Bit Descriptions Bit 63:16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name RSVD P7_ASMI_EN P6_ASMI_EN P5_ASMI_EN P4_ASMI_EN P3_ASMI_EN P2_ASMI_EN P1_ASMI_EN P0_ASMI_EN P7_ASMI_FLAG (RO) P6_ASMI_FLAG (RO) P5_ASMI_FLAG (RO) P4_ASMI_FLAG (RO) P3_ASMI_FLAG (RO) P2_ASMI_FLAG (RO) P1_ASMI_FLAG (RO) P0_ASMI_FLAG (RO) Description Reserved. Port 7 (GLCP) Asynchronous SMI Enable. Port 6 (USBC1) Asynchronous SMI Enable. Port 5 (ACC) Asynchronous SMI Enable. Port 4 (DD) Asynchronous SMI Enable. Port 3 (ATAC) Asynchronous SMI Enable. Port 2 (USBC2) Asynchronous SMI Enable. Port 1 (GLPCI_SB) Asynchronous SMI Enable. Port 0 (GLIU) Asynchronous SMI Enable. Port 7 (GLCP) Asynchronous SMI Flag (Read Only). Port 6 (USBC1) Asynchronous SMI Flag (Read Only). Port 5 (ACC) Asynchronous SMI Flag (Read Only). Port 4 (DD) Asynchronous SMI Flag (Read Only). Port 3 (ATAC) Asynchronous SMI Flag (Read Only). Port 2 (USBC2) Asynchronous SMI Flag (Read Only). Port 1 (GLPCI_SB) Asynchronous SMI Flag (Read Only). Port 0 (GLIU) Asynchronous SMI Flag (Read Only). 5.1.3.5 Asynchronous Error (GLIU_AERR) MSR Address 51010084h Type R/W Reset Value 00000000_00000000h ERR is a condensed version of the port (asynchronous) ERR signals. The EN bits ([15:8]) can be used to prevent a device from issuing an ERR. A write of 1 to the EN bit disables the device’s ERR. The FLAG bits ([7:0]) are status bits. If high, an ERR was generated due to the associated device. (See Section 3.1.4 "ASMI and Error" on page 51 for further details.) GLIU_AERR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 P7_AERR_EN P6_AERR_EN P5_AERR_EN P4_AERR_EN P3_AERR_EN P2_AERR_EN RSVD 9 P1_AERR_EN 8 P0_AERR_EN 7 P7_AERR_FLAG 6 P6_AERR_FLAG 5 P5_AERR_FLAG 4 P4_AERR_FLAG 3 P3_AERR_FLAG 2 P2_AERR_FLAG 1 P1_AERR_FLAG 0 P0_AERR_FLAG GLIU_AERR Bit Descriptions Bit 63:16 15 14 Name RSVD P7_AERR_EN P6_AERR_EN Description Reserved. Port 7 (GLCP) Asynchronous Error Enable. Port 6 (USBC1) Asynchronous Error Enable. www.national.com 198 Revision 0.8 Geode™ CS5535 GLIU Register Descriptions (Continued) GLIU_AERR Bit Descriptions Bit 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name P5_AERR_EN P4_AERR_EN P3_AERR_EN P2_AERR_EN P1_AERR_EN P0_AERR_EN P7_AERR_FLAG (RO) P6_AERR_FLAG (RO) P5_AERR_FLAG (RO) P4_AERR_FLAG (RO) P3_AERR_FLAG (RO) P2_AERR_FLAG (RO) P1_AERR_FLAG (RO) P0_AERR_FLAG (RO) Description Port 5 (ACC) Asynchronous Error Enable. Port 4 (DD) Asynchronous Error Enable. Port 3 (ATAC) Asynchronous Error Enable. Port 2 (USBC2) Asynchronous Error Enable. Port 1 (GLPCI_SB) Asynchronous Error Enable. Port 0 (GLIU) Asynchronous Error Enable. Port 7 (GLCP) Asynchronous Error Flag (Read Only). Port 6 (USBC1) Asynchronous Error Flag (Read Only). Port 5 (ACC) Asynchronous Error Flag (Read Only). Port 4 (DD) Asynchronous Error Flag (Read Only). Port 3 (ATAC) Asynchronous Error Flag (Read Only). Port 2 (USBC2) Asynchronous Error Flag (Read Only). Port 1 (GLPCI_SB) Asynchronous Error Flag (Read Only). Port 0 (GLIU) Asynchronous Error Flag (Read Only). 5.1.3.6 Debug (GLIU_DEBUG) MSR Address 51010085h Type R/W Reset Value 00000000_00000004h GLIU_DEBUG Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RSVD 9 8 7 6 5 4 3 2 1 0 GLIU_DEBUG Bit Descriptions Bit 63:0 Name RSVD Description Reserved. Write as read. Revision 0.8 199 www.national.com Geode™ CS5535 GLIU Register Descriptions (Continued) 5.1.3.7 Physical Capabilities (GLIU_PHY_CAP) MSR Address 51010086h Type RO Reset Value 327920A0_80000003h This register provides the resources available in the CS5535. GLIU_PHY_CAP Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD NSTAT_ CNT NDBG_DA_ NDBG_RQ CMP _CMP NPORTS NCOH NIOD_SC 9 8 NIOD_BM 7 6 5 4 NP2D_BMK 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 NP2D_ BMK NP2D_SC NP2D_RO NP2D_R NP2D_BMO NP2D_BM GLIU_PHY_CAP Bit Descriptions Bit 63 62:60 59:57 56:54 53:51 50:48 47:42 41:36 35:30 29:24 23:18 17:12 11:6 5:0 Name RSVD NSTAT_CNT NDBG_DA_CMP NDBG_RQ_CMP NPORTS NCOH NIOD_SC NIOD_BM NP2D_BMK NP2D_SC NP2D_RO NP2D_R NP2D_BMO NP2D_BM Description Reserved. Returns 0. Number Of Statistic Counters. Provides the number of available Statistic Counters. Number Of Data Comparators. Provides the number of available Data Comparators. Number Of Request Comparators. Provides the number of available Request Comparators. Number of Ports on the GLIU. Provides the number of available ports on the GLIU. Number of Coherent Devices. Provides the number of available Coherent Devices. Number of IOD_SC Descriptors. Provides the number of available IOD_SC Descriptors. Number of IOD_BM Descriptors. Provides the number of available IOD_BM Descriptors. Number of P2D_BMK Descriptors. Provides the number of available P2D_BMK Descriptors. Number of P2D_SC Descriptors. Provides the number of available P2D_SC Descriptors Number of P2D_RO Descriptors. Provides the number of available P2D_RO Descriptors. Number of P2D_R Descriptors. Provides the number of available P2D_R Descriptors. Number of P2D_BMO Descriptors. Provides the number of available P2D_BMO Descriptors. Number of P2D_BM Descriptors. Provides the number of available P2D_BM Descriptors. www.national.com 200 Revision 0.8 Geode™ CS5535 GLIU Register Descriptions (Continued) 5.1.3.8 N Outstanding Response (GLIU_NOUT_RESP) MSR Address 51010087h Type RO Reset Value 00000000_00000000h . GLIU_NOUT_RESP Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RSVD 9 8 7 6 5 4 3 2 1 0 GLIU_NOUT_RESP Bit Descriptions Bit 63:0 Name RSVD Description Reserved. Returns 0. 5.1.3.9 Number of Outstanding Write Data (GLIU_NOUT_WDATA) MSR Address 51010088h Type RO Reset Value 00000000_00000000h GLIU_NOUT_WDATA Register Map (RO) 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RSVD 9 8 7 6 5 4 3 2 1 0 GLIU_NOUT_WDATA Bit Descriptions Bit 63:0 Name RSVD Description Reserved. Returns 0. 5.1.3.10 WHO AM I (GLIU_WHOAMI) MSR Address 5101008Bh Type RO Reset Value Configuration Dependent GLIU_WHOAMI Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RSVD 9 8 7 6 5 4 3 2 1 0 GLIU_WHOAMI Bit Descriptions Bit 63:0 Name RSVD Description Reserved. Returns 0. Revision 0.8 201 www.national.com Geode™ CS5535 GLIU Register Descriptions (Continued) 5.1.3.11 Slave Disable (GLIU_SLV_DIS) MSR Address 5101008Ch Type R/W Reset Value 00000000_00000000h GLIU_SLV_DIS Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RSVD 9 8 7 6 5 4 3 2 1 0 GLIU_SLV_DIS Bit Descriptions Bit 63:0 Name RSVD Description Reserved. Write as read. www.national.com 202 Revision 0.8 Geode™ CS5535 GLIU Register Descriptions (Continued) 5.1.3.12 Descriptor Statistic Counters (GLIU_STATISTIC_CNT[x]) Descriptor Statistic Counter 0 (GLIU_STATISTIC_CNT0) MSR Address 510100A0h Type WO Reset Value 00000000_00000000h Descriptor Statistic Counter 1 (GLIU_STATISTIC_CNT1) MSR Address 510100A4h Type WO Reset Value 00000000_00000000h Descriptor Statistic Counter 2 (GLIU_STATISTIC_CNT2) MSR Address 510100A8h Type WO Reset Value 00000000_00000000h These registers work in conjunction with the GLIU_STATISTIC_MASK[x] and the GLIU_STATISTIC_ACTION[x] registers. The counters count ‘hits’ on the P2D and IOD descriptors. The counter behaves as setup in the GLIU_STATISTIC_ACTION[x] register. GLIU_STATISTIC_CNT[x] Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 LOAD_VAL 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 CNT 9 8 7 6 5 4 3 2 1 0 GLIU_STATISTIC_CNT[x] Bit Descriptions Bit 63:32 31:0 Name LOAD_VAL CNT Description Counter Load Value. A value loaded here will be used as the initial Statistics Counter value when a LOAD action occurs or is commanded. Counter Value. These bits provide the current counter value when read. Revision 0.8 203 www.national.com Geode™ CS5535 GLIU Register Descriptions (Continued) 5.1.3.13 Descriptor Statistic Mask (GLIU_STATISTIC_MASK[x]) Descriptor Statistic Mask 0 (GLIU_STATISTIC_MASK0) MSR Address 510100A1h Type R/W Reset Value 00000000_00000000h Descriptor Statistic Mask 1 (GLIU_STATISTIC_MASK1) MSR Address 510100A5h Type R/W Reset Value 00000000_00000000h Descriptor Statistic Mask 2 (GLIU_STATISTIC_MASK2) MSR Address 510100A9h Type R/W Reset Value 00000000_00000000h GLIU_STATISTIC_MASK[x] Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 IOD_MASK 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 P2D_MASK 9 8 7 6 5 4 3 2 1 0 GLIU_STATISTIC_MASK[x] Bit Descriptions Bit 63:32 Name IOD_MASK Description Mask for Hits to each IOD. Hits are determined after the request is arbitrated. A hit is determined by the following logical equation: hit = |(IOD_MASK[n-1:0] & RQ_DESC_HIT[n-1:0] && is_io) | |(P2D_MASK[n-1:0] & RQ_DESC_HIT[n-1:0] && is_mem) 31:0 P2D_MASK Mask for Hits to each P2D. A hit is determined by the following logical equation: hit = |(IOD_MASK[n-1:0] & RQ_DESC_HIT[n-1:0] && is_io) | |(P2D_MASK[n-1:0] & RQ_DESC_HIT[n-1:0] && is_mem) www.national.com 204 Revision 0.8 Geode™ CS5535 GLIU Register Descriptions (Continued) 5.1.3.14 Descriptor Statistic Action (GLIU_STATISTIC_ACTION[x]) Descriptor Statistic Action 0 (GLIU_STATISTIC_ACTION0) MSR Address 510100A2h Type R/W Reset Value 00000000_00000000h Descriptor Statistic Action 1 (GLIU_STATISTIC_ACTION1) MSR Address 510100A6h Type R/W Reset Value 00000000_00000000h Descriptor Statistic Action 2 (GLIU_STATISTIC_ACTION2) MSR Address 510100AAh Type R/W Reset Value 00000000_00000000h GLIU_STATISTIC_ACTION[x] Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RSVD PREDIV WRAP 9 8 7 6 ZERO_ERR 5 ZERO_SMI 4 ALWAYS_DEC 3 HIT_ERR 2 HIT_SMI 1 HIT_DEC 0 HIT_LDEN GLIU_STATISTIC_ACTION[x] Bit Descriptions Bit 63:24 23:8 7 Name RSVD PREDIV WRAP Description Reserved. Write as read. Pre-divider used for ALWAYS_DEC. The pre-divider is free running and extends the depth of the counter. Decrement Counter Beyond Zero and Wrap. 0: Disable wrap; counter stops when it reaches zero. 1: Enable wrap; counter decrements through 0 to all ones. 6 ZERO_ERR Asset AERR on Cnt = 0. Assert AERR (internal GLIU_P_SERR) when STATISTIC_CNT[x] = 0. 0: Disable. 1: Enable. 5 ZERO_SMI Assert ASMI on Cnt = 0. Assert ASMI (internal GLIU_P_ASMI) when STATISTIC_CNT[x] = 0. 0: Disable. 1: Enable. 4 ALWAYS_DEC Always Decrement Counter. If enabled, the counter will decrement on every memory clock, subject to the prescaler value PREDIV (bits [23:8]). Decrementing will continue unless loading is occurring due to another action, or if the counter reaches zero and WRAP is disabled (bit[7]). 0: Disable. 1: Enable. Revision 0.8 205 www.national.com Geode™ CS5535 GLIU Register Descriptions (Continued) GLIU_STATISTIC_ACTION[x] Bit Descriptions (Continued) Bit 3 Name HIT_ERR Description Assert AERR on Descriptor Hit. This bit causes an asynchronous error to be generated when a matching descriptor hit occurs, or not. The descriptor hits are ANDed with the masks and then all ORed together. 0: Disable. 1: Enable. 2 HIT_SMI Assert ASMI on Descriptor Hit. This bit causes an ASMI to be generated when a matching descriptor hit occurs, or not. The descriptor hits are ANDed with the masks and then all ORed together. 0: Disable. 1: Enable. 1 HIT_DEC Decrement Counter on Descriptor Hit. This bit causes the associated counter to decrement when a matching descriptor hit occurs, or not.The descriptor hits are ANDed with the masks and then all ORed together. 0: Disable. 1: Enable. 0 HIT_LDEN Load Counter on Descriptor Hit. This bit causes the associated counter to reload its LOAD_VAL when a matching descriptor hit occurs, or not.The descriptor hits are ANDed with the masks and then all ORed together. 0: Disable. 1: Enable. 5.1.3.15 Request Compare Value (GLIU_RQ_COMP_VAL) MSR Address 510100C0h Type R/W Reset Value 001FFFFF_FFFFFFFFh The RQ Compare Value and the RQ Compare Mask enable traps on specific transactions. A hit to the RQ Compare is determined by hit = (RQ_IN & RQ_COMP_MASK) == RQ_COMP_VAL). A hit can trigger the RQ_COMP error sources when they are enabled. The value is compared only after the packet is arbitrated. GLIU_RQ_COMP_VAL Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD RQ_COMPVAL 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RQ_COMPVAL GLIU_RQ_COMP_VAL Bit Descriptions Bit 63:53 52:0 Name RSVD RQ_COMPVAL Description Reserved. Write as read. Request Packet Value. This is the value compared against the logical bit-wise AND of the incoming request packet and the RQ_COMP_MASK in order to determine a hit. www.national.com 206 Revision 0.8 Geode™ CS5535 GLIU Register Descriptions (Continued) 5.1.3.16 Request Compare Mask (GLIU_RQ_COMP_MASK) MSR Address 510100C1h Type R/W Reset Value 00000000_00000000h The RQ Compare Value and the RQ Compare Mask enable traps on specific transactions. A hit to the RQ Compare is determined by hit = (RQ_IN & RQ_COMP_MASK) == RQ_COMP_VAL). A hit can trigger the RQ_COMP error sources when they are enabled. The value is compared only after the packet is arbitrated. GLIU_RQ_COMP_MASK Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD RQ_COMPMASK 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RQ_COMPMASK GLIU_RQ_COMP_MASK Bit Descriptions Bit 63:53 52:0 Name RSVD RQ_COMPMASK Description Reserved. Write as read. Request Packet Mask. This field is bit-wise logically ANDed with the incoming Request Packet before it is compared to the RQ_COMPVAL. 5.1.3.17 Data Compare Value Low (GLIU_DA_COMP_VAL_LO) MSR Address 510100D0h Type R/W Reset Value 00001FFF_FFFFFFFFh The DA Compare Value and the DA Compare Mask enable traps on specific transactions. A hit to the DA Compare is determined by hit = (DA_IN & DA_COMP_MASK) == DA_COMP_VAL). A hit can trigger the DA_CMP error sources when they are enabled. The value is compared only after the packet is arbitrated. GLIU_DA_COMP_VAL_LO Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DALO_COMPVAL 9 DALO_COMPVAL 8 7 6 5 4 3 2 1 0 GLIU_DA_COMP_VAL_LO Bit Descriptions Bit 63:45 44:0 Name RSVD DALO_COMPVAL Description Reserved. Write as read. Data Packet Compare Value [44:0]. This field forms the lower portion of the data value that is compared to the logical bit-wise AND of the incoming data value and the data value compare mask in order to determine a hit. The “HI” and “LO” portions of the incoming data, the compare value, and the compare mask, are assembled into complete bit patterns before these operations occur. Revision 0.8 207 www.national.com Geode™ CS5535 GLIU Register Descriptions (Continued) 5.1.3.18 Data Compare Value High (GLIU_DA_COMP_VAL_HI) MSR Address 510100D1h Type R/W Reset Value 0000000F_FFFFFFFFh The DA Compare Value and the DA Compare Mask enable traps on specific transactions. A hit to the DA Compare is determined by hit = (DA_IN & DA_COMP_MASK) == DA_COMP_VAL). A hit can trigger the DA_CMP error sources when they are enabled. The value is compared only after the packet is arbitrated. GLIU_DA_COMP_VAL_HI Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DAHI_COMPVAL 9 8 7 6 5 4 3 DAHI_ COMPVAL 2 1 0 GLIU_DA_COMP_VAL_HI Bit Descriptions Bit 63:36 35:0 Name RSVD DAHI_ COMPVAL Description Reserved. Write as read. DA Packet Compare Value [80:45]. This field forms the upper portion of the data value that is compared to the logical bit-wise AND of the incoming data value and the data value compare mask in order to determine a hit. The “HI” and “LO” portions of the incoming data, the compare value, and the compare mask, are assembled into complete bit patterns before these operations occur. 5.1.3.19 Data Compare Mask Low (GLIU_DA_COMP_MASK_LO) MSR Address 510100D2h Type R/W Reset Value 00000000_00000000h The DA Compare Value and the DA Compare Mask enable traps on specific transactions. A hit to the DA Compare is determined by hit = (DA_IN & DA_COMP_MASK) == DA_COMP_VAL). A hit can trigger the DA_COMP error sources when they are enabled. The value is compared only after the packet is arbitrated. GLIU_DA_COMP_MASK_LO Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DALO_COMPMASK 9 DALO_COMPMASK 8 7 6 5 4 3 2 1 0 GLIU_DA_COMP_MASK_LO Bit Descriptions Bit 63:45 44:0 Name RSVD DALO_COMPMASK Description Reserved. Write as read. Data Packet Compare Value [44:0]. This field is forms the lower portion of the data COMPMASK value, that is then bit-wise logically ANDed with the incoming data value before it is compared to the DA_COMPVAL. The “HI” and “LO” portions of the incoming data, the compare value, and the compare mask, are assembled into complete bit patterns before these operations occur. www.national.com 208 Revision 0.8 Geode™ CS5535 GLIU Register Descriptions (Continued) 5.1.3.20 Data Compare Mask High (GLIU_DA_COMP_MASK_HI) MSR Address 510100D3h Type R/W Reset Value 00000000_00000000h GLIU_DA_COMP_MASK_HI Register 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DAHI_COMPMASK 9 8 7 6 5 4 DAHI_ COMPMASK 3 2 1 0 GLIU_DA_COMP_MASK_HI Bit Descriptions Bit 63:36 35:0 Name RSVD DAHI_COMPMASK Description Reserved. Write as read. DA Packet Compare Mask [80:45]. This field is forms the upper portion of the data COMPMASK value that is then bit-wise logically ANDed with the incoming data value before it is compared to the DA_COMP_VAL.The “HI” and “LO” portions of the incoming data (the compare value and compare mask) are assembled into complete bit patterns before these operations occur. Revision 0.8 209 www.national.com Geode™ CS5535 GLIU Register Descriptions (Continued) 5.1.4 5.1.4.1 IOD Descriptor MSRs IOD Base Mask Descriptors (GLIU_IOD_BM[x]) IOD Base Mask 5 (GLIU_IOD_BM5) MSR Address 510100E5h Type R/W Reset Value 000000FF_FFF00000h IOD Base Mask 6 (GLIU_IOD_BM6) MSR Address 510100E6h Type R/W Reset Value 000000FF_FFF00000h IOD Base Mask 7 (GLIU_IOD_BM7) MSR Address 510100E7h Type R/W Reset Value 000000FF_FFF00000h IOD Base Mask 8 (GLIU_IOD_BM8) MSR Address 510100E8h Type R/W Reset Value 000000FF_FFF00000h IOD Base Mask 9 (GLIU_IOD_BM9) MSR Address 510100E9h Type R/W Reset Value 000000FF_FFF00000h IOD Base Mask 0 (GLIU_IOD_BM0) MSR Address 510100E0h Type R/W Reset Value 60000000_1F0FFFF0h IOD Base Mask 1 (GLIU_IOD_BM1) MSR Address 510100E1h Type R/W Reset Value 000000FF_FFF00000h IOD Base Mask 2 (GLIU_IOD_BM2) MSR Address 510100E2h Type R/W Reset Value 000000FF_FFF00000h IOD Base Mask 3 (GLIU_IOD_BM3) MSR Address 510100E3h Type R/W Reset Value 000000FF_FFF00000h IOD Base Mask 4 (GLIU_IOD_BM4) MSR Address 510100E4h Type R/W Reset Value 000000FF_FFF00000h GLIU_IOD_BM[x] Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 ICMP_BIZ_BM IDID_BM RSVD IBASE 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 IBASE_BM 9 8 7 6 5 4 3 2 1 0 IMASK_BM GLIU_IOD_BM[x] Bit Descriptions Bit 63:61 Name IDID_BM Description I/O Descriptor Destination ID. These bits define which port to route the request to if it is a hit based on the other settings in this register. 000: Port 0 (GLIU) 001: Port 1 (GLPCI_SB) 010: Port 2 (USBC2) 011: Port 3 (ATAC) 60 ICMP_BIZ_BM Compare BIZZARO Flag. 0: Consider only transactions whose BIZZARO flag is low as a potentially valid address hit. A low BIZZARO flag indicates a normal transaction cycle such as a memory or I/O. 1: Consider only transactions whose BIZZARO flag is high as a potentially valid address hit. A high BIZZARO flag indicates a ‘special’ transaction, such as a PCI Shutdown or Halt cycle. 100: Port 4 (DD) 101: Port 5 (ACC) 110: Port 6 (USBC1) 111: Port 7 (GLCP) www.national.com 210 Revision 0.8 Geode™ CS5535 GLIU Register Descriptions (Continued) GLIU_IOD_BM[x] Bit Descriptions (Continued) Bit 59:40 39:20 Name RSVD IBASE_BM Description Reserved. Write as read. Physical I/O Address Base.These bits form the matching value against which the masked value of the physical address, bits [31:12] are directly compared. If a match is found, then a hit is declared, depending on the setting of the BIZZARO flag comparator. Physical I/O Address Mask. These bits are used to mask address bits [31:12] for the purposes of this hit detection. 19:0 IMASK_BM 5.1.4.2 IOD Swiss Cheese Descriptors (GLIU_IOD_SC[x]) IOD Swiss Cheese 4 (GLIU_IOD_SC4) MSR Address 510100EEh Type R/W Reset Value 00000000_00000000h IOD Swiss Cheese 5 (GLIU_IOD_SC5) MSR Address 510100EFh Type R/W Reset Value 00000000_00000000h IOD Swiss Cheese 6 (GLIU_IOD_SC6) MSR Address 510100F0h Type R/W Reset Value 00000000_00000000h IOD Swiss Cheese 7 (GLIU_IOD_SC7) MSR Address 510100F1h Type R/W Reset Value 00000000_00000000h IOD Swiss Cheese 0 (GLIU_IOD_SC0) MSR Address 510100EAh Type R/W Reset Value 60000000_403003F0h IOD Swiss Cheese 1 (GLIU_IOD_SC1) MSR Address 510100EBh Type R/W Reset Value 00000000_00000000h IOD Swiss Cheese 2 (GLIU_IOD_SC2) MSR Address 510100ECh Type R/W Reset Value 00000000_00000000h IOD Swiss Cheese 3 (GLIU_IOD_SC3) MSR Address 510100EDh Type R/W Reset Value 00000000_00000000h Each of these eight descriptors checks that the physical address supplied by the device’s request on the address bits is equal to the IBASE_SC field of descriptor register bits and that the enable write or read conditions given by the descriptor register fields WEN and REN respectively matches the request type and enable fields given on the physical address bits of the device’s request. If the above matches, then the descriptor has a hit condition and routes the received address to the programmed destination ID, IDID1_SC field of the descriptor register bits. GLIU_IOD_SC[x] Register 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 ICMP_BIZ_SC IDID_SC RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 WEN_SC REN_SC EN_SC RSVD IBASE_SC 9 8 7 6 5 4 3 2 1 RSVD 0 Revision 0.8 211 www.national.com Geode™ CS5535 GLIU Register Descriptions (Continued) GLIU_IOD_SC Bit Descriptions Bit 63:61 Name IDID_SC Description I/O Descriptor Destination ID. Encoded port number of the destination of addresses which produce a hit based on the other fields in this descriptor. 000: Port 0 (GLIU) 001: Port 1 (GLPCI_SB) 010: Port 2 (USBC2) 011: Port 3 (ATAC) 60 ICMP_BIZ_SC 100: Port 4 (DD) 101: Port 5 (ACC) 110: Port 6 (USBC1) 111: Port 7 (GLCP) Compare BIZZARO Flag. Used to check that the BIZZARO flag of the request is equal to the PICMP_BIZ_SC bit (this bit). If a match does not occur, then the incoming request cannot generate a hit. The BIZZARO flag, if set in the incoming request, signifies a “special’ cycle such as a PCI Shutdown or Halt. Reserved. Write as read. Enable for Hits to IDID_SC else SUBP. bit 0, if set, hit on I/O Address Base plus 0. bit 1, if set, hit on I/O Address Base plus 1. : bit 7, if set, hit on I/O Address Base plus 7. Descriptor Hits IDID_SC on Write Request Types else SUBP. If set, causes the incoming request to be routed to the port specified in IDID_SC if the incoming request is a WRITE type. Descriptors Hit IDID_SC on Read Request Types else SUBP. If set, causes the incoming request to be routed to the port specified in IDID_SC if the incoming request is a READ type. I/O Address Base. This field forms the basis of comparison with the incoming checks that the physical address supplied by the device’s request on address bits [31:18] are equal to the PBASE field of descriptor register bits [13:0] Reserved. Write as read. 59:32 31:24 RSVD EN_SC 21 WEN_SC 20 REN_SC 19:0 IBASE_SC 2:0 RSVD www.national.com 212 Revision 0.8 Geode™ CS5535 5.2 GEODELINK PCI SOUTH BRIDGE REGISTER DESCRIPTIONS Section 5.2.3 "PCI Configuration Registers" on page 225 for details. The PCI configuration registers can only be accessed through the PCI interface and include: • The first 16 bytes of standard PCI configuration registers. • MSR access registers: — PMCTRL — PMADDR — PMDATA0 — PMDATA1 Tables 5-5 through 5-7 are register summary tables that include reset values and page references where the bit descriptions are provided. The GeodeLink PCI South Bridge (GLPCI_SB) register set consists of: • Standard GeodeLink Device MSRs • GLPCI_SB Specific MSRs • PCI Configuration Registers The MSRs (both Standard and GLPCI_SB Specific) are accessed via the RDMSR and WRMSR processor instructions. The MSR address is derived from the perspective of the CPU Core. See Section 3.2 "CS5535 MSR Addressing" on page 53 for more details on MSR addressing. Additionally, all GLPCI_SB Specific MSRs can be accessed through both the PCI and GLIU interfaces. See Table 5-5. Standard GeodeLink Device MSRs Summary MSR Address 51000000h 51000001h 51000002h 51000003h 51000004h 51000005h Type RO R/W R/W R/W R/W R/W Register GeodeLink Device Capabilities MSR (GLPCI_GLD_MSR_CAP) GeodeLink Device Master Configuration MSR (GLPCI_GLD_MSR_CONFIG) GeodeLink Device SMI MSR (GLPCI_GLD_MSR_SMI) GeodeLink Device Error MSR (GLPCI_GLD_MSR_ERROR) GeodeLink Device Power Management MSR (GLPCI_GLD_MSR_PM) GeodeLink Device Diagnostic MSR (GLPCI_GLD_MSR_DIAG) Reset Value 00000000_002051xxh 00000000_00000000h 00000000_00000000h 00000000_00000000h 00000000_00000000h 00000000_00000000h Reference Page 214 Page 215 Page 215 Page 216 Page 218 Page 219 Table 5-6. GLPCI_SB Specific MSRs Summary MSR Address 51000010h 51000020h 51000021h 51000022h 51000023h 51000024h 51000025h 51000026h 51000027h 51000028h 51000029h 5100002Ah 5100002Bh 5100002Ch Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Register Global Control (GLPCI_CTRL) Region 0 Configuration (GLPCI_R0) Region 1 Configuration (GLPCI_R1) Region 2 Configuration (GLPCI_R2) Region 3 Configuration (GLPCI_R3) Region 4 Configuration (GLPCI_R4) Region 5 Configuration (GLPCI_R5) Region 6 Configuration (GLPCI_R6) Region 7 Configuration (GLPCI_R7) Region 8 Configuration (GLPCI_R8) Region 9 Configuration (GLPCI_R9) Region 10 Configuration (GLPCI_R10) Region 11 Configuration (GLPCI_R11) Region 12 Configuration (GLPCI_R12) Reset Value 44000030_00000003h 00000000_00000000h 00000000_00000000h 00000000_00000000h 00000000_00000000h 00000000_00000000h 00000000_00000000h 00000000_00000000h 00000000_00000000h 00000000_00000000h 00000000_00000000h 00000000_00000000h 00000000_00000000h 00000000_00000000h Reference Page 219 Page 223 Page 223 Page 223 Page 223 Page 223 Page 223 Page 223 Page 223 Page 223 Page 223 Page 223 Page 223 Page 223 Revision 0.8 213 www.national.com Geode™ CS5535 GLPCI_SB Register Descriptions (Continued) Table 5-6. GLPCI_SB Specific MSRs Summary MSR Address 5100002Dh 5100002Eh 5100002Fh 51000030h 51000031h 51000032h 51000033h Type R/W R/W R/W RO RO RO RO Register Region 13 Configuration (GLPCI_R13) Region 14 Configuration (GLPCI_R14) Region 15 Configuration (GLPCI_R15) PCI Configuration Space Header Byte 0-3 (GLPCI_PCIHEAD_BYTE0-3) PCI Configuration Space Header Byte 4-7 (GLPCI_PCIHEAD_BYTE4-7) PCI Configuration Space Header Byte 8-B (GLPCI_PCIHEAD_BYTE8-B) PCI Configuration Space Header Byte C-F (GLPCI_PCIHEAD_BYTEC-F) Reset Value 00000000_00000000h 00000000_00000000h 00000000_00000000h 00000000_002A100Bh 00000000_00000000h 00000000_00000000h 00000000_00000000h Reference Page 223 Page 223 Page 223 Page 224 Page 224 Page 224 Page 224 Table 5-7. PCI Configuration Registers Index 00h 04h 08h 0Ch F0h F4h F8h FCh Type RO RO RO RO R/W R/W R/W R/W Width (Bits) 32 (Note 1) 32 (Note 1) 32 (Note 1) 32 (Note 1) 32 32 32 32 Name PCI Configuration Space Header Byte 0-3 (GLPCI_PCI_HEAD_BYTE0-3) PCI Configuration Space Header Byte 4-7 (GLPCI_PCI_HEAD_BYTE4-7) PCI Configuration Space Header Byte 8-B (GLPCI_PCI_HEAD_BYTE8-B) PCI Configuration Space Header Byte C-F (GLPCI_PCI_HEAD_BYTEC-F) PCI MSR Control (GLPCI_PMCTRL) PCI MSR Address (GLPCI_PMADDR) PCI MSR Data 0 (GLPCI_PMDATA0) PCI MSR Data 1 (GLPCI_PMDATA1) Reset Value 002A100Bh 00000000h FF0000xxh 00000000h 00000001h 00000000h 00000000h 00000000h Reference Page 225 Page 226 Page 226 Page 227 Page 227 Page 228 Page 228 Page 229 Note 1. Read address bits [1:0] are ignored and taken as 00. 5.2.1 Standard GeodeLink Device MSRs 5.2.1.1 GeodeLink Device Capabilities MSR (GLPCI_GLD_MSR_CAP) MSR Address 51000000h Type RO Reset Value 00000000_002051xxh GLPCI_GLD_MSR_CAP Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RSVD DEV_ID 9 8 7 6 5 4 3 2 1 0 REV_ID www.national.com 214 Revision 0.8 Geode™ CS5535 GLPCI_SB Register Descriptions (Continued) GLPCI_GLD_MSR_CAP Bit Descriptions Bit 63:24 23:8 7:0 Name RSVD DEV_ID REV_ID Description Reserved. Reads as 0. Device ID. Identifies module (2051h). Revision ID. Identifies module revision. See CS5535 I/O Companion Device Errata document for value. 5.2.1.2 GeodeLink Device Master Configuration MSR (GLPCI_GLD_MSR_CONFIG) MSR Address 51000001h Type R/W Reset Value 00000000_00000000h GLCPI_GLD_MSR_CONFIG Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RSVD 9 8 7 6 5 PRI 4 3 RSVD 2 1 PID 0 GLPCI_GLD_MSR_CONFIG Bit Descriptions Bit 63:7 6:4 3 2:0 Name RSVD (RO) PRI RSVD (RO) PID Description Reserved (Read Only). Returns 0. Priority Level. Always write 0. Reserved (Read Only). Returns 0. Priority ID. Always write 0. 5.2.1.3 GeodeLink Device SMI MSR (GLPCI_GLD_MSR_SMI) MSR Address 51000002h Type R/W Reset Value 00000000_00000000h The flags are set by internal conditions. The internal conditions are enabled if the EN bit is 1. Reading the FLAG bit returns the value; writing 1 clears the flag; writing 0 has no effect. (See Section 3.8.3 "MSR Address 2: SMI Control" on page 67 for further SMI/ASMI generation details.) GLPCI_GLD_MSR_SMI Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 EXCEP_ASMI_FLAG SYSE_ASMI_FLAG SSMI_ASMI_FLAG MAR_ASMI_FLAG PAR_ASMI_FLAG TAR_ASMI_FLAG TAS_ASMI_FLAG RSVD 9 8 7 6 TAS_ASMI_EN 5 PAR_ASMI_EN 4 SYSE_ASMI_EN 3 EXCEP_ASMI_EN 2 SSMI_ASMI_EN 1 TAR_ASMI_EN 0 MAR_ASMI_EN RSVD Revision 0.8 215 www.national.com Geode™ CS5535 GLPCI_SB Register Descriptions (Continued) GLPCI_GLD_MSR_SMI Bit Descriptions Bit 63:23 22 Name RSVD (RO) TAS_ASMI_ FLAG PAR_ASMI_ FLAG SYSE_ASMI_ FLAG EXCEP_ASMI_ FLAG SSMI_ASMI_ FLAG TAR_ASMI_ FLAG MAR_ASMI_ FLAG RSVD (RO) TAS_ASMI_EN PAR_ASMI_EN SYSE_ASMI_ EN EXCEP_ASMI_ EN SSMI_EN TAR_ASMI_EN MAR_ASMI_EN Description Reserved (Read Only). Returns 0. Target Abort Signaled ASMI Flag. If high, records that an ASMI was generated due the signaling of a target abort on the PCI bus. Write 1 to clear; writing 0 has no effect. TA_ASMI_EN (bit 6) must be high to generate ASMI and set flag. Parity Error ASMI Flag. If high, records that an ASMI was generated due to the detection of a PCI bus parity error. Write 1 to clear; writing 0 has no effect. PAR_ASMI_EN (bit 5) must be high to generate ASMI and set flag. System Error ASMI Flag. If high, records that an ASMI was generated due to the detection of a PCI bus system error. Write 1 to clear; writing 0 has no effect. SYSE_ASMI_EN (bit 4) must be high to generate ASMI and set flag. Exception Bit Flag. If high, records that an ASMI was generated due to the EXCEP bit being set in the received GLIU read or write response packet. Write 1 to clear; writing 0 has no effect. EXCEP_ASMI_EN (bit 3) must be set to enable this flag. SSMI ASMI Flag. If high, records that an ASMI was generated due to the SSMI bit being set in the received GLIU read or write response packet. Write 1 to clear; writing 0 has no effect. SSMI_ASMI_EN (bit 2) must be set to enable this flag. Target Abort Received ASMI Flag. If high, records that an ASMI was generated due to the reception of a target abort on the PCI bus. Write 1 to clear; writing 0 has no effect. TAR_ASMI_EN (bit 1) must be high to generate ASMI and set flag. Master Abort Received ASMI Flag. If high, records that an ASMI was generated due to the reception of a master abort on the PCI bus. Write 1 to clear; writing 0 has no effect. MAR_ASMI_EN (bit 0) be high to generate ASMI and set flag. Reserved (Read Only). Returns 0. Target Abort Signaled ASMI Enable. Write 1 to enable TAS_ASMI_FLAG (bit 22) and to allow the event to generate an ASMI. Parity Error ASMI Enable. Write 1 to enable PAR_ASMI_FLAG (bit 21) and to allow the event to generate an ASMI. System Error SMI Enable. Write 1 to enable SYSE_ASMI_FLAG (bit 20) and to allow the event to generate an ASMI. Exception Bit Enable. Write 1 to enable EXCEP_ASMI_FLAG (bit 19) and to allow the event. SSMI Enable. Write 1 to enable SSMI_ASMI_FLAG bit (bit 18) and to allow the event. Target Abort Received ASMI Enable. Write 1 to enable TAR_ASMI_FLAG (bit 17) and to allow the event to generate an ASMI. Master Abort Received ASMI Enable. Write 1 to enable MAR_ASMI_FLAG (bit 16) and to allow the event to generate an ASMI. 21 20 19 18 17 16 15:7 6 5 4 3 2 1 0 5.2.1.4 GeodeLink Device Error MSR (GLPCI_GLD_MSR_ERROR) MSR Address 51000003h Type R/W Reset Value 00000000_00000000h The flags are set by internal conditions. The internal conditions are enabled if the EN bit is 1. Reading the FLAG bit returns the value; writing 1 clears the flag; writing 0 has no effect. (See Section 3.8.4 "MSR Address 3: Error Control" on page 71 for further details.) www.national.com 216 Revision 0.8 Geode™ CS5535 GLPCI_SB Register Descriptions (Continued) GLPCI_GLD_MSR_ERROR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 EXCEP_ERR_FLAG SYSE_ERR_FLAG PARE_ERR_FLAG MAR_ERR_FLAG TAR_ERR_FLAG TAS_ERR_FLAG RSVD RSVD TAS_ERR_EN 9 8 7 6 5 PARE_ERR_EN 4 SYSE_ERR_EN 3 EXCEP_ERR_EN 2 1 TAR_ERR_EN 0 MAR_ERR_EN GLPCI_GLD_MSR_ERROR Bit Descriptions Bit 63:23 22 Name RSVD (RO) TAS_ERR_ FLAG PARE_ERR_ FLAG SYSE_ERR_ FLAG EXCEP_ERR_ FLAG RSVD (RO) TAR_ERR_ FLAG MAR_ERR_ FLAG RSVD (RO) TAS_ERR_EN PARE_ERR_EN SYSE_ERR_EN EXCEP_ERR_ EN RSVD (RO) TAR_ERR_EN MAR_ERR_EN Description Reserved (Read Only). Returns 0. Target Abort Signaled Error Flag. If high, records that an ERR was generated due to signaling of a target abort on the PCI bus. Write 1 to clear; writing 0 has no effect. TAS_ERR_EN (bit 6) must be set to enable this event and set flag. Parity Error Error Flag. If high, records that an ERR was generated due to the detection of a PCI bus parity error. Write 1 to clear; writing 0 has no effect. PARE_ERR_EN (bit 5) must be set to enable this event and set flag. System Error Error Flag. If high, records that an ERR was generated due to the detection of a PCI bus system error. Write 1 to clear; writing 0 has no effect. SYSE_ERR_EN (bit 4) must be set to enable this event and set flag. Exception Bit Error Flag. If high, records that the EXCP bit in the received GLIU read or write response packet is set. Write 1 to clear. EXCEP_ERR_EN (bit 3) must be set to enable this event and set flag. Reserved (Read Only). Returns 0. Target Abort Received Error Flag. If high, records that an ERR was generated due to the reception of a target abort on the PCI bus. Write 1 to clear; writing 0 has no effect. TAR_ERR_EN (bit 1) must be set to enable this event and set flag. Master Abort Received Error Flag. If high, records that an ERR was generated due to the reception of a master abort on the PCI bus. Write 1 to clear; writing 0 has no effect. MAR_ERR_EN (bit 0) must be set to enable this event and set flag. Reserved (Read Only). Returns 0. Target Abort Signaled Error Enable. Write 1 to enable TAS_ERR_FLAG (bit 22) and to allow the event to generate an ERR. Parity Error Error Enable. Write 1 to enable PAR_ERR_FLAG (bit 21) and to allow the event to generate an ERR. System Error Error Enable. Write 1 to enable SYSE_ERR_FLAG (bit 20) and to allow the event to generate an ERR. Exception Bit Error Enable. Write 1 to enable EXCEP_ERR_FLAG (bit 19) and to allow the event to generate an ERR. Reserved (Read Only). Returns 0. Target Abort Received Error Enable. Write 1 to enable TAR_ERR_FLAG (bit 17) and to allow the event to generate an ERR. Master Abort Received Enable. Write 1 to enable MAR_ERR_FLAG (bit 16) and to allow the event to generate an ERR. 21 20 19 18 17 16 15:7 6 5 4 3 2 1 0 Revision 0.8 RSVD 217 www.national.com RSVD Geode™ CS5535 GLPCI_SB Register Descriptions (Continued) 5.2.1.5 GeodeLink Device Power Management MSR (GLPCI_GLD_MSR_PM) MSR Address 51000004h Type R/W Reset Value 00000000_00000000h CLPCI_GLD_MSR_PM Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD IO MODEA 9 RSVD 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RSVD P P P MODE2 MODE1 MODE0 GLPCI_GLD_MSR_PM Bit Descriptions Bit 63:50 49:48 Name RSVD (RO) IOMODEA Description Reserved (Read Only). Returns 0. I/O Mode A Control. These bits determine how the associated PCI inputs and outputs will behave when the PMC asserts two internal signals that are controlled by PMS I/O Offset 20h and 0Ch. The list of affected signals is given in Table 3-11 "Sleep Driven PCI Signals" on page 71. 00: No gating of I/O cells during a Sleep sequence (Default). 01: During a power management Sleep sequence, force inputs to their non-asserted state when PM_IN_SLPCTL is enabled. 10: During a power management Sleep sequence, force inputs to their non-asserted state when PM_IN_SLPCTL is enabled, and park (force) outputs low when PM_OUT_SLPCTL is enabled. 11: Immediately and unconditionally, force inputs to their not asserted state, and park (force) outputs low. 47:35 34:32 31:6 5:4 RSVD (RO) RSVD RSVD (RO) PMODE2 Reserved (Read Only). Returns 0. Reserved. Write as read. Reserved (Read Only). Returns 0. Power Mode 2. Power mode for PCI-fast clock domain. 00: Disable clock gating. Clocks are always on. 01: Enable active hardware clock gating. Clock goes off whenever this module’s circuits are not busy. 10: Reserved. 11: Reserved. 3:2 PMODE1 Power Mode 1. Power mode for PCI clock domain. 00: Disable clock gating. Clocks are always on. 01: Enable active hardware clock gating. Clock goes off whenever this module’s circuits are not busy. 10: Reserved. 11: Reserved. www.national.com 218 Revision 0.8 Geode™ CS5535 GLPCI_SB Register Descriptions (Continued) GLPCI_GLD_MSR_PM Bit Descriptions (Continued) Bit 1:0 Name PMODE0 Description Power Mode 0. Power mode for GLIU clock domain. 00: Disable clock gating. Clocks are always on. 01: Enable active hardware clock gating. Clock goes off whenever this module’s circuits are not busy. 10: Reserved. 11: Reserved. 5.2.1.6 GeodeLink Device Diagnostic MSR (GLPCI_GLD_MSR_DIAG) MSR Address 51000005h Type R/W Reset Value 00000000_00000000h This register is reserved for internal use by National and should not be written to. 5.2.2 GLPCI_SB Specific MSRs 5.2.2.1 Global Control (GLPCI_CTRL) MSR Address 51000010h Type R/W Reset Value 44000030_00000003h GLPCI_CTRL Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 SLTO FTH RTH RSVD RTL RSVD ILTO 9 HCD 8 IOED 7 6 RSVD LAT 5 4 3 0 2 OD 0 1 IE 0 0 ME 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 SDOFF RPIDE PPIDE PSIDE RDHP RSVD LRH RSVD SUS FPIDE LEGACT CISM GLPCI_CTRL Bit Descriptions Bit 63:60 Name FTH IB/OB IB Description In-Bound Flush Threshold. Controls the timing for requesting new read data while concurrently flushing previously prefetched, stale read data. While flushing stale data, if the number of prefetched 64-bit WORDs reaches this level, then a new read request is made. In-Bound Read Threshold. Controls the timing for prefetching read data. If the number of prefetched 32-bit WORDs is decremented and reaches this threshold, a subsequent GLIU request is generated to fetch the next cache-line of read data. Reserved (Read Only). Returns 0. Retry Transaction Limit. Limits the number of out-bound retries. If a target signals retry indefinitely the PCI interface may be configured to abort the failing out-bound request. 000: No limit. 001: 8 retries. 010: 16 retries. 011: 32 retries. 100: 64 retries. 101: 128 retries. 110: 256 retries. 111: 512 retries. 59:56 RTH IB 55:52 51:49 RSVD (RO) RTL --OB Revision 0.8 219 www.national.com Geode™ CS5535 GLPCI_SB Register Descriptions (Continued) GLPCI_CTRL Bit Descriptions (Continued) Bit 48:43 42 Name RSVD (RO) SLTO IB/OB --IB Description Reserved (Read Only). Returns 0. Subsequent Latency Time-Out Select. Specifies the subsequent target latency timeout limit. If, within a burst, the GLPCI_SB module does not respond with the configured number of clock edges the PCI interface terminates the PCI bus cycle. 0: 8 PCI clock edges. 1: 4 PCI clock edges. 41:40 ILTO IB Initial Latency Time-out Select. Specifies the initial target latency time-out limit for the PCI interface. If the GLPCI_SB module does not respond with the first data phase within the configured number of clock edges the PCI interface terminates the PCI bus cycle. 00: 32 PCI clock edges. 01: 16 PCI clock edges. 39:35 34:32 31:24 23:21 LAT 0 (RO) RSVD (RO) SUS IB/OB IB/OB --IB/OB 10: 8 PCI clock edges. 11: 4 PCI clock edges. PCI Usage Timer. Usage time-out value for limiting bus tenure. Constant 0 (Read Only). The three least significant bits of the PCI latency timer field are fixed as zeros. These bits are not used as part of the PCI latency timer comparison. Reserved (Read Only). Returns 0. Busy Sustain. Controls the sustain time for keeping the clocks running after the internal busy signals indicate that the clocks may be gated. 000: No sustain. 001: 4 clock cycles. 010: 8 clock cycles. 011: 16 clock cycles. 100: 32 clock cycles. 101: 64 clock cycles. 110: 128 clock cycles. 111: 256 clock cycles. 20 19:18 RSVD (RO) FPIDE --IB Reserved (Read Only). Returns 0. Prefetch Primary IDE. If these bits are set, I/O reads to address 1F0h conform to a prefetching behavior. Under this mode, the GLPCI_SB issues GLIU Read Request Packets for this specific address before receiving a request on the PCI bus for it. When IDE prefetch is enabled, all PCI accesses to 1F0h must be DWORDs; that is, 4 bytes. This setting can only be changed between PIO operations. 00: Off. (Default) 01: At “beginning” initialize pipeline with two read requests. 10: At “beginning” initialize pipeline with three read requests. 11: Reserved. The prefetch only applies if the current command is "read". The current command is assumed from the last write to IDE Command Register at 1F7h. The following commands are considered "reads": Read sectors - 20h Read multiple - C4h Read buffer - E4h Prefetch does not cross sector boundaries; that is, 512-byte boundaries. Any prefetched data is discarded and the “boundary” set to 0 on any write to 1F7h. 17 PPIDE IB Post Primary IDE. Defaults to 0. If this bit is set, I/O writes to address 1F0h are posted; that is, the “send response” flag is not set in the GLIU Write Request Packet. Effectively, an I/O write to this specific address is posted just like memory writes are posted. When IDE posting is enabled, single and double WORD writes may be mixed without restriction. www.national.com 220 Revision 0.8 Geode™ CS5535 GLPCI_SB Register Descriptions (Continued) GLPCI_CTRL Bit Descriptions (Continued) Bit 16 Name LRH IB/OB IB Description Legacy I/O Retry/Hold. 0: Legacy I/O retry. 1: Legacy I/O hold. Regardless of the above settings an I/O read or write to 1F0h always causes a retry if data can not be immediately transferred. 15 RDHP IB Reject DMA High Page. Controls the decoding of I/O range associated with the DMA High Page registers (480h-48Fh). 0: Considered part of legacy I/O. 1: Subtractive decode. 14 RSIDE IB Reject Secondary IDE. Controls the decoding of I/O range associated with Secondary IDE address of 170h-177h and 376h. 0: Considered part of legacy I/O. 1: Subtractive decode. 13 RPIDE IB Reject Primary IDE. Controls the decoding of I/O range associated with Primary IDE address of 1F0h-1F7h and 3F6h. 0: Considered part of legacy I/O. 1: Subtractive decode. 12:11 LEGACT IB Legacy I/O Space Active Decode. 00: Subtractive decode (claim on fourth clock). 01: Slow decode (claim on third clock). 10: Medium decode (Claim on second clock). 11: Reserved (implemented as medium decode and returned 10 when read). 10 SDOFF OB Non Legacy Subtractive Decode Off. 0: Subtractive decode enabled. 1: Subtractive decode disabled. 9 HCD IB Hold for CIS Transfer Disable. 0: Hold for CIS transfer enabled. 1: Hold for CIS transfer disabled. 8 IOED IB I/O Addressing Error Checking Disable. 0: I/O addressing error checking enabled. 1: I/O addressing error checking disabled. 7:5 4:3 RSVD (RO) CISM --IB/OB Reserved (Read Only). Returns 0. CIS Mode. 00: Mode A (Default). Not used in normal operation. 01: Mode B. Not used in normal operation. 10: Mode C. Used in normal operation. 11: Reserved. See Section 4.2.14 "CPU Interface Serial (CIS)" on page 79 for details regarding operation modes. 2 OD OB Out-Bound Request Disable. 0: Out-bound request enabled. 1: Out-bound request disabled. When an out-bound request is disabled, all outstanding out-bound requests are serviced before a read response packet with SSMI bit and all data bits cleared and EXCEP bit set is returned. Revision 0.8 221 www.national.com Geode™ CS5535 GLPCI_SB Register Descriptions (Continued) GLPCI_CTRL Bit Descriptions (Continued) Bit 1 Name IE IB/OB IB Description I/O Enable. Enable handling of in-bound I/O transactions from PCI. When set to 1 the PCI interface accepts all in-bound I/O transactions from PCI. This mode is only intended for design verification purposes. When cleared to 0 no in-bound I/O transactions are accepted. Memory Enable. Enable handling of in-bound memory access transaction from PCI. When cleared to 0, the PCI interface does not accept any in-bound memory transactions from the PCI bus. 0 ME IB www.national.com 222 Revision 0.8 Geode™ CS5535 GLPCI_SB Register Descriptions (Continued) 5.2.2.2 Region 0-15 Configuration MSRs (GLPCI_R[x]) Region 8 Configuration (GLPCI_R8) MSR Address 51000028h Type R/W Reset Value 00000000_00000000h Region 9 Configuration (GLPCI_R9) MSR Address 51000029h Type R/W Reset Value 00000000_00000000h Region 10 Configuration (GLPCI_R10) MSR Address 5100002Ah Type R/W Reset Value 00000000_00000000h Region 11 Configuration (GLPCI_R11) MSR Address 5100002Bh Type R/W Reset Value 00000000_00000000h Region 12 Configuration (GLPCI_R12) MSR Address 5100002Ch Type R/W Reset Value 00000000_00000000h Region 13 Configuration (GLPCI_R13) MSR Address 5100002Dh Type R/W Reset Value 00000000_00000000h Region 14 Configuration (GLPCI_R14) MSR Address 5100002Eh Type R/W Reset Value 00000000_00000000h Region 15 Configuration (GLPCI_R15) MSR Address 5100002Fh Type R/W Reset Value 00000000_00000000h Region 0 Configuration (GLPCI_R0) MSR Address 51000020h Type R/W Reset Value 00000000_00000000h Region 1 Configuration (GLPCI_R1) MSR Address 51000021h Type R/W Reset Value 00000000_00000000h Region 2 Configuration (GLPCI_R2) MSR Address 51000022h Type R/W Reset Value 00000000_00000000h Region 3 Configuration (GLPCI_R3) MSR Address 51000023h Type R/W Reset Value 00000000_00000000h Region 4 Configuration (GLPCI_R4) MSR Address 51000024h Type R/W Reset Value 00000000_00000000h Region 5 Configuration (GLPCI_R5) MSR Address 51000025h Type R/W Reset Value 00000000_00000000h Region 6 Configuration (GLPCI_R6) MSR Address 51000026h Type R/W Reset Value 00000000_00000000h Region 7 Configuration (GLPCI_R7) MSR Address 51000027h Type R/W Reset Value 00000000_00000000h GLPCI_R[x] Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 TOP RSVD SPACE 5 4 3 PF 2 RSVD 1 RH 0 EN www.national.com 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 BASE 9 8 7 6 RSVD GLPCI_REGCONF[x] Bit Descriptions Bit 63:44 43:33 Name TOP RSVD (RO) Description Top of Region. For memory use [63:44] as top of address bits [31:12]. For I/O use [63:46] as top of address bits [19:2]. (Note 1) Reserved (Read Only): Returns 0. Revision 0.8 223 Geode™ CS5535 GLPCI_SB Register Descriptions (Continued) GLPCI_REGCONF[x] Bit Descriptions (Continued) Bit 32 Name SPACE Description Region Space Indicator. 0: Memory space. 1: I/O space. 31:12 11:4 3 BASE RSVD (RO) PF Base of Region. For memory use [31:12] as base of address bits [31:12]. For I/O use [31:14] as base of address bits [19:2]. (Note 1) Reserved (Read Only). Returns 0. Prefetchable. If region is memory and this bit is set, it indicates a prefetechable memory region. Reads to this region have no side-effects. If region is I/O and this bit is set, post all I/O writes to this region. Reserved (Read Only). Returns 0. Retry/Hold. Defines whether GLPCI_SB PCI slave generates a retry condition or holds the PCI bus until cycle completion. Note that even if hold is selected, the cycle will be terminated if initial latency time-out is reached. 0: Retry. 1: Hold. 0 EN Region Enable. Set to 1 to enable access to this region. 2 1 RSVD (RO) RH Note 1. For memory, 4 kB granularity, inclusive: [63:44]