HPC36400EV2

HPC36400E HPC46400E High-Performance Communications MicroController PRELIMINARY November 1992 HPC36400E HPC46400E High-Performance Communications MicroController General Description The HPC46400E is an upgraded HPC16400 Features have been added to support V 120 the 8-bit mode has been enhanced to support all instructions and the UART has been changed to provide more flexibility and power The HPC46400E is fully upward compatible with the HPC16400 The HPC46400E has 4 functional blocks to support a wide range of communication application-2 HDLC channels 4 channel DMA controller to facilitate data flow for the HDLC channels programmable serial interface and UART The serial interface decoder allows the 2 HDLC channels to be used with devices using interchip serial link for point-topoint and multipoint data exchanges The decoder generates enable signals for the HDLC channels allowing multiplexed D and B channel data to be accessed The HDLC channels manage the link by providing sequencing using the HDLC framing along with error control based upon a cyclic redundancy check (CRC) Multiple address recognition modes and both bit and byte modes of operation are supported The HPC36400E and HPC46400E are available in 68-pin PLCC and 80-pin PQFP packages Y Y Y Y Y Features Y HPCTM family core features 16-bit data bus ALU and registers 64 kbytes of external memory addressing FAST 20 0 MHz system clock Four 16-bit timer counters with WATCHDOGTM logic MICROWIRE PLUSTM serial I O interface CMOS low power with two power save modes Y Y Y Two full duplex HDLC channels Optimized for ISDN X 25 V 120 and LAPD applications Programmable frame address recognition Up to 4 65 Mbps serial data rate Built in diagnostics Synchronous bypass mode Optional CRC generation Received CRC bytes can be read by the CPU Four channel DMA controller 8- or 16-bit external data bus UART Full duplex 7 8 or 9 data bits Even odd mark space or no parity 7 8 1 or 2 stop bit generation Accurate internal baud rate generation up to 625k baud without penalty of using expensive crystal Synchronous and asynchronous modes of operation Serial Decoder Supports 6 popular time division multiplexing protocols for inter-chip communications Optional rate adaptation of 64 kbit s data rate to 56 kbit s Over Mbyte of extended addressing Easy interface to National’s DASL ‘U’ and ‘S’ transceivers TP3400 TP3410 and TP3420 Commercial (0 C to a 70 C) and industrial (b40 C to a 85 C) Block Diagram TL DD 10422 – 1 TapePak and TRI-STATE are registered trademarks of National Semiconductor Corporation HPCTM MICROWIRE PLUSTM and WATCHDOGTM are trademarks of National Semiconductor Corporation IBM PC-AT are registered trademarks of International Business Machines Corporation Sun is a registered trademark of Sun Microsystems SunOSTM is a trademark of Sun Microsystems UNIX is a registered trademark of AT T Bell Laboratories C1995 National Semiconductor Corporation TL DD10422 RRD-B30M115 Printed in U S A Absolute Maximum Ratings If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Total Allowable Source or Sink Current Storage Temperature Range Lead Temperature (Soldering 10 sec ) 100 mA b 65 C to a 150 C VCC with Respect to GND All Other Pins b 0 5V to 7 0V (VCC a 0 5)V to (GND b 0 5)V 300 C Note Absolute maximum ratings indicate limits beyond which damage to the device may occur DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings DC Electrical Characteristics VCC e 5 0V g 10% unless otherwise specified HPC46400E b40 C to a 85 C for HPC36400E Symbol ICC1 ICC2 ICC3 Parameter Supply Current Test Conditions VCC e 5 5V fin e 20 0 MHz (Note 1) VCC e 5 5V fin e 2 0 MHz (Note 1) IDLE Mode Current VCC e 5 5V fin e 20 0 MHz (Note 1) VCC e 5 5V fin e 2 0 MHz (Note 1) HALT Mode Current VCC e 5 5V fin e 0 kHz (Note 1) VCC e 2 5V fin e 0 kHz (Note 1) INPUT VOLTAGE LEVELS VIH1 VIL1 VIH2 VIL2 VIH3 VIL3 ILI CI CIO VOH1 VOL1 VOH2 VOL2 VOH3 VOL3 VOH4 VOL4 VRAM IOZ RAM Keep-Alive Voltage TRI-STATE Leakage Current Logic High Logic Low PORT A TA e 0 C to a 70 C for Min Max 70 10 10 2 500 150 Units mA mA mA mA mA mA SCHMITT TRIGGERED RESET WO D0 NMI I2 I3 AND ALSO CKI 0 9 VCC 0 1 VCC V V INPUT VOLTAGE LEVELS Logic High Logic Low 20 08 ALL OTHERS 0 7 VCC 0 2 VCC (Note 2) (Note 3) (Note 3) g1 V V INPUT VOLTAGE LEVELS Logic High Logic Low V V mA pF pF Input Leakage Current Input Capacitance I O Capacitance 10 20 OUTPUT VOLTAGE LEVELS Logic High (CMOS) Logic Low (CMOS) Port A B Drive CK2 (A0 – A15 B10 B11 B12 B15) Other Port Pin Drive WO (open drain) (B0 – B9 B13 B14 R0 – R7 D5 D7) ST1 and ST2 Drive IOH e b10 mA (Note 3) IOL e 10 mA (Note 3) IOH e b1 mA IOL e 3 mA IOH e b1 6 mA (except WO) IOL e 0 5 mA IOH e b6 mA IOL e 1 6 mA (Note 4) (Note 5) VIN e 0 and VIN e VCC 25 g5 VCC b 0 1 01 24 04 24 04 24 04 V V V V V V V V V mA Note 1 ICC1 ICC2 ICC3 measured with no external drive (IOH and IOL e 0 IIH and IIL e 0) ICC1 is measured with RESET e VSS ICC3 is measured with NMI e VCC CKI driven to VIH1 and VIL1 with rise and fall times less than 10 ns Note 2 RDY HLD and RDY I4 pins have internal pullups and meet this spec only at VIN e VCC Note 3 These parameters are guaranteed by design and are not tested Note 4 ST2 drive will not meet this spec under condition of RESET pin e low Note 5 Test duration is 100 ms 2 AC Electrical Characteristics (see Notes 1 and 4 and Figures 1 thru 5 ) VCC e 5V g 10% TA e 0 C to a 70 C for HPC46400E b40 C to a 85 C for HPC36400E Symbol and Formula fC tC1 e 1 fC tCKIH tCKIL tC e 2 fC tWAIT e tC tDC1C2R tDC1C2F fU e fC 8 fMW tHCK e 4tC1 a 14 Timers fXIN e fC 22 tXIN e tC tUWS tUWH tUWV tSALE e External Hold tHWP e tHAE e tHAD e tBF tBE e tC b 66 tC a 40 tC a 35 tC a 100 tC a 85 Parameter and Notes Operating Frequency Operating Period CKI Rise Time CKI Fall Time CPU or DMA Timing Cycle CPU or DMA Wait State Period Delay of CK2 Rising Edge after CKI Falling Edge Delay of CK2 Falling Edge after CKI Falling Edge External UART Clock Input Frequency External MICROWIRE PLUS Clock Input Frequency HDLC Clock Input Period External Timer Input Frequency Pulse Width for Timer Inputs MICROWIRE Setup Time MICROWIRE Hold Time Master Slave Master Slave Master Slave 115 110 175 210 66 34 100 100 20 20 50 50 150 214 0 91 Min 2 50 22 5 22 5 100 100 0 0 55 55 25 1 25 Max 20 500 Units MHz ns ns ns ns ns ns ns MHz MHz ns kHz ns ns ns ns ns ns ns ns ns ns ns ns ns (Note 3) (Note 2) (Note 2) Note MICROWIRE PLUS Clocks MICROWIRE Output Valid Time HLD Falling Edge before ALE Rising Edge HLD Pulse Width HLDA Falling Edge after HLD Falling Edge HLDA Rising Edge after HLD Rising Edge Bus Float after HLDA Falling Edge Bus Enable after HLDA Rising Edge Note 1 These AC characteristics are guaranteed with external clock drive on CKI having 50% duty cycle and with less than 15 pF load on CKO Spec’d tC1R tC1F and CKI duty cycle limits are not tested but are guaranteed functional by design Keep in mind that when SLOW mode is selected fC (Operating Frequency) will be the external frequency divided by 4 and that value should be used in all formulas relating to the AC Characteristics Note 2 Do not design with this parameter unless CKI is driven with an active signal and SLOW mode is not selected When using a passive crystal circuit its stability is not guaranteed if either CKI or CKO is connected to any external logic other than the passive components of the crystal circuit Note 3 tHAE is spec’d for case with HLD falling edge occurring at the latest time it can be accepted during the present CPU or DMA cycle being executed If HLD falling edge occurs later tHAE as long as (3 tC a 4 WS a 72 tC a 100) may occur depending on the following CPU instruction or DMA cycle its wait states and ready input Note 4 WS (tWAIT) c (number of preprogrammed wait states) Minimum and maximum values are calculated at maximum operating frequency fC e 20 MHz with one wait state preprogrammed These values are guaranteed with AC loading of 100 pF on Port A 50 pF on CK2 80 pF on other outputs and DC loading of the pin’s DC spec non CMOS IOL or IOH 3 AC Electrical Characteristics (Continued) CPU and DMA Timing (see Notes 1 and 4 and Figures 2 4 6 7 8 and 9 ) VCC e 5V g 10% TA e 0 C to a 70 C for HPC46400E b40 C to a 85 C for HPC36400E Symbol t1ALR Address Cycles t1ALF t2ALR t2ALF tLL tST tVP tARR Read Cycles tACC tRD tRW tDR tRDA Write Cycles tARW tWW tV tHW Ready Input tRDYS tRDYH tRDYV WS b tC b 47 tC b 47 CPU DMA tC a 20 tC a 20 tC b 9 tC b 20 tC b 10 tC b 10 tC b 20 tC a WS b 55 tC a WS b 75 tC a WS b 35 tC a WS tC a WS b 15 tC a WS b 15 tC b 25 tC b 20 tC b 20 tC a WS b 15 tC a WS b 15 tC a WS b 40 tC a WS b 50 tC b 10 CPU DMA CPU DMA CPU DMA CPU DMA CPU DMA CPU DMA Formula Cycle CPU DMA CPU DMA CPU CPU Parameter Delay of ALE Rising Edge after CKI Rising Edge Delay of ALE Rising Edge after CKI Falling Edge Delay of ALE Falling Edge after CKI Rising Edge Delay of ALE Falling Edge after CKI Falling Edge ALE Rising Edge after CK2 Rising Edge ALE Falling Edge after CK2 Falling Edge ALE Pulse Width Setup of Address Valid before ALE Falling Edge Hold of Address Valid after ALE Falling Edge ALE Falling Edge to RD Falling Edge Data Input Valid after Address Output Valid Data Input Valid after RD Falling Edge RD Pulse Width Hold of Data Input Valid after RD Rising Edge Bus Enable after RD Rising Edge ALE Falling Edge to WR Falling Edge WR Pulse Width Data Output Valid before WR Rising Edge Hold of Data Output Valid after WR Rising Edge RDY Falling Edge before CK2 Rising Edge RDY Rising Edge after CK2 Rising Edge RDY Falling Edge after RD or WR Falling Edge 110 135 0 55 30 160 135 110 100 15 45 0 28 53 50 41 5 15 40 30 145 150 90 115 Min 0 0 0 0 Max 35 35 35 35 45 45 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (Note 6) (Note 5) (Note 3) Note (Note 2) (Note 2) (Note 2) (Note 2) Note 1 These AC characteristics are guaranteed with external clock drive on CKI having 50% duty cycle and with less than 15 pF load on CKO Spec’d tC1R tC1F and CKI duty cycle limits are not tested but are guaranteed functional by design Keep in mind that when SLOW mode is selected fC (Operating Frequency) will be the external frequency divided by 4 and that value should be used in all formulas relating to the AC Characteristics Note 2 Do not design with this parameter unless CKI is driven with an active signal meeting TC1R and TC1F specs When using a passive crystal circuit its stability is not guaranteed if either CKI or CKO is connected to any external logic other than the passive components of the crystal circuit Note 3 Setup of HBE valid before ALE falling edge is 0 ns minimum Setup of BS0 thru BS3 valid before ALE falling edge when in extended addressing mode is 0 ns minimum Note 4 WS (tWAIT) c (number of preprogrammed wait states) Minimum and maximum values are calculated at maximum operating frequency fC e 20 MHz with one wait state preprogrammed These values are guaranteed with AC loading of 100 pF on Port A 50 pF on CK2 80 pF on other outputs and DC loading of the pin’s DC spec non CMOS IOL or IOH Note 5 Hold of HBE Output Valid after WR rising edge is 0 ns minimum Hold of BS0 thru BS3 Output Valid after WR rising edge when in extended addressing mode is 0 ns minimum Note 6 In HPC in-circuit emulators the tRDYV formulas are WS b respectively tC b 57 and tC b 57 yielding minimums of 18 ns and 43 ns for CPU and DMA cycles 4 Timing Waveforms Rise Fall Time Duty Cycle TL DD 10422 – 2 TL DD 10422 – 3 FIGURE 1 CKI Input Signal TL DD 10422 – 4 Note AC testing inputs are driven at VIH for a logic ‘‘1’’ and VIL for a logic ‘‘0’’ Output timing measurements are made at 2 0V for a logic ‘‘1’’ and at 0 8V for a logic ‘‘0’’ FIGURE 2 Input and Output for AC Tests TL DD 10422 – 5 FIGURE 3 MICROWIRE Setup Hold Timing TL DD 10422 – 6 FIGURE 4 CKI CK2 ALE Timing Diagram TL DD 10422 – 7 FIGURE 5 External Hold Timing 5 Timing Waveforms (Continued) TL DD 10422 – 8 FIGURE 6 CPU and DMA Write Cycles TL DD 10422 – 9 FIGURE 7 CPU and DMA Read Cycles TL DD 10422 – 10 FIGURE 8 CPU Ready Mode with 1 Wait State and Ready Wait Extension TL DD 10422 – 11 FIGURE 9 DMA Ready Mode with 2 Wait States and Ready Wait Extension 6 Timing Waveforms (Continued) Timing Diagrams for TX Using External Enable TL DD 10422 – 12 Symbol TETE TLTE TVTE TVTC THTE TSTE TTTE TVTR Parameter Hold of TEN Low after HCK Rising Edge Setup of TEN Rising Edge before HCK Rising Edge Delay of TX Output Valid after TEN Rising Edge Delay of TX Output Valid after HCK Rising Edge Hold of TEN High after HCK Falling Edge Setup of TEN Falling Edge before HCK Falling Edge Delay of TX Output TRI-STATE after TEN Falling Edge TVTC in Rate Adaptation Mode Min 5 85 Max Units ns ns ns ns ns ns ns ns 40 65 60 20 40 75 Timing Diagrams for RX Using External Enable TL DD 10422 – 13 Symbol TERE TLRE TVRS TVRH THRE TSRE Parameter Hold of REN Low after HCK Rising Edge Setup of REN Rising Edge before HCK Falling Edge Setup of RX Data Input Valid before HCK Falling Edge Hold of RX Data Input Valid after HCK Falling Edge Hold of REN High after HCK Rising Edge Setup of REN Falling Edge before HCK Falling Edge Min 5 30 20 20 5 30 Max Units ns ns ns ns ns ns 7 Timing Waveforms (Continued) Serial Decoder Timing Diagram (Mode 2) TL DD 10422 – 14 Symbol TPFS TAFS TEFS TLFS TVFC THFS TSFS TTTC TVFR Parameter Number of HCK1 Periods between FS Falling Edges Number of HCK1 Rising Edges during FS Low Hold of FS High after HCK1 Rising Edge Setup of FS Falling Edge before HCK1 Rising Edge Delay of TX Output Valid after HCK1 Rising Edge Hold of FS Low after HCK1 Rising Edge Setup of FS Rising Edge before HCK1 Rising Edge Delay of TX output TRI-STATE after HCK1 Rising Edge TVFC in Rate Adaptation Mode Min 34 1 10 20 20 20 Max 32 Comments Units 60 Early FS Late FS (Note 8) (Note 7) 40 75 ns ns ns ns ns ns ns Serial Decoder Timing Diagram (Modes 3 4) TL DD 10422 – 15 Symbol TPFS TPFS TAFS TAFS TEFS TLFS TVFS THFS TSFS TTTC Parameter Number of HCK1 Periods between FS Rising Edges Number of HCK1 Periods between FS Rising Edges Number of HCK1 Falling Edges during FS High Number of HCK1 Falling Edges during FS High Hold of FS Low after HCK1 Falling Edge Setup of FS Rising Edge before HCK1 Falling Edge Delay of TX Output Valid after HCK1 and FS Rising Edges Hold of FS High after HCK1 Falling Edge Setup of FS Falling Edge before HCK1 Rising Edge Delay of TX output TRI-STATE after HCK1 Rising Edge Min 64 32 2 2 10 45 20 20 Max Comments SD Mode 3 SD Mode 4 SD Mode 3 SD Mode 4 Early FS Late FS (Note 8) (Note 9) Units 62 30 70 40 ns ns ns ns ns ns Note 7 This spec is for 1st bit only Remaining bits are spec’d by transmitter TVTC spec Note 8 Receiver specs TVRS and TVRH are required along with TLFS for receiver operation using serial decoder Note 9 This spec is for 1st bit only and is measured from the later of either FS or HCK1 rising edge Remaining bits are spec’d from HCK1 rising edges by transmitter TVTC spec 8 Timing Waveforms (Continued) Serial Decoder Timing Diagram (Modes 5 6 7) TL DD 10422 – 16 Symbol TPFS TAFS TEFS TLFS TVFC THFS TSFS TTTC Parameter Number of HCK1 Periods between FS Rising Edges Number of HCK1 Falling Edges during FS High Hold of FS Low after HCK1 Falling Edge Setup of FS Rising Edge before HCK1 Falling Edge Delay of TX Output Valid after HCK1 Rising Edge Hold of FS High after HCK1 Falling Edge Setup of FS Falling Edge before HCK1 Rising Edge Delay of TX output TRI-STATE after HCK1 Rising Edge Min 34 1 10 45 20 20 Max 32 Comments Units 60 Early FS Late FS (Note 8) (Note 7) 40 ns ns ns ns ns ns Note 7 This spec is for 1st bit only Remaining bits are spec’d by transmitter TVTC spec Note 8 Receiver specs TVRS and TVRH are required along with TLFS for receiver operation using serial decoder 9 Pin Descriptions I O PORTS Port A is a 16-bit multiplexed address data bus used for accessing external program and data memory Four associated bus control signals are available on port B The Address Latch Enable (ALE) signal is used to provide timing to demultiplex the bus Reading from and writing to external memory are signalled by RD and WR respectively External memory can be addressed as either bytes or words with the decoding controlled by two lines Bus High Byte enable (HBE) and Address Data Line 0 (A0) Port B is a 16-bit port with 12 bits of bidirectional I O Pins B10 B11 B12 and B15 are the control bus signals for the address data bus Port B may also be configured via a function register BFUN to individually allow each bidirectional I O pin to have an alternate function B0 TDX UART Data Output B1 CFLG1 Closing Flag Output for HDLC 1 Transmitter B2 CKX UART Clock (Input or Output) B3 T2IO Timer2 I O Pin B4 B5 B6 B7 B8 B9 B10 B11 B12 T3IO SO SK HLDA TS0 TS1 ALE WR HBE Timer3 I O Pin MICROWIRE PLUS Output MICROWIRE PLUS Clock (Input or Output) Hold Acknowledge Output Timer Synchronous Output Timer Synchronous Output Address Latch Enable Output for Address Data Bus Address Data Bus Write Output High Byte Enable Output for Address Data Bus also 8-Bit Mode Strap Input on Reset Timer Synchronous Output Timer Synchronous Output B13 BS2 Memory bank switch output 2 B14 BS3 Memory bank switch output 3 (MSB) Port I is an 8-bit input port that can be read as general purpose inputs and can also be used for the following functions I0 HCK2 HLDC 2 Clock Input Nonmaskable Interrupt Input Maskable Interrupt Input Capture Maskable Interrupt Input Capture Maskable Interrupt Input Capture Ready Input I5 SI MICROWIRE PLUS Data Input I6 RDX UART Data Input I7 HCK1 HDLC 1 Clock and Serial Decoder Clock Input Port D is an 8-bit input port that can be read as general purpose inputs and can also be used for the following functions D0 REN1 FS Receiver 1 Enable Serial Decoder RHCK1 Frame Sync Input Receiver 1 Clock Input D1 TEN1 Transmitter 1 Enable Input D2 D3 D4 D5 D6 D7 REN2 RHCK2 TEN2 RX1 TX1 RX2 TX2 Receiver 2 Enable Input Receiver 2 Clock Input Transmitter 2 Enable Input Receiver 1 Data Input Transmitter 1 Data Output Receiver 2 Data Input Transmitter 2 Data Output I1 I2 I3 I4 NMI INT2 INT3 INT4 RDY B13 TS2 B14 TS3 B15 RD Address Data Bus Read Output When operating in the extended memory addressing mode four bits of port B can be used as follows B8 BS0 Memory bank switch output 0 (LSB) B9 BS1 Memory bank switch output 1 Note Any of these pins can be read by software Therefore unused functions can be used as general purpose inputs notably external enable lines when the internal serial decoder is used Port R is an 8-bit bidirectional I O port available for general purpose I O operations Port R has a direction register to enable each separate pin to be individually defined as an input or output It has a data register which contains the value to be output In addition the Port R pins can be read directly using the Port R pins address 10 Pin Descriptions (Continued) POWER SUPPLIES VCC1 VCC2 Positive Power Supply (two pins) GND DGND Ground for On-Chip Logic Ground for Output Buffers OTHER PINS WO This is an active low open drain output which signals an illegal situation has been detected by the WATCHDOG logic ST1 Bus Cycle Status Output indicates first opcode fetch ST2 Bus Cycle Status Output indicates machine states (skip and interrupt) RESET Active low input that forces the chip to restart and sets the ports in a TRI-STATE mode RDY HLD Has two uses selected by a software bit This pin is either a READY input to extend the bus cycle for slower memories or a HOLD-REQUEST input to put the bus in a high impedance state for external DMA purposes In the second case the I4 pin can become the READY input Note There are multiple electrically connected VCC pins on the chip GND and DGND are electrically isolated All VCC pins and all ground pins must be used CLOCK PINS CKI The System Clock Input CKO The System Clock Output (Inversion of CKI) Pins CKI and CKO are usually connected across an external crystal CK2 Clock Output (CKI divided by 2) Connection Diagrams Plastic and Leaded Chip Carriers TL DD 10422 – 18 Top View See NS Package Number V68A 11 Connection Diagrams (Continued) TL DD 10422 – 32 Top View See NS Package Number VHG80A Wait States The HPC46400E provides software selectable Wait States for access to slower memories and for shared bus applications The number of Wait States for the CPU are selected by two bits in the PSW register The number of Wait States for DMA are selected by a bit in the Message System Configuration register Additionally the RDY input may be used to extend the RD or WR cycle allowing the HPC to be used in shared memory applications and allowing the user to interface with slow memories and peripherals input will generate a vectored interrupt and resume operation from that point with no initialization The HALT mode can be enabled or disabled by means of a control register HALT enable To prevent accidental use of the HALT mode the HALT enable register can be modified only once IDLE MODE The HPC46400E is placed in the IDLE mode through the PSW In this mode all processor activity except the onboard oscillator and Timer T0 is stopped The HPC46400E resumes normal operation upon timer T0 overflow As with the HALT mode the processor is also returned to full operation by the RESET or NMI inputs but without waiting for oscillator stabilization SLOW MODE The HPC46400E is placed in the SLOW mode under software control by setting ‘‘SLOW’’ bit in ‘‘FEXT’’ Feature Extension register In this mode CKI is divided by 4 and each CK2 cycle will be 8 CKI clock cycles This reduction in frequency of operation of HPC16400E is achieved without altering the state of the machine CKI and CKO signals remain unaffected reagardless of the status of the SLOW bit At RESET the ‘‘SLOW’’ bit comes up as 0 i e the clocking of the HPC46400E is normal Software can cause the division to be enabled or disabled by writing a 1 or a 0 to the ‘‘SLOW’’ bit Note that when the ‘‘SLOW’’ bit is set to 1 HALT or IDLE power down mode cannot be entered ‘‘SLOW’’ bit has to be cleared to a 0 first Power Save Modes Two power saving modes are available on the HPC46400E HALT and IDLE In the HALT mode all processor activities are stopped In the IDLE mode the on-board oscillator and timer T0 are active but all other processor activities are stopped In either mode on-board RAM registers and I O are unaffected (except the HDLC and UART which are reset) HALT MODE The HPC46400E is placed in the HALT mode under software control by setting bits in the PSW All processor activities including the clock and timers are stopped In the HALT mode power requirements for the HPC46400E are minimal and the applied voltage (VCC) may be decreased without altering the state of the machine There are two ways of exiting the HALT mode via the RESET or the NMI The RESET input reinitializes the processor Use of the NMI 12 HPC46400E Interrupts Complex interrupt handling is easily accomplished by the HPC46400E’s vectored interrupt scheme There are eight possible interrupt sources as shown in Table I TABLE I Interrupts Vector Address FFFFlFFFE FFFDlFFFC FFFBlFFFA FFF9lFFF8 FFF7lFFF6 FFF5lFFF4 FFF3lFFF2 FFF1lFFF0 Interrupt Source Reset Nonmaskable Ext (NMI) External on I2 External on I3 External on I4 Internal on Timers Internal on UART End of Message (EOM) Arbitration Ranking 0 1 2 3 4 5 6 7 For the interrupts from the on-board peripherals the user has the responsibility of acknowledging the interrupt through software INTERRUPT CONDITION REGISTER (IRCD) Three bits of the register select the input polarity of the external interrupt on I2 I3 and I4 Servicing the Interrupts The Interrupt once acknowledged pushes the program counter (PC) onto the stack thus incrementing the stack pointer (SP) twice The Global Interrupt Enable (GIE) bit is reset thus disabling further interrupts The program counter is loaded with the contents of the memory at the vector address and the processor resumes operation at this point At the end of the interrupt service routine the user does a RETI instruction to pop the stack set the GIE bit and return to the main program The GIE bit can be set in the interrupt service routine to nest interrupts if desired Figure 10 shows the Interrupt Enable Logic The HPC46400E contains arbitration logic to determine which interrupt will be serviced first if two or more interrupts occur simultaneously Interrupts are serviced after the current instruction is completed except for the RESET which is serviced immediately The NMI interrupt will immediately stop DMA activity Byte transfers in progress will finish thereby allowing an orderly transition to the interrupt service vector (see DMA description) The HDLC channels continue to operate and the user must service data errors that might have occurred during the NMI service routine Reset The RESET input initializes the processor and sets all pins at TRI-STATE except CK0 CK2 and WO HBE and ST2 have pull-downs designed to withstand override RESET is an active-low Schmitt trigger input The processor vectors to FFFF FFFE and resumes operation at the address contained at that memory location The RESET pin must be asserted low for at least 16 cycles of the CK2 clock In applications using the WATCHDOG feature RESET should be asserted for at least 64 cycles of the CK2 clock On application of power RESET must be held low for at least five times the power supply rise time to ensure that the on-chip oscillator circuit has time to stabilize Interrupt Processing Interrupts are serviced after the current instruction is completed except for the RESET which is serviced immediately RESET holds on-chip logic in a reset state while low and triggers the RESET interrupt on its rising edge All other interrupts are edge-sensitive NMI is positive-edge sensitive The external interrupts on I2 I3 and I4 can be software selected to be rising or falling edge sensitive Timer Overview The HPC46400E contains a powerful set of flexible timers enabling the HPC46400E to perform extensive timer functions not usually associated with microcontrollers The HPC46400E contains four 16-bit timers Three of the timers have an associated 16-bit register Timer T0 is a freerunning timer counting up at a fixed CKI 16 (Clock Input 16) rate It is used for WATCHDOG logic high speed event capture and to exit from the IDLE mode Consequently it cannot be stopped or written to under software control Timer T0 permits precise measurements by means of the capture registers I2CR I3CR and I4CR A control bit in the register T0CON configures timer T1 and its associated register R1 as capture registers I3CR and I2CR The capture registers I2CR I3CR and I4CR respectively record the value of timer T0 when specific events occur on the interrupt pins I2 I3 and I4 The control register IRCD programs the capture registers to trigger on either a rising edge or a falling edge of its respective input The specified edge can also be programmed to generate an interrupt (see Figure 11 ) The timers T2 and T3 have selectable clock rates The clock input to these two timers may be selected from the following two sources an external pin or derived internally by dividing the clock input Timer T2 has additional capability of being clocked by the timer T3 underflow This allows the user to cascade timers T3 and T2 into a 32-bit timer counter The control register DIVBY programs the clock input to timers T2 and T3 (see Figure 12 ) Interrupt Control Registers The HPC46400E allows the various interrupt sources and conditions to be programmed This is done through the various control registers A brief description of the different control registers is given below INTERRUPT ENABLE REGISTER (ENIR) RESET and the External Interrupt on I1 are non-maskable interrupts The other interrupts can be individually enabled or disabled Additionally a Global Interrupt Enable Bit in the ENIR Register allows the Maskable interrupts to be collectively enabled or disabled Thus in order for a particular interrupt to request service both the individual enable bit and the Global Interrupt bit (GIE) have to be set INTERRUPT PENDING REGISTER (IRPD) The IRPD register contains a bit allocated for each interrupt vector The occurrence of specified interrupt trigger conditions causes the appropriate bit to be set There is no indication of the order in which the interrupts have been received The bits are set independently of the fact that the interrupts may be disabled IRPD is a Read Write register The bits corresponding to the external interrupts are normally cleared by the HPC46400E upon entering the interrupt servicing routine 13 Timer Overview (Continued) TL DD 10422 – 19 FIGURE 10 Interrupt Enable Logic TL DD 10422–21 FIGURE 11 Timers T0–T1 Block TL DD 10422 – 20 FIGURE 12 Timers T2 – T3 Block 14 Timer Overview (Continued) The timers T1 through T3 in conjunction with their registers form Timer-Register pairs The registers hold the pulse duration values All the Timer-Register pairs can be read from or written to Each timer can be started or stopped under software control Once enabled the timers count down and upon underflow the contents of its associated register are automatically loaded into the timer SYNCHRONOUS OUTPUTS The flexible timer structure of the HPC46400E simplifies pulse generation and measurement There are four synchronous timer outputs (TS0 through TS3) that work in conjunction with the timer T2 The synchronous timer outputs can be used either as regular outputs or individually programmed to toggle on timer T2 underflows (see Figure 12 ) Maximum output frequency for any timer output can be obtained by setting timer register pair to zero This then will produce an output frequency equal to the frequency of the source used for clocking the timer WATCHDOG Logic The WATCHDOG Logic monitors the operations taking place and signals upon the occurrence of any illegal activity The illegal conditions that trigger the WATCHDOG logic are potentially infinite loops Should the WATCHDOG register not be written to before Timer T0 overflows twice or more often than once every 4096 counts an infinite loop condition is assumed to have occurred The illegal condition forces the Watch Out (WO) pin low The WO pin is an open drain output and can be connected to the RESET or NMI inputs or to the users external logic MICROWIRE PLUS MICROWIRE PLUS is used for synchronous serial data communications (see Figure 15 ) MICROWIRE PLUS has an 8-bit parallel-loaded serial shift register using SI as the input and SO as the output SK is the clock for the serial shift register (SIO) The SK clock signal can be provided by an internal or external source The internal clock rate is programmable by the DIVBY register A DONE flag indicates when the data shift is completed The MICROWIRE PLUS capability enables it to interface with any of National Semiconductor’s MICROWIRE peripherals (i e ISDN Transceivers A D converters display drivers EEPROMs) Timer Registers There are four control registers that program the timers The divide by (DIVBY) register programs the clock input to timers T2 and T3 The timer mode register (TMMODE) contains control bits to start and stop timers T1 through T3 It also contains bits to latch acknowledge and enable interrupts from timers T0 through T3 Timer Applications The use of Pulse Width Timers for the generation of various waveforms is easily accomplished by the HPC46400E Frequencies can be generated by using the timer register pairs A square wave is generated when the register value is a constant The duty cycle can be controlled simply by changing the register value TL DD 10422 – 22 FIGURE 13 Square Wave Frequency Generation Synchronous outputs based on Timer T2 can be generated on the 4 outputs TS0–TS3 Each output can be individually programmed to toggle on T2 underflow Register R2 contains the time delay between events Figure 14 is an example of synchronous pulse train generation TL DD 10422 – 24 FIGURE 15 MICROWIRE PLUS TL DD 10422 – 23 FIGURE 14 Synchronous Pulse Generation 15 MICROWIRE PLUS Operation The HPC46400E can enter the MICROWIRE PLUS mode as the master or a slave A control bit in the IRCD register determines whether the HPC46400E is the master or slave The shift clock is generated when the HPC46400E is configured as a master An externally generated shift clock on the SK pin is used when the HPC46400E is configured as a slave When the HPC46400E is a master the DIVBY register programs the frequency of the SK clock The DIVBY register allows the SK clock frequency to be programmed in 14 selectable steps from 122 Hz to 1 MHz with CKI at 16 MHz The contents of the SIO register may be accessed through any of the memory access instructions Data waiting to be transmitted in the SIO register is shifted out on the falling edge of the SK clock Serial data on the SI pin is latched in on the rising edge of the SK clock HPC46400E UART The HPC46400E contains a software programmable UART The UART (see Figure 16 ) consists of a transmit shift register a receiver shift register and five addressable registers as follows a transmit buffer register (TBUF) a receiver buffer register (RBUF) a UART control and status register (ENU) a UART receive control and status register (ENUR) and a UART interrupt and clock source register (ENUI) The ENU register contains flags for transmit and receive functions this register also determines the length of the data frame (7 8 or 9 bits) and the value of the ninth bit in transmission The ENUR register flags framing parity and data overrun errors while the UART is receiving Other functions of the ENUR register include saving the ninth bit received in the data frame reporting receiving and transmitting status and enabling or disabling the UART’s Wake-up Mode of operation The determination of an internal or external clock source is done by the ENUI register as well as selecting the number of stop bits ( 11 2) selecting between the synchronous or asynchronous mode and enabling or disabling transmit and receive interrupts The clock inputs to the Transmitter and Receiver sections of the UART can be individually selected to come from either an off-chip source on the CKX pin or one of the three on-chip sources Presently two of the on-chip sources the Divide-By (DIVBY) Register and the Precision UART Timer (PUT) are primarily for reasons of upward compatibility from earlier HPC family members The most flexible and accurate on-chip clocking is provided by the third source the Baud Rate Generator (BRG) The Baud Rate Generator is controlled by the register pair PSR and BAUD shown below The Prescaler factor is selected by the upper 5 bits of the PSR register (the PRESCALE field) in units of the CK2 clock from 1 to 16 in step increments The lower 3 bits of the PSR register in conjunction with the 8 bits of the baud register form the 11-bit BAUDRATE field which defines a baud rate divisor ranging from 1 to 2048 in units of the prescaled clock selected by the PRESCALE field In Asynchronous Mode the resulting baud rate is of the clocking rate selected through the BRG circuit The maximum baud rate generated using the BRG is 625 kbaud In the Synchronous Mode data is transmitted on the rising edge and received on the falling edge of the external clock Although the data is transmitted and received synchronously it is still contained within an asynchronous frame i e a start bit parity bit (if selected) and stop bit(s) are still present TL DD 10422 – 25 FIGURE 16 UART Block Diagram TL DD 10422 – 26 UART Baud Rate Generator (BRG) Registers PSR and BAUD 16 UART Attention Mode The HPC46400E UART features an Attention Mode of operation This mode of operation enables the HPC46400E to be networked with other processors Typically in such environments the messages consist of addresses and actual data Addresses are specified by having the ninth bit in the data frame set to 1 Data in the message is specified by having the ninth bit in the data frame reset to 0 The UART monitors the communication stream looking for addresses When the data word with the ninth bit set is received the UART signals the HPC46400E with an interrupt The processor then examines the content of the receiver buffer to decide whether it has been addressed and whether to accept subsequent data cedure is used in both point-to-point and point-to-multipoint configurations On the HPC46400E the HDLC controller contains user programmable features that allow for the efficient processing of LAPD Information HDLC Channel Pin Description Each HDLC channel has the following pins associated with it HCK HDLC Channel Clock Input Signal RX Receive Serial Data Input Data latched on the negative HCK edge REN RHCK HDLC Channel Receiver Enable Input Receiver Clock Input TEN HDLC Channel Transmitter Enable Input TX Transmit Serial Data Output Data clocked out on the positive HCK edge Data (not including CRC) is sent LSB first TRI-STATE when transmitter not enabled CFLG1 Closing Flag output for Channel 1 Programmable Serial Decoder Interface The programmable serial decoder interface allows the two HDLC channels to be used with devices employing several popular Time Division Multiplexing (TDM) serial protocols for point-to-point and multipoint data exchanges These protocols combine the ‘B’ and ‘D’ channels onto common pins received data transmit data clock and Sync which normally occurs at an 8 KHz rate and provides framing for the particular protocol The decoder uses the serial link clock and Sync signals to generate internal enables for the ‘D’ and ‘B’ channels thereby allowing the HDLC channels to access the appropriate channel data from the multiplexed link Additionally 64 kbit s to 56 kbits s rate adaptation can be done using the Serial Decoder generated enable signals B1 or B2 The rate adaption to 56 kbits s is accomplished by using only the first 7 bits of each B channel time slot for each TDM frame The transmitter will insert a ‘‘1’’ in the eighth bit of each frame The receiver will only receive the first seven data bits and skip the eighth bit See Figure 17 65 kbit 56 kbit Rate Adaption Timing Diagram HDLC Functional Description TRANSMITTER DESCRIPTION Data is transferred from external memory through the DMA controller into the transmit buffer register from which it is loaded into a 8-bit serial shift register The CRC is computed and appended to the frame prior to the closing flag being transmitted Data is output at the TX output pin If no further transmit commands are given the transmitter sends out continous flags aborts or the idle pattern as selected by the control register An interrupt is generated when the DMA has transferred the last byte from RAM to the HDLC channel for a particular message or on a transmit error condition An associated transmit status register will contain the status information indicating the specific interrupt source To support transmitting data packets at an ‘‘R’’ interface for V 120 in synchronous UI mode to support the use of the HPC in test equipment or to support proprietary CRC algorithms the transmitter has the option of preventing the transmitting of the hardware generated CRC bytes TRANSMITTER FEATURES Interframe fill the transmitter can send either continuous ‘1’s or repeated flags or aborts between the closing flag of one packet and the opening flag of the next When the CPU commands the transmitter to open a new frame the interframe fill is terminated immediately Abort the abort sequence a zero followed by seven ones will be immediately sent on command from the CPU or on an underrun condition in the DMA Bit Byte boundaries The message length between packet headers may have any number of bits and is not confined to an integral number of bytes Three bits in the control register are used to indicate the number of valid bits in the last byte These bits are loaded by the users software RECEIVER DESCRIPTION Data is input to the receiver on the RX pin The receive clock can be externally input at either the HCK pin or the REN RHCK pin Incoming data is routed through one of several paths depending on whether it is the flag data or CRC Once the receiver is enabled it waits for the opening flag of the incoming frame then starts the zero bit deletion ad17 HDLC Channel Description HDLC DMA Structure HDLC 1 HDLC1 Receive DMAR1 HDLC1 Transmit DMAT1 HDLC 2 HDLC2 Receive DMAR2 HDLC2 Transmit DMAT2 GENERAL INFORMATION Both HDLC channels on the HPC46400E are identical and operate up to 4 65 Mbps When used in an ISDN Basic Rate access application HDLC channel 1 has been designated for use with the 16 kbps D-channel or either B channel and HDLC 2 can be used with either of the 64 kbps B-channels If the ‘D’ and ‘B’ channels are present on a common serial link the programmable serial decoder interface generates the necessary enable signals needed to access the D and B channel data There are two sources for the receive and transmit channel enable signals They can be internally generated from the serial decoder interface or they can be externally enabled LAPD the Link Access Protocol for the D channel is derived from the X 25 packet switching LAPB protocol LAPD specifies the procedure for a terminal to use the D channel for the transfer of call control or user-data information The pro- HDLC Functional Description (Continued) TL DD 10422 – 31 FIGURE 17 64 kbit 56 kbit Rate Adaption Timing Diagram dressing handling and CRC checking All data between the flags is shifted through two 8-bit serial shift registers before being loaded into the buffer register The user programmable address register values are compared to the incoming data while it resides in the shift registers If an address match occurs or if operating in the transparent address recognition mode the DMA channel is signaled that attention is required and the data is transferred by it to external memory Appropriate interrupts are generated to the CPU on the reception of a complete frame or on the occurance of a frame error The receive interrupt in conjunction with status data in the control registers allows interrupts to be generated on the following conditions frame length error CRC error receive error abort and receive complete To support V 120 UI data packets at the ‘‘R’’ interface proprietary CRC algorithms and test equipment the two bytes preceding the closing flag (usually the CRC bytes) will be loaded into registers The two bytes can then be read by the CPU and placed into memory The DMA address pointers used for that particular message will already contain the address that the first byte should be placed into RECEIVER FEATURES Flag sharing the closing flag of one packet may be shared as the opening flag of the next Receiver will also be able to share a zero between flags 011111101111110 is a valid two flag sequence for receive (not transmit) Interframe fill the receiver automatically accepts either repeated flags repeated aborts or all ‘1’s as the interframe fill Idle Reception of successive flags as the interframe fill sequence to be signaled to the user by setting the Flag bit in the Receiver Status register Short Frame Rejection Reception of greater than 2 bytes but less than 4 bytes between flags will generate a frame error terminating reception of the current frame and setting the Frame Error (FER) status bit in the Receive Control and Status register Reception of less than 2 bytes will be ignored Abort the 7 ‘1’s abort sequence will be immediately recognized and will cause the receiver to reinitialize and return to searching the incoming data for an opening flag Reception of the abort will cause the abort status bit in the Interrupt Error Status register to be set and will signal an End of Message (EOMR) Bit Byte boundaries The message length between packet headers may have any number of bits and it is not confined to an integral number of bytes Three bits in the status register are used to indicate the number of valid bits in the last byte Address Recognition Two user programmable bytes are available to allow frame address recognition on the two bytes immediately following the opening flag When the received address matches the programmed value(s) the frame is passed through to the DMA channel If no match occurs the received frame address information is disregarded and the receiver returns to searching for the next opening flag and the address recognition process starts anew Support is provided to allow recognition of the Broadcast address Additionally a transparent mode of operation is available where no address decoding is done HDLC INTERRUPT CONDITIONS The end of message interrupt (EOM) indicates that a complete frame has been received or transmitted by the HDLC controller Thus there are four separate sources for this interrupt two each from each HDLC channel The Message Control Register contains the pending bits for each source HDLC ERROR DETECTION The HDLC DMA detects several error conditions and reports them in the two Error Status Registers These conditions are a DMA transmitter underrun a DMA receiver overrun a CRC error a frame too long a frame too short and an aborted message HDLC CHANNEL CLOCK Each HDLC channel uses the falling edge of the clock to sample the receive data Outgoing transmit data is shifted out on the rising edge of the external clock The maximum data rate when using the externally provided clocks is 4 65 Mb s The receiver transmitter pair can share a single clock input to save I O pins or the inputs can be separated to allow different receive and transmit clocks This feature allows the receiver and transmitter to operate at different frequencies or enables them to each be synchronized to different parts of the user’s system CYCLIC REDUNDACY CHECK There are two standard CRC codes used in generating the 16-bit Frame Check Sequence (FCS) that is appended to the end of the data frame Both codes are supported and 18 HDLC Functional Description (Continued) the user selects the error checking code to be used through software control (HDLC control reg) The two error checking polynomials available are (1) CRC-16 (x16 a x15 a x2 a 1) (2) CCITT CRC (x16 a x12 a x5 a 1) SYNCHRONOUS BYPASS MODE When the BYPAS bit is set in the HDLC control register all HDLC framing formatting functions for the specified HDLC channel are disabled This allows byte-oriented data to be transmitted and received synchronously thus ‘‘bypassing’’ the HDLC functions LOOP BACK OPERATIONAL MODE The user has the ability by setting the appropriate bit in the register to internally route the transmitter output to the receiver input and to internally route the RX pin to the TX pin this number is exceeded a Frame Too Long error is generated DMA is stopped to prevent memory from being overwritten however the receiver continues until the closing flag is received in order to check the CRC B CNTRL ADDR 1 DATA ADDR 1 CNTRL ADDR 2 DATA ADDR 2 For split frame operation the CNTRL ADDR register contains the external memory address where the Frame Header (Control Address fields) are to be stored and the DATA ADDR register contains an equivalent address for the Information field For non-split frame operation the CNTRL and DATA ADDR registers each contain the external memory address for entire frames DMA Controller GENERAL INFORMATION The HPC46400E uses Direct Memory Access (DMA) logic to facilitate data transfer between the 2 full Duplex HDLC channels and external packet RAM There are four DMA channels to support the four individual HDLC channels Control of the DMA channels is accomplished through registers which are configured by the CPU These control registers define specific operation of each channel and changes are immediately reflected in DMA operation In addition to individual control registers global control bits (MSS and MSSC in Message Control Register) are available so that the HDLC channels may be globally controlled The DMA issues a bus request to the CPU when one or more of the individual HDLC channels request service Upon receiving a bus acknowledge from the CPU the DMA completes all requests pending and any requests that may have occurred during DMA operation before returning control to the CPU If no further DMA transfers are pending the DMA relinquishes the bus and the CPU can again initiate a bus cycle Four memory expansion bits have been added for each of the four channels to support data transfers into the expanded memory bank areas The DMA has priority logic for servicing DMA requests The priorities are 1st priority Receiver channel 1 2nd priority Transmit channel 1 3rd priority Receive channel 2 4th priority Transmit channel 2 RECEIVER DMA OPERATION The receiver DMA consists of a shift register and two buffers A receiver DMA operation is initiated by the buffer registers Once a byte has been placed in a buffer register from the HDLC it generates a request and upon obtaining control of the bus the DMA places the byte in external memory RECEIVER REGISTERS All the following registers are Read Write A Frame Length Register This user programmable 16-bit register contains the maximum number of bytes to be placed in a data ‘‘block’’ If 19 TRANSMITTER DMA OPERATION The transmitter DMA consists of a shift register and two buffers A transmitter DMA cycle is initiated by the TX data buffers The TX data buffers generate a request when either one is empty and the DMA responds by placing a byte in the buffer The HDLC transmitter can then accept the byte to send when needed upon which the DMA will issue another request resulting in a subsequent DMA cycle TRANSMITTER REGISTERS The following registers are Read Write FIELD ADDRESS 1 Field Address 1 and Field Address 2 are starting addresses of blocks BYTE COUNT 1 of information to be transmitted FIELD ADDRESS 2 Byte Count 1 and Byte Count 2 are BYTE COUNT 2 the number of bytes in the block to be transmitted Shared Memory Support Shared memory access provides a rapid technique to exchange data It is effective when data is moved from a peripheral to memory or when data is moved between blocks of memory A related area where shared memory access proves effective is in multiprocessing applications where two CPUs share a common memory block The HPC46400E supports shared memory access with two pins The pins are the RDY HLD input pin and the HLDA output pin The user can software select either the Hold or Ready function on the RDY HLD pin by the state of a control bit The HLDA output must be selected as the HLDA output on pin B7 by software The host uses DMA to interface with the HPC46400E The host initiates a data transfer by activating the HLD input of the HPC46400E In response the HPC46400E places its system bus in a TRI-STATE Mode freeing it for use by the host The host waits for the acknowledge signal (HLDA) from the HPC46400E indicating that the sytem bus is free On receiving the acknowledge the host can rapidly transfer data into or out of the shared memory by using a conventional DMA controller Upon completion of the message transfer the host removes the HOLD request and the HPC46400E resumes normal operations See Figure 18 (HPC46400E shared Memory Using HOLD) An alternate approach is to use the Ready function available on either the RDY HLD pin or the INT4 RDY pin See Figure 19 (HPC46400E Shared Memory Using READY) This technique is often required when the HPC is sharing memory over a system backplane bus Shared Memory Support (Continued) TL DD 10422 – 27 FIGURE 18 HPC46400E Shared Memory Using HOLD TL DD 10422 – 28 FIGURE 19 HPC46400E Shared Memory Using READY 20 Memory The HPC46400E has been designed to offer flexibility in memory usage A total address space of 64 kbytes can be addressed with 256 bytes of RAM available on the chip itself Program memory addressing is accomplished by the 16-bit program counter on a byte basis Memory can be addressed directly by instructions or indirectly through the B X and SP registers Memory can be addressed as words or bytes Words are always accessed on even-byte boundaries The HPC46400E uses memory-mapped organization to support registers I O and on-chip peripheral functions The HPC46400E memory address space extends to 64 kbytes and registers and I O are mapped as shown in Table II lows four I O lines of Port B (B8 B9 B13 B14) to be used in extending the address range This gives the user a main routine area of 32k and 16 banks of 32k each for subroutine and data thus getting a total of 536 5k of memory Note If all four lines are not needed for memory expansion the unused lines can be used as general purpose inputs Extended Memory Addressing If more than 64k of addressing is desired in a HPC46400E system on board bank select circuitry is available that al- The Extended Memory Addressing mode is entered by setting the EMA control bit in the Message Control Register If this bit is not set the port B lines (B8 B9 B13 B14) are available as general purpose I O or synchronous outputs as selected by the BFUN register The main memory area contains the interrupt vectors service routines stack memory and common memory for the bank subroutines to use The 16 banks of memory can contain program or data memory (note since the on chip resources are mapped into addresses 0000-01FF the first 512 bytes of each bank are not usable actual available memory is 536 5k) TABLE II Memory Map FFFF – FFF0 FFEF – FFD0 FFCF – FFCE External Expansion 0201 – 0200 01FF – 01FE On Chip RAM 01C1 – 01C0 01BC 01BA 01B8 01B6 01B4 01B2 01B0 01AC 01AA 01A8 01A6 01A4 01A2 01A0 0195 – 0194 0193 – 0192 0191 – 0190 018F – 018E 018D – 018C 018B – 018A 0189 – 0188 0187 – 0186 0185 – 0184 0183 – 0182 0181 – 0180 017F – 017E 017D – 017C 0179 – 0178 0177 – 0176 0175 – 0174 0173 – 0172 0171 – 0170 016B – 016A 0169 – 0168 0167 – 0166 0165 – 0164 0163 – 0162 0161 – 0160 CRC Byte 2 CRC Byte 1 Error Status Receiver Status Cntrl Recr Addr Comp Reg 2 Recr Addr Comp Reg 1 CRC Byte 2 CRC Byte 1 Error Status Receiver Status Cntrl Recr Addr Comp Reg 2 Recr Addr Comp Reg 1 WATCHDOG Register T0CON Register TMMODE Register DIVBY Register T3 Timer R3 Register T2 Timer R2 Register I2CR Register R1 I3CR Register T1 I4CR Register Baud Counter Baud Register Byte Count 2 Field Addr 2 Byte Count 1 Field Addr 1 Xmit Cntrl Status Frame Length Data Addr 2 Cntrl Addr 2 Data Addr 1 Cntrl Addr 1 Recv Cntrl Status USER RAM USER MEMORY Interrupt Vectors JSRP Vectors 0159 – 0158 0157 – 0156 0155 – 0154 0153 – 0152 0151 – 0150 014B – 014A 0149 – 0148 0147 – 0146 0145 – 0144 0143 – 0142 0141 – 0140 012C 012A 0128 0126 0124 0122 0120 0110 010E 010C 010A 0108 0106 0104 0102 0100 Timer Block T0 – T3 00F5 – 00F4 00F3 – 00F2 00E6 00E3 – 00E2 00DD – 00DC 00D8 00D6 00D4 00D2 00D0 00CF – 00CE 00CD – 00CC 00CB – 00CA 00C9 – 00C8 00C7 – 00C6 00C5 – 00C4 00C3 – 00C2 00C0 00BF – 00BE 0001 – 0000 Note All unused addresses are reserved by National Semiconductor Bytes 2 Field Addr 2 Bytes 1 Field Addr 1 Xmit Cntrl Status Frame Length Data Addr 2 Cntrl Addr 2 Data Addr 1 Cntrl Addr 1 Recv Cntrl Status Baud PSR - Prescaler ENUR Register TBUF Register RBUF Register ENUI Register ENU Register FEXT Register Port R Pins DIR R Register Port R Data Register Message System Configuration Serial Decoder Enable Configuration Reg Message Pending Message System Control Port D Input BFUN Register DIR B Register Chip Revision Register Port B Halt Enable Register Port I Input Register SIO Register IRCD Register IRPD Register ENIR Register X Register B Register K Register A Register PC Register SP Register (Reserved) PSW Register On Chip RAM DMAT 1 (Xmit) DMAR 1 (Recv) HDLC 2 UART HDLC 1 WATCHDOG Logic PORTS R D PORT B UART Timer PORT CONTROL INTERRUPT CONTROL REGISTERS DMAT 2 (Xmit) HPC CORE REGISTERS DMAR 2 (Recv) USER RAM 21 Design Considerations Designs using the HPC family of 16-bit high speed CMOS microcontrollers need to follow some general guidelines on usage and board layout Floating inputs are a frequently overlooked problem CMOS inputs have extremely high impedance and if left open can float to any voltage possibly causing internal devices to go into active mode and draw DC current You should thus tie unused inputs to VCC or ground either through a resistor or directly Unlike the inputs unused outputs should be left floating to allow the output to switch without drawing any DC current To reduce voltage transients keep the supply line’s parasitic inductances as low as possible by reducing trace lengths using wide traces ground planes and by decoupling the supply with bypass capacitors In order to prevent additional voltage spiking this local bypass capacitor must exhibit low inductive reactance You should therefore use high frequency ceramic capacitors and place them very near the IC to minimize wiring inductance surface of the board to provide signal shielding and a convenient location to ground both the HPC and the case of the crystal It is very critical to have an extremely clean power supply for the HPC crystal oscillator Ideally one would like a VCC and ground plane that provide low inductance power lines to the chip The power planes in the PC board should be decoupled with three decoupling capacitors as close to the chip as possible A 1 0 mF a 0 1 mF and a 0 001 mF dipped mica or ceramic cap mounted as close to the HPC as is physically possible on the board using the shortest leads or surface mount components This should provide a stable power supply and noiseless ground plane which will vastly improve the performance of the crystal oscillator network HPC Oscillator Table XTAL Frequency (MHz) s2 R1 (X) 1500 1200 910 750 600 470 390 300 220 180  Keep VCC bus routing short When using double sided or multilayer circuit boards use ground plane techniques  Keep ground lines short and on PC boards make them as wide as possible even if trace width varies Use separate ground traces to supply high current devices such as relay and transmission line drivers 4 6 8 10 12 14 16 18 20 RF e 3 3 M X C1 e 27 pF C2 e 33 pF  In systems mixing linear and logic functions and where supply noise is critical to the analog components’ performance provide separate supply buses or even separate supplies  When using local regulators bypass their inputs with a tantalum capacitor of at least 1 mF and bypass their outputs with a 10 mF to 50 mF tantalum or aluminum electrolytic capacitor  If the system uses a centralized regulated power supply use a 10 mF to 20 mF tantalum electrolytic capacitor or a 50 mF to 100 mF aluminum electrolytic capacitor to decouple the VCC bus connected to the circuit board  Provide localized decoupling For random logic a rule of thumb dictates approximately 10 nF (spaced within 12 cm) per every two to five packages and 100 nF for every 10 packages You can group these capacitances but it’s more effective to distribute them among the ICs If the design has a fair amount of synchronous logic with outputs that tend to switch simultaneously additional decoupling might be advisable Octal flip-flop and buffers in bus-oriented circuits might also require more decoupling Note that wire-wrapped circuits can require more decoupling than ground plane or multilayer PC boards A recommended crystal oscillator circuit to be used with the HPC is shown in Figure 20 See table for recommended component values The recommended values given in the table below have yielded consistent results and are made to match a crystal with a 20 pF load capacitance with some small allowance for layout capacitance A recommended layout for the oscillator network should be as close to the processor as physically possible entirely within 1 distance This is to reduce lead inductance from long PC traces as well as interference from other components and reduce trace capacitance The layout should contain a large ground plane either on the top or bottom XTAL Specifications The crystal used was an M-TRON Industries MP-1 Series XTAL ‘‘AT’’ cut parallel resonant CL e 18 pF Series Resistance is 40X 600X 10 MHz 2 MHz TL DD 10422 – 29 FIGURE 20 Recommended Crystal Circuit 22 HPC46400E CPU The HPC46400E CPU has a 16-bit ALU and six 16-bit registers Arithmetic Logic Unit (ALU) The ALU is 16 bits wide and can do 16-bit add subtract and shift or logic AND OR and exclusive OR in one timing cycle The ALU can also output the carry bit to a 1-bit C register Accumulator (A) Register The 16-bit A register is the source and destination register for most I O arithmetic logic and data memory access operations Address (B and X) Registers The 16-bit B and X registers can be used for indirect addressing They can automatically count up or down to sequence through data memory Boundary (K) Register The 16-bit K register is used to set limits in repetitive loops of code as register B sequences through data memory Stack Pointer (SP) Register The 16-bit SP register is the stack pointer that addresses the stack The SP register is incremented by two for each push or call and decremented by two for each pop or return The stack can be placed anywhere in user memory and be as deep as the available memory permits Program (PC) Register The 16-bit PC register addresses program memory Indirect The instruction contains an 8-bit address field The contents of the WORD addressed points to the memory for the operand Indexed The instruction contains an 8-bit address field and an 8- or 16-bit displacement field The contents of the WORD addressed is added to the displacement to get the address of the operand Immediate The instruction contains an 8-bit or 16-bit immediate field that is used as the operand Register Indirect (Auto Increment and Decrement) The operand is the memory addressed by the X register This mode automatically increments or decrements the X register (by 1 for bytes and by 2 for words) Register Indirect (Auto Increment and Decrement) with Conditional Skip The operand is the memory addressed by the B register This mode automatically increments or decrements the B register (by 1 for bytes and by 2 for words) The B register is then compared with the K register A skip condition is generated if B goes past K ADDRESSING MODES DIRECT MEMORY AS DESTINATION Direct Memory to Direct Memory The instruction contains two 8- or 16-bit address fields One field directly points to the source operand and the other field directly points to the destination operand Immediate to Direct Memory The instruction contains an 8- or 16-bit address field and an 8- or 16-bit immediate field The immediate field is the operand and the direct field is the destination Double Register Indirect using the B and X Registers Used only with Reset Set and IF bit instructions a specific bit within the 64 kbyte address range is addressed using the B and X registers The address of a byte of memory is formed by adding the contents of the B register to the most significant 13 bits of the X register The specific bit to be modified or tested within the byte of memory is selected using the least significant 3 bits of register X Addressing Modes ADDRESSING MODES ACCUMULATOR AS DESTINATION Register Indirect This is the ‘‘normal’’ mode of addressing for the HPC46400E (instructions are single-byte) The operand is the memory addressed by the B register (or X register for some instructions) Direct The instruction contains an 8-bit or 16-bit address field that directly points to the memory for the operand 23 HPC Instruction Set Description Mnemonic ADD ADDS ADC DADC SUBC DSUBC MULT DIV DIVD IFEQ IFGT AND OR XOR INC DECSZ BIT INSTRUCTIONS SBIT RBIT IFBIT LD ST X PUSH POP LDS XS Set bit Reset bit If bit Load Load incr decr X Store to Memory Exchange Exchange incr decr X Push Memory to Stack Pop Stack to Memory Load A incr decr B Skip on condition Exchange incr decr B Skip on condition Load A immediate Load B immediate Load K immediate Load X immediate Load B and K immediate Clear A Increment A Decrement A Complement A Swap nibbles of A Rotate A right thru C Rotate A left thru C Shift A right Shift A left Set C Reset C IF C IF not C 1 x Mem bit (bit is 0 to 7 immediate) 0 x Mem bit If Mem bit is true do next instr MemI x MA Mem(X) x A X g 1 (or 2) x X MA x Mem A Mem Mem Mem A Mem(X) X g 1 (or 2) x X W x W(SP) SP a 2 x SP SPb2 x SP W(SP) x W Mem(B) x A B g 1 (or 2) x B Skip next if B greater less than K Mem(B) A B g 1 (or 2) x B Skip next if B greater less than K imm x A imm x B imm x K imm x X imm x B imm x K 0xA A a 1xA A b 1xA 1’s complement of A x A A15 12 w A11 8 w A7 4 A3 0 C x A15 x x A0 x C C w A15 w w A0 w C 0 x A15 x x A0 x C C w A15 w w A0 w 0 1xC 0xC Do next if C e 1 Do next if C e 0 Description Add Add short imm8 Add with carry Decimal add with carry Subtract with carry Decimal subtract w carry Multiply (unsigned) Divide (unsigned) Divide Double Word (unsigned) If equal If greater than Logical and Logical or Logical exclusive-or Increment Decrement skip if 0 Action MA a MemI x MA MA a imm8 x MA MA a MemI a C x MA MA a MemI a C x MA (Decimal) MAbMemI a C x MA MAbMemI a C x MA (Decimal) MA MemI x MA X 0 x K 0 x C MA MemI x MA rem x X 0 x K 0 x C (x8 MA) MemI x MA rem x X 0 x K Compare MA MemI Do next if equal Compare MA MemI Do next if MA x MemI MA and MemI x MA MA or MemI x MA MA xor MemI x MA Mem a 1 x Mem Mem b1 x Mem Skip next if Mem e 0 carry x C carry x C carry x C carry x C carry x C carry x C carry x C ARITHMETIC INSTRUCTIONS MEMORY MODIFY INSTRUCTIONS MEMORY TRANSFER INSTRUCTIONS REGISTER LOAD IMMEDIATE INSTRUCTIONS LD A LD B LD K LD X LD BK CLR A INC A DEC A COMP A SWAP A RRC A RLC A SHR A SHL A SC RC IFC IFNC ACCUMULATOR AND C INSTRUCTIONS 24 HPC Instruction Set Description (Continued) Mnemonic Description Action PC x W(SP) SP a 2 x SP W(table ) x PC PC x W(SP) SP a 2 x SP PC a x PC ( is a 1024 to b1023) PC x W(SP) SP a 2 x SP PC a x PC PC a x PC( is a 32 to b31) PC a x PC( is a 256 to b255) PC a x PC PC a A a 1 x PC then Mem(PC) a PC x PC PC w PC a 1 SPb2 x SP W(SP) x PC SPb2 x SP W(SP) x PC skip SPb2 x SP W(SP) x PC interrupt re-enabled TRANSFER OF CONTROL INSTRUCTIONS JSRP JSR JSRL JP JMP JMPL JID JIDW NOP RET RETS RETI Jump subroutine from table Jump subroutine relative Jump subroutine long Jump relative short Jump relative Jump relative long Jump indirect at PC a A No Operation Return Return then skip next Return from interrupt Note W is 16-bit word of memory MA is Accumulator A or direct memory (8-bit or 16-bit) Mem is 8-bit byte or 16-bit word of memory MemI is 8-bit or 16-bit memory or 8-bit or 16-bit immediate data imm is 8-bit or 16-bit immediate data Memory Usage For information on memory usage and instruction timing please refer to the HPC46400E User’s Manual (See page 25 for ordering information) 3 Compare the B register to the K register 4 Generate a conditional skip if B has passed K The value of this multipurpose instruction becomes evident when looping through sequential areas of memory and exiting when the loop is finished BIT MANIPULATION INSTRUCTIONS Any bit of memory I O or registers can be set reset or tested by the single byte bit instructions The bits can be addressed directly or indirectly Since all registers and I O are mapped into the memory it is very easy to manipulate specific bits to do efficient control DECIMAL ADD AND SUBTRACT This instruction is needed to interface with the decimal user world It can handle both 16-bit words and 8-bit bytes The 16-bit capability saves code since many variables can be stored as one piece of data and the programmer does not have to break his data into two bytes Many applications store most data in 4-digit variables The HPC46400E supplies 8-bit byte capability for 2-digit variables and literal variables MULTIPLY AND DIVIDE INSTRUCTIONS The HPC46400E has 16-bit multiply 16-bit by 16-bit divide and 32-bit by 16-bit divide instructions This saves both code and time Multiply and divide can use immediate data or data from memory The ability to multiply and divide by immediate data saves code since this function is often needed for scaling base conversion computing indexes of arrays etc Code Efficiency The HPC46400E has been designed to be extremely codeefficient The HPC46400E looks very good in all the standard coding benchmarks however it is not realistic to rely only on benchmarks Many large jobs have been programmed onto the HPC46400E and the code savings over other popular microcontrollers has been considerable Reasons for this saving of code include the following SINGLE BYTE INSTRUCTIONS The majority of instructions on the HPC46400E are singlebyte There are two especially code-saving instructions JP is a 1-byte jump True it can only jump within a range of plus or minus 32 but many loops and decisions are often within a small range of program memory Most other micros need 2-byte instructions for any short jumps JSRP is a 1-byte call subroutine The user makes a table of his 16 most frequently called subroutines and these calls will only take one byte Most other micros require two and even three bytes to call a subroutine The user does not have to decide which subroutine addresses to put into his table the assembler can give him this information EFFICIENT SUBROUTINE CALLS The 2-byte JSR instructions can call any subroutine within plus or minus 1k of program memory MULTIFUNCTION INSTRUCTIONS FOR DATA MOVEMENT AND PROGRAM LOOPING The HPC46400E has single-byte instructions that perform multiple tasks For example the XS instruction will do the following 1 Exchange A and memory pointed to by the B register 2 Increment or decrement the B register 25 Part Selection The HPC family includes devices with many different options and configurations to meet various application needs The number HPC46400E has been generally used throughout this datasheet to represent the whole family of parts The following chart explains how to order various options available when ordering HPC family members Note All options may not currently be available Development Support HPC MICROCONTROLLER DEVELOPMENT SYSTEM The HPC microcontroller development system is an in-system emulator (ISE) designed to support the entire family of HPC Microcontrollers The complete package of hardware and software tools combined with a host system provides a powerful system for design development and debug of HPC based designs Software tools are available for IBM PC-AT (MS-DOS PC-DOS) and for UNIX based multiuser Sun SPARCstation (SunOS TM ) The stand alone unit comes complete with a power supply and external emulation POD This unit can be connected to various host systems through an RS-232 link The software package includes an ANSI compatible C-Compiler Linker Assembler and librarian package Source symbolic debug capability is provided through a user friendly MS-windows 3 0 interface for IBM PC-AT environment and through a line debugger under Sunview for Sun SPARCstations The ISE provides fully transparent in-system emulation at speeds up to 20 MHz 1 waitstate A 2K word (48-bit wide) trace buffer gives trace trigger and non intrusive monitoring of the system External triggering is also available through an external logic interface socket on the POD Comprehensive on-line help and diagnostics features reduce user’s design and debug time 8 hardware breakpoints (Address range) 64 kbytes of user memory and break on external events are some of the other features offered Hewlett Packard model HP64775 Emulator Analyzer providing in-system emulation for up to 30 MHz 1 waitstate is also available Contact your local sales office for technical details and support HPC46400E V 20 Speed In MHz Package Type V e Plastic Chip Carrier (PLCC) VHG e Plastic Quad Flat Pack (PQFP) Temperature 4 e Commercial (0 C TO a 70 C) 3 e Industrial (b40 C to a 85 C) FIGURE 15 HPC Family Part Numbering Scheme EXAMPLES HPC46400EV20 HPC36400EV20 Commercial temp (0 to a 70 C) PLCC Industrial temp (b40 C to a 85 C) PLCC Development Tools Selection Table Product Order Part Number HPC-DEV-ISE2 HPC-DEV-ISE2-E HPC-DEV-IBMA HPC-DEV-IBMC Description HPC In-System Emulator HPC In-System Emulator for Europe and South East Asia Assembler Linker Library Package for IBM PC-AT Included HPC MDS User’s Manual HPC46400E User’s Manual Manual Number 420420184-001 420420213-001 HPC Assembler Linker Librarian User’s Manual for IBM PC-AT 424410836-001 424410883-001 424410836-001 424420189-001 424410883-001 424410836-001 424410883-001 424410836-001 424420189-001 424410883-001 424410836-001 C Compiler Assembler HPC C Compiler User’s Manual Linker Library Package for IBM PC-AT HPC Assembler Linker Librarian User’s Manual Source Symbolic Debugger for IBM PC-AT C Compiler Assembler Linker Library Package for IBM PC-AT C Compiler Assembler Linker Library Package for Sun SPARCstation HPC Source Symbolic Debugger User’s Manual HPC C Compiler User’s Manual HPC Assembler Linker Librarian User’s Manual HPC C Compiler User’s Manual HPC Assembler Linker Library User’s Manual Source Symbolic Debugger User’s Manual HPC C Compiler User’s Manual HPC Assembler Linker Library User’s Manual HPC-DEV-WDBC HPC46400E HPC-DEV-SUNC HPC-DEV-SUNDB Source Symbolic Debugger C Compiler Assembler Linker Library Package for Sun SPARCstation 26 Development Support (Continued) Development Tools Selection Table (Continued) Product Order Part Number Description Complete System HPC-DEV-SYS2 HPC In-System Emulator with C Compiler Assembler Linker Library and Source Symbolic Debugger Same for Europe and South East Asia HPC Microcontroller Development System User’s Manual HPC 46400E User’s Manual C-Compiler Manual Assembler Manual Debugger User’s Manual DIAL-A-HELPER Dial-A-Helper is a service provided by the Microcontroller Applications Group Dial-A-Helper is an electronic bulletin board information system and additionally provides the capability of remotely accessing the development system at a customer site INFORMATION SYSTEM The Dial-A-Helper system provides access to an automated information storage and retrieval system that may be accessed over standard dial-up telephone lines 24 hours a day The system capabilities include a MESSAGE SECTION (electronic mail) for communications to and from the Microcontroller Applications Group and a FILE SECTION which consists of several file areas where valuable application software and utilities can be found The minimum requirement for accessing Dial-A-Helper is a Hayes compatible modem If the user has a PC with a communications package then files from the FILE SECTION can be down loaded to disk for later use Order P N MOLE-DIAL-A-HLP Information System Package Contains Dial-A-Helper Users Manual Public Domain Communications Software FACTORY APPLICATIONS SUPPORT Dial-A-Helper also provides immediate factory applications support If a user is having difficulty in operating a development system he can leave messages on our electronic bulletin board which we will respond to Voice (408) 721-5582 Modem (408) 739-1162 Baud 300 or 1200 baud Set-Up Length 8-Bit Parity None Stop Bit 1 Operation 24 Hrs 7 Days 420420184-001 Included Manual Number HPC-DEV-SYS2-E HPC46400E 420420213-001 424410883-001 424410836-001 424420189-001 27 28 Physical Dimensions inches (millimeters) Plastic Chip Carrier (V) Order Number HPC46400EV or HPC36400EV NS Package Number V68A 29 HPC36400E HPC46400E High-Performance Communications MicroController Physical Dimensions inches (millimeters) (Continued) Plastic Quad Flat Pack (PQFP) Order Number NS Package Number VHG80A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical 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