LM1851M

LM1851 Ground Fault Interrupter June 1992 LM1851 Ground Fault Interrupter General Description The LM1851 is designed to provide ground fault protection for AC power outlets in consumer and industrial environments Ground fault currents greater than a presettable threshold value will trigger an external SCR-driven circuit breaker to interrupt the AC line and remove the fault condition In addition to detection of conventional hot wire to ground faults the neutral fault condition is also detected Full advantage of the U S UL943 timing specification is taken to insure maximum immunity to false triggering due to line noise Special features include circuitry that rapidly resets the timing capacitor in the event that noise pulses introduce unwanted charging currents and a memory circuit that allows firing of even a sluggish breaker on either half-cycle of the line voltage when external full-wave rectification is used Features Y Y Y Y Y Y Internal power supply shunt regulator Externally programmable fault current threshold Externally programmable fault current integration time Direct interface to SCR Operates under line reversal both load vs line and hot vs neutral Detects neutral line faults Block and Connection Diagram TL H 5177 – 1 Order Number LM1851M or LM1851N See NS Package Number M08A or N08E C1995 National Semiconductor Corporation TL H 5177 RRD-B30M115 Printed in U S A Absolute Maximum Ratings If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Current Power Dissipation (Note 1) Operating Temperature Range Storage Temperature Range 19 mA 1250 mW b 40 C to a 70 C b 55 C to a 150 C Soldering Information Dual-In-Line Package (10 sec ) Small Outline Package Vapor Phase (60 sec ) Infrared (15 sec ) 260 C 215 C 220 C See AN-450 ‘‘Surface Mounting and Their Effects on Product Reliability’’ for other methods of soldering surface mount devices DC Electrical Characteristics Parameter Power Supply Shunt Regulator Voltage Latch Trigger Voltage Sensitivity Set Voltage Output Drive Current Output Saturation Voltage Output Saturation Resistance Output External Current Sinking Capability Noise Integration Sink Current Ratio TA e 25 C ISS e 5 mA Conditions Min 22 15 6 05 Typ 26 17 5 7 1 100 100 20 5 Max 30 20 82 24 240 Units V V V mA mV X mA Pin 8 Average Value Pin 7 Pin 8 to Pin 6 Pin 1 With Fault Pin 1 Without Fault Pin 1 Without Fault Pin 1 Without Fault Vpin 1 Held to 0 3V (Note 4) Pin 7 Ratio of Discharge Currents Between No Fault and Fault Conditions 20 28 36 mA mA AC Electrical Characteristics TA e 25 C Parameter Normal Fault Current Sensitivity Normal Fault Trip Time Normal Fault with Grounded Neutral Fault Trip Time Conditions ISS e 5 mA Min 3 Typ 5 18 18 Max 7 Units mA ms ms Figure 1 (Note 3) 500X Fault Figure 2 (Note 2) 500X Normal Fault 2X Neutral Figure 2 (Note 2) Note 1 For operation in ambient temperatures above 25 C the device must be derated based on a 125 C maximum junction temperature and a thermal resistance of 80 C W junction to ambient for the DIP and 162 C W for the SO Package Note 2 Average of 10 trials Note 3 Required UL sensitivity tolerance is such that external trimming of LM1851 sensitivity will be necessary Note 4 This externally applied current is in addition to the internal ‘‘output drive current’’ source TL H 5177 – 2 FIGURE 1 Normal Fault Sensitivity Test Circuit 2 Internal Schematic Diagram TL H 5177 – 3 3 Typical Performance Characteristics Average Trip Time vs Fault Current Normal Fault Current Threshold vs RSET Output Drive Current vs Output Voltage Pin 1 Saturation Voltage vs External Load Current IL TL H 5177 – 4 Circuit Description (Refer to Block and Connection Diagram) The LM1851 operates from 26V as set by an internal shunt regulator D3 In the absence of a fault (If e 0) the feedback path status signal (VS) is correspondingly zero Under these conditions the capacitor discharge current I1 sits quiescently at three times its threshold value ITH so that noise induced charge on the timing capacitor will be rapidly removed When a fault current If is induced in the secondary of the external sense transformer the operational amplifier A1 uses feedback to force a virtual ground at the input as it extracts If The presence of If during either half-cycle will cause VS to go high which in turn changes I1 from 3ITH to ITH Although ITH discharges the timing capacitor during both half-cycles of the line If only charges the capacitor during the half-cycle in which If exits pin 2 Thus during one half-cycle If –ITH charges the timing capacitor while during the other half-cycle ITH discharges it When the capacitor voltage reaches 17 5V the latch engages and turns off Q3 permitting I2 to drive the gate of an SCR 4 Application Circuits A typical ground fault interrupter circuit is shown in Figure 2 It is designed to operate on 120 VAC line voltage with 5 mA normal fault sensitivity A full-wave rectifier bridge and a 15k 2W resistor are used to supply the DC power required by the IC A 1 mF capacitor at pin 8 used to filter the ripple of the supply voltage and is also connected across the SCR to allow firing of the SCR on either half-cycle When a fault causes the SCR to trigger the circuit breaker is energized and line voltage is removed from the load At this time no fault current flows and the IC discharge current increases from ITH to 3ITH (see Circuit Description and Block Diagram) This quickly resets both the timing capacitor and the output latch At this time the circuit breaker can be reset and the line voltage again supplied to the load assuming the fault has been removed A 1000 1 sense transformer is used to detect the normal fault The fault current which is basically the difference current between the hot and neutral lines is stepped down by 1000 and fed into the input pins of the operational amplifier through a 10 mF capacitor The 0 0033 mF capacitor between pin 2 and pin 3 and the 200 pF between pins 3 and 4 are added to obtain better noise immunity The normal fault sensitivity is determined by the timing capacitor discharging current ITH ITH can be calculated by 7V d2 (1) ITH e RSET At the decision point the average fault current just equals the threshold current ITH If(rms) c 0 91 (2) ITH e 2 where If(rms) is the rms input fault current to the operational amp and the factor of 2 is due to the fact that If charges the timing capacitor only during one half-cycle while ITH discharges the capacitor continuously The factor 0 91 converts the rms value to an average value Combining equations (1) and (2) we have If(rms) c 0 91 For example to obtain 5 mA(rms) sensitivity for the circuit in Figure 2 we have 7V e 1 5M X (4) RSET e 5 mA c 0 91 1000 The correct value for RSET can also be determined from the characteristic curve that plots equation (3) Note that this is an approximate calculation the exact value of RSET depends on the specific sense transformer used and LM1851 tolerances Inasmuch as UL943 specifies a sensitivity ‘‘window’’ of 4 mA–6 mA provision should be made to adjust RSET on a per-product basis Independent of setting sensitivity the desired integration time can be obtained through proper selection of the timing capacitor Ct Due to the large number of variables involved proper selection of Ct is best done empirically The following design example then should only be used as a guideline Assume the goal is to meet UL943 timing requirements Also assume that worst case timing occurs during GF1 RSET e 7V (3) start-up (S1 closure) with both a heavy normal fault and a 2X grounded neutral fault present This situation is shown diagramatically below TL H 5177 – 5 UL943 specifies s25 ms average trip time under these conditions Calculation of Ct based upon charging currents due to normal fault only is as follows s 25 ms Specification b 3 ms GFI turn-on time (15k and 1 mF) b 8 ms Potential loss of one half-cycle due to fault current sense of half-cycles only b 4 ms Time required to open a sluggish circuit breaker s 10 ms Maximum integration time that could be allowed 8 ms Value of integration time that accommodates component tolerances and other variables IcT V where T e integration time V e threshold voltage Ct e I e average fault current into Ct Ie (5)  X 120 VAC(rms) RB J Y c XR RN G a RN Y J heavy fault current generated (swamps ITH) portion of fault current shunted around GFI c c  1000 turns J Y X 1 turn c 2J XY 1 Ct charging on halfcycles only (0 91) (6) XY rms to average conversion current division of input sense transformer therefore Ct e Ct e  500 J  1 6 120 c 04 a0 4 J  1000 J  2 J c 1 c 1 c (0 91) 17 5 ( c 0 0008 (7) 0 01 mF 5 Application Circuits (Continued) in practice the actual value of C1 will have to be modified to include the effects of the neutral loop upon the net charging current The effect of neutral loop induced currents is difficult to quantize but typically they sum with normal fault currents thus allowing a larger value of C1 For UL943 requirements 0 015 mF has been found to be the best compromise between timing and noise For those GFI standards not requiring grounded neutral detection a still larger value capacitor can be used and better noise immunity obtained The larger capacitor can be accommodated because RN and RG are not present allowing the full fault current I to enter the GFI In Figure 2 grounded neutral detection is accomplished by feeding the neutral coil with 120 Hz energy continuously and allowing some of the energy to couple into the sense transformer during conditions of neutral fault Typical Application Adjust RSET for desired sensitivity TL H 5177 – 6 FIGURE 2 120 Hz Neutral Transformer Approach 6 Definition of Terms Normal Fault An unintentional electrical path RB between the load terminal of the hot line and the ground as shown by the dashed lines Normal Fault plus Grounded Neutral Fault The combination of the normal fault and the grounded neutral fault as shown by the dashed lines TL H 5177 – 7 Grounded Neutral Fault An unintentional electrical path between the load terminal of the neutral line and the ground as shown by the dashed lines TL H 5177 – 9 TL H 5177 – 8 7 LM1851 Ground Fault Interrupter Physical Dimensions inches (millimeters) Molded Dual-In-Line Package (N) Order Number LM1851N NS Package Number N08E LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user National Semiconductor Corporation 1111 West Bardin Road Arlington TX 76017 Tel 1(800) 272-9959 Fax 1(800) 737-7018 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor Europe Fax (a49) 0-180-530 85 86 Email cnjwge tevm2 nsc com Deutsch Tel (a49) 0-180-530 85 85 English Tel (a49) 0-180-532 78 32 Fran ais Tel (a49) 0-180-532 93 58 Italiano Tel (a49) 0-180-534 16 80 National Semiconductor Hong Kong Ltd 13th Floor Straight Block Ocean Centre 5 Canton Rd Tsimshatsui Kowloon Hong Kong Tel (852) 2737-1600 Fax (852) 2736-9960 National Semiconductor Japan Ltd Tel 81-043-299-2309 Fax 81-043-299-2408 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications