LM20123MHX

LM20123 3A, 1.5MHz PowerWise® Synchronous Buck Regulator January 16, 2008 LM20123 3A, 1.5MHz PowerWise® Synchronous Buck Regulator General Description The LM20123 is a full featured 1.5 MHz synchronous buck regulator capable of delivering up to 3A of continuous output current. The current mode control loop can be compensated to be stable with virtually any type of output capacitor. For most cases, compensating the device only requires two external components, providing maximum flexibility and ease of use. The device is optimized to work over the input voltage range of 2.95V to 5.5V making it suited for a wide variety of low voltage systems. The device features internal over voltage protection (OVP) and over current protection (OCP) circuits for increased system reliability. A precision enable pin and integrated UVLO allows the turn on of the device to be tightly controlled and sequenced. Start-up inrush currents are limited by both an internally fixed and externally adjustable Soft-Start circuit. Fault detection and supply sequencing is possible with the integrated power good circuit. The LM20123 is designed to work well in multi-rail power supply architectures. The output voltage of the device can be configured to track a higher voltage rail using the SS/TRK pin. If the output of the LM20123 is pre-biased at startup it will not sink current to pull the output low until the internal soft-start ramp exceeds the voltage at the feedback pin. The LM20123 is offered in a 16-pin eTSSOP package with an exposed pad that can be soldered to the PCB, eliminating the need for bulky heatsinks. Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Input voltage range 2.95V to 5.5V Accurate current limit minimizes inductor size 96% efficiency with 1.5 MHz switching frequency 32 mΩ integrated FET switches Starts up into pre-biased loads Output voltage tracking Peak current mode control Adjustable output voltage down to 0.8V Adjustable Soft-Start with external capacitor Precision enable pin with hysteresis Integrated OVP, UVLO, power good and thermal shutdown ■ eTSSOP-16 exposed pad package Applications ■ Simple to design, high efficiency point of load regulation from a 5V or 3.3V bus microprocessors Infrastructure ■ High Performance DSPs, FPGAs, ASICs and ■ Broadband, Networking and Optical Communications Typical Application Circuit 30030101 PowerWise® is a registered trademark of National Semiconductor Corporation. © 2008 National Semiconductor Corporation 300301 www.national.com LM20123 Connection Diagram 30030102 Top View eTSSOP-16 Package Ordering Information Order Number LM20123MH LM20123MHE LM20123MHX Package Type eTSSOP-16 NSC Package Drawing MXA16A Package Marking 20123MH Supplied As 92 Units of Rail 250 Units of Tape and Reel 2500 Units of Tape and Reel Pin Descriptions Pin # 1 Name SS/TRK Description Soft-Start or Tracking control input. An internal 5 µA current source charges an external capacitor to set the Soft-Start ramp rate. If driven by a external source less than 800 mV, this pin overrides the internal reference that sets the output voltage. If left open, an internal 1ms Soft-Start ramp is activated. Feedback input to the error amplifier from the regulated output. This pin is connected to the inverting input of the internal transconductance error amplifier. An 800 mV reference connected to the noninverting input of the error amplifier sets the closed loop regulation voltage at the FB pin. Power good output signal. Open drain output indicating the output voltage is regulating within tolerance. A pull-up resistor of 10 kΩ to 100 kΩ is recommend for most applications. External compensation pin. Connect a resistor and capacitor to this pin to compensate the device. These pins must be connected to GND to ensure proper operation. Input voltage to the power switches inside the device. These pins should be connected together at the device. A low ESR capacitor should be placed near these pins to stabilize the input voltage. Switch pin. The PWM output of the internal power switches. Power ground pin for the internal power switches. Precision enable input for the device. An external voltage divider can be used to set the device turnon threshold. If not used the EN pin should be connected to PVIN. Internal 2.7V sub-regulator. This pin should be bypassed with a 1 µF ceramic capacitor. Analog input supply that generates the internal bias. Must be connected to VIN through a low pass RC filter. Quiet analog ground for the internal bias circuitry. Exposed metal pad on the underside of the package with a weak electrical connection to ground. It is recommended to connect this pad to the PC board ground plane in order to improve heat dissipation. 2 FB 3 4 5,16 6,7 8,9 10,11 12 13 14 15 EP PGOOD COMP NC PVIN SW PGND EN VCC AVIN AGND Exposed Pad www.national.com 2 LM20123 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Voltages from the indicated pins to GND AVIN, PVIN, EN, PGOOD, SS/ TRK, COMP, FB, SW Storage Temperature Junction Temperature -0.3V to +6V -65°C to 150°C 150°C Power Dissipation (Note 2) Lead Temperature (Soldering, 10 sec) Minimum ESD Rating (Note 3) 2.6W 260°C ±2kV Operating Ratings PVIN, AVIN to GND Junction Temperature 2.95V to 5.5V −40°C to + 125°C Electrical Characteristics Unless otherwise stated, the following conditions apply: AVIN = PVIN = VIN = 5V. Limits in standard type are for TJ = 25°C only, limits in bold face type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are guaranteed through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Symbol VFB ΔVOUT/ΔIOUT ICL RDS_ON RDS_ON IQ ISD VUVLO VUVLO_HYS VVCC ISS VTRACK Oscillator FOSC DCMAX TON_TIME TCL_BLANK IFB ICOMP_SRC ICOMP_SNK gm AVOL Power Good VOVP VOVP_HYS VPGTH VPGHYS TPGOOD IOL IOH Over Voltage Protection Rising Threshold Over Voltage Protection Hysteresis PGOOD Rising Threshold PGOOD Falling Hysteresis PGOOD deglitch time PGOOD Low Sink Current PGOOD High Leakage Current VPGOOD = 0.4V VPGOOD = 5V 0.6 With respect to VFB 92 With respect to VFB 105 108 2 94 2 16 1 5 100 111 3 96 3 % % % % µs mA nA Oscillator Frequency Maximum Duty Cycle Minimum On Time Current Sense Blanking Time Feedback pin bias current COMP Output Source Current COMP Output Sink Current Error Amplifier Transconductance Error Amplifier Voltage Gain After Rising VSW VFB = 0.8V VFB = VCOMP = 0.6V VFB = 1.0V, VCOMP = 0.6V ICOMP = ± 50 µA 80 80 450 ILOAD = 0A 1350 1500 1650 85 100 80 1 100 100 510 2000 600 100 kHz % ns ns nA µA µA µmho V/V Parameter Feedback pin voltage Load Regulation Switch Current Limit Threshold High-Side Switch On Resistance Low-Side Switch On Resistance Operating Quiescent Current Shutdown Quiescent current VIN Under Voltage Lockout VIN Under Voltage Lockout Hysteresis VCC Voltage Soft-Start Pin Source Current SS/TRK Accuracy, VSS - VFB Conditions VIN = 2.95V to 5.5V IOUT = 100 mA to 3A VIN = 3.3V ISW = 3.5A ISW = 3.5A Non-switching, VFB = VCOMP VEN = 0V Rising VIN Falling VIN IVCC = 0 µA VSS/TRK = 0V VSS/TRK = 0.4V 2.45 2 -10 2.45 4.3 Min 0.788 Typ 0.8 0.08 4.8 36 32 3.5 90 2.7 45 2.7 4.5 3 5.3 55 52 6 180 2.95 100 2.95 7 15 Max 0.812 Unit V %/A A mΩ mΩ mA µA V mV V µA mV Error Amplifier and Modulator 3 www.national.com LM20123 Symbol Logic VIH_EN VEN_HYS TSD TSD_HYS θJA Parameter EN Pin Turn on Threshold EN Pin Hysteresis Thermal Shutdown Thermal Shutdown Hysteresis Junction to Ambient Conditions VEN Rising Min 1.08 Typ 1.18 66 160 10 38 Max 1.28 Unit V mV °C °C °C/W Thermal Shutdown Thermal Resistance Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. Note 2: The maximum allowable power dissipation is a function of the maximum junction temperature, TJ_MAX, the junctions-to-ambient thermal resistance, θJA, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is calculated using: PD_MAX = (TJ_MAX – TA)/θJA. The maximum power dissipations of 2.6W is determined using TA = 25°C, θJA = 38°C/W, and TJ_MAX = 125°C. Note 3: The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor to each pin. Typical Performance Characteristics Unless otherwise specified: CIN = COUT = 100 µF, L = 1.0 µH (Coilcraft MSS1038), VIN = 5V, VOUT = 1.2V, RLOAD = 1.2Ω, TA = 25°C for efficiency curves, loop gain plots and waveforms, and TJ = 25°C for all others. Efficiency vs. Load Current (VIN = 5V) Efficiency vs. Load Current (VIN = 3.3V) 30030131 30030130 High-Side FET resistance vs. Temperature Low-Side FET resistance vs. Temperature 30030152 30030153 www.national.com 4 LM20123 Error Amplifier Gain vs. Frequency Line Regulation 30030136 30030137 Load Regulation Feedback Pin Voltage vs. Temperature 30030138 30030151 Switching Frequency vs. Temperature Quiescent Current vs. VIN (Not Switching) 30030139 30030140 5 www.national.com LM20123 Shutdown Current vs. Temperature Enable Threshold vs. Temperature 30030141 30030128 UVLO Threshold vs. Temperature Peak Current Limit vs. Temperature 30030145 30030142 Peak Current Limit vs. VOUT Peak Current Limit vs. VIN 30030154 30030155 www.national.com 6 LM20123 Load Transient Response Line Transient Response 30030134 30030143 Start-Up (Soft-Start) Start-Up (Tracking) 30030144 30030133 Power Down Short Circuit Input Current vs VIN 30030132 30030156 7 www.national.com LM20123 VPGOOD vs. IPGOOD 30030127 www.national.com 8 LM20123 Block Diagram 30030103 9 www.national.com LM20123 Operation Description GENERAL The LM20123 switching regulator features all of the functions necessary to implement an efficient low voltage buck regulator using a minimum number of external components. This easy to use regulator features two integrated switches and is capable of supplying up to 3A of continuous output current. The regulator utilizes peak current mode control with nonlinear slope compensation to optimize stability and transient response over the entire output voltage range. Peak current mode control also provides inherent line feed-forward, cycleby-cycle current limiting and easy loop compensation. The fixed 1.5 MHz operating frequency minimizes the inductor size while still achieving efficiencies up to 96%. The precision internal voltage reference allows the output to be set as low as 0.8V. Fault protection features include: current limiting, thermal shutdown, over voltage protection, and shutdown capability. The device is available in the eTSSOP-16 package featuring an exposed pad to aid thermal dissipation. The LM20123 can be used in numerous applications to efficiently step-down from a 5V or 3.3V bus. The typical application circuit for the LM20123 is shown in Figure 2 in the design guide. PRECISION ENABLE The enable (EN) pin allows the output of the device to be enabled or disabled with an external control signal. This pin is a precision analog input that enables the device when the voltage exceeds 1.18V (typical). The EN pin has 66 mV of hysteresis and will disable the output when the enable voltage falls below 1.11V (typical). If the EN pin is not used, it should be connected to VIN. Since the enable pin has a precise turn on threshold it can be used along with an external resistor divider network from VIN to configure the device to turn on at a precise input voltage. The precision enable circuitry will remain active even when the device is disabled. PEAK CURRENT MODE CONTROL In most cases, the peak current mode control architecture used in the LM20123 only requires two external components to achieve a stable design. The compensation can be selected to accommodate any capacitor type or value. The external compensation also allows the user to set the crossover frequency and optimize the transient performance of the device. For duty cycles above 50% all current mode control buck converters require the addition of an artificial ramp to avoid sub-harmonic oscillation. This artificial linear ramp is commonly referred to as slope compensation. What makes the LM20123 unique is the amount of slope compensation will change depending on the output voltage. When operating at high output voltages the device will have more slope compensation than when operating at lower output voltages. This is accomplished in the LM20123 by using a non-linear parabolic ramp for the slope compensation. The parabolic slope compensation of the LM20123 is much better than the traditional linear slope compensation because it optimizes the stability of the device over the entire output voltage range. CURRENT LIMIT The precise current limit of the LM20123 is set at the factory to be within 10% over the entire operating temperature range. This enables the device to operate with smaller inductors that have lower saturation currents. When the peak inductor current reaches the current limit threshold, an over current event is triggered and the internal high-side FET turns off and the low-side FET turns on allowing inductor current to ramp down until the next switching cycle. For each sequential over-curwww.national.com 10 rent event, the reference voltage is decremented and PWM pulses are skipped resulting in a current limit that does not aggressively fold back for brief over-current events, while at the same time providing frequency and voltage foldback protection during hard short circuit conditions. SOFT-START AND VOLTAGE TRACKING The SS/TRK pin is a dual function pin that can be used to set the start up time or track an external voltage source. The start up or Soft-Start time can be adjusted by connecting a capacitor from the SS/TRK pin to ground. The Soft-Start feature allows the regulator output to gradually reach the steady state operating point, thus reducing stresses on the input supply and controlling start up current. If no Soft-Start capacitor is used the device defaults to the internal Soft-Start circuitry resulting in a start up time of approximately 1 ms. For applications that require a monotonic start up or utilize the PGOOD pin, an external Soft-Start capacitor is recommended. The SS/TRK pin can also be set to track an external voltage source. The tracking behavior can be adjusted by two external resistors connected to the SS/TRK pin as shown in Figure 7 in the design guide. PRE-BIAS START UP CAPABILITY The LM20123 is in a pre-biased state when the device starts up with an output voltage greater than zero. This often occurs in many multi-rail applications such as when powering an FPGA, ASIC, or DSP. In these applications the output can be pre-biased through parasitic conduction paths from one supply rail to another. Even though the LM20123 is a synchronous converter it will not pull the output low when a prebias condition exists. During startup the LM20123 will not sink current until the Soft-Start voltage exceeds the voltage on the FB pin. Since the device can not sink current it protects the load from damage that might otherwise occur if current is conducted through the parasitic paths of the load. POWER GOOD AND OVER VOLTAGE FAULT HANDLING The LM20123 has built in under and over voltage comparators that control the power switches. Whenever there is an excursion in output voltage above the set OVP threshold, the part will terminate the present on-pulse, turn on the low side FET, and pull the PGOOD pin low. The low side FET will remain on until either the FB voltage falls back into regulation or the zero cross detection is triggered which in turn tri-states the FETs. If the output reaches the UVP threshold the part will continue switching and the PGOOD pin will be asserted and go low. Typical values for the PGOOD resistor are on the order of 100 kΩ or less. To avoid false tripping during transient glitches the PGOOD pin has 16 µs of built in deglitch time to both rising and falling edges. UVLO The LM20123 has a built-in under-voltage lockout protection circuit that keeps the device from switching until the input voltage reaches 2.7V (typical). The UVLO threshold has 45 mV of hysteresis that keeps the device from responding to power-on glitches during start up. If desired, the turn-on point of the supply can be changed by using the precision enable pin and a resistor divider network connected to VIN as shown in Figure 6 in the design guide. THERMAL PROTECTION Internal thermal shutdown circuitry is provided to protect the integrated circuit in the event that the maximum junction temperature is exceeded. When activated, typically at 160°C, the LM20123 tri-states the power FETs and resets soft start. After LM20123 the junction cools to approximately 150°C, the part starts up using the normal start up routine. This feature is provided to prevent catastrophic failures from accidental device overheating. LIGHT LOAD OPERATION The LM20123 offers increased efficiency when operating at light loads. Whenever the load current is reduced to a point where the peak to peak inductor ripple current is greater than two times the load current, the part will enter the diode emulation mode preventing significant negative inductor current. The point at which this occurs is the critical conduction boundary and can be calculated by the following equation: Several diagrams are shown in Figure 1 illustrating continuous conduction mode (CCM), discontinuous conduction mode, and the boundary condition. It can be seen that in diode emulation mode, whenever the inductor current reaches zero the SW node will become high impedance. Ringing will occur on this pin as a result of the LC tank circuit formed by the inductor and the parasitic capacitance at the node. If this ringing is of concern an additional RC snubber circuit can be added from the switch node to ground. At very light loads, usually below 100 mA, several pulses may be skipped in between switching cycles, effectively reducing the switching frequency and further improving light-load efficiency. 30030105 FIGURE 1. Modes of Operation for LM20123 11 www.national.com LM20123 Design Guide This section walks the designer through the steps necessary to select the external components to build a fully functional power supply. As with any DC-DC converter numerous tradeoffs are possible to optimize the design for efficiency, size, or performance. These will be taken into account and highlighted throughout this discussion. To facilitate component selection discussions the circuit shown in Figure 2 below may be used as a reference. Unless otherwise indicated all formulas assume units of amps (A) for current, farads (F) for capacitance, henries (H) for inductance and volts (V) for voltages. 30030109 FIGURE 3. Switch and Inductor Current Waveforms If needed, slightly smaller value inductors can be used, however, the peak inductor current, IOUT + ΔiL/2, should be kept below the peak current limit of the device. In general, the inductor ripple current, ΔiL, should be greater than 10% of the rated output current to provide adequate current sense information for the current mode control loop. If the ripple current in the inductor is too low, the control loop will not have sufficient current sense information and can be prone to instability. OUTPUT CAPACITOR SELECTION (COUT) The output capacitor, COUT, filters the inductor ripple current and provides a source of charge for transient load conditions. A wide range of output capacitors may be used with the LM20123 that provide excellent performance. The best performance is typically obtained using ceramic, SP, or OSCON type chemistries. Typical trade-offs are that the ceramic capacitor provides extremely low ESR to reduce the output ripple voltage and noise spikes, while the SP and OSCON capacitors provide a large bulk capacitance in a small volume for transient loading conditions. When selecting the value for the output capacitor the two performance characteristics to consider are the output voltage ripple and transient response. The output voltage ripple can be approximated by using the formula shown below. 30030123 FIGURE 2. Typical Application Circuit The first equation to calculate for any buck converter is dutycycle. Ignoring conduction losses associated with the FETs and parasitic resistances it can be approximated by: INDUCTOR SELECTION (L) The inductor value is determined based on the operating frequency, load current, ripple current, and duty cycle. The inductor selected should have a saturation current rating greater than the peak current limit of the device. Keep in mind the specified current limit does not account for delay of the current limit comparator, therefore the current limit in the application may be higher than the specified value. To optimize the performance and prevent the device from entering current limit at maximum load, the inductance is typically selected such that the ripple current, ΔiL, is less than 30% of the rated output current. Figure 3, shown below illustrates the switch and inductor ripple current waveforms. Once the input voltage, output voltage, operating frequency, and desired ripple current are known, the minimum value for the inductor can be calculated by the formula shown below: Where, ΔVOUT (V) is the amount of peak to peak voltage ripple at the power supply output, RESR (Ω) is the series resistance of the output capacitor, fSW(Hz) is the switching frequency, and COUT (F) is the output capacitance used in the design. The amount of output ripple that can be tolerated is application specific; however a general recommendation is to keep the output ripple less than 1% of the rated output voltage. Keep in mind ceramic capacitors are sometimes preferred because they have very low ESR; however, depending on package and voltage rating of the capacitor the value of the capacitance can drop significantly with applied voltage. The output capacitor selection will also affect the output voltage droop during a load transient. The peak droop on the output voltage during a load transient is dependent on many factors; however, an approximation of the transient droop ignoring loop bandwidth can be obtained using the following equation. www.national.com 12 LM20123 Where, COUT (F) is the minimum required output capacitance, L (H) is the value of the inductor, VDROOP (V) is the output voltage drop ignoring loop bandwidth considerations, ΔIOUTSTEP (A) is the load step change, RESR (Ω) is the output capacitor ESR, VIN (V) is the input voltage, and VOUT (V) is the set regulator output voltage. Both the tolerance and voltage coefficient of the capacitor needs to be examined when designing for a specific output ripple or transient drop target. INPUT CAPACITOR SELECTION (CIN) Good quality input capacitors are necessary to limit the ripple voltage at the VIN pin while supplying most of the switch current during the on-time. In general it is recommended to use a ceramic capacitor for the input as they provide both a low impedance and small footprint. One important note is to use a good dielectric for the ceramic capacitor such as X5R or X7R. These provide better over temperature performance and minimize the DC voltage derating that occurs on Y5V capacitors. For many applications, a 22 µF, X5R, 6.3V input capacitor is sufficient; however, additional capacitance may be required if the connection to the input supply bulk is far from the PVIN pins. The input capacitor should be placed as close as possible PVIN and PGND pins of the device. Non-ceramic input capacitors should be selected for RMS current rating and minimum ripple voltage. A good approximation for the required ripple current rating is given by the relationship: capacitor, inductor, load, and the device itself. Table 2 below gives values for the compensation network that will result in a stable system when using a 100 µF, 6.3V ceramic X5R output capacitor and 1 µH inductor. TABLE 2. Recommended Compensation for COUT = 100 µF and L = 1 µH VIN 5.00 5.00 5.00 5.00 5.00 5.00 3.30 3.30 3.30 3.30 3.30 VOUT 3.30 2.50 1.80 1.50 1.20 0.80 2.50 1.80 1.50 1.20 0.80 CC1 (nF) RC1 (kΩ) 4.7 4.7 4.7 4.7 4.7 4.7 4.7 4.7 4.7 4.7 4.7 17.86 12.93 8.81 7 3.96 1.79 12.24 11.24 7.94 6.03 1.793 As indicated by the RMS ripple current equation, highest requirement for RMS current rating occurs at 50% duty cycle. For this case, the RMS ripple current rating of the input capacitor should be greater than half the output current. For best performance, low ESR ceramic capacitors should be placed in parallel with higher capacitance capacitors to provide the best input filtering for the device. SETTING THE OUTPUT VOLTAGE (RFB1, RFB2) The resistors RFB1 and RFB2 are selected to set the output voltage for the device. Table 1, shown below, provides suggestions for RFB1 and RFB2 for common output voltages. TABLE 1. Suggested Values for RFB1 and RFB2 RFB1(kΩ) short 4.99 8.87 12.7 21.5 31.6 RFB2(kΩ) open 10 10.2 10.2 10.2 10.2 VOUT 0.8 1.2 1.5 1.8 2.5 3.3 If the desired solution differs from the table above the loop transfer function should be analyzed to optimize the loop compensation. The overall loop transfer function is the product of the power stage and the feedback network transfer functions. For stability purposes, the objective is to have a loop gain slope that is -20db/decade from a very low frequency to beyond the crossover frequency. Figure 4, shown below, shows the transfer functions for power stage, feedback/compensation network, and the resulting closed loop system for the LM20123. If different output voltages are required, RFB2 should be selected to be between 4.99 kΩ to 49.9 kΩ and RFB1 can be calculated using the equation below. 30030113 FIGURE 4. LM20123 Loop Compensation LOOP COMPENSATION (RC1, CC1) The purpose of loop compensation is to meet static and dynamic performance requirements while maintaining adequate stability. Optimal loop compensation depends on the output 13 The power stage transfer function is dictated by the modulator, output LC filter, and load; while the feedback transfer www.national.com LM20123 function is set by the feedback resistor ratio, error amp gain, and external compensation network. To achieve a -20dB/decade slope, the error amplifier zero, located at fZ(EA), should positioned to cancel the output filter pole (fP(FIL)). An additional error amp pole, located at fP2(EA), can be added to cancel the output filter zero at fZ(FIL). Cancellation of the output filter zero is recommended if larger value, non-ceramic output capacitors are used. Compensation of the LM20123 is achieved by adding an RC network as shown in Figure 5 below. pins, a high frequency RC filter is required between PVIN and AVIN. These components are shown in Figure 2. as CF and RF. The required value for RF is 1Ω. CF must be used. Recommended value of CF is 1.0 µF. The filter capacitor, CF should be placed as close to the IC as possible with a direct connection from AVIN to AGND. A good quality X5R or X7R ceramic capacitor should be used for CF. SUB-REGULATOR BYPASS CAPACITOR (CVCC) The capacitor at the VCC pin provides noise filtering and stability for the internal sub-regulator. The recommended value of CVCC should be no smaller than 1 µF and no greater than 10 µF. The capacitor should be a good quality ceramic X5R or X7R capacitor. In general, a 1 µF ceramic capacitor is recommended for most applications. SETTING THE START UP TIME (CSS) The addition of a capacitor connected from the SS pin to ground sets the time at which the output voltage will reach the final regulated value. Larger values for CSS will result in longer start up times. Table 3, shown below provides a list of soft start capacitors and the corresponding typical start up times. TABLE 3. Start Up Times for Different Soft-Start Capacitors Start Up Time (ms) 1 5 10 15 20 CSS (nF) none 33 68 100 120 30030114 FIGURE 5. Compensation Network for LM20123 A good starting value for CC1 for most applications is 4.7 nF. Once the value of CC1 is chosen the value of RC1 should be calculated using the equation below to cancel the output filter pole (fP(FIL)) as shown in Figure 4. A higher crossover frequency can be obtained, usually at the expense of phase margin, by lowering the value of CC1 and recalculating the value of RC1. Likewise, increasing CC1 and recalculating RC1 will provide additional phase margin at a lower crossover frequency. As with any attempt to compensate the LM20123 the stability of the system should be verified for desired transient droop and settling time. If the output filter zero, fZ(FIL) approaches the crossover frequency (fC), an additional capacitor (CC2) should be placed at the COMP pin to ground. This capacitor adds a pole to cancel the output filter zero assuring the crossover frequency will occur before the double pole at fSW/2 degrades the phase margin. The output filter zero is set by the output capacitor value and ESR as shown in the equation below. If different start up times are needed the equation shown below can be used to calculate the start up time. If needed, the value for CC2 should be calculated using the equation shown below. As shown above, the start up time is influenced by the value of the Soft-Start capacitor CSS(F) and the 5 µA Soft-Start pin current ISS(A). that may be found in the electrical characteristics table. While the Soft-Start capacitor can be sized to meet many start up requirements, there are limitations to its size. The SoftStart time can never be faster than 1 ms due to the internal default 1 ms start up time. When the device is enabled there is an approximate time interval of 50 µs when the Soft-Start capacitor will be discharged just prior to the Soft-Start ramp. If the enable pin is rapidly pulsed or the Soft-Start capacitor is large there may not be enough time for CSS to completely discharge resulting in start up times less than predicted. To aid in discharging the Soft-Start capacitor during long disable periods an external 1 MΩ resistor from SS/TRK to ground can be used without greatly affecting the start-up time. USING PRECISION ENABLE AND POWER GOOD The precision enable (EN) and power good (PGOOD) pins of the LM20123 can be used to address many sequencing requirements. The turn-on of the LM20123 can be controlled with the precision enable pin by using two external resistors as shown in Figure 6. Where RESR is the output capacitor series resistance and RC1 is the calculated compensation resistance. AVIN FILTERING COMPONENTS (CF and RF) To prevent high frequency noise spikes from disturbing the sensitive analog circuitry connected to the AVIN and AGND www.national.com 14 LM20123 30030126 FIGURE 6. Sequencing LM20123 with Precision Enable The value for resistor RB can be selected by the user to control the current through the divider. Typically this resistor will be selected to be between 10 kΩ and 1 MΩ. Once the value for RB is chosen the resistor RA can be solved using the equation below to set the desired turn-on voltage. When designing for a specific turn-on threshold (VTO) the tolerance on the input supply, enable threshold (VIH_EN), and external resistors needs to be considered to insure proper turn-on of the device. The LM20123 features an open drain power good (PGOOD) pin to sequence external supplies or loads and to provide fault detection. This pin requires an external resistor (RPG) to pull PGOOD high while when the output is within the PGOOD tolerance window. Typical values for this resistor range from 10 kΩ to 100 kΩ. TRACKING AN EXTERNAL SUPPLY By using a properly chosen resistor divider network connected to the SS/TRK pin, as shown in Figure 7, the output of the LM20123 can be configured to track an external voltage source to obtain a simultaneous or ratiometric start up. 30030121 FIGURE 8. Common Start Up Sequences A simultaneous start up is preferred when powering most FPGAs, DSPs, or other microprocessors. In these systems the higher voltage, VOUT1, usually powers the I/O, and the lower voltage, VOUT2, powers the core. A simultaneous start up provides a more robust power up for these applications since it avoids turning on any parasitic conduction paths that may exist between the core and the I/O pins of the processor. The second most common power on behavior is known as a ratiometric start up. This start up is preferred in applications where both supplies need to be at the final value at the same time. Similar to the Soft-Start function, the fastest start up possible is 1ms regardless of the rise time of the tracking voltage. When using the track feature the final voltage seen by the SS/ TRACK pin should exceed 1V to provide sufficient overdrive and transient immunity. THERMAL CONSIDERATIONS The thermal characteristics of the LM20123 are specified using the parameter θJA, which relates the junction temperature to the ambient temperature. Although the value of θJA is dependent on many variables, it still can be used to approximate the operating junction temperature of the device. To obtain an estimate of the device junction temperature, one may use the following relationship: TJ = PDθJA + TA and PD = PIN x (1 - Efficiency) - 1.1 x IOUT2 x DCR Where: TJ is the junction temperature in °C. PIN is the input power in Watts (PIN = VIN x IIN). θJA is the junction to ambient thermal resistance for the LM20123. 15 www.national.com 30030120 FIGURE 7. Tracking an External Supply Since the Soft-Start charging current ISS is always present on the SS/TRK pin, the size of R2 should be less than 10 kΩ to minimize the errors in the tracking output. Once a value for R2 is selected the value for R1 can be calculated using appropriate equation in Figure 8, to give the desired start up. Figure 8 shows two common start up sequences; the top waveform shows a simultaneous start up while the waveform at the bottom illustrates a ratiometric start up. LM20123 TA is the ambient temperature in °C. IOUT is the output load current. DCR is the inductor series resistance. It is important to always keep the operating junction temperature (TJ) below 125°C for reliable operation. If the junction temperature exceeds 160°C the device will cycle in and out of thermal shutdown. If thermal shutdown occurs it is a sign of inadequate heatsinking or excessive power dissipation in the device. Figure 9., shown below, provides a better approximation of the θJA for a given PCB copper area. The PCB heatsink area consists of 2oz. copper located on the bottom layer of the PCB directly under the eTSSOP exposed pad. The bottom copper area is connected to the eTSSOP exposed pad by means of a 4 x 4 array of 12 mil thermal vias. 30030135 FIGURE 9. Thermal Resistance vs PCB Area PCB LAYOUT CONSIDERATIONS PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance of a DCDC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage loss in the traces. These can send erroneous signals to the DC-DC converter resulting in poor regulation or instability. Good layout can be implemented by following a few simple design rules. 1. Minimize area of switched current loops. In a buck regulator there are two loops where currents are switched very fast. The first loop starts from the input capacitor, to the regulator VIN pin, to the regulator SW pin, to the inductor then out to the output capacitor and load. The second loop starts from the output capacitor ground, to the regulator PGND pins, to the inductor and then out to the load (see Figure 10). To minimize both loop areas the input capacitor should be placed as close as possible to the PVIN pin. Grounding for both the input and output capacitor should consist of a small localized top side plane that connects to PGND and the die attach pad (DAP). The inductor should be placed as close as possible to the SW pin and output capacitor. 2. Minimize the copper area of the switch node. Since the LM20123 has the SW pins on opposite sides of the package it is recommended to via these pins down to the bottom or internal layer with 2 to 4 vias on each SW pin. The SW pins should be directly connected with a trace that runs across the bottom of the package. To minimize IR losses this trace should be no smaller that 50 mils wide, but no larger than 100 mils wide to keep the copper area to a minimum. In general the SW pins should not be connected on the top layer since it could block the ground return path for the power ground. The inductor should be placed as close as possible to one of the SW pins to further minimize the copper area of the switch node. 3. Have a single point ground for all device analog grounds located under the DAP. The ground connections for the compensation, feedback, and Soft-Start components should be connected together then routed to the AGND pin of the device. The AGND pin should connect to PGND under the DAP. This prevents any switched or load currents from flowing in the analog ground plane. If not properly handled poor grounding can result in degraded load regulation or erratic switching behavior. 4. Minimize trace length to the FB pin. Since the feedback node can be high impedance the trace from the output resistor divider to FB pin should be as short as possible. This is most important when high value resistors are used to set the output voltage. The feedback trace should be routed away from the SW pin and inductor to avoid contaminating the feedback signal with switch noise. 5. Make input and output bus connections as wide as possible. This reduces any voltage drops on the input or output of the converter and can improve efficiency. If voltage accuracy at the load is important make sure feedback voltage sense is made at the load. Doing so will correct for voltage drops at the load and provide the best output accuracy. 6. Provide adequate device heatsinking. Use as many vias as is possible to connect the DAP to the power plane heatsink. For best results use a 4x4 via array with a minimum via diameter of 12 mils. See the Thermal Considerations section to insure enough copper heatsinking area is used to keep the junction temperature below 125°C. 30030122 FIGURE 10. Schematic of LM20123 Highlighting Layout Sensitive Nodes www.national.com 16 LM20123 Typical Application Circuit This section provides several application solutions with a bill of materials. All bill of materials reference the below figure. The compensation for these solutions were optimized to work over a wide range of input and output voltages; if a faster transient response is needed reduce the value of CC1 and calculate the new value for RC1 as outline in the design guide. 30030101 FIGURE 11. Bill of Materials (VIN = 5V, VOUT = 3.3V, IOUTMAX = 3A) Designator U1 CIN COUT L RF CF CVCC RC1 CC1 CSS RFB1 RFB2 Description Synchronous Buck Regulator 47 µF, 1210, X5R, 6.3V 47 µF, 1210, X5R, 6.3V 1.2 µH, 17 mΩ 1Ω, 0603 100 nF, 0603, X7R, 16V 1 µF, 0603, X5R, 6.3V 8.45 kΩ, 0603 1.5 nF, 0603, X7R, 25V 33 nF, 0603, X7R, 25V 31.6 kΩ, 0603 10.2 kΩ, 0603 Part Number LM20123 GRM32ER60J476ME20 GRM32ER60J476ME20 DO1813H-122ML CRCW06031R0J-e3 GRM188R71C104KA01 GRM188R60J105KA01 CRCW06038451F-e3 VJ0603Y152KXXA VJ0603Y333KXXA CRCW06033162F-e3 CRCW06031022F-e3 Manufacturer National Semiconductor Murata Murata Coilcraft Vishay-Dale Murata Murata Vishay-Dale Vishay-Vitramon Vishay-Vitramon Vishay-Dale Vishay-Dale Qty 1 1 1 1 1 1 1 1 1 1 1 1 Bill of Materials (VIN = 3.3V to 5V, VOUT = 1.2V, IOUTMAX = 3A) Designator U1 CIN COUT L RF CF CVCC RC1 CC1 CSS RFB1 RFB2 Description Synchronous Buck Regulator 47 µF, 1210, X5R, 6.3V 47 µF, 1210, X5R, 6.3V 0.68 µH, 5 mΩ 1Ω, 0603 100 nF, 0603, X7R, 16V 1 µF, 0603, X5R, 6.3V 5.76 kΩ, 0603 2.2 nF, 0603, X7R, 25V 33 nF, 0603, X7R, 25V 4.99 kΩ, 0603 10 kΩ, 0603 Part Number LM20123 GRM32ER60J476ME20 GRM32ER60J476ME20 IHLP2525CZER0R68M01 CRCW06031R0J-e3 GRM188R71C104KA01 GRM188R60J105KA01 CRCW06035761F-e3 VJ0603Y222KXXA VJ0603Y333KXXA CRCW06034991F-e3 CRCW06031002F-e3 Manufacturer National Semiconductor Murata Murata Vishay Vishay-Dale Murata Murata Vishay-Dale Vishay-Vitramon Vishay-Vitramon Vishay-Dale Vishay-Dale Qty 1 1 1 1 1 1 1 1 1 1 1 1 17 www.national.com LM20123 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead eTSSOP Package NS Package Number MXA16A www.national.com 18 LM20123 Notes 19 www.national.com LM20123 3A, 1.5MHz PowerWise® Synchronous Buck Regulator Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Amplifiers Audio Clock Conditioners Data Converters Displays Ethernet Interface LVDS Power Management Switching Regulators LDOs LED Lighting PowerWise Serial Digital Interface (SDI) Temperature Sensors Wireless (PLL/VCO) www.national.com/amplifiers www.national.com/audio www.national.com/timing www.national.com/adc www.national.com/displays www.national.com/ethernet www.national.com/interface www.national.com/lvds www.national.com/power www.national.com/switchers www.national.com/ldo www.national.com/led www.national.com/powerwise www.national.com/sdi www.national.com/tempsensors www.national.com/wireless WEBENCH Analog University App Notes Distributors Green Compliance Packaging Design Support www.national.com/webench www.national.com/AU www.national.com/appnotes www.national.com/contacts www.national.com/quality/green www.national.com/packaging www.national.com/quality www.national.com/refdesigns www.national.com/feedback Quality and Reliability Reference Designs Feedback THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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