LM2506 Low Power Mobile Pixel Link (MPL) Level 0, 18-bit RGB Display Interface Serializer and Deserializer
August 2006
LM2506 Low Power Mobile Pixel Link (MPL) Level 0, 18-bit RGB Display Interface Serializer and Deserializer
General Description
The LM2506 device adapts RGB style display interfaces to the Mobile Pixel Link (MPL) Level zero serial link. The LM2506 supports one RGB display at up to 18-bit color depth and 800 X 300 pixels (over 216 Mbps and 13.2 MHz PCLK) is supported. A mode pin configures the device as a Serializer (SER) or Deserializer (DES) so the same chip can be used on both sides of the interface. The interconnect is reduced from 22 signals to only 3 active signals with the LM2506 chipset easing flex interconnect design, size constraints and cost. The LM2506 in SER mode resides beside an application, graphics or baseband processor and translates a parallel bus from LVCMOS levels to serial Mobile Pixel Link levels for transmission over a flex cable (or coax) and PCB traces to the DES located near the display module. When the Power_Down (PD*) input is asserted on the SER, the MDn and MC line drivers are powered down to save current. The DES can be controlled by a separate Power_Down input or via a signal from the SER (PDOUT*). The LM2506 implements the physical layer of the MPL Level 0 Standard (MPL-0) and a 150 µA IB current (Class 0).
Features
n RGB Display Interface support up to 800 x 300 1⁄2SVGA formats n MPL-Level 0 Physical Layer using two data and one clock signal n Low Power Consumption n Pinout mirroring enables straight through layout with minimal vias n Level translation between host and display n Auto Power Down on STOP PCLK n Link power down mode reduces quiescent power under < 10 µA n 1.74V to 2.0V core / analog supply voltage range n 1.74V to 3.0V I/O supply voltage range n −30C to 85C Operating temperature range
System Benefits
n n n n Small Interface Low Power Low EMI Intrinsic Level Translation
Typical Application Diagram - Bridge Chips
20125522
© 2006 National Semiconductor Corporation
DS201255
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LM2506
Typical Application Diagram - RGB Mode to Display Driver
20125533
Ordering Information
NSID LM2506GR LM2506SQ Package Type 49L MicroArray, 4.0 X 4.0 X 1.0 mm, 0.5 mm pitch 40L LLP, 5.0 X 5.0 X 0.8 mm, 0.4 mm pitch Package ID GRA49A SQF40A
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LM2506
Pin Descriptions - RGB Mode
Pin Name No. of Pins 2 1 I/O, Type Description RGB Serializer MPL Data Line Driver MPL Clock Line Driver MPL Ground - see Power/Ground Pins RGB Mode Input Tie Low Tie High for Serializer (Master) Test Mode control input Tie Low (normal mode) RGB Mode control input zero Tie Low RGB Mode control input one Tie Low PCLK input Power Down Output, L = device in Power Down H = Device active. Power Down input, L = Powered down (sleep mode) H = active mode RGB Data Bus inputs Vertical Sync. Input Horizontal Sync. Input Data Enable Input NA RGB Data Bus outputs Vertical Sync. Output Horizontal Sync. Output Data Enable Output Parity Error Output PCLK output NA Tie Low for Deserializer (Slave) RGB Deserializer MPL Data Receiver MPL Clock Receiver
MPL SERIAL BUS PINS MD[1:0] MC VSSA RGB* M/S* TM RM0 RM1 1 1 1 1 1 IO, MPL IO, MPL Ground I, LVCMOS I, LVCMOS I, LVCMOS I, LVCMOS I, LVCMOS IO, LVCMOS O, LVCMOS I, LVCMOS
CONFIGURATION/PARALLEL BUS PINS
CLOCK / POWER DOWN SIGNALS PCLK PDOUT* 1 1
PD*
1
PARALLEL INTERFACE SIGNALS D[17:0] VS HS DE PE 18 1 1 1 1 IO, LVCMOS IO, LVCMOS IO, LVCMOS IO, LVCMOS O, LVCMOS Power Ground Power Ground Power Ground
POWER/GROUND PINS VDDA VSSA VDDcore VSScore VDDIO VSSIO Vbulk DAP 1 1 1 1 2 2 9 1 Power Supply Pin for the SER PLL and MPL Interface. 1.74V to 2.0V Ground Pin for the MPL Interface, and analog circuitry. Power Supply Pin for the digital core. 1.74V to 2.0V Ground Pin for the digital core. Power Supply Pin for the parallel interface I/Os. 1.74V to 3.0V Ground Pin for the parallel interface I/Os. Connect to Ground - uArray Package Connect to Ground - LLP Package
Note: I = Input, O = Output, IO = Input/Output. Do not float input pins.
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LM2506
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VDDA) Supply Voltage (VDD) Supply Voltage (VDDIO) LVCMOS Input/Output Voltage MPL Input/Output Voltage Junction Temperature Storage Temperature Lead Temperature Soldering, 40 Seconds ESD Ratings: HBM, 1.5 kΩ, 100 pF EIAJ, 0Ω, 200 pF ≥ ± 2 kV ≥ ± 200V −0.3V to +2.2V −0.3V to +2.2V −0.3V to +3.6V −0.3V to (VDDIO +0.3V) −0.3V to VDDA +150˚C −65˚C to +150˚C +260˚C
Maximum Package Power Dissipation Capacity at 25˚C GRA Package Derate GRA Package above 25˚C SQF Package Derate SQF Package above 25˚C 1.8W 15mW/˚C 1.8W 15mW/˚C
Recommended Operating Conditions
Min Typ Max Supply Voltage VDDA to VSSA and VDDcore to VSScore VDDIO to VSSIO PCLK Frequency Ambient Temperature 1.74 1.8 1.74 2 −30 25 2.0 3.0 13.3 85 V V MHz ˚C Units
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 2, 3) Symbol MPL IOLL IOMS IOLH IB IOFF VIH VIL VHY IIH IIL VOH VOL IDD Logic Low Current (5X IB) Mid Scale Current (Notes 4, 9) Logic High Current (1X IB) Current Bias MPL Leakage Current Input Voltage High Level Input Voltage Low Level Input Hysteresis Input Current High Level Input Current Low Level Output Voltage High Level Output Voltage Low Level Total Supply Current — Enabled Conditions: MC = 80 MHz, MD = 160 Mbps (Note 5) Supply Current — Enabled 1.8V (Note 6) IOH = −2 mA IOL = 2 mA SER VDDIO VDD/VDDA DES VDDIO VDD/VDDA SER DES VDDIO VDD/VDDA VDDIO VDD/VDDA VDDIO = 1.74V VDDIO = 3.0V Includes IOZ Vin = VDDIO Vin = GND −1 −1 0.75 VDDIO VSSIO 20 5 4 6 10 4.7 2.3 6.2 VMPL = 0.8V −2 0.7 VDDIO GND 150 200 0 0 +1 +1 VDDIO 0.2 VDDIO 66 12 10 11 3.67 IB 2.1IB 0.7 IB 5.0 IB 3.0 IB 1.0 IB 150 +2 VDDIO 0.3 VDDIO 6.33 IB 3.9IB 1.4 IB µA µA µA µA µA V V mV mV µA µA V V µA mA mA mA µA mA mA mA Parameter Conditions Min Typ Max Units
LVCMOS (1.74V to 3.0V Operation)
SUPPLY CURRENT
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LM2506
Electrical Characteristics
Symbol MPL IDDZ Supply Current — Disable TA = 25˚C Power Down Modes Parameter
(Continued) Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 2, 3) Conditions SER PD* = L SER Stop Clock DES PD* = L VDDIO VDD/VDDA VDDIO VDD/VDDA VDDIO VDD/VDDA SER DES Min Typ Max 2 2.2 2 2.2 2 2.2 Units µA µA µA µA µA µA mW mW
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