LM2512ASN

LM2512A Mobile Pixel Link (MPL-1), 24-Bit RGB Display Interface Serializer with Optional Dithering and Look Up Table September 2007 LM2512A Mobile Pixel Link (MPL-1), 24-Bit RGB Display Interface Serializer with Optional Dithering and Look Up Table General Description The LM2512A is a MPL Serializer (SER) that performs a 24bit to 18-bit Dither operation and serialization of the video signals to Mobile Pixel link (MPL) levels on only 3 or 4 active signals. An optional Look Up Table (Three X 256 X 8 bit RAM) is also provided for independent color correction. 18-bit Bufferless or partial buffer displays from QVGA (320 x 240) up to VGA (640 x 480) pixels can utilize a 24-bit video source. The interconnect is reduced from 28 signals to only 3 or 4 active signals with the LM2512A and companion deserializer easing flex interconnect design, size constraints and cost. The LM2512A SER resides by the application, graphics or baseband processor and translates the wide parallel video bus from LVCMOS levels to serial Mobile Pixel Link levels for transmission over a flex cable (or coax) and PCB traces to the DES located near or in the display module. When in Power_Down, the SER is put to sleep and draws less than 10μA. The link can also be powered down by stopping the PCLK (DES dependant) or by the PD* input pins. The LM2512A provides enhanced AC performance over the LM2512. It implements the physical layer of the MPL-1 and uses a single-ended current-mode transmission. Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 24-bit RGB Interface support up to 640 x 480 VGA format Optional 24 to 18-bit Dithering Optional Look Up Table for independent color correction MPL-1 Physical Layer SPI Interface for Look Up Table control and loading Low Power Consumption & Powerdown state Level translation between host and display Optional Auto Power Down on STOP PCLK Frame Sequence bits auto resync upon data or clock error 1.6V to 2.0V core / analog supply voltage 1.6V to 3.0V I/O supply voltage range System Benefits ■ ■ ■ ■ ■ Dithered Data Reduction Independent RGB Color Correction 24-bit Color Input Small Interface, Low Power and Low EMI Intrinsic Level Translation Typical 3 MD Lane Application Diagram - Bridge Chip 30015301 Ordering Information NSID LM2512ASM LM2512ASMX LM2512ASN LM2512ASNX Package Type, Qty Size 49L UFBGA, 4.0 X 4.0 X 1 mm, 0.5 mm pitch, Reel of 1000 49L UFBGA, 4.0 X 4.0 X 1 mm, 0.5 mm pitch, Reel of 4500 40L LLP, 6.0 X 6.0 X 0.4 mm, 0.5 mm pitch, Reel of 1000 40L LLP, 6.0 X 6.0 X 0.4 mm, 0.5 mm pitch, Reel of 4500 Package ID SLH49A SLH49A SNA40A SNA40A © 2007 National Semiconductor Corporation 300153 www.national.com LM2512A Pin Descriptions Pin Name MPL SERIAL BUS PINS MD[2:0] MC SPI_CSX SPI_SCL SPI_SDA/HS 3 1 1 1 1 O, MPL O, MPL I, LVCMOS I, LVCMOS IO, LVCMOS MPL Data Line Driver MPL Clock Line Driver SPI_Chip Select Input SPI port is enabled when: SPI_CSX is Low, PD* is High, and PCLK is static. SPI_Clock Input Multi-function Pin: If SPI_CSX is Low, this is the SPI_SDA IO signal. Default is Input. Pin will be an output for a SPI Read transaction. See HS description below also. Power Down Mode Input SER is in sleep mode when PD* = Low, SER is enabled when PD* = High In PD*=L - Sleep mode: SPI interface is OFF, Register settings are RESET, and LUT data is retained. Reserved 1 - Tie High (VDDIO) only available on SLH49A package Test Mode L = Normal Mode, tie to GND H = Test Mode (Reserved) Not Connected - Leave Open; only on SLH49A package Pixel Clock Input Video Signals are latched on the RISING edge. RGB Data Bus Inputs – Bit 7 is the MSB. No. of Pins I/O, Type Description RGB Serializer SPI INTERFACE and CONFIGURATION PINS PD* 1 I, LVCMOS RES1 TM 1 1 I, LVCMOS I, LVCMOS NA I, LVCMOS I, LVCMOS I, LVCMOS IO, LVCMOS I, LVCMOS Power Power Power Ground Ground Ground NC VIDEO INTERFACE PINS PCLK R[7:0] G[7:0] B[7:0] VS 1 1 24 1 Vertical Sync. Input This signal is used as a frame start for the Dither block and is required. The VS signal is serialized unmodified. Multi-function Pin: Horizontal Sync. Input (when SPI_CSX = High) See SPI_SDA description above also. Data Enable Input SPI_SDA/HS 1 DE POWER/GROUND PINS VDDA VDD VDDIO VSSA VSS VSSIO 1 1 1 3 1 1 4 Power Supply Pin for the PLL (SER) and MPL Interface. 1.6V to 2.0V Power Supply Pin for the digital core. 1.6V to 2.0V Power Supply Pin for the parallel interface I/Os. 1.6V to 3.0V Ground Pin for PLL (SER) and MPL interface Ground Pin for digital core. For SN40A package, this is the large center pad. Ground Pin for the parallel interface I/Os. For SNA40A package, this is the large center pad. Note: I = Input, O = Output, IO = Input/Output. Do not float input pins. www.national.com 2 LM2512A Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VDDA) Supply Voltage (VDD) Supply Voltage (VDDIO) LVCMOS Input/Output Voltage MPL Output Voltage Junction Temperature Storage Temperature ESD Ratings: HBM - JESD22−A114C std. MM - JESD22−A115−A std. CDM - JESD22−C101−C std. −0.3V to +2.2V −0.3V to +2.2V −0.3V to +3.3V −0.3V to (VDDIO +0.3V) −0.3V to VDDA +150°C −65°C to +150°C Maximum Package Power Dissipation Capacity at 25°C SLH49A Package 2.5 W SNA40A Package 3.2 W Derate SLH49A Package above 25°C 25 mW/°C Derate SNA40A Package above 25°C 26 mW/°C Recommended Operating Conditions Min Typ Max Supply Voltage Units ≥±2 kV ≥±200V ≥±500V  VDDA to VSSA and  VDD to VSS  VDDIO to VSSIO PClock Frequency (4X) PClock Frequency (6X) MC Frequency Ambient Temperature 1.6 1.6 7.5 5 30 −30 1.8 2.0 3.0 22.5 15 90 85 V V MHz MHz MHz °C 25 Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 2, 3) Symbol MPL IOLL IOMS IOLH IB IOFF VIH VIL VHY IIN VOH VOL IDD Logic Low Current (5X IB) Mid Scale Current Logic High Current (1X IB) Current Bias MPL Leakage Current Input Voltage High Level Input Voltage Low Level Input Hysteresis Input Current Output Voltage High Level Output Voltage Low Level Total Supply Current Enabled (Note 4) MC = 80 MHz, Checkerboard Pattern 3 MD Lane (Note 5) MC = 60 MHz, Checkerboard Pattern 2 MD Lane Supply Current -Enabled MC = 60 MHz, Pseudo-Random Pattern 2 MD Lane PD* = L Stop Clock SPI_SDA IOH = −1 mA IOL = 1 mA VDDIO VDD/VDDA 5.4 9.0 mA −1 0.7 VDDIO VSSIO 0.02 VMPL = 0V −2 0.7 VDDIO GND 100 0 +1 VDDIO 0.2 VDDIO 0.07 0.711 IB 3.947IB 5.0 IB 3.0 IB 1.0 IB 190 +2 VDDIO 0.3 VDDIO 1.368 IB 6.842IB µA µA µA µA µA V V mV µA V V mA Parameter Conditions Min Typ Max Units LVCMOS (1.6V to 3.0V Operation) SUPPLY CURRENT VDDIO VDD/VDDA 0.01 4.1 mA mA mA mA 2 5 2 5 µA µA µA µA www.national.com VDDIO VDD/VDDA 0.02 3.7 IDDZ Supply Current—Disable Power Down Modes Ta = 25°C VDDIO VDD/VDDA VDDIO VDD/VDDA 3