LM2722

LM2722 High Speed Synchronous/Asynchronous MOSFET Driver December 2001 LM2722 High Speed Synchronous/Asynchronous MOSFET Driver General Description The LM2722, part of the LM2726 family, is designed to be used with multi-phase controllers. This part differs from the LM2726 by changing the functionality of the SYNC_EN pin from a whole chip enable to a low side MOSFET enable. As a result, the SYNC_EN pin now provides control between Synchronous and Asynchronous operations. Having this control can be advantageous in portable systems since Asynchronous operations can be more efficient at very light loads. The LM2722 drives both top and bottom MOSFETs in a push-pull structure simultaneously. It takes a logic level PWM input and splits it into two complimentary signals with a typical 20ns dead time in between. The built-in cross-conduction protection circuitry prevents the top and bottom FETs from turning on simultaneously. The cross-conduction protection circuitry detects both the driver outputs and will not turn on a driver until the other driver output is low. With a bias voltage of 5V, the peak sourcing and sinking current for each driver of the LM2722 is typically 3A. In an SO-8 package, each driver is able to handle 50mA average current. Input UVLO (Under-Voltage-Lock-Out) forces both driver outputs low to ensure proper power-up and power-down operation. The gate drive bias voltage needed by the high side MOSFET is obtained through an external bootstrap. Minimum pulse width is as low as 55ns. Features n n n n n Synchronous or Asynchronous Operation Adaptive shoot-through protection Input Under-Voltage-Lock-Out Typical 20ns internal delay Plastic 8-pin SO package Applications n Driver for LM2723 Intel Mobile Northwood CPU core power supply. n High Current DC/DC Power Supplies n High Input Voltage Switching Regulators n Fast Transient Microprocessors Typical Application 20028901 Note: National is an Intel Mobile Voltage Positioning (IMVP) licensee. © 2001 National Semiconductor Corporation DS200289 www.national.com LM2722 Connection Diagram 8-Lead Small Outline Package 20028902 Top View Ordering Information Order Number LM2722 Package Type LM2722M LM2722MX NSC Package Drawing M08A Supplied As 95 Units/Rail 2500 Units/Reel Pin Description Pin 1 2 3 4 5 6 7 8 Name SW HG CBOOT PWM_IN SYNC_EN VCC LG GND Function Top driver return. Should be connected to the common node of top and bottom FETs Top gate drive output Bootstrap. Accepts a bootstrap voltage for powering the high-side driver Accepts a 5V-logic control signal Low gate Enable Connect to +5V supply Bottom gate drive output Ground www.national.com 2 LM2722 Block Diagram 20028904 3 www.national.com LM2722 Absolute Maximum Ratings (Note 1) Storage Temperature ESD Susceptibility Human Body Model (Note 3) Soldering Time, Temperature −65˚ to 150˚C 1kV 10sec., 300˚C If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. VCC CBOOT CBOOT to SW SW to PGND Junction Temperature Power Dissipation (Note 2) 7.5V 42V 8V 36V +150˚C 720mW Operating Ratings (Note 1) VCC Junction Temperature Range 4V to 7V −40˚ to 125˚C Electrical Characteristics VCC = CBOOT = 5V, SW = GND = 0V, unless otherwise specified. Typicals and limits appearing in plain type apply for TA = TJ = +25˚C. Limits appearing in boldface type apply over the entire operating temperature range. Symbol POWER SUPPLY Iq_op TOP DRIVER Peak Pull-Up Current Pull-Up Rds_on Peak Pull-down Current Pull-down Rds_on t4 t6 t3 t5 Rise Time Fall Time Pull-Up Dead Time Pull-Down Delay Test Circuit 1, Vbias = 5V, R = 0.1Ω ICBOOT = IHG = 0.7A Test Circuit 2, Vbias = 5V, R = 0.1Ω ISW = IHG = 0.7A Timing Diagram, CLOAD = 3.3nF Timing Diagram Timing Diagram, from PWM_IN Falling Edge Test Circuit 3, Vbias = 5V, R = 0.1Ω IVCC = ILG = 0.7A Test Circuit 4, Vbias = 5V, R = 0.1Ω IGND = ILG = 0.7A Timing Diagram, CLOAD = 3.3nF Timing Diagram Timing Diagram, from PWM_IN Rising Edge VCC rises from 0V toward 5V 3.0 1.0 −3.2 0.5 17 12 23 27 A Ω A Ω ns ns ns ns Operating Quiescent Current PWM_IN = 0V 190 300 µA Parameter Condition Min Typ Max Units BOTTOM DRIVER Peak Pull-Up Current Pull-up Rds_on Peak Pull-down Current Pull-down Rds_on t8 t2 t7 t1 LOGIC Vuvlo_up Vuvlo_dn Vuvlo_hys VIH_EN VIL_EN Power On Threshold Under-Voltage-Lock-Out Threshold Under-Voltage-Lock-Out Hysteresis SYNC_EN Pin High Input SYNC_EN Pin Low Input 2.4 0.8 4 3.7 3.0 0.7 2.5 V V V V V Rise Time Fall Time Pull-up Dead Time Pull-down Delay 3.2 1.0 3.2 0.5 17 14 28 13 A Ω A Ω ns ns ns ns www.national.com 4 LM2722 Electrical Characteristics Symbol Ileak_EN ton_min Parameter SYNC_EN Pin Leakage Current Minimum Positive Input Pulse Width (Note 4) Minimum Negative Input Pulse Width (Note 5) (Continued) VCC = CBOOT = 5V, SW = GND = 0V, unless otherwise specified. Typicals and limits appearing in plain type apply for TA = TJ = +25˚C. Limits appearing in boldface type apply over the entire operating temperature range. Condition EN = 5V EN = 0V Min −2 −2 55 ns 55 When PWM_IN pin goes high from 0V When PWM_IN pin goes low from 5V Typ Max 2 2 Units µA toff_min VIH_PWM VIL_PWM PWM_IN High Level Input Voltage PWM_IN Low Level Input Voltage 2.4 0.8 V Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating ratings are conditions under which the device operates correctly. Operating Ratings do not imply guaranteed performance limits. Note 2: Maximum allowable power dissipation is a function of the maximum junction temperature, TJMAX, the junction-to-ambient thermal resistance, θJA, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is calculated using: PMAX = (TJMAX-TA) / θJA. The junction-toambient thermal resistance, θJA, for the LM2722, it is 172˚C/W. For a TJMAX of 150˚C and TA of 25˚C, the maximum allowable power dissipation is 0.7W. Note 3: ESD machine model susceptibility is 100V. Note 4: If after a rising edge, a falling edge occurs sooner than the specified value, the IC may intermittently fail to turn on the bottom gate when the top gate is off. As the falling edge occurs sooner and sooner, the driver may start to ignore the pulse and produce no output. Note 5: If after a falling edge, a rising edge occurs sooner than the specified value, the IC may intermittently fail to turn on the top gate when the bottom gate is off. As the rising edge occurs sooner and sooner, the driver may start to ignore the pulse and produce no output. Timing Diagram 20028903 5 www.national.com LM2722 Test Circuits 20028905 20028906 Test Circuit 1 Test Circuit 2 20028907 20028908 Test Circuit 3 Test Circuit 4 www.national.com 6 LM2722 Typical Waveforms 20028915 20028913 FIGURE 3. When Input Goes Low FIGURE 1. Switching Waveforms of Test Circuit 20028916 20028914 FIGURE 4. Minimum Positive Pulse FIGURE 2. When Input Goes High Application Information Minimum Pulse Width In order for the shoot-through prevention circuitry in the LM2722 to work properly, the pulses into the PWM_IN pin must be longer than 55ns. The internal logic waits until the first FET is off plus 20ns before turning on the opposite FET. If, after a falling edge, a rising edge occurs sooner than the specified time, toff_min, the IC may intermittently fail to turn on the top gate when the bottom gate is off. As the rising edge occurs sooner and sooner, the driver may start to ignore the pulse and produce no output. This condition results in the PWM_IN pin in a high state and neither FET turned on. To get out of this state, the PWM_IN pin must see a low signal for greater than 55ns, before the rising edge. This will also assure that the gate drive bias voltage has been restored by forcing the top FET source and Cboot to ground first. Then the internal circuitry is reset and normal operation will resume. Conversely, if, after a rising edge, a falling edge occurs sooner than the specified miniumum pulse width, ton_min, the IC may intermittently fail to turn on the bottom FET. As the falling edge occurs sooner and sooner, the driver will start to ignore the pulse and produce no output. This will result in the toff inductor current taking a path through a diode provided for non-synchronous operation. The circuit will resume synchronous operation when the rising PWM pulses exceed 55ns in duration. High Input Voltages or High Output Currents At input voltages above twice the output voltage and at higher power levels, the designer may find snubber networks and gate drive limiting useful in reducing EMI and preventing injurious transients. A small resistor, 1Ω to 5Ω, between the driver outputs and the MOSFET gates will slightly increase the rise time and fall time of the output stage and reduce switching noise. The trade-off is 1% to 2% in efficiency. A series R-C snubber across in parallel with the bottom FET can also be used to reduce ringing. Values of 10nF and 10Ω to 100Ω are a good starting point. 7 www.national.com LM2722 High Speed Synchronous/Asynchronous MOSFET Driver Physical Dimensions unless otherwise noted inches (millimeters) 8-Lead Small Outline Package NS Package Number M08A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Email: support@nsc.com National Semiconductor Europe Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: ap.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 www.national.com National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.