LM27965_07

LM27965 Dual Display White LED Driver System with I2C Compatible Brightness Control October 2007 LM27965 Dual Display White LED Driver with I2C Compatible Brightness Control General Description The LM27965 is a highly integrated charge-pump-based dual-display LED driver. The device can drive up to 9 LEDs in parallel with a total output current of 180mA. Regulated internal current sinks deliver excellent current and brightness matching in all LEDs. The LED driver current sinks are split into three independently controlled groups. The primary group can beconfigurabled with 4 or 5 LEDs, for backlighting a larger main display and the second group can be configured with 2 or 3 LEDs, for backlighing a smaller secondary display. An additional, independently controlled led driver is provided for driving an indicator or general purpose LED. The LM27965 has an I2C compatible interface that allows the user to independently control the brightness on each bank of LEDs. The device provides excellent efficiency without the use of an inductor by operating the charge pump in a gain of 3/2, or in Pass-Mode. The proper gain for maintaining current regulation is chosen based on LED forward voltage, so that efficiency is maximized over the input voltage range. The LM27965 is available in National's small 24-pin Leadless Leadframe Package (LLP-24). Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 91% Peak LED Drive Efficiency No Inductor Required 0.3% Current Matching Drives LEDs with up to 30mA per LED 180mA of total drive current I2C Compatible Brightness Control Interface Adaptive 1× - 3/2× Charge Pump Resistor-Programmable Current Settings External Chip RESET Pin Extended Li-Ion Input: 2.7V to 5.5V Small low profile industry standard leadless package, LLP 24 : (4mm x 4mm x 0.8mm) ■ 25mm2 total solution size ■ Two I2C Compatible Chip Address Options: 0x36 for LM27965SQ and 0x38 for LM27965SQ-M Applications ■ Mobile Phone Display Lighting ■ PDA Backlighting ■ General LED Lighting Typical Application Circuit 20155001 © 2007 National Semiconductor Corporation 201550 www.national.com LM27965 Connection Diagram 24 Pin Quad LLP Package NS Package Number SQA24A 20155002 Pin Descriptions Pin #s 24 23 19, 22 (C1) 20, 21 (C2) Pin Names VIN POUT C1, C2 Charge Pump Output Voltage Flying Capacitor Connections Pin Descriptions Input voltage. Input range: 2.7V to 5.5V. 12, 13, 14, 15, 16 D5A, D4A, D3A, D2A, LED Drivers - GroupA D1A 4, 5, 6 3 17 D1B, D2B, D3B D1C ISET LED Drivers - GroupB LED Driver - Indicator LED Placing a resistor (RSET) between this pin and GND sets the full-scale LED current for DxA , DxB, and D1C LEDs. Full-Scale LED Current = 200 × (1.25V ÷ RSET) Serial Clock Pin Serial Data Input/Output Pin Serial Bus Voltage Level Pin Harware Reset Pin. High = Normal Operation, Low = RESET Ground No Connect 1 2 7 10 9, 18, DAP 8, 11 SCL SDIO VIO RESET GND NC Ordering Information Order Information LM27965SQ LM27965SQX LM27965SQ-M LM27965SQX-M I2C Compatible Chip Address 0x36 0x36 0x38 0x38 SQA24 LLP Package Supplied As 1000 Units, Tape & Reel 4500 Units, Tape & Reel 1000 Units, Tape & Reel 4500 Units, Tape & Reel www.national.com 2 LM27965 Absolute Maximum Ratings (Notes 1, 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. VIN pin voltage SCL, SDIO, VIO, RESET pin voltages IDxx Pin Voltages Continuous Power Dissipation (Note 3) Junction Temperature (TJ-MAX) Storage Temperature Range Maximum Lead Temperature (Soldering) ESD Rating(Note 5) Human Body Model -0.3V to 6.0V -0.3V to (VIN+0.3V) w/ 6.0V max -0.3V to (VPOUT+0.3V) w/ 6.0V max Internally Limited 150ºC -65ºC to +150º C (Note 4) Operating Rating (Notes 1, 2) Input Voltage Range LED Voltage Range Junction Temperature (TJ) Range Ambient Temperature (TA) Range (Note 6) 2.7V to 5.5V 2.0V to 4.0V -30°C to +100°C -30°C to +85°C Thermal Properties Junction-to-Ambient Thermal Resistance (θJA), SQA24A Package (Note 7) 41.3°C/W ESD Caution Notice 2.0kV (Notes 2, 8) National Semiconductor recommends that all integrated circuits be handled with appropriate ESD precautions. Failure to observe proper ESD handling techniques can result in damage to the device. Electrical Characteristics Limits in standard typeface are for TJ = 25°C, and limits in boldface type apply over the full operating temperature range. Unless otherwise specified: VIN = 3.6V; VRESET = VIN; VIO = 1.8V VDxA = VDxB = VDxC = 0.4V; RSET = 12.7kΩ; BankA = BankB = BankC = Fullscale Current; ENA, ENB, ENC, EN5A, EN3B Bits = “1”; C1 = C2 = CIN= COUT= 1.0µF; Specifications related to output current (s) and current setting pins (IDxx and ISET) apply to BankA and BankB. (Note 9) Symbol Parameter Output Current Regulation BankA or BankB Enabled Output Current Regulation BankC Enabled Maximum Diode Current per Dxx Output(Note 10) Condition 3.0V ≤ VIN ≤ 5.5V ENA = '1' or ENB = '1' and ENC= '0' 3.0V ≤ VIN ≤ 5.5V ENC = '1' and ENA = ENB= '0' RSET = 8.33kΩ Min 18.2 (-9.5%) 19.2 (-7.7%) Typ 20.1 20.8 30 20 DxA 20 DxB 20 DxC BankA BankB 0.3 0.3 2.75 1 175 1.7 1.4 % Ω mV mA Max 22.0 (+9.5%) 22.4 (+7.7%) Units mA (%) mA (%) mA IDxx Output Current Regulation 3.2V ≤ VIN ≤ 5.5V BankA, BankB, and BankC Enabled VLED = 3.6V (Note 10) IDxx-MATCH LED Current Matching(Note 11) ROUT VDxTH Open-Loop Charge Pump Output Resistance VDxx 1x to 3/2x Gain Transition Threshold Current sink Headroom Voltage Requirement (Note 12) Quiescent Supply Current Shutdown Supply Current ISET Pin Voltage Output Current to Current Set Ratio BankA, BankB, BankC Switching Frequency Start-up Time Internal Diode Current PWM Frequency 3.0V ≤ VIN ≤ 5.5V Gain = 3/2 Gain = 1 VDxA and/or VDxB Falling RSET = 16.9kΩ IDxx = 95% ×IDxx (nom.) (IDxx (nom) ≈ 15mA) RSET = 16.9kΩ Gain = 1.5x, No Load All ENx bits = "0" 2.7V ≤ VIN ≤ 5.5V VHR IQ ISD VSET IDxA-B-C / ISET fSW tSTART fPWM 110 2.90 3.4 1.25 200 0.89 1.27 250 20 1.57 3.32 5.4 mV mA µA V MHz µs kHz POUT = 90% steady state 3 www.national.com LM27965 Symbol VRESET Parameter Reset Voltage Thresholds Condition Reset 2.7V ≤ VIN ≤ 5.5V Normal Operation Min 0 1.2 Typ Max 0.45 VIN Units V I2C Compatible Interface Voltage Specifications (SCL, SDIO, VIO) VIO VIL VIH VOL I2C t1 t2 t3 t4 t5 Serial Bus Voltage Level Input Logic Low "0" Input Logic High "1" Output Logic Low "0" SCL (Clock Period) Data In Setup Time to SCL High Data Out stable After SCL Low SDIO Low Setup Time to SCL Low (Start) SDIO High Hold Time After SCL High (Stop) 2.7V ≤ VIN ≤ 5.5V (Note 13) 2.7V ≤ VIN ≤ 5.5V, VIO= 3.0V 2.7V ≤ VIN ≤ 5.5V, VIO= 3.0V ILOAD = 3mA 2.5 100 0 100 100 1.4 0 0.7 × VIO VIN 0.3 × VIO VIO 400 V V V mV µs ns ns ns ns Compatible Interface Timing Specifications (SCL, SDIO, VIO)(Note 14) 20155013 Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical Characteristics tables. Note 2: All voltages are with respect to the potential at the GND pins. Note 3: Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 170°C (typ.) and disengages at TJ = 165°C (typ.). Note 4: For detailed soldering specifications and information, please refer to National Semiconductor Application Note 1187: Leadless Leadframe Package (AN-1187). Note 5: The human body model is a 100pF capacitor discharged through 1.5kΩ resistor into each pin. (MIL-STD-883 3015.7) Note 6: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 100°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX). Note 7: Junction-to-ambient thermal resistance is highly dependent on application and board layout. In applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design. For more information, please refer to National Semiconductor Application Note 1187: Leadless Leadframe Package (AN-1187). Note 8: Min and Max limits are guaranteed by design, test, or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm. Note 9: CIN, CPOUT, C1, and C2 : Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics Note 10: The maximum total output current for the LM27965 should be limited to 180mA. The total output current can be split among any of the three banks (IDxA = IDxB = IDxC = 30mA Max.). Under maximum output current conditions, special attention must be given to input voltage and LED forward voltage to ensure proper current regulation. See the Maximum Output Current section of the datasheet for more information. Note 11: For the two groups of current sinks on a part (BankA and BankB), the following are determined: the maximum sink current in the group (MAX), the minimum sink current in the group (MIN), and the average sink current of the group (AVG). For each group, two matching numbers are calculated: (MAX-AVG)/ www.national.com 4 LM27965 AVG and (AVG-MIN)/AVG. The largest number of the two (worst case) is considered the matching figure for the bank. The matching figure for a given part is considered to be the highest matching figure of the two banks. The typical specification provided is the most likely norm of the matching figure for all parts. Note 12: For each Dxx pin, headroom voltage is the voltage across the internal current sink connected to that pin. For Group A, B, and C current sinks, VHRx = VOUT -VLED. If headroom voltage requirement is not met, LED current regulation will be compromised. Note 13: SCL and SDIO signals are referenced to VIO and GND for minimum VIO voltage testing. Note 14: SCL and SDIO should be glitch-free in order for proper brightness control to be realized. Block Diagram 20155003 5 www.national.com LM27965 Typical Performance Characteristics LED Drive Efficiency vs Input Voltage Unless otherwise specified: TA = 25°C; VIN = 3.6V; VRESET = VIN; VLEDxA = VLEDxB = VLED1C = 3.6V; RSET = 16.9kΩ; C1=C2= CIN = CPOUT = 1µF; ENA = ENB = ENC =EN5A = EN3B = '1'. Input Current vs Input Voltage 20155033 20155034 BankA Current Regulation vs Input Voltage BankB Current Regulation vs Input Voltage 20155030 20155029 BankC Current Regulation vs Input Voltage BankA Current Matching vs Input Voltage 20155028 20155031 www.national.com 6 LM27965 BankB Current Matching vs Input Voltage BankA Diode Current vs Brightness Register Code 20155032 20155026 BankB Diode Current vs Brightness Register Code 20155027 7 www.national.com LM27965 Circuit Description OVERVIEW The LM27965 is a white LED driver system based upon an adaptive 3/2× - 1× CMOS charge pump capable of supplying up to 180mA of total output current. With three separately controlled banks of constant current sinks, the LM27965 is an ideal solution for platforms requiring a single white LED driver for main display, sub display, and indicator lighting. The tightly matched current sinks ensure uniform brightness from the LEDs across the entire small-format display. Each LED is configured in a common anode configuration, with the peak drive current being programmed through the use of an external RSET resistor. An I2C compatible interface is used to enable the device and vary the brightness within the individual current sink banks. For BankA and BankB, 32 levels of brightness control are available. The brightness control is achieved through a mix of analog and pulse width modulated (PWM) methods. BankC has 4 analog brightness levels available. CIRCUIT COMPONENTS Charge Pump The input to the 3/2× - 1x charge pump is connected to the VIN pin, and the regulated output of the charge pump is connected to the VOUT pin. The recommended input voltage range of the LM27965 is 3.0V to 5.5V. The device’s regulated charge pump has both open loop and closed loop modes of operation. When the device is in open loop, the voltage at VOUT is equal to the gain times the voltage at the input. When the device is in closed loop, the voltage at VOUT is regulated to 4.6V (typ.). The charge pump gain transitions are actively selected to maintain regulation based on LED forward voltage and load requirements. LED Forward Voltage Monitoring The LM27965 has the ability to switch converter gains (1x or 3/2x) based on the forward voltage of the LED load. This ability to switch gains maximizes efficiency for a given load. Forward voltage monitoring occurs on all diode pins within BankA and BankB. At higher input voltages, the LM27965 will operate in pass mode, allowing the POUT voltage to track the input voltage. As the input voltage drops, the voltage on the DXX pins will also drop (VDXX = VPOUT – VLEDx). Once any of the active Dxx pins reaches a voltage approximately equal to 175mV, the charge pump will switch to the gain of 3/2. This switch-over ensures that the current through the LEDs never becomes pinched off due to a lack of headroom across the current sinks. Only active Dxx pins will be monitored. For example, if only BankA is enabled, the LEDs in BankB will not affect the gain transition point. If both banks are enabled, all diodes will be monitored, and the gain transition will be based upon the diode with the highest forward voltage. Diode pins D5A and D3B can have the diode sensing circuity disabled through the general purpose register if those drivers are not going to be used. BankC (D1C) is not a monitored LED current sink. RESETPin The LM27965 has a hardware reset pin (RESET) that allows the device to be disabled by an external controller without requiring an I2C write command. Under normal operation, the RESET pin should be held high (logic '1') to prevent an unwanted reset. When the RESET is driven low (logic '0'), all internal control registers reset to the default states and the part becomes disabled. Please see the Electrical Characteristics section of the datasheet for required voltage thresholds. I2C Compatible Interface DATA VALIDITY The data on SDIO line must be stable during the HIGH period of the clock signal (SCL). In other words, state of the data line can only be changed when CLK is LOW. 20155025 FIGURE 1. Data Validity Diagram A pull-up resistor between VIO and SDIO must be greater than [ (VIO-VOL) / 3mA] to meet the VOL requirement on SDIO. Using a larger pull-up resistor results in lower switching current with slower edges, while using a smaller pull-up results in higher switching currents with faster edges. START AND STOP CONDITIONS START and STOP conditions classify the beginning and the end of the I2C session. A START condition is defined as SDIO signal transitioning from HIGH to LOW while SCL line is HIGH. A STOP condition is defined as the SDIO transitioning from LOW to HIGH while SCL is HIGH. The I2C master always generates START and STOP conditions. The I2C bus is considered to be busy after a START condition and free after a STOP condition. During data transmission, the I2C master can generate repeated START conditions. First START and repeated START conditions are equivalent, function-wise. 20155011 FIGURE 2. Start and Stop Conditions TRANSFERING DATA Every byte put on the SDIO line must be eight bits long, with the most significant bit (MSB) transferred first. Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated by the master. The master releases the SDIO line (HIGH) during the acknowledge clock pulse. The LM27965 pulls down the SDIO line during the 9th clock pulse, signifying an acknowledge. The LM27965 generates an acknowledge after each byte is received. After the START condition, the I2C master sends a chip address. This address is seven bits long followed by an eighth bit which is a data direction bit (R/W). The LM27965 address is 36h (38h for -M version). For the eighth bit, a “0” indicates a WRITE and a “1” indicates a READ. The second byte se8 www.national.com LM27965 lects the register to which the data will be written. The third byte contains data to write to the selected register. 20155012 FIGURE 3. Write Cycle w = write (SDIO = "0") r = read (SDIO = "1") ack = acknowledge (SDIO pulled down by either master or slave) id = chip address, 36h for LM27965 or 38h for LM27965-M I2C COMPATIBLE CHIP ADDRESS The chip address for LM27965 is 0110110, or 36h. The chip address for LM27965-M is 0111000, or 38h. Internal Hex Address: 10h Note: ENA: Enables DxA LED drivers (Main Display) ENB: Enables DxB LED drivers (Aux Lighting) ENC: Enables D1C LED driver (Indicator Lighting) EN5A: Enables D5A LED voltage sense EN3B: Enables D3B LED driver and voltage sense 20155009 FIGURE 4. Chip Address INTERNAL REGISTERS OF LM27965 Register General Purpose Register Internal Hex Address 10h Power On Value 20155005 20155006 0010 0000 1110 0000 1110 0000 1111 1100 20155007 Bank A Brightness A0h Control Register Bank B Brightness B0h Control Register Bank C Brightness C0h Control Register FIGURE 6. Brightness Control Register Description Internal Hex Address: 0xA0 (BankA), 0xB0 (BankB), 0xC0 (BankC) Note: DxA4-DxA0: Sets Brightness for DxA pins (BankA). 11111=Fullscale DxB4-DxB0: Sets Brightness for DxB pins (BankB). 11111=Fullscale Bit7 to Bit 5: Not Used DxC1-DxC0: Sets Brightness for DxC pin. 11 = Fullscale Bit7 to Bit2:Not Used Full-Scale Current set externally by the following equation: IDxx = 200 × 1.25V / RSET 20155008 FIGURE 5. General Purpose Register Description 9 www.national.com LM27965 Brightness Level Control Table (BankA and BankB) Brightness Code (hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F Analog Current (% of Full-Scale) 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 40 40 40 40 40 40 40 70 70 70 70 70 70 100 100 100 Duty Cycle (%) 1/16 2/16 3/16 4/16 5/16 6/16 7/16 8/16 9/16 10/16 11/16 12/16 13/16 14/16 15/16 16/16 10/16 11/16 12/16 13/16 14/16 15/16 16/16 11/16 12/16 13/16 14/16 15/16 16/16 13/16 15/16 16/16 Perceived Brightness Level (%) 1.25 2.5 3.75 5 6.25 7.5 8.75 10 11.25 12.5 13.75 15 16.25 17.5 18.75 20 25 27.5 30 32.5 35 37.5 40 48.125 52.5 56.875 61.25 65.625 70 81.25 93.75 100 BankC Brightness Levels (%of Full-Scale) = 20%, 40%, 70%, 100% Application Information SETTING LED CURRENT The current through the LEDs connected to DxA and DxB can be set to a desired level simply by connecting an appropriately sized resistor (RSET) between the ISET pin of the LM27965 and GND. The DxA and DxB LED currents are proportional to the current that flows out of the ISET pin and are a factor of 200 times greater than the ISET current. The feedback loops of the internal amplifiers set the voltage of the ISET pin to 1.25V (typ.). The statements above are simplified in the equations below: IDxA/B/C (A)= 200 × (VISET / RSET) RSET (Ω)= 200 × (1.25V / IDxA/B/C) Once the desired RSET value has been chosen, the LM27965 has the ability to internally dim the LEDs using a mix of Pulse Width Modulation (PWM) and analog current scaling. The PWM duty cycle is set through the I2C compatible interface. LEDs connected to BankA and BankB current sinks (DxA and DxB) can be dimmed to 32 different levels/duty-cycles. The internal PWM frequency for BankA and BankB is fixed at 20kHz. BankC(D1C) has 4 analog current levels. Please refer to the I2C Compatible Interface section of this datasheet for detailed instructions on how to adjust the brightness control registers. MAXIMUM OUTPUT CURRENT, MAXIMUM LED VOLTAGE, MINIMUM INPUT VOLTAGE The LM27965 can drive 8 LEDs at 22.5mA each (BankA and BankB) from an input voltage as low as 3.2V, so long as the LEDs have a forward voltage of 3.6V or less (room temperature). www.national.com 10 LM27965 The statement above is a simple example of the LED drive capabilities of the LM27965. The statement contains the key application parameters that are required to validate an LEDdrive design using the LM27965: LED current (ILEDx), number of active LEDs (Nx), LED forward voltage (VLED), and minimum input voltage (VIN-MIN). The equation below can be used to estimate the maximum output current capability of the LM27965: ILED_MAX = [(1.5 x VIN) - VLED - (IADDITIONAL × ROUT)] / [(Nx x ROUT) + kHRx] (eq. 1) ILED_MAX = [(1.5 x VIN ) - VLED - (IADDITIONAL × 2.75Ω)] / [(Nx x 2.75Ω) + kHRx] IADDITIONAL is the additional current that could be delivered to the other LED banks. ROUT – Output resistance. This parameter models the internal losses of the charge pump that result in voltage droop at the pump output POUT. Since the magnitude of the voltage droop is proportional to the total output current of the charge pump, the loss parameter is modeled as a resistance. The output resistance of the LM27965 is typically 2.75Ω (VIN = 3.6V, TA = 25°C). In equation form: VPOUT = (1.5 × VIN) – [(NA× ILEDA + NB × ILEDB ) × ROUT] (eq. 2) kHR – Headroom constant. This parameter models the minimum voltage required to be present across the current sinks for them to regulate properly. This minimum voltage is proportional to the programmed LED current, so the constant has units of mV/mA. The typical kHR of the LM27965 is 8mV/mA. In equation form: (VPOUT – VLEDx) > kHRx × ILEDx (eq. 3) Typical Headroom Constant Values kHRA = 8mV/mA kHRB = 8mV/mA The "ILED-MAX" equation (eq. 1) is obtained from combining the ROUT equation (eq. 2) with the kHRx equation (eq. 3) and solving for ILEDx. Maximum LED current is highly dependent on minimum input voltage and LED forward voltage. Output current capability can be increased by raising the minimum input voltage of the application, or by selecting an LED with a lower forward voltage. Excessive power dissipation may also limit output current capability of an application. Total Output Current Capability The maximum output current that can be drawn from the LM27965 is 180mA. Each driver bank has a maximum allotted current per Dxx sink that must not be exceeded. DRIVER TYPE DxA DxB DxC MAXIMUM Dxx CURRENT 30mA per DxA Pin 30mA per DxB Pin 30mA per DxB Pin current. For example, if 60mA is the desired drive current for a single LED, RSET should be selected such that the current through each of the current sink inputs is 12mA. Connecting the outputs in parallel does not affect internal operation of the LM27965 and has no impact on the Electrical Characteristics and limits previously presented. The available diode output current, maximum diode voltage, and all other specifications provided in the Electrical Characteristics table apply to this parallel output configuration, just as they do to the standard 5-LED application circuit. Both BankA and BankB utilize LED forward voltage sensing circuitry on each Dxx pin to optimize the charge-pump gain for maximum efficiency. Due to the nature of the sensing circuitry, it is not recommended to leave any of the DxA (D1AD4A) or DxB (D1B-D2B) pins open if either diode bank is going to be used during normal operation. Leaving DxA and/ or DxB pins unconnected will force the charge-pump into 3/2× mode over the entire VIN range negating any efficiency gain that could have been achieved by switching to 1× mode at higher input voltages. If D5A is not used, it is recommended that the driver pin be grounded and the general purpose register bit EN5A be set to 0 to ensure proper gain transitions. The D3B driver can be completely turned on or off on the fly using the general purpose register. The diode monitoring circuity is enabled and disabled with the driver. If D3B is not used, it is recommended that the driver pin be grounded and the general purpose register bit EN3B be set to 0 to ensure proper gain transitions. Care must be taken when selecting the proper RSET value. The current on any Dxx pin must not exceed the maximum current rating for any given current sink pin. POWER EFFICIENCY Efficiency of LED drivers is commonly taken to be the ratio of power consumed by the LEDs (PLED) to the power drawn at the input of the part (PIN). With a 3/2× - 1× charge pump, the input current is equal to the charge pump gain times the output current (total LED current). The efficiency of the LM27965 can be predicted as follows: PLEDTOTAL = (VLEDA × NA × ILEDA) + (VLEDB × NB × ILEDB) + (VLEDC × ILEDC) PIN = VIN × IIN PIN = VIN × (GAIN × ILEDTOTAL + IQ) E = (PLEDTOTAL ÷ PIN) The LED voltage is the main contributor to the charge-pump gain selection process. Use of low forward-voltage LEDs (3.0V- to 3.5V) will allow the LM27965 to stay in the gain of 1× for a higher percentage of the lithium-ion battery voltage range when compared to the use of higher forward voltage LEDs (3.5V to 4.0V). See the LED Forward Voltage Monitoring section of this datasheet for a more detailed description of the gain selection and transition process. For an advanced analysis, it is recommended that power consumed by the circuit (VIN x IIN) for a given load be evaluated rather than power efficiency. POWER DISSIPATION The power dissipation (PDISS) and junction temperature (TJ) can be approximated with the equations below. PIN is the power generated by the 3/2× - 1× charge pump, PLED is the power consumed by the LEDs, TA is the ambient temperature, and θJA is the junction-to-ambient thermal resistance for the LLP-24 package. VIN is the input voltage to the LM27965, 11 www.national.com The 180mA load can be distributed in many different configurations. Special care must be taken when running the LM27965 at the maximum output current to ensure proper functionality. PARALLEL CONNECTED AND UNUSED OUTPUTS Outputs D1A-5A or D1B-D3B may be connected together to drive one or two LEDs at higher currents. In such a configuration, all five parallel current sinks (BankA) of equal value can drive a single LED. The LED current programmed for BankA should be chosen so that the current through each of the outputs is programmed to 20% of the total desired LED LM27965 VLED is the nominal LED forward voltage, N is the number of LEDs and ILED is the programmed LED current. PDISS = PIN - PLEDA - PLEDB - PLEDC PDISS= (GAIN × VIN × IBANKA + BANKB + BANKC ) - (VLEDA × NA × ILEDA) - (VLEDB × NB × ILEDB) - (VLEDC × ILEDC) TJ = TA + (PDISS x θJA) The junction temperature rating takes precedence over the ambient temperature rating. The LM27965 may be operated outside the ambient temperature rating, so long as the junction temperature of the device does not exceed the maximum operating rating of 100°C. The maximum ambient temperature rating must be derated in applications where high power dissipation and/or poor thermal resistance causes the junction temperature to exceed 100°C. THERMAL PROTECTION Internal thermal protection circuitry disables the LM27965 when the junction temperature exceeds 170°C (typ.). This feature protects the device from being damaged by high die temperatures that might otherwise result from excessive power dissipation. The device will recover and operate normally when the junction temperature falls below 165°C (typ.). It is important that the board layout provide good thermal conduction to keep the junction temperature within the specified operating ratings. CAPACITOR SELECTION The LM27965 requires 4 external capacitors for proper operation (C1 = C2 = CIN = COUT = 1µF). Surface-mount multi-layer ceramic capacitors are recommended. These capacitors are small, inexpensive and have very low equivalent series resistance (ESR