LM3280

LM3280 Adjustable Step-Down DC-DC Converter and 3 LDOs for RF Power Management January 2007 LM3280 Adjustable Step-Down DC-DC Converter and 3 LDOs for RF Power Management General Description The LM3280 is a multi-functional Power Management Unit, optimized for low-power handheld applications such as Cellular Phones. The LM3280 incorporates three low-dropout LDO voltage regulators and one step down PWM DC-DC converter with an internal Bypass FET. The step down converter's output voltage can be set using an analog input (VCON) for optimizing efficiency of the RF PA at various power levels. The LDO operates a nominal output voltage of 2.85V and maximum load current capability of 20mA for a reference voltage required by linear RF power amplifiers. The LM3280 additionally features a separate enable pin for each output. The LM3280 is available in a 16-pin lead free micro SMD package. Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 2MHz (typ.) PWM Switching Frequency Operates from a single Li-Ion cell (2.7V to 5.5V) Adjustable Output Voltage (0.8V to 3.6V) DC-DC High-efficiency synchronous buck converter 300mA Maximum load capability (PWM mode) 500mA Maximum load capability (Bypass mode) PWM, Forced and Automatic Bypass Mode 3 Low-dropout and fast transient response LDOs 16-pin micro SMD Package Current Overload Protection Thermal Overload Protection Applications ■ Cellular Phones ■ Hand-Held Radios ■ Battery Powered RF Devices Typical Application 20181901 FIGURE 1. LM3280 Typical Application © 2007 National Semiconductor Corporation 201819 www.national.com LM3280 Connection Diagrams 20181902 16–Bump Thin Micro SMD Package, Large Bump See NS Package Number TLA16QQA Order Information Order Number LM3280TL LM3280TLX LM3280TL-275 LM3280TLX-275 LM3280TL-280 LM3280TLX-280 LM3280TL-290 LM3280TLX-290 LDO3 Option 2.85V (Default) 2.85V (Default) 2.75V* 2.75V* 2.80V* 2.80V* 2.90V* 2.90V* Package Marking (Note) XYTT V001 XYTT V001 XYTT V002 XYTT V002 XYTT V003 XYTT V003 XYTT V004 XYTT V004 Supplied As 250 Units, Tape and Reel 3000 Units, Tape and Reel 250 Units, Tape and Reel 3000 Units, Tape and Reel 250 Units, Tape and Reel 3000 Units, Tape and Reel 250 Units, Tape and Reel 3000 Units, Tape and Reel Note: The package marking “XY” designates the date code. “TT” is a NSC internal code for die traceability. *: The other 3 options apart from the default are available on request, contact your local sales representative. www.national.com 2 LM3280 Pin Descriptions Pin # A1 B1 C1 D1 A2 B2 C2 D2 A3 B3 C3 D3 A4 B4 C4 Name LDO1 LDO2 LDO3 ENLDO3 SVIN FB ENLDO2 VCON SGND ENBUCK ENLDO1 BYP BYPOUT PVIN SW LDO1 Output. LDO2 Output. LDO3 Output. LDO3 Enable Input. Set this digital input high to turn on LDO3. (ENBUCK pin must be also set high.) For turning LDO3 off, set low. Analog, Signal, and LDO Supply Input. Buck Converter Feedback Analog Input. Connect to the output at the output filter capacitor. LDO2 Enable Input. Set this digital input high to turn on LDO2. (ENBUCK pin must be also set high.) For turning LDO2 off, set low. Buck Converter Voltage Control Analog Input. This pin controls VOUT in PWM mode. Set: VOUT = 3 x VCON. Do not leave floating. Analog, Signal, and LDO Ground. Buck Converter Enable Input. Set this digital input high after Vin >2.7V for normal operation. For shutdown, set low. LDO1 Enable Input. Set this digital input high to turn on LDO1. (ENBUCK pin must be also set high.) For turning LDO1 off, set low. Forced Bypass Input. Use this digital input to command operation in Bypass mode. Set BYP low ( 0.94A) 25 µs Min Typ Max Units TSTARTUP Time for VOUT to rise to 3.4V VIN = 4.2V, COUT = 4.7µF, in PWM Mode RLOAD = 15Ω (Note 14) L = 2.2µH (ISAT = 0.94A) EN = Low to High VCON Input Capacitance VIN = 3.6V, VCON = 1V, Test Freq. = 100kHz 36 µs CCON TON_BYP 15 pF Bypass FET Turn On Time In VIN = 3.6V, VCON = 0.267V, Bypass Mode COUT = 4.7µF, RLOAD = 15Ω BYP = Low to High Auto Bypass Detect Delay Time (Note 10) 10 15 30 µs TBYP 20 µs 5 www.national.com LM3280 (Notes 2, 7) Limits in standard typeface are for TA = TJ = 25°C. Limits in boldface type apply over the full operating ambient temperature range (−30°C ≤ TA = TJ ≤ +85°C). Unless otherwise noted, specifications apply to the LM3280 with: VIN = 3.6V, ENBUCK = 3.6V, BYP = 0V, FB = 2V, VCON = 0.267V, ENLDOx = 3.6V (Note 16). Symbol VLDO ΔVLDO Parameter LDO Output Voltage Accuracy Line Regulation Load Regulation ILIM_LDO IPU RPD VDROP LDO Current Limit Pull-Up Current Pull-Down Resistance Dropout Voltage Conditions VLDO = 2.85V, IOUT = 1mA VIN = VLDO(nom) + 0.5V to 5.5V, IOUT = 1mA IOUT = 1mA to 20mA (Note 15) (Note 15) IOUT = -50mA, ENBUCK = all ENLDO = 0V IOUT = 20mA (Note 17) 30 40 10 Min -1 -2 0.1 0.01 40 60 13.5 70 0.04 55 80 17 115 Typ Max +1 +2 Units % % %/V %/mA mA mA Ω mV LDO1, 2, and 3 Electrical Characteristics LDO1, 2, and 3 System Characteristics Symbol PSRR TLDO_ON Parameter Power Supply Ripple Rejection Ratio Time to reach 90% of VLDO(nom) after ENLDO signal goes high. (Note 2) The following spec table entries are guaranteed by design if the component values in the typical application circuit are used. Unless otherwise noted, specifications apply to the LM3280 with: VIN = 3.6V. These parameters are not guaranteed by production testing. Conditions Test Freq. = 1KHz, VRIPPLE = 0.5Vpp COUT = 1µF, IOUT = 1mA, BYP = VIN VIN = ENBUCK = 3V, COUT = 1µF, ENLDOx = Low to High, RLOAD = 270Ω VIN = 3V, COUT = 1µF, ENBUCK = ENLDOx = Low to High, RLOAD = 270Ω TLDO_OFF Time to reach 0.1V of VLDO after ENLDO signal goes low. VIN = 3V, COUT = 1µF, ENLDOx = High to Low, IOUT = 0mA 50 200 µs 80 130 µs Min Typ 55 50 100 Max Units dB µs Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical Characteristics tables. Note 2: All voltages are with respect to the potential at the GND pins. Note 3: Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 150°C (typ.) and disengages at TJ = 125°C (typ.). Note 4: The Human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin. (MIL-STD-883 3015.7) The machine model is a 200pF capacitor discharged directly into each pin. National Semiconductor recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper ESD handling techniques can result in damage. Note 5: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX). Note 6: Junction-to-ambient thermal resistance (θJA) is taken from thermal measurements, performed under the conditions and guidelines set forth in the JEDEC standard JESD51-7. A 1" x 1", 4 layer, 1.5oz. Cu board was used for the measurements. The θJA, which is performed under the 4 layer cellphone board condition, is 86°C/W. Note 7: Min and Max limits are guaranteed by design, test, or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm. Note 8: The LM3280 is designed for mobile phone applications where turn-on after power-up is controlled by the system controller and where requirements for a small package size overrule increased die size for internal Under Voltage Lock-Out (UVLO) circuitry. Thus, it should be kept in shutdown by holding the EN pin low until the input voltage exceeds 2.7V. Note 9: Over-Voltage protection (OVP) threshold is the voltage above the nominal VOUT where the OVP comparator turns off the PFET switch while in PWM mode. Note 10: SVIN is compared to the programmed output voltage (VOUT). When SVIN – VOUT falls below VBYPASS− for longer than TBYP the Bypass FET turns on and the switching FETs turn off. This is called the Bypass mode. The device comes out of Bypass mode when SVIN – VOUT exceeds VBYPASS+ for longer than www.national.com 6 LM3280 TBYP, and PWM mode returns. The hysteresis for the bypass detection threshold VBYPASS+ – VBYPASS− will always be positive and will be approximately 200mV (typ.). Note 11: Shutdown current includes leakage current of PFET and Bypass FET. Note 12: Electrical Characteristic table reflects open loop data (FB = 0V and current drawn from SW pin ramped up until cycle by cycle current limit is activated). Refer to datasheet curves for closed loop data and its variation with regards to supply voltage and temperature. Closed loop current limit is the peak inductor current measured in the application circuit by increasing output current until output voltage drops by 10%. Note 13: The current is defined as the load current at which the BYPOUT voltage is 1V lower than PVIN. Note 14: The startup time is the time to reach 90% of 3.4V nominal output voltage from the ENBUCK being low to high. Note 15: The current is defined as the load current at which the LDOx voltage is 1.0V lower than the nominal output voltage. Note 16: The ENLDOx means that the one of ENLDO1, ENLDO2, and ENLDO3 is set high (> 1.2V) and the others are set 0V. Note 17: Dropout voltage is the voltage difference between the input and the output at which the output voltage drops to 100mV below the nominal voltage. 7 www.national.com LM3280 Typical Performance Characteristics otherwise noted) Quiescent Current vs Supply Voltage (VCON = 0.267V, FB = 2V, No Switching, LDO Disabled) (VIN = ENBUCK = 3.6V, ENLDOx = BYP = 0V, TA = 25°C, unless Quiescent Current vs Supply Voltage (VCON = 0.267V, FB = 2V, No Switching, LDO Enabled) 20181904 20181905 Shutdown Current vs Temperature (all EN = BYPOUT = VCON = SW = FB = 0V) LDO Line Transient Response (RLOAD = 270Ω, COUT = 1µF) 20181944 20181906 www.national.com 8 LM3280 LDO Turn ON (ENLDO = Low to High) LDO Turn ON (ENBUCK = ENLDO = Low to High) 20181940 20181941 LDO Turn OFF (ENLDO = High to Low) LDO Load Transient Response (COUT = 1µF) 20181942 20181943 LDO Voltage vs Supply Voltage LDO Voltage vs Temperature 20181936 20181937 9 www.national.com LM3280 LDO Dropout Voltage vs Output Current LDO Voltage vs Output Current (VIN = 3.6V) 20181938 20181939 PWM Startup (VCON = 1.13V) PWM Shutdown Response (VCON = 1.08V) 20181926 20181927 Automatic Bypass Operation (VIN = 4.2V to 3.0V) Forced Bypass Operation (VIN = 3.0V) 20181928 20181929 www.national.com 10 LM3280 Line Transient Response (VIN = 3.0V to 3.6V) Load Transient Response (VCON = 0.5V) 20181930 20181924 VCON Voltage Response (VIN = 4.2V, VCON = 0.5V / 1.1V) Timed Current Limit Response (Normal Operation to Short Circuit) 20181931 20181932 Output Voltage Ripple (VOUT = 1.5V) Output Voltage Ripple in Dropout (VIN = 3.75V, VOUT = 3.25V, IOUT = 200mA) 20181933 20181934 11 www.national.com LM3280 Switching Frequency Variation vs Temperature (VOUT = 1.5V) RDSON vs Temperature (Bypass FET) 20181908 20181922 RDSON vs Temperature (P-FET) RDSON vs Temperature (N-FET) 20181920 20181921 www.national.com 12 LM3280 PWM Output Voltage vs Supply Voltage (VOUT = 1.5V) PWM Output Voltage vs Temperature (VOUT = 1.5V) 20181909 20181910 Open/Closed Loop Current Limit vs Temperature (PWM mode) Dropout Voltage vs Output Current (Bypass mode, VIN = BYP = 3.6V) 20181912 20181913 13 www.national.com LM3280 VCON Voltage vs PWM Output Voltage (IOUT = 200mA) Low VCON Voltage vs Output Voltage (RLOAD = 15Ω) 20181914 20181915 Efficiency vs Output Voltage (VIN = 3.9V) Efficiency vs Output Current (VOUT = 1.5V) 20181917 20181918 www.national.com 14 LM3280 Efficiency vs Output Current (VOUT = 3.25V) 20181919 15 www.national.com LM3280 Block Diagram 20181935 FIGURE 2. Functional Block Diagram Device Information The LM3280 a multi-functional Power Management Unit, optimized for low-power handheld applications such as Cellular Phones. It incorporates one adjustable voltage PWM DC-DC converter with an internal Bypass FET and three LDOs. It also provides a separate enable pin for each output. The buck converter output voltage can be programmed from 0.8V to 3.6V in PWM mode. The buck converter is designed for a maximum load capability of 300mA in PWM mode and 500mA www.national.com 16 in Bypass mode. Maximum load range may vary from this depending on input voltage, output voltage and the inductor chosen. The LDO operates a nominal output voltage of 2.85V and maximum load current capability of 20mA. The buck converter is designed to allow the RF PA (Power Amplifier) to operate at maximum efficiency over a wide range of power levels from a single Li-Ion battery cell. It is based on current-mode buck architecture, with synchronous rectification for high efficiency. It has three of pin-selectable operating modes. Fixed-frequency PWM operation offers regulated out- LM3280 put at high efficiency while minimizing interference with sensitive IF and data acquisition circuits. Bypass mode (Forced or Automatic) turns on an internal FET bypass switch to power the PA directly from the battery. This helps the RF PA maintain its operating power during low battery conditions by reducing the dropout voltage across the buck converter. Shutdown mode turns the device off and reduces battery consumption to 0.1µA (typ.). DC PWM mode output voltage precision is +/-2% for 3.6VOUT. Efficiency is typically around 96% for a 120mA load with 3.2V output, 3.6V input. PWM mode quiescent current is 0.72mA typ. The output voltage is dynamically programmable from 0.8V to 3.6V by adjusting the voltage on the control pin (VCON) without the need for external feedback resistors. An LDO is used to provide a regulated 2.85V reference voltage supply to each RF PA. Since each LDO has its own enable pin, it can be used to enable or disable its respective PA. The LDO can be enabled only after the buck converter is activated. The LDO will automatically be disabled whenever the ENBUCK or ENLDOx is disabled. Single LDO must be turned on at the same time. Each LDO provides an active charge circuit. The LDO output is pulled to ground potential via an internal resistor when the ENBUCK or ENLDOx pin is low. Additional features include current overload protection and thermal shutdown. The buck converter also provides over voltage protection. The LM3280 is constructed using a chip-scale 16-pin micro SMD package. This package offers the smallest possible size, for space-critical applications such as cell phones, where board area is an important design consideration. Use of a micro SMD package requires special design considerations for implementation. (See Micro SMD Package Assembly and use in the Applications Information section.) Its fine bump-pitch requires careful board design and precision assembly equipment. Use of this package is best suited for opaque-case applications, where its edges are not subject to high-intensity ambient red or infrared light. Also, the system controller should set ENBUCK low during power-up and other low supply voltage conditions. (See Shutdown Mode in the Device Information section.) angular wave formed by the switch and synchronous rectifier at SW to a low-pass filter formed by the inductor and output filter capacitor. The output voltage is equal to the average voltage at the SW pin. PWM MODE While in PWM (Pulse Width Modulation) mode, the output voltage is regulated by switching at a constant frequency (2MHz typ.) and then modulating the energy per cycle to control power to the load. Energy per cycle is set by modulating the PFET switch on-time pulse width to control the peak inductor current. This is done by comparing the PFET drain current to a slope-compensated reference current generated by the error amplifier. At the beginning of each cycle, the clock turns on the PFET switch, causing the inductor current to ramp up. When the current sense signal ramps past the error amplifier signal, the PWM comparator turns off the PFET switch and turns on the NFET synchronous rectifier, ending the first part of the cycle. If an increase in load pulls the output down, the error amplifier output increases, which allows the inductor current to ramp higher before the comparator turns off the PFET. This increases the average current sent to the output and adjusts for the increase in the load. The minimum on-time of PFET in PWM mode is 50ns (typ.). BYPASS MODE The buck converter contains an internal PFET switch for bypassing the PWM DC-DC converter during Bypass mode. In Bypass mode, this PFET is turned on to power the PA directly from the battery for maximum RF output power. Bypass mode is more efficient than operating in PWM mode at 100% duty cycle because the resistance of the bypass PFET is less than the series resistance of the PWM PFET and inductor. This translates into higher voltage available on the output in Bypass mode, for a given battery voltage. The part can be placed in bypass mode by sending BYP pin high. This is called Forced Bypass Mode and it remains in bypass mode until BYP pin goes low. Alternatively the part can go into Bypass mode automatically. This is called Auto-bypass mode or Automatic Bypass mode. The bypass switch turns on when the difference between the input voltage and programmed output voltage is less than 250mV (typ.) for more than the bypass delay time of 15µs (typ.). The bypass switch turns off when the input voltage is higher than the programmed output voltage by 450mV (typ.) for longer than the bypass delay time. The bypass delay time is provided to prevent false triggering into Automatic Bypass mode by either spikes or dips in VIN. This method is very system resource friendly in that the Bypass PFET is turned on automatically when the input voltage gets close to the output voltage, typical scenario of a discharging battery. It is also turned off automatically when the input voltage rises, typical scenario of a charger connected. Another scenario could be changes made to VCON voltage causing Bypass PFET to turn on and off automatically. It is recommended to connect BYPOUT pin directly to the output capacitor with a separate trace and not to the FB pin. OPERATING MODE SELECTION CONTROL The BYP digital input pin is used to select between PWM/ Auto-bypass and Bypass operating mode. Setting BYP pin high (>1.2V) places the device in Forced Bypass mode. Setting BYP pin low (1.2V) after the buck converter has been enabled. The LDO will automatically be disabled whenever the ENBUCK or ENLDOx is disabled. Only one LDO may be enabled on at a time. A 2µs period of time needs to occur between disabled one LDO and enabling another. Otherwise, all LDOs are disabled. CHARGE AND DISCHARGE Each LDO includes an active charge circuit. 7.5us (typ.) after the LDO is enabled, the current limit of the LDO is set to 60mA. A 1µF load capacitor will be charged to 90% of the nominal output voltage in approximately 50us (typ.). (Note: This number is based on the assumption that the PWM loop has been enabled and given time to stabilize before the LDO is enabled.) The current limit is then reduced to 40mA. An internal pull-down resistor is also included in each LDO. The LDO discharges the output capacitor through the pulldown resistor when LDO is disabled. Shutdown Mode Setting the ENBUCK digital pin low (1.2V) enables normal operation. ENBUCK should be set low to turn off the LM3280 during power-up and under voltage conditions when the power supply is less than the 2.7V minimum operating voltage. The LM3280 is designed for compact portable applications, such as cellular phones. In such applications, the system controller determines power supply sequencing and requirements for small package size outweigh the benefit of including UVLO (Under Voltage Lock-Out) circuitry. Thermal Overload Protection The LM3280 has a thermal overload protection function to protect the device from short-term misuse and overload conditions. When the junction temperature exceeds around 150° C, the device inhibits operation. Both the PFET and the NFET are turned off in PWM mode, and the Bypass PFET is turned off in Bypass mode. The LDO is also turned off. When the temperature drops below 125°C, normal operation resumes. Prolonged operation in thermal overload conditions may damage the device. www.national.com 18 LM3280 Application Information BUCK CONVERTER SETTING THE OUTPUT VOLTAGE The buck converter features a pin-controlled variable output voltage to eliminate the need for external feedback resistors. It can be programmed for an output voltage from 0.8V to 3.6V by setting the voltage on the VCON pin, as in the following formula: VOUT = 3 x VCON When VCON is between 0.267V and 1.20V, the output voltage will follow proportionally by 3 times of VCON. If VCON is over 1.20V (VOUT = 3.6V), sub-harmonic oscillation may occur because of insufficient slope compensation. If VCON voltage is less than 0.267V (VOUT = 0.8V), the output voltage may not be regulated due to the required on-time being less than the minimum on-time (50ns). The output voltage can go lower than 0.8V providing a limited VIN range is used. Refer to datasheet curve (Low VCON Voltage vs. Output Voltage) for details. This curve is for a typical part and there could be part to part variation for output voltages less than 0.8V over the limited VIN range. In addition, if the VCON is less than approximately 0.15V, the PWM mode output is turned off, but the internal bias circuits are still active. INDUCTOR SELECTION A 2.2μH inductor with saturation current rating over 940mA is recommended for almost all applications. The inductor resistance should be less than 0.2Ω for better efficiency. Table 1 lists suggested inductors and suppliers. TABLE 1. Suggested Inductors and Their Suppliers Model DO3314-222MX LPS3010-222MLC LPS3008-222MLC MIPSA2520D2R2** KSLI252010AG2R2* VLF3010AT-2R2M1R0 NR3010T2R2M NR3012T2R2M 1117AS-2R2M (DE2810C) Size (WxLxH) [mm] 3.3 x 3.3 x 1.4 3.1 x 3.1 x 1.0 3.1 x 3.1 x 0.8 2.5 x 2.0 x 1.2 2.5 x 2.0 x 1.0 2.6 x 2.8 x 1.0 3.0 x 3.0 x 1.0 3.0 x 3.0 x 1.2 2.8 x 3.0 x 1.0 Vendor Coilcraft Coilcraft Coilcraft FDK HitachiMetal TDK TaiyoYuden TaiyoYuden Toko density from current through the windings of the inductor exceeds what the inductor’s core material can support with a corresponding magnetic field. This can cause poor efficiency, regulation errors or stress to a DC-DC converter like the LM3280. CAPACITOR SELECTION The LM3280 is designed to be used with ceramic capacitors. Use a 10µF ceramic capacitor for the power input, a 4.7µF ceramic capacitor for the buck converter output, and a 1µF ceramic capacitor for the LDO and the signal input. Ceramic capacitors such as X5R, X7R and B are recommended for both filters. These provide an optimal balance between small size, cost, reliability and performance for cell phones and similar applications. Table 2 lists suggested capacitors and suppliers. TABLE 2. Suggested Capacitors and Their Suppliers Model C1608X5R0J475M C2012X5R0J106M GRM188B10J105KA01 LMK107BJ105KA C1608JB1C105K Size (EIA) 1608 (0603) 2012 (0805) 1608 (0603) 1608 (0603) 1608 (0603) Vendor TDK TDK Murata Taiyo-Yuden TDK The DC bias characteristics of the capacitor must be considered when making the selection. If smaller case size such as 1608 (0603) is selected, the DC bias could reduce the cap value by as much as 40%, in addition to the 20% tolerances and 15% temperature coefficients. Request DC bias curves from manufacturer when making selection. The buck converter has been designed to be stable with output capacitors as low as 3μF to account for capacitor tolerances. The LDO has been done with output capacitors as low as 0.5µF. These values include DC bias reduction, manufacturing tolerances and temp coefficients. The input filter capacitor supplies AC current drawn by the PFET switch of the LM3280 in the first part of each cycle and reduces the voltage ripple imposed on the input power source. A 1µF capacitor is also recommended close to SVIN pin. The output filter capacitor absorbs the AC inductor current, helps maintain a steady output voltage during transient load changes and reduces output voltage ripple. These capacitors must be selected with sufficient capacitance and sufficiently low ESR (Equivalent Series Resistance) to perform these functions. The ESR of the filter capacitors is generally a major factor in voltage ripple. MICRO SMD PACKAGE ASSEMBLY AND USE Use of the Micro SMD package requires specialized board layout, precision mounting and careful re-flow techniques, as detailed in National Semiconductor Application Note 1112. Refer to the section Surface Mount Technology (SMD) Assembly Considerations. For best results in assembly, alignment ordinals on the PC board should be used to facilitate placement of the device. The pad style used with Micro SMD package must be the NSMD (non-solder mask defined) type. This means that the solder-mask opening is larger than the pad size. This prevents a lip that otherwise forms if the soldermask and pad overlap, from holding the device off the surface of the board and interfering with mounting. See Application Note 1112 for specific instructions how to do this. The 16Bump package used for the LM3280 has 300 micron solder balls and requires 10.82 mil pads for mounting on the circuit board. The trace to each pad should enter the pad with a 90° entry angle to prevent debris from being caught in deep cor19 www.national.com Note *:Mass production in April 2007. Contact vendor for further information. **:Mass production in Feb. 2007. Contact vendor for futher information. If a higher value inductor is used the LM3280 may become unstable and exhibit large under or over shoot during line, load and VCON transients. If smaller inductance value is used, slope compensation maybe insufficient causing sub-harmonic oscillations. The device has been tested with inductor values in the range 1.55μH to 3.1μH to account for inductor tolerances. For low-cost applications, an un-shielded bobbin inductor can be used. For noise-critical applications, an un-shielded or shielded-bobbin inductor should be used. A good practice is to layout the board with footprints accommodating both types for design flexibility. This allows substitution of an un-shielded inductor, in the event that noise from low-cost bobbin models is unacceptable. Saturation occurs when the magnetic flux LM3280 ners. Initially, the trace to each pad should be 6-7 mil wide, for a section approximately 6 mil long or longer, as a thermal relief. Then each trace should neck up or down to its optimal width. The important criterion is symmetry. This ensures the solder bumps on the LM3280 re-flow evenly and that the device solders level to the board. In particular, special attention must be paid to the pads for bumps B4, C4 and D4. Because PVIN and PGND are typically connected to large copper planes, inadequate thermal relief can result in inadequate reflow of these bumps. The Micro SMD package is optimized for the smallest possible size in applications with red or infrared opaque cases. Because the Micro SMD package lacks the plastic encapsulation characteristic of larger devices, it is vulnerable to light. Backside metallization and/or epoxy coating, along with frontside shading by the printed circuit board, reduce this sensitivity. However, the package has exposed die edges. In particular, Micro SMD devices are sensitive to light, in the red and infrared range, shining on the package’s exposed die edges. Do not use or power-up the LM3280 while subjecting it to high intensity red or infrared light; otherwise degraded, unpredictable or erratic operation may result. Examples of light sources with high red or infrared content include the sun and halogen lamps. Place the device in a case opaque to red or infrared light. BOARD LAYOUT CONSIDERATIONS PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance of a DCDC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage loss in the traces. These can send erroneous signals to the DC-DC converter, resulting in poor regulation or instability. Poor layout can also result in re-flow problems leading to poor solder joints between the Micro SMD package and board pads. Poor solder joints can result in erratic or degraded performance. Good layout for the LM3280 can by implemented by following a few simple design rules. 1. Place the LM3280 on 10.82 mil pads. As a thermal relief, connect to each pad with a 7 mil wide, approximately 7 mil long traces, and when incrementally increase each trace to its optimal width. The important criterion is symmetry to ensure the solder bumps on the LM3280 reflow evenly (see Micro SMD Package Assembly and Use). 2. 3. 4. 5. 6. 7. Place the LM3280, inductor and filter capacitors close together and make the trace short. The traces between these components carry relatively high switching currents and act as antennas. Following this rule reduces radiated noise. Place the capacitors and inductor close to the LM3280. The input capacitor should be placed right next to the device between PVIN and PGND pin. Arrange the components so that the switching current loops curl in the same direction. During the first half of each cycle, current flows from the input filter capacitor, through the LM3280 and inductor to the output filter capacitor and back through ground, forming a current loop. In the second half of each cycle, current is pulled up from ground, through the LM3280 by the inductor, to the output filter capacitor and then back through ground, forming a second current loop. Routing these loops so the current curls in the same direction, prevents magnetic field reversal between the two half-cycles and reduces radiated noise. Connect the ground pins of the LM3280, and filter capacitors together using generous component side copper fill as a pseudo-ground plane. Then connect this to the ground-plane (if one is used) with several vias. This reduces ground plane noise by preventing the switching currents from circulating through the ground plane. It also reduces ground bounce at the LM3280 by giving it a low impedance ground connection. Use wide traces between the power components and for power connections to the DC-DC converter circuit. This reduces voltage errors caused by resistive losses across the traces. Route noise sensitive traces, such as the voltage feedback trace, away from noisy traces and components. The voltage feedback trace must remain close to the LM3280 circuit and should be routed directly from FB pin to VOUT at the output capacitor. A good approach is to route the feedback trace on another layer and to have a ground plane between the top layer and the layer on which the feedback trace is routed. This reduces EMI radiation on to the DC-DC converter’s own voltage feedback trace. It is recommended to connect BYPOUT pin to VOUT at the output capacitor using a separate trace, instead of connecting it directly to the FB pin for better noise immunity. www.national.com 20 LM3280 Physical Dimensions inches (millimeters) unless otherwise noted 16-Bump Thin Micro SMD, Large Bump X1 = 2.352mm ± 0.030mm X2 = 2.352mm ± 0.030mm X3 = 0.600mm ± 0.075mm NS Package Number TLA16QQA 21 www.national.com LM3280 Adjustable Step-Down DC-DC Converter and 3 LDOs for RF Power Management Notes THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. NATIONAL MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE ACCURACY OR COMPLETENESS OF THE CONTENTS OF THIS PUBLICATION AND RESERVES THE RIGHT TO MAKE CHANGES TO SPECIFICATIONS AND PRODUCT DESCRIPTIONS AT ANY TIME WITHOUT NOTICE. NO LICENSE, WHETHER EXPRESS, IMPLIED, ARISING BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. 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