LM3445M

LM3445 Triac Dimmable Offline LED Driver September 22, 2010 LM3445 Triac Dimmable Offline LED Driver General Description The LM3445 is an adaptive constant off-time AC/DC buck (step-down) constant current controller designed to be compatible with triac dimmers. The LM3445 provides a constant current for illuminating high power LEDs and includes a triac dim decoder. The dim decoder allows wide range LED dimming using standard triac dimmers. The high frequency capable architecture allows the use of small external passive components. The LM3445 includes a bleeder circuit to ensure proper triac operation by allowing current flow while the line voltage is low to enable proper firing of the triac. A passive PFC circuit ensures good power factor by drawing current directly from the line for most of the cycle, and provides a constant positive voltage to the buck regulator. Additional features include thermal shutdown, current limit and V CC under-voltage lockout. Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Triac dim decoder circuit for LED dimming Application voltage range 80VAC – 277VAC Capable of controlling LED currents greater than 1A Adjustable switching frequency Low quiescent current Adaptive programmable off-time allows for constant ripple current Thermal shutdown No 120Hz flicker Low profile 10 pin MSOP Package or 14 pin SOIC Patent pending drive architecture Applications ■ ■ ■ ■ Retro Fit Triac Dimming Solid State Lighting Industrial and Commercial Lighting Residential Lighting Typical LM3445 LED Driver Application Circuit 30060305 30060301 © 2010 National Semiconductor Corporation 300603 www.national.com LM3445 Connection Diagrams Top View Top View 30060303 10-Pin MSOP NS Package Number MUB10A 30060373 14-Pin SOIC NS Package Number M14A Ordering Information Order Number LM3445MM LM3445MMX LM3445M LM3445MX Spec. NOPB NOPB NOPB NOPB Package Type MSOP-10 MSOP-10 SOIC-14L SOIC-14L NSC Package Drawing MUB10A MUB10A M14A M14A Top Mark SULB SULB LM3445M LM3445M Supplied As 1000 Units, Tape and Reel 3500 Units, Tape and Reel 55 Units, Rail 2500 Units, Tape and Reel Pin Descriptions SOIC 12 13 MSOP 1 2 Name ASNS FLTR1 Description PWM output of the triac dim decoder circuit. Outputs a 0 to 4V PWM signal with a duty cycle proportional to the triac dimmer on-time. First filter input. The 120Hz PWM signal from ASNS is filtered to a DC signal and compared to a 1 to 3V, 5.85 kHz ramp to generate a higher frequency PWM signal with a duty cycle proportional to the triac dimmer firing angle. Pull above 4.9V (typical) to tri-state DIM. Input/output dual function dim pin. This pin can be driven with an external PWM signal to dim the LEDs. It may also be used as an output signal and connected to the DIM pin of other LM3445s or other LED drivers to dim multiple LED circuits simultaneously. OFF time setting pin. A user set current and capacitor connected from the output to this pin sets the constant OFF time of the switching controller. Second filter input. A capacitor tied to this pin filters the PWM dimming signal to supply a DC voltage to control the LED current. Could also be used as an analog dimming input. Circuit ground connection. LED current sense pin. Connect a resistor from main switching MOSFET source, ISNS to GND to set the maximum LED current. Power MOSFET driver pin. This output provides the gate drive for the power switching MOSFET of the buck controller. Input voltage pin. This pin provides the power for the internal control circuitry and gate driver. Bleeder pin. Provides the input signal to the angle detect circuitry as well as a current path through a switched 230Ω resistor to ensure proper firing of the triac dimmer. No Connect 14 3 DIM 1 3 4 7 8 9 10 2,5,6,11 4 5 6 7 8 9 10 - COFF FLTR2 GND ISNS GATE VCC BLDR N/C www.national.com 2 LM3445 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. BLDR to GND VCC, GATE, FLTR1 to GND ISNS to GND ASNS, DIM, FLTR2, COFF to GND COFF Input Current Continuous Power Dissipation (Note 2) -0.3V to +17V -0.3V to +14V -0.3V to +2.5V -0.3V to +7.0V 100mA Internally Limited ESD Susceptibility HBM (Note 3) Junction Temperature (TJ-MAX) Storage Temperature Range Maximum Lead Temp. Range (Soldering) 2 kV 150°C -65°C to +150°C 260°C Operating Conditions VCC Junction Temperature 8.0V to 12V −40°C to +125°C Electrical Characteristics Limits in standard type face are for TJ = 25°C and those with boldface type apply over the full Operating Temperature Range ( TJ = −40°C to +125°C). Minimum and Maximum limits are guaranteed through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = +25ºC, and are provided for reference purposes only. Symbol Parameter Bleeder resistance to GND Operating supply current Rising threshold Falling threshold Hysterisis 6.0 Conditions IBLDR = 10mA Min Typ 230 2.00 7.4 6.4 1 1.225 1.276 33 180 1.174 1.269 125 180 ISNS = 0 to 1.75V step 33 5.85 0.96 2.85 96.5 Observed on BLDR pin 6.79 3.85 VASNS = 2V VASNS = 2V VDIM = 1V VDIM = 4V PWM input voltage threshold Apply to FLTR1 pin 10 0.9 1.65 1.00 3.00 98.0 7.21 4 4.00 7.6 -4.3 2.80 -4.00 1.33 2.33 4.87 3.15 5.25 V MΩ -3.00 V 4.15 7.81 1.04 3.08 % V µs V mA 1.364 1.327 60 V Ω µs V ns µs ns kHz V Max 325 2.85 7.7 Units Ω mA V BLEEDER RBLDR VCC SUPPLY IVCC VCC-UVLO COFF VCOFF RCOFF tCOFF CURRENT LIMIT VISNS tISNS ISNS limit threshold Leading edge blanking time Current limit reset delay ISNS limit to GATE delay INTERNAL PWM RAMP fRAMP VRAMP DRAMP DIM DECODER tANG_DET VASNS IASNS Angle detect rising threshold ASNS filter delay ASNS VMAX ASNS drive capability sink ASNS drive capability source DIM low sink current DIM High source current VDIM DIM low voltage DIM high voltage VTSTH RDIM Tri-state threshold voltage DIM comparator tri-state impedance Frequency Valley voltage Peak voltage Maximum duty cycle Time out threshold Off timer sinking impedance Restart timer 3 www.national.com LM3445 Symbol VFLTR2 RFLTR2 VOS VDRVH VDRVL IDRV tDV Parameter FLTR2 open circuit voltage FLTR2 impedance Current sense comparator offset voltage GATE high saturation GATE low saturation Peak souce current Peak sink current Rise time Fall time Conditions Min 720 -4.0 Typ 750 420 0.1 0.24 0.22 -0.77 0.88 15 15 165 20 121 Max 780 4.0 0.50 0.50 Units mV kΩ mV V A ns CURRENT SENSE COMPARATOR GATE DRIVE OUTPUT IGATE = 50 mA IGATE = 100 mA GATE = VCC/2 GATE = VCC/2 Cload = 1 nF Cload = 1 nF (Note 4) THERMAL SHUTDOWN TSD Thermal shutdown temperature Thermal shutdown hysteresis THERMAL SHUTDOWN RθJA MSOP-10 junction to ambient °C/W °C Note 1: Absolute maximum ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions for which the device is intended to be functional, but device parameter specifications may not be guaranteed. For guaranteed specifications and test conditions, see the Electrical Characteristics. All voltages are with respect to the potential at the GND pin, unless otherwise specified. Note 2: Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 165°C (typ.) and disengages at TJ = 145°C (typ). Note 3: Human Body Model, applicable std. JESD22-A114-C. Note 4: Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design. In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (RθJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (RθJA × PD-MAX). www.national.com 4 LM3445 Typical Performance Characteristics fSW vs Input Line Voltage Efficiency vs Input Line Voltage 30060304 30060305 BLDR Resistor vs Temperature VCC UVLO vs Temperature 30060306 30060307 Min On-Time (tON) vs Temperature Off Threshold (C11) vs Temperature 30060308 30060309 5 www.national.com LM3445 Normalized Variation in fSW over VBUCK Voltage Leading Edge Blanking Variation Over Temperature 30060310 30060372 www.national.com 6 LM3445 Simplified Internal Block Diagram 30060311 FIGURE 1. Simplified Block Diagram 7 www.national.com LM3445 Application Information FUNCTIONAL DESCRIPTION The LM3445 contains all the necessary circuitry to build a linepowered (mains powered) constant current LED driver whose output current can be controlled with a conventional triac dimmer. OVERVIEW OF PHASE CONTROL DIMMING A basic "phase controlled" triac dimmer circuit is shown in Figure 2. 30060312 FIGURE 2. Basic Triac Dimmer An RC network consisting of R1, R2, and C1 delay the turn on of the triac until the voltage on C1 reaches the trigger voltage of the diac. Increasing the resistance of the potentiometer (wiper moving downward) increases the turn-on delay which decreases the on-time or "conduction angle" of the triac (θ). This reduces the average power delivered to the load. Voltage waveforms for a simple triac dimmer are shown in Figure 3. Figure 3a shows the full sinusoid of the input voltage. Even when set to full brightness, few dimmers will provide 100% on-time, i.e., the full sinusoid. 30060313 FIGURE 3. Line Voltage and Dimming Waveforms Figure 3b shows a theoretical waveform from a dimmer. The on-time is often referred to as the "conduction angle" and may be stated in degrees or radians. The off-time represents the delay caused by the RC circuit feeding the triac. The off-time be referred to as the "firing angle" and is simply 180° - θ. Figure 3c shows a waveform from a so-called reverse phase dimmer, sometimes referred to as an electronic dimmer. These typically are more expensive, microcontroller based dimmers that use switching elements other than triacs. Note that the conduction starts from the zero-crossing, and terminates some time later. This method of control reduces the noise spike at the transition. Since the LM3445 has been designed to assess the relative on-time and control the LED current accordingly, most phasecontrol dimmers, both forward and reverse phase, may be used with success. www.national.com 8 LM3445 Theory of Operation Refer to figure 4 below which shows the LM3445 along with basic external circuitry. 30060301 FIGURE 4. LM3445 Schematic 9 www.national.com LM3445 SENSING THE RECTIFIED TRIAC WAVEFORM A bridge rectifier, BR1, converts the line (mains) voltage (5c) into a series of half-sines as shown in 5b. Figure 5a shows a typical voltage waveform after diode D3 (valley fill circuit, or VBUCK). 30060315 FIGURE 5. Voltage Waveforms After Bridge Rectifier Without Triac Dimming 30060317 Figure 6c and 6b show typical triac dimmed voltage waveforms before and after the bridge rectifier. Figure 6a shows a typical triac dimmed voltage waveform after diode D3 (valley fill circuit, or VBUCK). FIGURE 7. LM3445 AC Line Sense Circuitry D1 is typically a 15V zener diode which forces transistor Q1 to “stand-off” most of the rectified line voltage. Having no capacitance on the source of Q1 allows the voltage on the BLDR pin to rise and fall with the rectified line voltage as the line voltage drops below zener voltage D1 (see the section on Angle Detect). A diode-capacitor network (D2, C5) is used to maintain the voltage on the VCC pin while the voltage on the BLDR pin goes low. This provides the supply voltage to operate the LM3445. Resistor R5 is used to bleed charge out of any stray capacitance on the BLDR node and may be used to provide the necessary holding current for the dimmer when operating at light output currents. TRIAC HOLDING CURRENT RESISTOR In order to emulate an incandescent light bulb (essentially a resistor) with any LED driver, the existing triac will require a small amount of holding current throughout the AC line cycle. An external resistor (R5) needs to be placed on the source of Q1 to GND to perform this function. Most existing triac dimmers only require a few milliamps of current to hold them on. A few “less expensive” triacs sold on the market will require a bit more current. The value of resistor R5 will depend on: • What type of triac the LM3445 will be used with • How many light fixtures are running off of the triac With a single LM3445 circuit on a common triac dimmer, a holding current resistor between 3 kΩ and 5 kΩ will be required. As the number of LM3445 circuits is added to a single dimmer, the holding resistor R5’s resistance can be increased. A few triac dimmers will require a resistor as low as 1 kΩ or lower for a single LM3445 circuit. The trade-off will be 10 30060316 FIGURE 6. Voltage Waveforms After Bridge Rectifier With Triac Dimming LM3445 LINE SENSING CIRCUITRY An external series pass regulator (R2, D1, and Q1) translates the rectified line voltage to a level where it can be sensed by the BLDR pin on the LM3445. www.national.com LM3445 performance vs efficiency. As the holding resistor R5 is increased, the overall efficiency per LM3445 will also increase. ANGLE DETECT The Angle Detect circuit uses a comparator with a fixed threshold voltage of 7.21V to monitor the BLDR pin to determine whether the triac is on or off. The output of the comparator drives the ASNS buffer and also controls the Bleeder circuit. A 4 µs delay line on the output is used to filter out noise that could be present on this signal. The output of the Angle Detect circuit is limited to a 0V to 4.0V swing by the buffer and presented to the ASNS pin. R1 and C3 comprise a low-pass filter with a bandwidth on the order of 1.0Hz. The Angle Detect circuit and its filter produce a DC level which corresponds to the duty cycle (relative on-time) of the triac dimmer. As a result, the LM3445 will work equally well with 50Hz or 60Hz line voltages. BLEEDER While the BLDR pin is below the 7.21V threshold, the bleeder MOSFET is on to place a small load (230Ω) on the series pass regulator. This additional load is necessary to complete the circuit through the triac dimmer so that the dimmer delay circuit can operate correctly. Above 7.21V, the bleeder resistor is removed to increase efficiency. FLTR1 PIN The FLTR1 pin has two functions. Normally, it is fed by ASNS through filter components R1 and C3 and drives the dim decoder. However, if the FLTR1 pin is tied above 4.9V (typical), e.g., to VCC, the Ramp Comparator is tri-stated, disabling the dim decoder. See the Master/Slave section. DIM DECODER The ramp generator produces a 5.85 kHz saw tooth wave with a minimum of 1.0V and a maximum of 3.0V. The filtered ASNS signal enters pin FLTR1 where it is compared against the output of the Ramp Generator. The output of the ramp comparator will have an on-time which is inversely proportional to the average voltage level at pin FLTR1. However, since the FLTR1 signal can vary between 0V and 4.0V (the limits of the ASNS pin), and the Ramp Generator signal only varies between 1.0V and 3.0V, the output of the ramp comparator will be on continuously for VFLTR1 < 1.0V and off continuously for VFLTR1 > 3.0V. This allows a decoding range from 45° to 135° to provide a 0 – 100% dimming range. The output of the ramp comparator drives both a commonsource N-channel MOSFET through a Schmitt trigger and the DIM pin (see the Master/Slave section for further functions of the DIM pin). The MOSFET drain is pulled up to 750 mV by a 50 kΩ resistor. Since the MOSFET inverts the output of the ramp comparator, the drain voltage of the MOSFET is proportional to the duty cycle of the line voltage that comes through the triac dimmer. The amplitude of the ramp generator causes this proportionality to "hard limit" for duty cycles above 75% and below 25%. The MOSFET drain signal next passes through an RC filter comprised of an internal 370 kΩ resistor, and an external capacitor on pin FLTR2. This forms a second low pass filter to further reduce the ripple in this signal, which is used as a reference by the PWM comparator. This RC filter is generally set to 10Hz. The net effect is that the output of the dim decoder is a DC voltage whose amplitude varies from near 0V to 750 mV as the duty cycle of the dimmer varies from 25% to 75%. This corresponds to conduction angles of 45° to 135°, respectively. The output voltage of the Dim Decoder directly controls the peak current that will be delivered by Q2 during its on-time. See the Buck Converter section for details. As the triac fires beyond 135°, the DIM decoder no longer controls the dimming. At this point the LEDs will dim gradually for one of two reasons: 1. The voltage at VBUCK decreases and the buck converter runs out of headroom and causes LED current to decrease as VBUCK decreases. 2. Minimum on-time is reached which fixes the duty-cycle and therefore reduces the voltage at VBUCK. The transition from dimming with the DIM decoder to headroom or minimum on-time dimming is seamless. LED currents from full load to as low as 0.5 mA can be easily achieved. VALLEY-FILL CIRCUIT VBUCK supplies the power which drives the LED string. Diode D3 allows VBUCK to remain high while V+ cycles on and off. VBUCK has a relatively small hold capacitor C10 which reduces the voltage ripple when the valley fill capacitors are being charged. However, the network of diodes and capacitors shown between D3 and C10 make up a "valley-fill" circuit. The valley-fill circuit can be configured with two or three stages. The most common configuration is two stages. Figure 8 illustrates a two and three stage valley-fill circuit. 30060318 FIGURE 8. Two and Three Stage Valley Fill Circuit 11 www.national.com LM3445 The valley-fill circuit allows the buck regulator to draw power throughout a larger portion of the AC line. This allows the capacitance needed at VBUCK to be lower than if there were no valley-fill circuit, and adds passive power factor correction (PFC) to the application. Besides better power factor correction, a valley-fill circuit allows the buck converter to operate while separate circuitry translates the dimming information. This allows for dimming that isn’t subject to 120Hz flicker that can be perceived by the human eye. VALLEY-FILL OPERATION When the “input line is high”, power is derived directly through D3. The term “input line is high” can be explained as follows. The valley-fill circuit charges capacitors C7 and C9 in series (see figure 9) when the input line is high. A three stage valley-fill circuit performs exactly the same as two-stage valley-fill circuit except now three capacitors are now charged in series, and when the line voltage decreases to: Diode D3 is reversed biased and three capacitors are in parallel to each other. The valley-fill circuit can be optimized for power factor, voltage hold up and overall application size and cost. The LM3445 will operate with a single stage or a three stage valley-fill circuit as well. Resistor R8 functions as a current limiting resistor during start-up, and during the transition from series to parallel connection. Resistors R6 and R7 are 1 M Ω bleeder resistors, and may or may not be necessary for each application. BUCK CONVERTER The LM3445 is a buck controller that uses a proprietary constant off-time method to maintain constant current through a string of LEDs. While transistor Q2 is on, current ramps up through the inductor and LED string. A resistor R3 senses this current and this voltage is compared to the reference voltage at FLTR2. When this sensed voltage is equal to the reference voltage, transistor Q2 is turned off and diode D10 conducts the current through the inductor and LEDs. Capacitor C12 eliminates most of the ripple current seen in the inductor. Resistor R4, capacitor C11, and transistor Q3 provide a linear current ramp that sets the constant off-time for a given output voltage. 30060319 FIGURE 9. Two stage Valley-Fill Circuit when AC Line is High The peak voltage of a two stage valley-fill capacitor is: As the AC line decreases from its peak value every cycle, there will be a point where the voltage magnitude of the AC line is equal to the voltage that each capacitor is charged. At this point diode D3 becomes reversed biased, and the capacitors are placed in parallel to each other (figure 10), and VBUCK equals the capacitor voltage. 30060321 FIGURE 10. Two stage Valley-Fill Circuit when AC Line is Low www.national.com 12 LM3445 30060323 FIGURE 11. LM3445 Buck Regulation Circuit OVERVIEW OF CONSTANT OFF-TIME CONTROL A buck converter’s conversion ratio is defined as: against the voltage of dim decoder output, FLTR2, at which point Q2 is turned off by the controller. Constant off-time control architecture operates by simply defining the off-time and allowing the on-time, and therefore the switching frequency, to vary as either VIN or VO changes. The output voltage is equal to the LED string voltage (VLED), and should not change significantly for a given application. The input voltage or VBUCK in this analysis will vary as the input line varies. The length of the on-time is determined by the sensed inductor current through a resistor to a voltage reference at a comparator. During the on-time, denoted by tON, MOSFET switch Q2 is on causing the inductor current to increase. During the on-time, current flows from VBUCK, through the LEDs, through L2, Q2, and finally through R3 to ground. At some point in time, the inductor current reaches a maximum (IL2-PK) determined by the voltage sensed at R3 and the ISNS pin. This sensed voltage across R3 is compared 30060325 FIGURE 12. Inductor Current Waveform in CCM During the off-period denoted by tOFF, the current through L2 continues to flow through the LEDs via D10. 13 www.national.com LM3445 MASTER/SLAVE OPERATION Multiple LM3445s can be configured so that large strings of LEDs can be controlled by a single triac dimmer. By doing so, smooth consistent dimming for multiple LED circuits is achieved. When the FLTR1 pin is tied above 4.9V (typical), preferably to VCC, the ramp comparator is tri-stated, disabling the dim decoder. This allows one or more LM3445 devices or PWM LED driver devices (slaves) to be controlled by a single LM3445 (master) by connecting their DIM pins together. MASTER/SLAVE CONFIGURATION National Semiconductor offers an LM3445 demonstration PCB for customer evaluation through our website. The following description and theory uses reference designators that follow our evaluation PCB. The LM3445 Master/Slave schematics are illustrated below (figures 13 - 15) for clarity. Each board contains a separate circuit for the Master and Slave function. Both the Master and Slave boards will need to be modified from their original stand alone function so that they can be coupled together. Only the Master LM3445 requires use of the Master/Slave circuit for any number of slaves. MASTER BOARD MODIFICATIONS • Remove R10 and replace with a BAS40 diode • Connect TP18 to TP14 (VCC) • Connect TP17 (gate of Q5) to TP15 (gate of Q2) SLAVE BOARD(S) MODIFICATIONS • Remove R11 (disconnects BLDR) • Tie TP14 (FLTR1) to VCC MASTER/SLAVE(S) INTERCONNECTION • Connect TP19 of Master to TP10 of Slave (Master VCC Control) • Connect TP6 (DIM pin) of Master to TP6 (DIM pin) of Slave (Master DIM Control) MASTER/SLAVE THEORY OF OPERATION By placing two series diodes on the Master VCC circuit one forces the master VCC UVLO to become the dominant threshold. When Master VCC drops below UVLO, GATE stops switching and the RC timer (>200 µs) rises above the TL431 threshold (2.5V) which in turn pulls down on the gate of the Slave pass device (Q1). The valley-fill circuit could consist of one large circuit to power all LM3445 series connected, or each LM3445 circuit could have a separate valley-fill circuit located near the buck converter. www.national.com 14 LM3445 MASTER/SLAVE CONNECTION DIAGRAM 30060326 FIGURE 13. Master Slave Configuration MASTER/SLAVE BLOCK DIAGRAMS 30060327 FIGURE 14. Master/Slave configuration with Separate Valley-Fill Circuits 15 www.national.com LM3445 30060328 FIGURE 15. Master/Slave configuration with One Valley-Fill Circuit THERMAL SHUTDOWN Thermal shutdown limits total power dissipation by turning off the output switch when the IC junction temperature exceeds 165°C. After thermal shutdown occurs, the output switch doesn’t turn on until the junction temperature drops to approximately 145°C. www.national.com 16 LM3445 Design Guide DETERMINING DUTY-CYCLE (D) Duty cycle (D) approximately equals: With efficiency of the buck converter in mind: Substitute equations and rearrange: With efficiency considered: For simplicity, choose efficiency between 75% and 85%. CALCULATING OFF-TIME The “Off-Time” of the LM3445 is set by the user and remains fairly constant as long as the voltage of the LED stack remains constant. Calculating the off-time is the first step in determining the switching frequency of the converter, which is integral in determining some external component values. PNP transistor Q3, resistor R4, and the LED string voltage define a charging current into capacitor C11. A constant current into a capacitor creates a linear charging characteristic. Off-time, and switching frequency can now be calculated using the equations above. SETTING THE SWITCHING FREQUENCY Selecting the switching frequency for nominal operating conditions is based on tradeoffs between efficiency (better at low frequency) and solution size/cost (smaller at high frequency). The input voltage to the buck converter (VBUCK) changes with both line variations and over the course of each half-cycle of the input line voltage. The voltage across the LED string will, however, remain constant, and therefore the off-time remains constant. The on-time, and therefore the switching frequency, will vary as the VBUCK voltage changes with line voltage. A good design practice is to choose a desired nominal switching frequency knowing that the switching frequency will decrease as the line voltage drops and increase as the line voltage increases (see figure 16). Resistor R4, capacitor C11 and the current through resistor R4 (iCOLL), which is approximately equal to VLED/R4, are all fixed. Therefore, dv is fixed and linear, and dt (tOFF) can now be calculated. Common equations for determining duty cycle and switching frequency in any buck converter: 30060310 FIGURE 16. Graphical Illustration of Switching Frequency vs VBUCK Therefore: 17 www.national.com LM3445 The off-time of the LM3445 can be programmed for switching frequencies ranging from 30 kHz to over 1 MHz. A trade-off between efficiency and solution size must be considered when designing the LM3445 application. The maximum switching frequency attainable is limited only by the minimum on-time requirement (200 ns). Worst case scenario for minimum on time is when VBUCK is at its maximum voltage (AC high line) and the LED string voltage (VLED) is at its minimum value. Given a fixed inductor value, L, this equation states that the change in the inductor current over time is proportional to the voltage applied across the inductor. During the on-time, the voltage applied across the inductor is, VL(ON-TIME) = VBUCK - (VLED + VDS(Q2) + IL2 x R3) Since the voltage across the MOSFET switch (Q2) is relatively small, as is the voltage across sense resistor R3, we can simplify this to approximately, VL(ON-TIME) = VBUCK - VLED During the off-time, the voltage seen by the inductor is approximately: VL(OFF-TIME) = VLED The value of VL(OFF-TIME) will be relatively constant, because the LED stack voltage will remain constant. If we rewrite the equation for an inductor inserting what we know about the circuit during the off-time, we get: The maximum voltage seen by the Buck Converter is: INDUCTOR SELECTION The controlled off-time architecture of the LM3445 regulates the average current through the inductor (L2), and therefore the LED string current. The input voltage to the buck converter (VBUCK) changes with line variations and over the course of each half-cycle of the input line voltage. The voltage across the LED string is relatively constant, and therefore the current through R4 is constant. This current sets the off-time of the converter and therefore the output volt-second product (VLED x off-time) remains constant. A constant volt-second product makes it possible to keep the ripple through the inductor constant as the voltage at VBUCK varies. Re-arranging this gives: From this we can see that the ripple current (Δi) is proportional to off-time (tOFF) multiplied by a voltage which is dominated by VLED divided by a constant (L2). These equations can be rearranged to calculate the desired value for inductor L2. Where: Finally: 30060340 FIGURE 17. LM3445 External Components of the Buck Converter The equation for an ideal inductor is: Refer to “Design Example” section of the datasheet to better understand the design process. www.national.com 18 LM3445 SETTING THE LED CURRENT The LM3445 constant off-time control loop regulates the peak inductor current (IL2). The average inductor current equals the average LED current (I AVE). Therefore the average LED current is regulated by regulating the peak inductor current. This is important to calculate because this peak current multiplied by the sense resistor R3 will determine when the internal comparator is tripped. The internal comparator turns the control MOSFET off once the peak sensed voltage reaches 750 mV. 30060325 Current Limit: Under normal circumstances, the trip voltage on the PWM comparator would be less than or equal to 750 mV, depending on the amount of dimming. However, if there is a short circuit or an excessive load on the output, higher than normal switch currents will cause a voltage above 1.27V on the ISNS pin which will trip the I-LIM comparator. The ILIM comparator will reset the RS latch, turning off Q2. It will also inhibit the Start Pulse Generator and the COFF comparator by holding the COFF pin low. A delay circuit will prevent the start of another cycle for 180 µs. VALLEY FILL CAPACITORS Determining voltage rating and capacitance value of the valley-fill capacitors: The maximum voltage seen by the valley-fill capacitors is: FIGURE 18. Inductor Current Waveform in CCM Knowing the desired average LED current, IAVE and the nominal inductor current ripple, ΔiL, the peak current for an application running in continuous conduction mode (CCM) is defined as follows: Or, the maximum, or "undimmed", LED current would then be, This is, of course, if the capacitors chosen have identical capacitance values and split the line voltage equally. Often a 20% difference in capacitance could be observed between like capacitors. Therefore a voltage rating margin of 25% to 50% should be considered. 19 www.national.com LM3445 Determining the capacitance value of the valley-fill capacitors: The valley fill capacitors should be sized to supply energy to the buck converter (VBUCK) when the input line is less than its peak divided by the number of stages used in the valley fill (tX). The capacitance value should be calculated when the triac is not firing, i.e. when full LED current is being drawn by the LED string. The maximum power is delivered to the LED string at this time, and therefore the most capacitance will be needed. operate at much lower and higher input voltages a range is needed to illustrate the design process. 2. How many stages are implemented in the valley-fill circuit (1, 2 or 3). In this example the most common valley-fill circuit will be used (two stages). 30060354 FIGURE 20. AC Line with Firing Angles 30060352 FIGURE 19. Two Stage Valley-Ffill VBUCK Voltage with no TRIAC Dimming From the above illustration and the equation for current in a capacitor, i = C x dV/dt, the amount of capacitance needed at VBUCK will be calculated as follows: At 60Hz, and a valley-fill circuit of two stages, the hold up time (tX) required at VBUCK is calculated as follows. The total angle of an AC half cycle is 180° and the total time of a half AC line cycle is 8.33 ms. When the angle of the AC waveform is at 30° and 150°, the voltage of the AC line is exactly ½ of its peak. With a two stage valley-fill circuit, this is the point where the LED string switches from power being derived from AC line to power being derived from the hold up capacitors (C7 and C9). 60° out of 180° of the cycle or 1/3 of the cycle the power is derived from the hold up capacitors (1/3 x 8.33 ms = 2.78 ms). This is equal to the hold up time (dt) from the above equation, and dv is the amount of voltage the circuit is allowed to droop. From the next section (“Determining Maximum Number of Series Connected LEDs Allowed”) we know the minimum VBUCK voltage will be about 45V for a 90VAC to 135VAC line. At 90VAC low line operating condition input, ½ of the peak voltage is 64V. Therefore with some margin the voltage at VBUCK can not droop more than about 15V (dv). (i) is equal to (POUT/VBUCK), where POUT is equal to (VLED x ILED). Total capacitance (C7 in parallel with C9) can now be calculated. See “ Design Example" section for further calculations of the valley-fill capacitors. Determining Maximum Number of Series Connected LEDs Allowed: The LM3445 is an off-line buck topology LED driver. A buck converter topology requires that the input voltage (VBUCK) of the output circuit must be greater than the voltage of the LED stack (VLED) for proper regulation. One must determine what the minimum voltage observed by the buck converter will be before the maximum number of LEDs allowed can be determined. Two variables will have to be determined in order to accomplish this. 1. AC line operating voltage. This is usually 90VAC to 135VAC for North America. Although the LM3445 can Figure 21 show three triac dimmed waveforms. One can easily see that the peak voltage (VPEAK) from 0° to 90° will always be: Once the triac is firing at an angle greater than 90° the peak voltage will lower and equal to: The voltage at VBUCK with a valley fill stage of two will look similar to the waveforms of figure 22. The purpose of the valley fill circuit is to allow the buck converter to pull power directly off of the AC line when the line voltage is greater than its peak voltage divided by two (two stage valley fill circuit). During this time, the capacitors within the valley fill circuit (C7 and C8) are charged up to the peak of the AC line voltage. Once the line drops below its peak divided by two, the two capacitors are placed in parallel and deliver power to the buck converter. One can now see that if the peak of the AC line voltage is lowered due to variations in the line voltage, or if the triac is firing at an angle above 90°, the DC offset (VDC) will lower. VDC is the lowest value that voltage VBUCK will encounter. Example: Line voltage = 90VAC to 135VAC Valley-Fill = two stage Depending on what type and value of capacitors are used, some derating should be used for voltage droop when the 20 www.national.com LM3445 capacitors are delivering power to the buck converter. When the triac is firing at 135° the current through the LED string will be small. Therefore the droop should be small at this point and a 5% voltage droop should be a sufficient derating. With this derating, the lowest voltage the buck converter will see is about 42.5V in this example. 30060355 FIGURE 21. AC Line with Various Firing Angles 30060356 FIGURE 22. VBUCK Waveforms with Various Firing Angles To determine how many LEDs can be driven, take the minimum voltage the buck converter will see (42.5V) and divide it by the worst case forward voltage drop of a single LED. Example: 42.5V/3.7V = 11.5 LEDs (11 LEDs with margin) OUTPUT CAPACITOR A capacitor placed in parallel with the LED or array of LEDs can be used to reduce the LED current ripple while keeping the same average current through both the inductor and the LED array. With a buck topology the output inductance (L2) can now be lowered, making the magnetics smaller and less expensive. With a well designed converter, you can assume that all of the ripple will be seen by the capacitor, and not the LEDs. One must ensure that the capacitor you choose can handle the RMS current of the inductor. Refer to manufacture’s datasheets to ensure compliance. Usually an X5R or X7R capacitor between 1 µF and 10 µF of the proper voltage rating will be sufficient. SWITCHING MOSFET The main switching MOSFET should be chosen with efficiency and robustness in mind. The maximum voltage across the switching MOSFET will equal: The average current rating should be greater than: IDS-MAX = ILED(-AVE)(DMAX) RE-CIRCULATING DIODE The LM3445 Buck converter requires a re-circulating diode D10 (see the Typical Application circuit figure 4) to carry the inductor current during the MOSFET Q2 off-time. The most efficient choice for D10 is a diode with a low forward drop and near-zero reverse recovery time that can withstand a reverse voltage of the maximum voltage seen at VBUCK. For a common 110VAC ± 20% line, the reverse voltage could be as high as 190V. The current rating must be at least: ID = 1 - (DMIN) x ILED(AVE) Or: 21 www.national.com LM3445 Design Example The following design example illustrates the process of calculating external component values. Known: 1. Input voltage range (90VAC – 135VAC) 2. Number of LEDs in series = 7 3. Forward voltage drop of a single LED = 3.6V 4. LED stack voltage = (7 x 3.6V) = 25.2V Choose: 1. Nominal switching frequency, fSW-TARGET = 250 kHz 2. ILED(AVE) = 400 mA 3. Δi (usually 15% - 30% of ILED(AVE)) = (0.30 x 400 mA) = 120 mA 4. Valley fill stages (1,2, or 3) = 2 5. Assumed minimum efficiency = 80% Calculate: 1. Calculate minimum voltage VBUCK equals: 5. 6. Calculate C11 and R4: Choose current through R4: (between 50 µA and 100 µA) 70 µA 7. 8. 9. Use a standard value of 365 kΩ Calculate C11: 10. Use standard value of 120 pF 11. Calculate ripple current: 400 mA X 0.30 = 120 mA 12. Calculate inductor value at tOFF = 3 µs: 2. Calculate maximum voltage VBUCK equals: 13. Choose C10: 1.0 µF 200V 14. Calculate valley-fill capacitor values: VAC low line = 90VAC, VBUCK minimum equals 60V (no triac dimming at maximum LED current). Set droop for 20V maximum at full load and low line. 3. Calculate tOFF at VBUCK nominal line voltage: 4. Calculate tON(MIN) at high line to ensure that tON(MIN) > 200 ns: i) equals POUT/VBUCK (270 mA), dV equals 20V, dt equals 2.77 ms, and then CTOTAL equals 37 µF. Therefore C7 = C9 = 22 µF www.national.com 22 LM3445 LM3445 Design Example 1 Input = 90VAC to 135VAC, VLED = 7 x HB LED String Application @ 400 mA 30060369 23 www.national.com LM3445 Bill of Materials Qty 1 1 1 1 2 1 3 1 1 2 2 1 1 1 1 1 1 2 4 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 2 1 1 1 1 Ref Des U1 BR1 L1 L2 L3, L4 L5 C1, C2, C15 C3 C4 C5, C6 C7, C9 C10 C12 C11 C13 C14 D1 D2, D13 D3, D4, D8, D9 D10 D11 D12 R1 R2 R3 R4 R5 R6, R7 R8, R10 R9 R11 R12 R13 R14 RT1 Q1, Q2 Q3 Q5 J1 F1 Description IC, CTRLR, DRVR-LED, MSOP10 Bridge Rectifiier, SMT, 400V, 800 mA Common mode filter DIP4NS, 900 mA, 700 µH Inductor, SHLD, SMT, 1A, 470 µH Diff mode inductor, 500 mA 1 mH Bead Inductor, 160Ω, 6A Cap, Film, X2Y2, 12.5MM, 250VAC, 20%, 10 nF Cap, X7R, 0603, 16V, 10%, 470 nF Cap, X7R, 0603, 16V, 10%, 100 nF Cap, X5R, 1210, 25V, 10%, 22 µF Cap, AL, 200V, 105C, 20%, 33 µF Cap, Film, 250V, 5%, 10 nF Cap, X7R, 1206, 50V, 10%, 1.0 uF Cap, C0G, 0603, 100V, 5%, 120 pF Cap, X7R, 0603, 50V, 10%, 1.0 nF Cap, X7R, 0603, 50V, 10%, 22 nF Diode, ZNR, SOT23, 15V, 5% Diode, SCH, SOD123, 40V, 120 mA Diode, FR, SOD123, 200V, 1A Diode, FR, SMB, 400V, 1A IC, SHNT, ADJ, SOT23, 2.5V, 0.5% TVS, VBR = 209V Resistor, 0603, 1%, 280 kΩ Resistor, 1206, 1%, 100 kΩ Resistor, 1210, 5%, 1.8Ω Resistor, 0603, 1%, 576 kΩ Resistor, 1206, 1%, 1.00 kΩ Resistor, 0805, 1%, 1.00 MΩ Resistor, 1206, 0.0Ω Resistor, 1812, 0.0Ω Resistor, 0603, 0.0Ω Resistor, 0603, 1%, 33.2 kΩ Resistor, 0603, 1%, 2.0 kΩ Resistor, 0805, 1%, 3.3 MΩ Thermistor, 120V, 1.1A, 50Ω @ 25°C XSTR, NFET, DPAK, 300V, 4A XSTR, PNP, SOT23, 300V, 500 mA XSTR, NFET, SOT23, 100V, 170 mA Terminal Block 2 pos Fuse, 125V, 1,25A Yageo Panasonic Panasonic Rohm Thermometrics Fairchild Fairchild Fairchild Phoenix Contact bel RC0603JR-070RL ERJ-3EKF3322V ERJ-3EKF2001V MCR10EZHF3304 CL-140 FQD7N30TF MMBTA92 BSS123 1715721 SSQ 1.25 Mfr NSC DiodesInc Panasonic Coilcraft Coilcraft Steward Panasonic MuRata MuRata MuRata UCC Epcos Kemet MuRata Kemet Kemet OnSemi NXP Rohm OnSemi TI LittleFuse Panasonic Panasonic Panasonic Panasonic Panasonic Rohm Yageo Mfr PN LM3445MM HD04-T ELF-11090E MSS1260-474-KLB MSS1260-105KL-KLB HI1206T161R-10 ECQ-U2A103ML GRM188R71C474KA88D GRM188R71C104KA01D GRM32ER61E226KE15L EKXG201ELL330MK20S B32521C3103J C1206F105K5RACTU GRM1885C2A121JA01D C0603C102K5RACTU C0603C223K5RACTU BZX84C15LT1G BAS40H RF071M2S MURS140T3G TL431BIDBZR P6SMB220CA ERJ-3EKF2803V ERJ-8ENF1003V ERJ-14RQJ1R8U ERJ-3EKF5763V ERJ-8ENF1001V MCR10EZHF1004 RC1206JR-070RL www.national.com 24 LM3445 Physical Dimensions inches (millimeters) unless otherwise noted MSOP-10 Pin Package (MM) For Ordering, Refer to Ordering Information Table NS Package Number MUB10A SOIC-14 Pin Package (M) For Ordering, Refer to Ordering Information Table NS Package Number M14A 25 www.national.com LM3445 Triac Dimmable Offline LED Driver Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: www.national.com Products Amplifiers Audio Clock and Timing Data Converters Interface LVDS Power Management Switching Regulators LDOs LED Lighting Voltage References PowerWise® Solutions Temperature Sensors PLL/VCO www.national.com/amplifiers www.national.com/audio www.national.com/timing www.national.com/adc www.national.com/interface www.national.com/lvds www.national.com/power www.national.com/switchers www.national.com/ldo www.national.com/led www.national.com/vref www.national.com/powerwise WEBENCH® Tools App Notes Reference Designs Samples Eval Boards Packaging Green Compliance Distributors Quality and Reliability Feedback/Support Design Made Easy Design Support www.national.com/webench www.national.com/appnotes www.national.com/refdesigns www.national.com/samples www.national.com/evalboards www.national.com/packaging www.national.com/quality/green www.national.com/contacts www.national.com/quality www.national.com/feedback www.national.com/easy www.national.com/solutions www.national.com/milaero www.national.com/solarmagic www.national.com/training Applications & Markets Mil/Aero PowerWise® Design University Serial Digital Interface (SDI) www.national.com/sdi www.national.com/wireless www.national.com/tempsensors SolarMagic™ THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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