LM3450 Evaluation Board
LM3450 Evaluation Board
National Semiconductor Application Note 2098 James Patterson November 17, 2010
Introduction
The LM3450 evaluation board is designed to provide an AC to LED solution for a 15W LED load. Specifically, it takes an AC mains input and converts it to a constant current output of 350mA for a series string of 1 to 14 LEDs (maximum LED stack voltage of 45V). There are two assembly versions designed to operate from two different nominal AC input voltages, 120VAC or 230VAC. The board employs a two stage design with an LM3450 flyback primary stage and an LM3409 secondary stage. The LM3450 provides an isolated 50V regulated output voltage and a power factor corrected input current. The LM3409 uses the 50V flyback output as its input and provides a constant current of 350mA to the LED load. This two stage design provides excellent line and load regulation as well as isolation. The board is comprised of two copper layers with components on both sides and an FR4 dielelctric. The two stage design has several key advantages over a single stage design including: • No 120Hz LED current ripple. • Better dimming performance at low dimming levels. • Better line disturbance rejection. • Better efficiency using small LED stack voltages.
Specifications
120VAC 15W Version • Input Voltage Range: VIN = 90VAC – 135VAC • Regulated Flyback Output Voltage: VOUT = 50V • Maximum LED Stack Voltage: VLED < 45V • Regulated LED Current: ILED = 350mA 230VAC 15W Version • Input Voltage Range: VIN = 180VAC – 265VAC • Regulated Flyback Output Voltage: VOUT = 50V • Maximum LED Stack Voltage: VLED < 45V • Regulated LED Current: ILED = 350mA
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© 2010 National Semiconductor Corporation
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Typical Performance
120V 15W Version Efficiency vs. Output Power 230V 15W Version Efficiency vs. Output Power
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120V 15W Version Power Factor vs. Output Power
230V 15W Version Power Factor vs. Output Power
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Dimming Efficiency Comparison
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EMI Performance
120V 15W Conducted EMI Peak Scan Line and Neutral - CISPR/FCC Class B Quasi Peak and Average Limits
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230V 15W Conducted EMI Peak Scan Line and Neutral - CISPR/FCC Class B Quasi Peak and Average Limits
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120V 15W THD Measurements EN 61000-3 Class C Limits
230V 15W THD Measurements EN 61000-3 Class C Limits
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LM3450 Pin Descriptions
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Pin 1
Name VREF
Description 3V Reference
Application Information Reference Output: Connect directly to VADJ or to resistor divider feeding VADJ and to necessary external circuits. Analog Dim and Phase Dimming Range Input: Connect directly to VREF to force standard 70% phase dimming range. Connect to resistor divider from VREF to extend usable range of some phase dimmers or for analog dimming. Connect to GND for low power mode. Ramp Comparator Input: Connect a series resistor from FLT1 capacitor and a capacitor to GND to establish second filter pole. Angle Decoder Output: Connect a series resistor to a capacitor to ground to establish first filter pole. Open Drain PWM Dim Output: Connect to dimming input of output stage LED driver (directly or with isolation) to provide decoded dimming command. Multiplier and Angle Decoder Input: Connect to resistor divider from rectified AC line. Error Amplifier Output and PWM Comparator Input: Connect a capacitor to GND to set the compensation. Error Amplifier Inverting Input: Connect to output voltage via resistor divider to control PFC voltage loop for non-isolated designs. Connect to a 5.11kΩ resistor to GND for isolated designs (bypasses error amplifier). Also includes over-voltage protection and shutdown modes. Input Current Sense Non-Inverting Input: Connect to diode bridge return and resistor to GND to sense input current for dynamic hold. Connect a 0.1µF capacitor and Schottky diode to GND, and a 0.22µF capacitor to HOLD. System Ground MosFET Current Sense Input: Connect to positive terminal of sense resistor in PFC MosFET source. Gate Drive Output: Connect to gate of main power MosFET for PFC.Gate Drive Output: Connect to gate of main power MosFET for PFC. Power Supply Input: Connect to primary bias supply. Connect a 0.1µF bypass capacitor to ground. Demagnetization Sense Input: Connect a resistor to transformer/inductor winding to detect when all energy has been transferred. Open Drain Dynamic Hold Input: Connect to holding resistor which is connected to source of passFET. Pre-regulator Gate Bias Output: Connect to gate of passFET and to resistor to rectified AC (drain of passFET) to aid with startup.
2
VADJ
Analog Adjust
3 4 5 6 7
FLT2 FLT1 DIM VAC COMP
Filter 2 Filter 1 500 Hz PWM Output Sampled Rectified Line Compensation
8
FB
Feedback
9 10 11 12 13 14 15 16
ISEN GND CS GATE VCC ZCD HOLD BIAS
Input Current Sense Power Ground Current Sense Gate Drive Input Supply Zero Crossing Detector Dynamic Hold Pre-regulator Gate Bias
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LM3409HV Pin Descriptions
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Pin 1 2 3 4 5 6 7 8 9 10 DAP
Name UVLO IADJ EN COFF GND PGATE CSN CSP VCC VIN DAP
Description Input Under Voltage Lock-out Analog LED Current Adjust Logic Level Enable Off-time programming Power Ground Gate Drive Negative Current Sense Positive Current Sense
Application Information Connect to a resistor divider from VIN. UVLO threshold is 1.24V and hysteresis is provided by a 22µA current source. Apply a voltage between 0 - 1.24V, or connect a resistor from this pin to GND, to set the current sense threshold voltage. Apply a voltage >1.6V to enable device, a PWM signal to dim, or a voltage
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