LM3489MM

LM3489 Hysteretic PFET Buck Controller with Enable Pin May 2006 LM3489 Hysteretic PFET Buck Controller with Enable Pin General Description The LM3489 is a high efficiency PFET switching regulator controller that can be used to quickly and easily develop a small, cost effective, switching buck regulator for a wide range of applications. The hysteretic control architecture provides for simple design without any control loop stability concerns using a wide variety of external components. The PFET architecture also allows for low component count as well as ultra-low dropout, 100% duty cycle operation. Another benefit is high efficiency operation at light loads without an increase in output ripple. A dedicated Enable Pin provides a shutdown mode drawing only 7µA. Leaving the Enable Pin unconnected defaults to on. Current limit protection can be implemented by measuring the voltage across the PFET’s RDS(ON), thus eliminating the need for a sense resistor. A sense resistor may be used to improve current limit accuracy if desired. The cycle-by-cycle current limit can be adjusted with a single resistor, ensuring safe operation over a range of output currents. n n n n n n n n n n Wide 4.5V to 35V input range 1.239V to VIN adjustable output range High efficiency 93% ± 1.3% ( ± 2% over temp) internal reference 100% duty cycle operation Maximum operation frequency > 1MHz Current limit protection Dedicated enable pin (on if unconnected) Shutdown mode draws only 7µA supply current MSOP-8 Applications n n n n n n n n n Set-Top Box DSL/Cable Modem PC/IA Auto PC TFT Monitor Battery Powered Portable Applications Distributed Power Systems Always On Power High Power LED Driver Features n Easy to use control methodology n No control loop compensation required Typical Application Circuit 20186908 © 2006 National Semiconductor Corporation DS201869 www.national.com LM3489 Connection Diagram Top View 20186909 8 Lead Plastic MSOP-8 NS package Number MUA08A Package Marking and Ordering Information Order Number LM3489MM LM3489MMX Package Type MSOP-8 MSOP-8 Package Marking SKSB SKSB Supplied As: 1000 units on Tape and Reel 3500 units on Tape and Reel Pin Descriptions Pin # 1 2 3 Name ISENSE GND EN Description The current sense input pin. This pin should be connected to the PFET drain terminal directly or through a series resistor up to 600 ohm for 28V > Vin > 35V. Signal ground. Enable pin. Connect EN pin to ground to shutdown the part or float to enable operation (Internally pulled high). This pin can also be used to perform UVLO function. The feedback input. Connect the FB to a resistor voltage divider between the output and GND for an adjustable output voltage. Current limit threshold adjustment. Connected to an internal 5.5µA current source. A resistor is connected between this pin and VIN. The voltage across this resistor is compared with the ISENSE pin voltage to determine if an over-current condition has occurred. Power ground. Gate Drive output for the external PFET. PGATE swings between VIN and VIN-5V. Power supply input pin. 4 5 FB ADJ 6 7 8 PGND PGATE VIN www.national.com 2 LM3489 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. VIN Voltage PGATE Voltage FB Voltage ISENSE Voltage ADJ Voltage EN Voltage (Note 3) Maximum Junction Temp. Power Dissipation, TA = 25˚C (Note 2) −0.3V to 36V −0.3V to 36V −0.3V to 5V −1.0V to 36V -1V ( < 100ns) −0.3V to 36V −0.3V to 6V 150˚C 417mW ESD Susceptibilty (Note 4) Human Body Model Lead Temperature Vapor Phase (60 sec.) Infared (15 sec.) Storage Temperature 2kV 215˚C 220˚C −65˚C to 150˚C Operating Ratings (Note 1) Supply Voltage Range (VIN) EN Voltage (max.) (Note 3) Operating Junction Temperature (TJ) 4.5V to 35V 5.5V −40˚C to +125˚C Electrical Characteristics (Note 5), (Note 6) Specifications in Standard type face are for TJ = 25˚C, and in bold type face apply over the full Operating Temperature Range (TJ = −40˚C to +125˚C). Unless otherwise specified, VIN = 12V, VISNS = VIN − 1V, and VADJ = VIN − 1.1V. Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. Symbol ISHDN VEN VEN_HYST IQ VFB (Note 7) VHYST VCL_OFFSET ICL_ADJ TCL Parameter Shutdown input supply current Enable threshold voltage Enable threshold hysteresis Quiescent Current at ground pin Feedback Voltage Comparator Hysteresis Current limit comparator offset Current limit ADJ current source Current limit one shot off time VFB = 1.0V VFB = 1.5V VADJ = 11.5V VISNS = 11.0V VFB = 1.0V Source ISOURCE = 100mA Sink ISINK = 100mA IPGATE Driver Output current Source VIN = 7V, PGATE = 3.5V Sink VIN = 7V, PGATE = 3.5V IFB (Note 9) TONMIN_NOR TONMIN_CL FB pin Bias Current Minimum on time in normal operation Minimum on time in current limit VFB = 1.0V VISNS = VADJ + 0.1V Cload on OUT = 1000pF (Note 10) VISNS = VADJ - 0.1V VFB = 1.0V Cload on OUT = 1000pF (Note 10) 4.5 ≤ VIN ≤ 35V -20 3.0 6 FB = 1.5V (Not Switching) 1.223 1.214 EN = 0V Enable rising 1.15 Conditions Min Typ 7 1.5 130 280 1.239 10 14 0 5.5 9 400 1.255 1.264 15 20 +20 7.0 14 Max 15 1.85 Units µA V mV µA V mV mV µA µs RPGATE Driver resistance 5.5 8.5 0.44 0.1 300 100 200 750 Ω A nA ns ns %VFB/∆VIN Feedback Voltage Line Regulation 0.01 %/V 3 www.national.com LM3489 Electrical Characteristics (Note 5), (Note 6) Specifications in Standard type face are for TJ = 25˚C, and in bold type face apply over the full Operating Temperature Range (TJ = −40˚C to +125˚C). Unless otherwise specified, VIN = 12V, VISNS = VIN − 1V, and VADJ = VIN − 1.1V. Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. (Continued) Note 1: Absolute maximum ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions for which the device is intended to be functional, but device parameter specifications may not be guaranteed. For guaranteed specifications and test conditions, see the Electrical Characteristics. Note 2: The maximum allowable power dissipation is a function of the maximum junction temperature, TJ_MAX, the junction-to-ambient thermal resistance, θJA = 240˚C/W, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is calculated using: PD_MAX = (TJ_MAX - TA)/θJA. Exceeding the maximum allowable power dissipation will cause excessive die temperature. Note 3: This pin is internally pulled high and clamped at 8V typical. The absolute maximum and operating maximum rating specifies the input level allowed for an external voltage source applied to this pin without triggering the internal clamp with margin. Note 4: The human body model is a 100 pF capacitor discharged through a 1.5kΩ resistor into each pin. The machine model is a 200pF capacitor discharged directly into each pin. MIL-STD-883 3015.7 Note 5: All limits are guaranteed at room temperature (standard type face) and at temperature extremes (bold type face). All room temperature limits are 100% tested. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level (AOQL). Note 6: Typical numbers are at 25˚C and represent the most likely norm. Note 7: The VFB is the trip voltage at the FB pin when PGATE switches from high to low. Note 8: VCL = ICL_ADJ * RADJ Note 9: Bias current flows out from the FB pin. Note 10: A 1000pF capacitor is connected between VIN and PGATE. www.national.com 4 LM3489 Typical Performance Characteristics All curves taken at VIN = 12V with configuration in typical application circuit shown in Application Information section of this datasheet. TJ = 25˚C, unless otherwise specified. Quiescent Current vs Input Voltage Shutdown Current vs Input Voltage 20186901 20186902 Feedback Voltage vs Temperature Feedback Voltage Hysteresis vs Input Voltage 20186903 20186904 Feedback Voltage Hysteresis vs Temperature Current Limit ADJ Current vs Temperature 20186905 20186906 5 www.national.com LM3489 Typical Performance Characteristics All curves taken at VIN = 12V with configuration in typical application circuit shown in Application Information section of this datasheet. TJ = 25˚C, unless otherwise specified. (Continued) Current Limit One Shot OFF Time vs. Temperature VIN - VPGATE vs VIN 20186940 20186907 Minimum ON Time vs Temperature (Normal Operation) Minimum ON Time vs Temperature (Current Limit) 20186941 20186910 Operating ON Time vs Load Current Operating Frequency vs Input Voltage 20186952 20186911 www.national.com 6 LM3489 Typical Performance Characteristics All curves taken at VIN = 12V with configuration in typical application circuit shown in Application Information section of this datasheet. TJ = 25˚C, unless otherwise specified. (Continued) Efficiency vs Load Current (VOUT = 3.3V, L = 22µH) VOUT Regulation vs Load Current (VOUT = 3.3V, L = 22µH) 20186913 20186942 Efficiency vs Load Current (VOUT = 5V, L = 22µH) VOUT Regulation vs Load Current (VOUT = 5V, L = 22µH) 20186915 20186916 Power Up (No Load, CADJ = 1nF) (VIN Continuous Mode Operation = 12V, VOUT = 3.3 V, IOUT = 500mA) 20186957 20186918 7 www.national.com LM3489 Typical Performance Characteristics All curves taken at VIN = 12V with configuration in typical application circuit shown in Application Information section of this datasheet. TJ = 25˚C, unless otherwise specified. (Continued) Discontinuous Mode Operation (VIN = 12V, VOUT =3.3 V, IOUT = 50mA) Load Transient (VOUT = 3.3 V, 50 mA - 500 mA Load) 20186951 20186954 Enable Transient (VOUT = 3.3 V, 500 mA Loaded) Shutdown Transient (VOUT = 3.3 V, 500 mA Loaded) 20186955 20186956 www.national.com 8 LM3489 Simplified Functional Block Diagram 20186938 Functional Description OVERVIEW The LM3489 is a buck (step-down) DC-DC controller that uses a hysteretic control scheme. The control comparator is designed with approximately 10mV of hysteresis. In response to the voltage at the FB pin, the gate drive (PGATE pin) turns the external PFET on or off. When the inductor current is too high, the current limit protection circuit engages and turns the PFET off for approximately 9µs. Hysteretic control does not require an internal oscillator. Switching frequency depends on the external components and operating conditions. The operating frequency reduces at light loads resulting in excellent efficiency compared to other architectures. The output voltage can be programmed by two external resistors. The output can be set in a wide range from 1.239V (typical) to VIN. HYSTERETIC CONTROL CIRCUIT When the FB input to the control comparator falls below the reference voltage (1.239V), the output of the comparator switches to a low state. This results in the driver output, PGATE, pulling the gate of the PFET low and turning on the PFET. With the PFET on, the input supply charges COUT and supplies current to the load via the series path through the PFET and the inductor. Current through the Inductor ramps up linearly and the output voltage increases. As the FB voltage reaches the upper threshold, which is the internal reference voltage plus 10mV, the output of the comparator changes from low to high, and the PGATE responds by turning the PFET off. As the PFET turns off, the inductor voltage reverses, the catch diode turns on, and the current through the inductor ramps down. Then, as the output voltage reaches the internal reference voltage again, the next cycle starts. The LM3489 operates in discontinuous conduction mode at light load current or continuous conduction mode at heavy load current. In discontinuous conduction mode, current through the inductor starts at zero and ramps up to the peak, then ramps down to zero. The next cycle starts when the FB voltage reaches the reference voltage. Until then, the inductor current remains zero and the output capacitor supplies the load. The operating frequency is lower and switching losses reduced. In continuous conduction mode, current always flows through the inductor and never ramps down to zero. The output voltage (VOUT) can be programmed by 2 external resistors. It can be calculated as follows: VOUT = 1.239 x (R1 + R2) / R2 20186923 FIGURE 1. Hysteretic Window 9 www.national.com LM3489 Functional Description (Continued) The minimum output voltage ripple (VOUT_PP) can be calculated in the same way. VOUT_PP = VHYST (R1 + R2) / R2 For example, with VOUT set to 3.3V, VOUT_PP is 26.6mV VOUT_PP = 0.01 x (33K + 20k) / 20k = 0.0266V Operating frequency (F) is determined by knowing the input voltage, output voltage, inductor, VHYST, ESR (Equivalent Series Resistance) of output capacitor, and the delay. It can be approximately calculated using the formula: LM3489 turns off the external PFET for a period of 9µs(typical). The current limit is adjusted by an external resistor, RADJ. The current limit circuit is composed of the ISENSE comparator and the one-shot pulse generator. The positive input of the ISENSE comparator is the ADJ pin. An internal 5.5µA current sink creates a voltage across the external RADJ resistor. This voltage is compared to the voltage across the PFET or sense resistor. The ADJ voltage can be calculated as follows: VADJ = VIN − (RADJ x 3.0µA) Where 3.0µA is the minimum ICL-ADJ value. The negative input of the ISENSE comparator is the ISENSE pin that should be connected to the drain of the external PFET. The inductor current is determined by sensing the VDS. It can be calculated as follows. VISENSE = VIN − (RDSON x IIND_PEAK) = VIN − VDS where: α: (R1 + R2) / R2 delay: It includes the LM3489 propagation delay time and the PFET delay time. The propagation delay is 90ns typically. (See the Propagation Delay curve below.) 20186925 FIGURE 3. Current Sensing by VDS The current limit is activated when the voltage at the ADJ pin exceeds the voltage at the ISENSE pin. The ISENSE comparator triggers the 9µs one shot pulse generator forcing the driver to turn the PFET off. The driver turns the PFET back on after 9µs. If the current has not reduced below the set threshold, the cycle will repeat continuously. A filter capacitor, CADJ, should be placed as shown in Figure 3. CADJ filters unwanted noise so that the ISENSE comparator will not be accidentally triggered. A value of 100pF to 1nF is recommended in most applications. Higher values can be used to create a soft-start function (See Start Up section). The current limit comparator has approximately 100ns of blanking time. This ensures that the PFET is fully on when the current is sensed. However, under extreme conditions such as cold temperature, some PFETs may not fully turn on within the blanking time. In this case, the current limit threshold must be increased. If the current limit function is used, the on time must be greater than 100ns. Under low duty cycle operation, the maximum operating frequency will be limited by this minimum on time. During current limit operation, the output voltage will drop significantly as will operating frequency. As the load current is reduced, the output will return to the programmed voltage. However, there is a current limit fold back phenomenon inherent in this current limit architecture. See Figure 4. 20186914 FIGURE 2. Propagation Delay The operating frequency and output ripple voltage can also be significantly influenced by the speed up capacitor (Cff). Cff is connected in parallel with the high side feedback resistor, R1. The location of this capacitor is similar to where a phase lead capacitor would be located in a PWM control scheme. However it’s effect on hysteretic operation is much different. Cff effectively shorts out R1 at the switching frequency and applies the full output ripple to the FB pin without dividing by the R2/R1 ratio. The end result is a reduction in output ripple and an increase in operating frequency. When adding Cff, calculate the formula above with α = 1. The value of Cff depend on the desired operating frequency and the value of R2. A good starting point is 470pF ceramic at 100kHz decreasing linearly with increased operating frequency. Also note that as the output voltage is programmed below 2.5V, the effect of Cff will decrease significantly. CURRENT LIMIT OPERATION The LM3489 has a cycle-by-cycle current limit. Current limit is sensed across the VDS of the PFET or across an additional sense resistor. When current limit is activated, the www.national.com 10 LM3489 Functional Description (Continued) 20186926 20186927 FIGURE 4. Current Limit Fold Back Phenomenon At high input voltages ( > 28V) increased undershoot at the switch node can cause an increase in the current limit threshold. To avoid this problem, a low Vf Schottky catch diode must be used (See Catch Diode Selection). Additionally, a resistor can be placed between the ISENSE pin and the switch node. Any value in the range of 220Ω to 600Ω is recommended. START UP The current limit circuit is active during start-up. During start-up the PFET will stay on until either the current limit or the feedback comparator is tripped If the current limit comparator is tripped first then the fold back characteristic should be taken into account. Start-up into full load may require a higher current limit set point or the load must be applied after start-up. One problem with selecting a higher current limit is inrush current during start-up. Increasing the capacitance (CADJ) in parallel with RADJ results in a soft-start characteristic. CADJ and RADJ create an RC time constant forcing current limit to activate at a lower current. The output voltage will ramp more slowly when using this technique. There is example start-up plot for CADJ equal to 1nF in the Typical Performance Characteristics. Lower values for CADJ will have little to no effect on soft-start. EXTERNAL SENSE RESISTOR The VDS of a PFET will tend to vary significantly over temperature. This will result an equivalent variation in current limit. To improve current limit accuracy an external sense resistor can be connected from VIN to the source of the PFET, as shown in Figure 5. The current sense resistor, RCS should have value comparable with RDSON of the PFET used, typically in the range of 50mΩ to 200 mΩ. The equation in the Current Limit Operation section can be used by replacing the RDSON with RCS. FIGURE 5. Current Sensing by External Resistor PGATE When switching, the PGATE pin swings from VIN (off) to some voltage below VIN (on). How far the PGATE will swing depends on several factors including the capacitance, on time, and input voltage. PGATE voltage swing will increase with decreasing gate capacitance. Although PGATE voltage will typically be around VIN-5V, with very small gate capacitances, this value can increase to a typical maximum of VIN-8.3V. Additionally, PGATE swing voltage will increase as on time increases. During long on times, such as when operating at 100% duty cycle, the PGATE voltage will eventually fall to its maximum voltage of VIN-8.3V (typical) regardless of the PFET gate capacitance. The PGATE voltage will not fall below 0.4V (typical). Therefore, when the input voltage falls below approximately 9V, the PGATE swing voltage range will be reduced. At an input voltage of 7V, for instance, PGATE will swing from 7V to a minimum of 0.4V. DEVICE ENABLE, SHUTDOWN The LM3489 can be remotely shutdown by forcing the enable pin to ground. With EN pin grounded, the internal blocks other than the enable logic are de-activated and the shutdown current of the device will be lowered to only 7µA (typical). Releasing the EN pin allows for normal operation to resume. The EN pin is internally pulled high with the voltage clamped at 8V typical. For normal operation this pin should be left open. In case an external voltage source is applied to this pin for enable control, the applied voltage should not exceed the maximum operating voltage level specified in this datasheet, i.e. 5.5V. ADJUSTABLE UVLO The under-voltage-lockout function can be implemented as shown in Figure 6. By incorporating the feature of the internal enable threshold, the lockout level can be programmed through an external potential divider formed with R3 and R4. The input voltage information is detected and compared with the enable threshold and the device operation will be inhibited when VIN drops below the preset UVLO level. The UVLO and hysteresis voltage can be calculated as follows: 11 www.national.com LM3489 Functional Description (Continued) where VEN is the enable rising threshold voltage and VEN_HYST is the enable threshold hysteresis. 20186930 FIGURE 6. Adjustable UVLO Design Information Hysteretic control is a simple control scheme. However the operating frequency and other performance characteristics highly depend on external conditions and components. If either the inductance, output capacitance, ESR, VIN, or Cff is changed, there will be a change in the operating frequency and output ripple. The best approach is to determine what operating frequency is desirable in the application and then begin with the selection of the inductor and COUT ESR. INDUCTOR SELECTION (L) The important parameters for the inductor are the inductance and the current rating. The LM3489 operates over a wide frequency range and can use a wide range of inductance values. A rule of thumb is to use the equations used for ® National’s Simple Switchers . The equation for inductor ripple (∆i) as a function of output current (IOUT) is: for Iout < 2.0Amps ∆i ≤ Iout x Iout−0.366726 for Iout > 2.0Amps ∆i ≤ Iout x 0.3 The inductance can be calculated based upon the desired operating frequency where: The inductor should be rated to the following: The inductance value and the resulting ripple is one of the key parameters controlling operating frequency. The second is the inductor ESR that contribute to the steady state power loss due to current flowing through the inductor. OUTPUT CAPACITOR SELECTION (COUT) The ESR of the output capacitor times the inductor ripple current is equal to the output ripple of the regulator. However, the VHYST sets the first order value of this ripple. As ESR is increased with a given inductance, operating frequency increases as well. If ESR is reduced then the operating frequency reduces. The use of ceramic capacitors has become a common desire of many power supply designers. However, ceramic capacitors have a very low ESR resulting in a 90˚ phase shift of the output voltage ripple. This results in low operating frequency and increased output ripple. To fix this problem a low value resistor should be added in series with the ceramic output capacitor. Although counter intuitive, this combination of a ceramic capacitor and external series resistance provides highly accurate control over the output voltage ripple. Other types capacitor, such as Sanyo POS CAP and OSCON, Panasonic SP CAP, and Nichicon "NA" series, are also recommended and may be used without additional series resistance. For all practical purposes, any type of output capacitor may be used with proper circuit verification. And where D is the duty cycle, VD is the diode forward voltage, and VDS is the voltgae drop across the PFET. www.national.com 12 LM3489 Design Information (Continued) INPUT CAPACITOR SELECTION (CIN) A bypass capacitor is required between the input source and ground. It must be located near the source pin of the external PFET. The input capacitor prevents large voltage transients at the input and provides the instantaneous current when the PFET turns on. The important parameters for the input capacitor are the voltage rating and the RMS current rating. Follow the manufacturer’s recommended voltage derating. For high input voltage applications, low ESR electrolytic, Nichicon "UD" series or the Panasonic "FK" series are available. The RMS current in the input capacitor can be calculated as follows: CATCH DIODE SELECTION (D1) The important parameters for the catch diode are the peak current, the peak reverse voltage, and the average power dissipation. The average current through the diode can be calculated as following. ID_AVE = IOUT x (1 − D) The off state voltage across the catch diode is approximately equal to the input voltage. The peak reverse voltage rating must be greater than input voltage. In nearly all cases a Schottky diode is recommended. In low output voltage applications a low forward voltage provides improved efficiency. For high temperature applications, diode leakage current may become significant and require a higher reverse voltage rating to achieve acceptable performance. P-CHANNEL MOSFET SELECTION (Q1) The important parameters for the PFET are the maximum Drain-Source voltage (VDS), the on resistance (RDSON), Current rating, and the input capacitance. The input capacitor power dissipation can be calculated as follows. PD(CIN) = IRMS_CIN2 x ESRCIN The input capacitor must be able to handle the RMS current and the dissipation. Several input capacitors may be connected in parallel to handle large RMS currents. In some cases it may be much cheaper to use multiple electrolytic capacitors than a single low ESR, high performance capacitor such as OS-CON or Tantalum. The capacitance value should be selected such that the ripple voltage created by the switch current pulses is less than 10% of the total DC voltage across the capacitor. For high VIN conditions ( > 28V), the fast switching, high swing of the internal gate drive introduces unwanted disturbance to the VIN rail and the current limit function can be affected. In order to eliminate this potential problem, a high quality ceramic capacitor of 0.1 µF is recommended to filter out the internal disturbance at the VIN pin. This capacitor should be placed right next to the VIN pin for best performance. PROGRAMMING THE CURRENT LIMIT (RADJ) The current limit is determined by connecting a resistor (RADJ) between input voltage and the ADJ pin, pin 5. The voltage across the PFET when it is turned off is equal to the sum of the input voltage and the diode forward voltage. The VDS must be selected to provide some margin beyond the input voltage. PFET drain current, Id, must be rated higher than the peak inductor current, IIND-PEAK. Depending on operating conditions, the PGATE voltage may fall as low as VIN - 8.3V. Therefore, a PFET must be selected with a VGS maximum rating greater than the maximum PGATE swing voltage. As input voltage desreases below 9V, PGATE swing voltage may also decrease. At 5.0V input the PGATE will swing from VIN to VIN - 4.6V. To ensure that the PFET turns on quickly and completely, a low threshold PFET should be used when the input voltage is less than 7V. Total power loss in the FET can be approximated using the following equation: PDswitch = RDSON x IOUT2x D + F x IOUT x VIN x (ton + toff)/2 where: ton = FET turn on time toff = FET turn off time A value of 10ns to 20ns is typical for ton and toff. A PFET should be selected with a turn on rise time of less than 100ns. Slower rise times will degrade efficiency, can cause false current limiting, and in extreme cases may cause abnormal spiking at the PGATE pin. The RDSON is used in determining the current limit resistor value, RADJ. Note that the RDSON has a positive temperature coefficient. At 100˚C, the RDSON may be as much as 150% higher than the 25˚C value. This increase in RDSON must be considered when determining RADJ in wide temperature range applications. If the current limit is set based upon 25˚C ratings, then false current limiting can occur at high temperature. Keeping the gate capacitance below 2000pF is recommended to keep switching losses and transition times low. This will also help keep the PFET drive current low, which will improve efficiency and lower the power dissipation within the controller. As gate capacitance increases, operating frequency should be reduced and as gate capacitance decreases operating frequency can be increased. 13 www.national.com where: RDSON : Drain-Source ON resistance of the external PFET ICL_ADJ : 3.0µA minimum IIND_PEAK = ILOAD + IRIPPLE/2 Using the minimum value for ICL_ADJ (3.0µA) ensures that the current limit threshold will be set higher than the peak inductor current. The RADJ value must be selected to ensure that the voltage at the ADJ pin does not fall below 3.5V. With this in mind, RADJ_MAX = (VIN-3.5)/7µA. If a larger RADJ value is needed to set the desired current limit, either use a PFET with a lower RDSON, or use a current sense resistor as shown in Figure 5. The current limit function can be disabled by connecting the ADJ pin to ground and ISENSE to VIN. LM3489 Design Information (Continued) INTERFACING WITH THE ENABLE PIN The enable pin is internally pulled high with clamping at 8V typical. For normal operation this pin should be left open. To disable the device, the enable pin should be connected to ground externally. If an external voltage source is applied to this pin for enable control, the applied voltage should not exceed the maximum operating voltage level specified in this datasheet, i.e. 5.5V. For most applications, an open drain or open collector transistor can be used to short this pin to ground to shutdown the device . it sees a large AC voltage at the switching frequency. It is always a good practice to use a ground plane in the design, particularly for high current applications. The two ground pins, PGND and GND, should be connected by as short a trace as possible. They can be connected underneath the device. These pins are resistively connected internally by approximately 50Ω. The ground pins should be tied to the ground plane, or to a large ground trace in close proximity to both the FB divider and COUT grounds. The gate pin of the external PFET should be located close to the PGATE pin. However, if a very small FET is used, a resistor may be required between PGATE pin and the gate of the PFET to reduce high frequency ringing. Since this resistor will slow down the PFET’s rise time, the current limit blanking time should be taken into consideration (refer to Current Limiting Operation). The feedback voltage signal line can be sensitive to noise. Avoid inductive coupling with the inductor or the switching node. The FB trace should be kept away from those areas. Also, the orientation of the inductor can contribute un-wanted noise coupling to the FB path. If noise problems are observed it may be worth trying a different orientation of the inductor and select the best for final component placement. PCB Layout The PCB board layout is very important in all switching regulator designs. Poor layout can cause switching noise into the feedback signal and generate EMI problems. For minimal inductance, the wires indicated by heavy lines in schematic diagram should be as wide and short as possible. Keep the ground pin of the input capacitor as close as possible to the anode of the catch diode. This path carries a large AC current. The switching node, the node with the diode cathode, inductor and FET drain should be kept short. This node is one of the main sources for radiated EMI since 20186953 FIGURE 7. Typical Application Schematic for VOUT = 3.3V/500mA www.national.com 14 LM3489 Hysteretic PFET Buck Controller with Enable Pin Physical Dimensions inches (millimeters) unless otherwise noted 8 Lead Plastic MSOP-8 NS package Number MUA08A National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. 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