LM3881MMX

LM3881 Power Sequencer February 6, 2008 LM3881 Power Sequencer General Description The LM3881 Power Sequencer offers the easiest method to control power up and power down of multiple power supplies (switching or linear regulators). By staggering the startup sequence, it is possible to avoid latch conditions or large in-rush currents that can affect the reliability of the system. Available in MSOP-8 package, the Power Sequencer contains a precision enable pin and three open drain output flags. Upon enabling the LM3881, the three output flags will sequentially release, after individual time delays, permitting the connected power supplies to startup. The output flags will follow a reverse sequence during power down to avoid latch conditions. Time delays are defined using an external capacitor and the output flag states can be inverted by the user. Features ■ ■ ■ ■ ■ ■ ■ Easiest method to sequence rails Power up and power down control Input voltage range of 2.7V to 5.5V Small footprint MSOP-8 package Low quiescent current of 80 µA Output invert feature Timing controlled by small value external capacitor Applications ■ Multiple Supply Sequencing ■ Microprocessor / Microcontroller Sequencing ■ FPGA Sequencing Typical Application Circuit 30048401 © 2008 National Semiconductor Corporation 300484 www.national.com LM3881 Connection Diagram 30048402 Top View MSOP-8 Package Ordering Information Order Number LM3881MM LM3881MMX Package Type MSOP-8 NSC Package Drawing MUA08A Supplied As 1000 Units on Tape and Reel 3500 Units on Tape and Reel Pin Descriptions Pin # 1 2 3 4 5 6 7 8 Name VCC EN GND INV TADJ FLAG3 FLAG2 FLAG1 Function Input Supply Precision Enable Ground Output Logic Invert Timer Adjust Open Drain Output #3 Open Drain Output #2 Open Drain Output #1 www.national.com 2 LM3881 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. VCC, EN, INV, TADJ, FLAG1, FLAG2, FLAG3 to GND Storage Temperature Range Junction Temperature Lead Temperature (Soldering, 5 sec.) Minimum ESD Rating (Note 2) -0.3V to +6.0V -65°C to +150°C 150°C 260°C 2 kV Operating Ratings (Note 1) 2.7V to 5.5V -0.3V to VCC + 0.3V -40°C to +125°C VCC to GND EN, INV, TADJ, FLAG1, FLAG2, FLAG3 to GND Junction Temperature Electrical Characteristics Specifications with standard typeface are for TJ = 25°C, and those in bold face type apply over the full Operating Temperature Range (TJ = -40°C to +125°C). Minimum and Maximum limits are guaranteed through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C and are provided for reference purposes only. VCC = 3.3V, unless otherwise specified. Symbol IQ Open Drain Flags IFLAG VOL Time Delays ITADJ_SRC ITADJ_SNK VHTH VLTH TCLK TD1, TD4 TD2, TD3, TD5, TD6 ENABLE Pin VEN IEN INV Pin VIH_INV VIL_INV Invert Pin VIH Invert Pin VIL 90% VCC 10% VCC V V EN Pin Threshold EN Pin Pull-up Current VEN = 0V 1.0 1.22 7 1.5 V µA TADJ Source Current TADJ Sink Current High Threshold Level Low Threshold Level Clock Cycle Flag Time Delay Flag Time Delay CADJ = 10 nF 9 8 4 4 1.0 0.3 12 12 1.22 0.5 1.2 10 20 20 1.4 0.7 µA µA V V ms Clock Cycles Clock Cycles FLAGx Leakage Current FLAGx Output Voltage Low VFLAGx = 3.3V IFLAGx = 1.2 mA 0.001 1 0.4 µA V Parameter Operating Quiescent Current Conditions Min Typ (Note 3) (Note 4) 80 Max (Note 3) 110 Unit µA Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but does not guarantee specific performance limits. For guaranteed specifications and conditions, see the Electrical Characteristics. Note 2: The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. Note 3: Limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality Control (SQC) methods. The limits are used to calculate National's Average Outgoing Quality Level (AOQL). Note 4: Typical numbers are at 25°C and represent the most likely parametric norm. 3 www.national.com LM3881 Typical Performance Characteristics Quiescent Current vs VCC VCC = 3.3V unless otherwise specified. Quiescent Current vs Temperature 30048415 30048414 Enable Threshold vs Temperature Time Delay vs VIN (CADJ = 10 nF Nominal) 30048416 30048417 Time Delay vs Temperature (CADJ = 10 nF Nominal) VFLAG vs VIN (INV Low, RFLAG = 100 kΩ) 30048418 30048419 www.national.com 4 LM3881 FLAG Voltage vs Current 30048420 5 www.national.com LM3881 Block Diagram 30048403 www.national.com 6 LM3881 Application Information OVERVIEW The LM3881 Power Sequencer provides a simple solution for sequencing multiple rails in a controlled manner. A clock signal is established that facilitates control of the power up and power down of three open drain FET output flags. These flags permit connection to shutdown or enable pins of linear regulators and/or switching regulators to control the power supplies’ operation. This allows a complete power system to be designed without worrying about large in-rush currents or latch-up conditions that can occur during an uncontrolled startup. An invert (INV) pin is provided that reverses the logic of the output flags. This pin should be tied to a logic output high or low and not allowed to remain open circuit. The following discussion assumes the INV pin is held low such that the flag output is active high. A small external timing capacitor is connected to the TADJ pin that establishes the clock waveform. This capacitor is linearly charged/discharged by a fixed current source/sink, denoted ITADJ_SRC / ITADJ_SNK, of magnitude 12 µA between predefined voltage threshold levels, denoted VLTH and VHTH, to generate the timing waveform as shown in the following diagram. 30048409 FIGURE 1. TADJ Pin Timing Waveform Thus, the clock cycle duration is directly proportional to the timing capacitor value. Considering the TADJ voltage threshold levels and the charge/discharge current magnitude, it can be shown that the timing capacitor-clock period relationship is typically 120 µs/nF. For example, a 10 nF capacitor sets up a clock period of 1.2 ms. The timing sequence of the LM3881 is controlled by the enable (EN) pin. Upon power up, all the flags are held low until the precision enable pin exceeds its threshold. After the EN pin is asserted, the power up sequence will commence and the open-drain flags will be sequentially released. An internal counter will delay the first flag (FLAG1) from rising until a fixed time period, denoted by TD1 in the following timing diagram, elapses. This corresponds to at least nine, maximum ten, clock cycles depending on where EN is asserted relative to the clock signal. Upon release of the first flag, another timer will begin to delay the release of the second flag (FLAG2). This time delay, denoted TD2, corresponds to exactly eight clock periods. Similarly, FLAG3 is released after time delay TD3, again eight clock cycles, has expired. Accordingly, a TADJ capacitor of 10 nF generates typical time delays TD2 and TD3 of 9.6 ms and TD1 of between 10.8 ms and 12.0 ms. The power down sequence is the same as power up, but in reverse order. When the EN pin is de-asserted, a timer will begin that delays the third flag (FLAG3) from pulling low. The second and first flag will then follow in a sequential manner after their appropriate time delays. These time delays, denoted TD4, TD5, TD6, are equal to TD1, TD2, TD3, respectively. For robustness, the pull down FET associated with each flag is designed such that it can sustain a short circuit to VCC. 7 www.national.com LM3881 30048425 FIGURE 2. Power Up Sequence, INV Low 30048405 FIGURE 3. Power Up Sequence, INV High www.national.com 8 LM3881 30048406 FIGURE 4. Power Down Sequence, INV Low 30048424 FIGURE 5. Power Down Sequence, INV High 9 www.national.com LM3881 ENABLE CIRCUIT The enable circuit is designed with an internal comparator, referenced to a bandgap voltage (1.22V), to provide a precision threshold. This allows the timing to be set externally using a capacitor as shown in the diagram below. Alternatively, sequencing can be based on a certain event such as a line voltage reaching 90% of its nominal value by employing a resistor divider from VCC to Enable. 30048410 FIGURE 8. Enable Based On Input Supply Level 30048407 FIGURE 6. Precision Enable Circuit Using the internal pull-up current source to charge the external capacitor CEN, the time delay while the enable voltage reaches the required threshold, assuming EN is charging from 0V, can be calculated by the equation as follows. One of the features of the enable pin is that it provides glitch free operation. The timer will start counting at a rising threshold, but will always reset if the enable pin is de-asserted before the first output flag is released. This is illustrated in the timing diagram below, assuming INV is low. 30048411 FIGURE 9. Enable Glitch Timing, INV Low If the EN pin remains high for the entire power up sequence, then the part will operate as shown in the standard timing diagrams. However, if the EN signal is de-asserted before the power-up sequence is completed, the part will enter a controlled shutdown. This allows the system to initiate a controlled power sequence, preventing any latch conditions to occur. The following timing diagrams describe the flag sequence if the EN pin is de-asserted after FLAG1 releases, but before the entire power-up sequence is completed. INV is assumed low. 30048404 FIGURE 7. Enable Delay Timing A resistor divider can also be used to enable the LM3881 based on exceeding a certain VCC supply voltage threshold. Care needs to be taken when sizing the resistor divider to include the effects of the internal EN pull-up current source. The supply voltage for which EN is asserted is given by www.national.com 10 LM3881 30048412 30048413 FIGURE 10. Incomplete Sequence Timing, INV Low 11 www.national.com LM3881 Physical Dimensions inches (millimeters) unless otherwise noted MSOP-8 Package NS Package Number MUA08A www.national.com 12 LM3881 Notes 13 www.national.com LM3881 Power Sequencer Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Amplifiers Audio Clock Conditioners Data Converters Displays Ethernet Interface LVDS Power Management Switching Regulators LDOs LED Lighting PowerWise Serial Digital Interface (SDI) Temperature Sensors Wireless (PLL/VCO) www.national.com/amplifiers www.national.com/audio www.national.com/timing www.national.com/adc www.national.com/displays www.national.com/ethernet www.national.com/interface www.national.com/lvds www.national.com/power www.national.com/switchers www.national.com/ldo www.national.com/led www.national.com/powerwise www.national.com/sdi www.national.com/tempsensors www.national.com/wireless WEBENCH Analog University App Notes Distributors Green Compliance Packaging Design Support www.national.com/webench www.national.com/AU www.national.com/appnotes www.national.com/contacts www.national.com/quality/green www.national.com/packaging www.national.com/quality www.national.com/refdesigns www.national.com/feedback Quality and Reliability Reference Designs Feedback THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. NATIONAL MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE ACCURACY OR COMPLETENESS OF THE CONTENTS OF THIS PUBLICATION AND RESERVES THE RIGHT TO MAKE CHANGES TO SPECIFICATIONS AND PRODUCT DESCRIPTIONS AT ANY TIME WITHOUT NOTICE. NO LICENSE, WHETHER EXPRESS, IMPLIED, ARISING BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. TESTING AND OTHER QUALITY CONTROLS ARE USED TO THE EXTENT NATIONAL DEEMS NECESSARY TO SUPPORT NATIONAL’S PRODUCT WARRANTY. EXCEPT WHERE MANDATED BY GOVERNMENT REQUIREMENTS, TESTING OF ALL PARAMETERS OF EACH PRODUCT IS NOT NECESSARILY PERFORMED. NATIONAL ASSUMES NO LIABILITY FOR APPLICATIONS ASSISTANCE OR BUYER PRODUCT DESIGN. BUYERS ARE RESPONSIBLE FOR THEIR PRODUCTS AND APPLICATIONS USING NATIONAL COMPONENTS. PRIOR TO USING OR DISTRIBUTING ANY PRODUCTS THAT INCLUDE NATIONAL COMPONENTS, BUYERS SHOULD PROVIDE ADEQUATE DESIGN, TESTING AND OPERATING SAFEGUARDS. EXCEPT AS PROVIDED IN NATIONAL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NATIONAL ASSUMES NO LIABILITY WHATSOEVER, AND NATIONAL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO THE SALE AND/OR USE OF NATIONAL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE CHIEF EXECUTIVE OFFICER AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness. National Semiconductor and the National Semiconductor logo are registered trademarks of National Semiconductor Corporation. All other brand or product names may be trademarks or registered trademarks of their respective holders. Copyright© 2008 National Semiconductor Corporation For the most current product information visit us at www.national.com National Semiconductor Americas Technical Support Center Email: new.feedback@nsc.com Tel: 1-800-272-9959 www.national.com National Semiconductor Europe Technical Support Center Email: europe.support@nsc.com German Tel: +49 (0) 180 5010 771 English Tel: +44 (0) 870 850 4288 National Semiconductor Asia Pacific Technical Support Center Email: ap.support@nsc.com National Semiconductor Japan Technical Support Center Email: jpn.feedback@nsc.com