LM4859

LM4859 Stereo 1.2W Audio Sub-system with 3D Enhancement June 2005 LM4859 Stereo 1.2W Audio Sub-system with 3D Enhancement General Description The LM4859 is an integrated audio sub-system designed for stereo cell phone applications. Operating on a 3.3V supply, it combines a stereo speaker amplifier delivering 495mW per channel into an 8Ω load and a stereo headphone amplifier delivering 33mW per channel into a 32Ω load. It integrates the audio amplifiers, volume control, mixer, power management control, and National 3D enhancement all into a single package. In addition, the LM4859 routes and mixes the stereo and mono inputs into 10 distinct output modes. The LM4859 is controlled through an I2C compatible interface. Other features include an ultra-low current shutdown mode and thermal shutdown protection. Boomer audio power amplifiers are designed specifically to provide high quality output power with a minimal amount of external components. The LM4859 is available in a 30–bump TL package and a 28–lead LLP package. Key Specifications j POUT, Stereo Loudspeakers, 4Ω, 5V, 1% THD+N (LM4859SP) j POUT, Stereo Loudspeakers, 8Ω, 5V, 1.6W (typ) 1.2W (typ) 75mW (typ) 495mW (typ) 33mW (typ) 0.06µA (typ) 1% THD+N j POUT, Stereo Headphones, 32Ω, 5V, 1% THD+N j POUT, Stereo Loudspeakers, 8Ω, 3.3V, 1% THD+N j POUT, Stereo Headphones, 32Ω, 3.3V, 1% THD+N j Shutdown Current Features n n n n n n n n n n Stereo speaker amplifier Stereo headphone amplifier Independent Left, Right, and Mono volume controls National 3D enhancement I2C compatible interface Ultra low shutdown current Click and Pop Suppression circuit 10 distinct output modes Thermal Shutdown Protection Available in micro SMD and LLP packages Applications n n n n n Cell Phones PDAs Portable Gaming Devices Internet Appliances Portable DVD/CD/AAC/MP3 players Boomer ® is a registered trademark of National Semiconductor Corporation. © 2006 National Semiconductor Corporation DS201061 www.national.com LM4859 Typical Application 20106101 FIGURE 1. Typical Audio Amplifier Application Circuit www.national.com 2 LM4859 Connection Diagrams 30 Bump TL Package micro SMD Marking 20106163 20106108 Top View XY - 2 Digit date code TT - Die run traceability G - Boomer Family F1 - LM4859TL Top View (Bump-side down) Order Number LM4859TL See NS Package Number TLA30CZA Pin Connections (TL) Pin A1 A2 A3 A4 A5 B1 B2 B3 B4 B5 C1 C2 C3 C4 C5 D1 D2 D3 D4 D5 E1 E2 E3 E4 E5 F1 F2 F3 F4 F5 Name RLS+ VDD SDA RHP3D RHP GND I2CVDD ADR LHP3D VDD RLSNC SCL NC GND LLSVDD MIN NC NC GND BYPASS LLS3D RIN NC LLS+ VDD RLS3D LIN LHP Pin Description Right Loudspeaker Positive Output Power Supply Data Right Headphone 3D Right Headphone Output Ground I2C Interface Power Supply I2C Address Select Left Headphone 3D Power Supply Right Loudspeaker Negative Output No Connect Clock No Connect Ground Left Loudspeaker Negative Output Power Supply Mono Input No Connect No Connect Ground Half-supply bypass Left Loudspeaker 3D Right Stereo Input No Connect Left Loudspeaker Positive Output Power Supply Right Loudspeaker 3D Left Stereo Input Left Headphone Output 3 www.national.com LM4859 Connection Diagram 28 – Lead SP Package 20106199 Top View Order Number LM4859SP See NS Package Number SPA28A www.national.com 4 LM4859 Pin Connections (SP) Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Name RHP VDD NC GND NC NC LHP RIN LIN MIN LLS3D RLS3D BYPASS VDD LLS+ GND LLSVDD RLSGND RLS+ VDD I2CVDD SDA ADR SCL RHP3D LHP3D Pin Description Right Headphone Output Power Supply No Connect Ground No Connect No Connect Left Headphone Output Right Stereo Input Left Stereo Input Mono Input Left Loudspeaker 3D Right Loudspeaker 3D Half-supply bypass Power Supply Left Loudspeaker Positive Output Ground Left Loudspeaker Negative Output Power Supply Right Loudspeaker Negative Output Ground Right Loudspeaker Positive Output Power Supply I2C Interface Power Supply Data I2C Address Select Clock Right Headphone 3D Left Headphone 3D 5 www.national.com LM4859 Absolute Maximum Ratings (Notes 1, 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage Storage Temperature Input Voltage Power Dissipation (Note 3) ESD Susceptibility (Note 4) ESD Susceptibility (Note 5) Junction Temperature (TJ) Thermal Resistance 6.0V −65˚C to +150˚C −0.3V to VDD +0.3V Internally Limited 2000V 200V 150˚C θJA (SPA28A) (Note 10) θJC (SPA28A) θJA (TLA30CZA) (Note 12) 42˚C/W 3˚C/W 62˚C/W Operating Ratings Temperature Range TMIN ≤ TA ≤ TMAX Supply Voltage 2.7V ≤ VDD ≤ 5.5V 2.5V ≤ I2CVDD ≤ 5.5V −40˚C ≤ TA ≤ +85˚C Audio Amplifier Electrical Characteristics VDD = 5.0V Symbol Parameter Conditions (Notes 1, 2) The following specifications apply for VDD = 5.0V, unless otherwise specified. Limits apply for TA = 25˚C. LM4859 Typical (Note 6) VIN = 0V, No load; LD5 = RD5 = 0 (Note 9) Mode 4, 9, 14 Mode 2, 3, 7, 8, 12, 13 ISD Shutdown Current Output mode 0 (Note 9) LM4859SP Speaker; THD+N = 1%; f = 1kHz; 4Ω BTL PO Output Power Speaker; THD+N = 1%; f = 1kHz; 8Ω BTL Headphone; THD+N = 1%; f = 1kHz; 32Ω SE LD5 = RD5 = 0 THD+N Total Harmonic Distortion Plus Noise Speaker; PO = 400mW; f = 1kHz; 8Ω BTL Headphone; PO = 15mW; f = 1kHz; 32Ω SE Speaker; LD5 = RD5 = 0 A-weighted, 0dB gain; (Note 11) LD5 = RD5 = 0; Audio Inputs Terminated NOUT Output Noise Speaker; Mode 2, 3, 7, 8 Speaker; Mode 12, 13 Headphone; Mode 3, 4, 8, 9 Headphone; Mode 13, 14 f = 217Hz; Vrip = 200mVpp; CB = 2.2µF; 0dB gain; (Note 11) LD5 = RD5 = 0; Audio Inputs Terminated PSRR Power Supply Rejection Ratio Speaker; Mode 2, 3, 7, 8 Speaker; Mode 12, 13, Headphone; Mode 3, 4, 8, 9 Headphone; Mode 13, 14 70 64 86 73 60 54 dB dB (min) dB dB (min) 27 38 10 14 µV µV µV µV 0.05 0.04 5 40 % % mV (max) 5 13 0.2 1.6 8 21 3 mA (max) mA (max) µA (max) W Limits (Notes 7, 8) Units (Limits) IDD Supply Current 1.2 75 0.9 60 W (min) mW (min) VOS Offset Voltage www.national.com 6 LM4859 Audio Amplifier Electrical Characteristics VDD = 5.0V Symbol Parameter Conditions (Notes 1, 2) (Continued) The following specifications apply for VDD = 5.0V, unless otherwise specified. Limits apply for TA = 25˚C. LM4859 Typical (Note 6) LD5 = RD5 = 0 Loudspeaker; PO = 400mW; f = 1kHz Headphone; PO = 15mW; f = 1kHz Limits (Notes 7, 8) Units (Limits) Xtalk Crosstalk 85 85 120 230 dB dB ms ms TWU Wake-up Time CD5 = 0; CB = 2.2µF CD5 = 1; CB = 2.2µF Audio Amplifier Electrical Characteristics VDD = 3.0V Symbol Parameter Conditions (Notes 1, 2) The following specifications apply for VDD = 3.0V, unless otherwise specified. Limits apply for TA = 25˚C. LM4859 Typical (Note 6) VIN = 0V, No load; LD5 = RD5 = 0 (Note 9) Mode 4, 9, 14 Mode 2, 3, 7, 8, 12, 13 ISD PO Shutdown Current Output Power Mode 0 (Note 9) LM4859SP Speaker; THD+N = 1%; f = 1kHz; 4Ω BTL Speaker; THD+N = 1%; f = 1kHz; 8Ω BTL Headphone; THD+N = 1%; f = 1kHz; 32Ω SE LD5 = RD5 = 0 THD+N Total Harmonic Distortion Plus Noise Speaker; PO = 200mW; f = 1kHz; 8Ω BTL Headphone; PO = 10mW; f = 1kHz; 32Ω SE Speaker; LD5 = RD5 = 0 A-weighted; 0dB gain; (Note 11) LD5 = RD5 = 0; All Inputs Terminated NOUT Output Noise Speaker; Mode 2, 3, 7, 8 Speaker; Mode 12, 13 Headphone; Mode 3, 4, 8, 9 Headphone; Mode 13, 14 f = 217Hz, Vrip = 200mVpp; CB = 2.2µF; 0dB gain; (Note 11) LD5 = RD5 = 0; All Audio Inputs Terminated PSRR Power Supply Rejection Ratio Speaker; Mode 2, 3, 7, 8 Speaker; Mode 12, 13, Headphone; Mode 3, 4, 8, 9 Headphone; Mode 13, 14 70 65 87 75 62 55 dB dB (min) dB dB (min) 27 38 10 14 µV µV µV µV 0.05 0.04 5 40 % % mV (max) 4.5 11.2 0.06 530 7.5 19 2.5 mA (max) mA (max) µA (max) mW Limits (Notes 7, 8) Units (Limits) IDD Supply Current 400 25 320 20 mW (min) mW (min) PO Output Power VOS Offset Voltage 7 www.national.com LM4859 Audio Amplifier Electrical Characteristics VDD = 3.0V Symbol Parameter Conditions (Notes 1, 2) (Continued) The following specifications apply for VDD = 3.0V, unless otherwise specified. Limits apply for TA = 25˚C. LM4859 Typical (Note 6) LD5 = RD5 = 0 Loudspeaker; PO = 200mW; f = 1kHz Headphone; PO = 10mW; f = 1kHz Limits (Notes 7, 8) Units (Limits) Xtalk Crosstalk 82 82 80 140 dB dB ms ms TWU Wake-up Time CD5 = 0; CB = 2.2µF CD5 = 1; CB = 2.2µF Volume Control Electrical Characteristics (Notes 1, 2) The following specifications apply for VDD = 5.0V and VDD = 3.0V, unless otherwise specified. Limits apply for TA = 25˚C. Symbol Parameter Conditions LM4859 Typical (Note 6) maximum gain setting Stereo Volume Control Range minimum gain setting maximum gain setting Mono Volume Control Range minimum gain setting Volume Control Step Size Volume Control Step Size Error Stereo Channel to Channel Gain Mismatch Mute Attenuation Mode 12, Vin = 1VRMS Headphone maximum gain setting LIN and RIN Input Impedance minimum gain setting maximum gain setting MIN Input Impedance minimum gain setting 98 100 20 85 33.5 25 42 75 125 15 25 73 123 dB kΩ (min) kΩ (max) kΩ (min) kΩ (max) kΩ (min) kΩ (max) kΩ (min) kΩ (max) -34.5 1.5 +/-0.2 +/-0.5 -40.5 12 6 Limits (Notes 7, 8) 5.5 6.5 -41 -40 11.5 12.5 -35 -34 Units (Limits) dB (min) dB (max) dB (min) dB (max) dB (min) dB (max) dB (min) dB (max) dB dB (max) 0.3 dB Control Interface Electrical Characteristics (Notes 1, 2) The following specifications apply for VDD = 5V and VDD = 3V and 2.5V ≤ I2CVDD ≤ 5.5V, unless otherwise specified. Limits apply for TA = 25˚C. Symbol Parameter Conditions LM4859 Typical (Note 6) t1 t2 t3 t4 t5 SCL period SDA Set-up Time SDA Stable Time Start Condition Time Stop Condition time 8 Limits (Notes 7, 8) 2.5 100 0 100 100 Units (Limits) µs (min) ns (min) ns (min) ns (min) ns (min) www.national.com LM4859 Control Interface Electrical Characteristics (Notes 1, 2) Symbol Parameter Conditions (Continued) The following specifications apply for VDD = 5V and VDD = 3V and 2.5V ≤ I2CVDD ≤ 5.5V, unless otherwise specified. Limits apply for TA = 25˚C. LM4859 Typical (Note 6) Limits (Notes 7, 8) 0.7 x I2CVDD 0.3 x I2CVDD Units (Limits) V (min) V (max) VIH VIL Digital Input High Voltage Digital Input Low Voltage Note 1: All voltages are measured with respect to the GND pin unless otherwise specified. Note 2: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional but do not guarantee specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which guarantee specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not guaranteed for parameters where no limit is given, however, the typical value is a good indication of device performance. Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature, TA. The maximum allowable power dissipation is PDMAX = (TJMAX - TA) / θJA or the number given in Absolute Maximum Ratings, whichever is lower. For the LM4859 operating in Mode 3, 8, or 13 with VDD = 5V, 8Ω stereo loudspeakers and 32Ω stereo headphones, the total power dissipation is 1.348W. θJA = 62˚C/W. Note 4: Human body model, 100pF discharged through a 1.5kΩ resistor. Note 5: Machine Model, 220pF-240pF discharged through all pins. Note 6: Typicals are measured at +25˚C and represent the parametric norm. Note 7: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). Note 8: Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. Note 9: Shutdown current and supply current are measured in a normal room environment. All digital input pins are connected to I2CVDD. Note 10: The given θJA is for an LM4859SP mounted on a PCB with a 2in2 area of 10oz printed circuit board ground plane. Note 11: “0dB gain” refers to the volume control gain setting of MIN, LIN, and RIN set at 0dB. Note 12: The given θJA is for an LM4859TL mounted on a PCB with a 2in2 area of 10oz printed circuit board ground plane. External Components Description Components 1. CIN Functional Description This is the input coupling capacitor. It blocks the DC voltage and couples the input signal to the amplifier’s input terminals. CIN also creates a high pass filter with the internal resistor Ri (Input Impedance) at fC = 1/(2πRiCIN). This is the supply bypass capacitor. It filters the supply voltage applied to the VDD pin and helps reduce the noise at the VDD pin. This is the BYPASS pin capacitor. It filters the VDD / 2 voltage and helps maintain the LM4859’s PSRR. This is the output coupling capacitor. It blocks the DC voltage and couples the output signal to the speaker load RL. COUT also creates a high pass filter with RL at fO = 1/(2πRLCOUT). This resistor sets the gain of the National 3D effect. Please refer to the National 3D Enhancement section for information on selecting the value of R3D. This capacitor sets the frequency at which the National 3D effect starts to occur. Please refer to the National 3D Enhancement section for information on selecting the value of C3D. 2. 3. 4. 5. 6. CS CB COUT R3D C3D 9 www.national.com LM4859 Typical Performance Characteristics LM4859SP THD+N vs Frequency (Note 11) LM4859SP THD+N vs Frequency 20106155 20106156 VDD = 5V; LLS, RLS; PO = 400mW; RL = 4Ω; Mode 7; 0dB Gain LM4859SP THD+N vs Output Power VDD = 3V; LLS, RLS; PO = 200mW; RL = 4Ω; Mode 7; 0dB Gain LM4859SP THD+N vs Output Power 20106157 20106158 VDD = 5V; LLS, RLS; f = 1kHz; RL = 4Ω; Mode 7; 0dB Gain VDD = 3V; LLS, RLS; f = 1kHz; RL = 4Ω; Mode 7; 0dB Gain www.national.com 10 LM4859 Typical Performance Characteristics THD+N vs Frequency (Note 11) (Continued) THD+N vs Frequency 20106110 20106111 VDD = 5V; LLS, RLS; PO = 400mW; RL = 8Ω; Mode 7; 0dB Gain THD+N vs Frequency VDD = 3V; LLS, RLS; PO = 200mW; RL = 8Ω; Mode 7; 0dB Gain THD+N vs Frequency 20106112 20106113 VDD = 5V; LHP, RHP; PO = 15mW; RL = 32Ω; Mode 9; 0dB Gain VDD = 3V; LHP, RHP; PO = 10mW; RL = 32Ω; Mode 9; 0dB Gain 11 www.national.com LM4859 Typical Performance Characteristics THD+N vs Output Power (Note 11) (Continued) THD+N vs Output Power 20106120 20106121 VDD = 5V; LLS, RLS; f = 1kHz; RL = 8Ω; Mode 7; 0dB Gain THD+N vs Output Power VDD = 3V; LLS, RLS; f = 1kHz; RL = 8Ω; Mode 7; 0dB Gain THD+N vs Output Power 20106122 20106123 VDD = 5V; LHP, RHP; f = 1kHz; RL = 32Ω; Mode 9; 0dB Gain VDD = 3V; LHP, RHP; f = 1kHz; RL = 32Ω; Mode 9; 0dB Gain www.national.com 12 LM4859 Typical Performance Characteristics PSRR vs Frequency (Note 11) (Continued) PSRR vs Frequency 20106126 20106127 VDD = 5V; LLS, RLS; RL = 8Ω; 0db Gain; All audio inputs terminated Top-Mode 12, 13; Mid-Mode 2, 3; Bot-Mode 7, 8 PSRR vs Frequency VDD = 3V; LLS, RLS; RL = 8Ω; 0db Gain; All audio inputs terminated Top-Mode 12, 13; Mid-Mode 2, 3; Bot-Mode 7, 8 PSRR vs Frequency 20106128 20106129 VDD = 5V; LHP, RHP; RL = 32Ω; 0db Gain; All audio inputs terminated Top-Mode 13, 14; Mid-Mode 3, 4; Bot-Mode 8, 9 VDD = 3V; LHP, RHP; RL = 32Ω; 0db Gain; All audio inputs terminated Top-Mode 13, 14; Mid-Mode 3, 4; Bot-Mode 8, 9 13 www.national.com LM4859 Typical Performance Characteristics Crosstalk vs Frequency (Note 11) (Continued) Crosstalk vs Frequency 20106134 20106135 VDD = 5V; LLS, RLS; PO = 400mW; RL = 8Ω; Mode 7; 0db Gain; 3D off Top-Left to Right; Bot-Right to Left Crosstalk vs Frequency VDD = 3V; LLS, RLS; PO = 200mW; RL = 8Ω; Mode 7; 0db Gain; 3D off Top-Left to Right; Bot-Right to Left Crosstalk vs Frequency 20106136 20106137 VDD = 5V; LHP, RHP; PO = 15mW; RL = 32Ω; Mode 9; 0db Gain; 3D off Top-Left to Right; Bot-Right to Left VDD = 3V; LHP, RHP; PO = 10mW; RL = 32Ω; Mode 9; 0db Gain; 3D off Top-Left to Right; Bot-Right to Left www.national.com 14 LM4859 Typical Performance Characteristics Frequency vs Response (Note 11) (Continued) Frequency vs Response 20106138 LLS, RLS; RL = 8Ω; Mode 2; Full Gain 20106139 LLS, RLS; RL = 8Ω; Mode 7; Full Gain Frequency vs Response Frequency vs Response 20106140 20106141 LHP, RHP; RL = 32Ω; CO = 100µF Mode 4; Full Gain LHP, RHP; RL = 32Ω; CO = 100µF Mode 9; Full Gain 15 www.national.com LM4859 Typical Performance Characteristics Power Dissipation vs Output Power (Note 11) (Continued) Power Dissipation vs Output Power 20106145 20106146 LLS, RLS; RL = 8Ω; THD+N ≤ 1% Top-VDD = 5V; Bot-VDD = 3V per channel Output Power vs Load Resistance LHP, RHP; RL = 32Ω; THD+N ≤ 1% Top-VDD = 5V; Bot-VDD = 3V per channel Output Power vs Load Resistance 20106148 20106149 LLS, RLS; RL = 8Ω; Top-VDD = 5V, 10% THD+N; Topmid-VDD = 5V, 1% THD+N; Botmid-VDD = 3V, 10% THD+N; Bot-VDD = 3V, 1% THD+N LHP, RHP; RL = 32Ω; Top-VDD = 5V, 10% THD+N; Topmid-VDD = 5V, 1% THD+N; Botmid-VDD = 3V, 10% THD+N; Bot-VDD = 3V, 1% THD+N www.national.com 16 LM4859 Typical Performance Characteristics Output Power vs Supply Voltage (Note 11) (Continued) Output Power vs Supply Voltage 20106152 20106153 LLS, RLS; RL = 8Ω; Top–10% THD+N; Bot–1% THD+N LHP, RHP; RL = 32Ω; Top–10% THD+N; Bot–1% THD+N 17 www.national.com LM4859 Application Information 201061F5 FIGURE 2. I2C Bus Format 201061F4 FIGURE 3. I2C Timing Diagram TABLE 1. Chip Address A7 Chip Address ADR = 0 ADR = 1 1 1 1 A6 1 1 1 A5 1 1 1 A4 1 1 1 A3 1 1 1 A2 0 0 0 A1 EC 0 1 A0 0 0 0 EC - externally configured by ADR pin TABLE 2. Control Registers D7 Mono Volume control Left Volume control Right Volume control Mode control 0 0 1 1 D6 0 1 0 1 D5 0 LD5 RD5 CD5 D4 MD4 LD4 RD4 0 D3 MD3 LD3 RD3 CD3 D2 MD2 LD2 RD2 CD2 D1 MD1 LD1 RD1 CD1 D0 MD0 LD0 RD0 CD0 www.national.com 18 LM4859 Application Information MD4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 MD3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 (Continued) TABLE 3. Mono Volume Control MD2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 MD1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 MD0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Gain (dB) -34.5 -33.0 -31.5 -30.0 -28.5 -27.0 -25.5 -24.0 -22.5 -21.0 -19.5 -18.0 -16.5 -15.0 -13.5 -12.0 -10.5 -9.0 -7.5 -6.0 -4.5 -3.0 -1.5 0.0 1.5 3.0 4.5 6.0 7.5 9.0 10.5 12.0 19 www.national.com LM4859 Application Information LD4//RD4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 LD3//RD3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 (Continued) TABLE 4. Stereo Volume Control LD2//RD2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 LD1//RD1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 LD0//RD0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Gain (dB) -40.5 -39.0 -37.5 -36.0 -34.5 -33.0 -31.5 -30.0 -28.5 -27.0 -25.5 -24.0 -22.5 -21.0 -19.5 -18.0 -16.5 -15.0 -13.5 -12.0 -10.5 -9.0 -7.5 -6.0 -4.5 -3.0 -1.5 0.0 1.5 3.0 4.5 6.0 www.national.com 20 LM4859 Application Information Mode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CD3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 CD2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 (Continued) TABLE 5. Mixer and Output Mode CD1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 CD0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Loudspeaker L SD 2(GM x M) 2(GM x M) SD Loudspeaker R SD Headphone L SD Headphone R SD MUTE (GM x M) (GM x M) RESERVED 2(GM x M) 2(GM x M) SD MUTE (GM x M) (GM x M) RESERVED RESERVED 2(GL x L) 2(GL x L) SD 2(GR x R) 2(GR x R) SD MUTE (GL x L) (GL x L) RESERVED RESERVED 2(GL x L) + 2(GM x M) 2(GL x L) + 2(GM x M) SD 2(GRx R) + 2(GM x M) 2(GR x R) + 2(GM x M) SD MUTE (GL x L) + (GM x M) (GL x L) + (GM x M) RESERVED GL - Left Stereo Volume Control Gain GR - Right Stereo Volume Control Gain SD - Shutdown MUTE - Mute MUTE (GR x R) + (GM x M) (GR x R) + (GM x M) MUTE (GR x R) (GR x R) M - MIN Input Level L - LIN Input Level R - RIN Input Level GM - Mono Volume Control Gain TABLE 6. National 3D Enhancement LD5 RD5 0 1 0 1 Loudspeaker National 3D Off Loudspeaker National 3D On Headphone National 3D Off Headphone National 3D On TABLE 7. Wake-up Time Select CD5 0 1 Fast Wake-up Setting Slow Wake-up Setting 21 www.national.com LM4859 Application Information I2C COMPATIBLE INTERFACE (Continued) The LM4859 uses a serial bus, which conforms to the I2C protocol, to control the chip’s functions with two wires: clock (SCL) and data (SDA). The clock line is uni-directional. The data line is bi-directional (open-collector). The maximum clock frequency specified by the I2C standard is 400kHz. In this discussion, the master is the controlling microcontroller and the slave is the LM4859. The I2C address for the LM4859 is determined using the ADR pin. The LM4859’s two possible I2C chip addresses are of the form 111110X10 (binary), where X1 = 0, if ADR is logic low; and X1 = 1, if ADR is logic high. If the I2C interface is used to address a number of chips in a system, the LM4859’s chip address can be changed to avoid any possible address conflicts. The bus format for the I2C interface is shown in Figure 2. The bus format diagram is broken up into six major sections: The "start" signal is generated by lowering the data signal while the clock signal is high. The start signal will alert all devices attached to the I2C bus to check the incoming address against their own address. The 8-bit chip address is sent next, most significant bit first. The data is latched in on the rising edge of the clock. Each address bit must be stable while the clock level is high. After the last bit of the address bit is sent, the master releases the data line high (through a pull-up resistor). Then the master sends an acknowledge clock pulse. If the LM4859 has received the address correctly, then it holds the data line low during the clock pulse. If the data line is not held low during the acknowledge clock pulse, then the master should abort the rest of the data transfer to the LM4859. The 8 bits of data are sent next, most significant bit first. Each data bit should be valid while the clock level is stable high. After the data byte is sent, the master must check for another acknowledge to see if the LM4859 received the data. If the master has more data bytes to send to the LM4859, then the master can repeat the previous two steps until all data bytes have been sent. The "stop" signal ends the transfer. To signal "stop", the data signal goes high while the clock signal is high. The data line should be held high when not in use. I2C INTERFACE POWER SUPPLY PIN (I2CVDD) The LM4859’s I2C interface is powered up through the I2CVDD pin. The LM4859’s I2C interface operates at a voltage level set by the I2CVDD pin which can be set independent to that of the main power supply pin VDD. This is ideal whenever logic levels for the I2C interface are dictated by a microcontroller or microprocessor that is operating at a lower supply voltage than the main battery of a portable system. NATIONAL 3D ENHANCEMENT The LM4859 features a 3D audio enhancement effect that widens the perceived soundstage from a stereo audio signal. The 3D audio enhancement improves the apparent stereo channel separation whenever the left and right speakers are too close to one another, due to system size constraints or equipment limitations. An external RC network, shown in Figure 1, is required to enable the 3D effect. There are separate RC networks for both the stereo loudspeaker outputs as well as the stereo headphone outputs, so the 3D effect can be set independently for each set of stereo outputs. The amount of the 3D effect is set by the R3D resistor. Decreasing the value of R3D will increase the 3D effect. The C3D capacitor sets the low cutoff frequency of the 3D effect. Increasing the value of C3D will decrease the low cutoff frequency at which the 3D effect starts to occur, as shown by Equation 1. f3D(-3dB) = 1 / 2π(R3D)(C3D) (1) Activating the 3D effect will cause an increase in gain by a multiplication factor of (1 + 9kΩ/R3D). Setting R3D to 9kΩ will result in a gain increase by a multiplication factor of (1+ 9kΩ/9kΩ) = 2 or 6dB whenever the 3D effect is activated. The volume control can be programmed through the I2C compatible interface to compensate for the extra 6dB increase in gain. For example, if the stereo volume control is set at 0dB (11011 from Table 4) before the 3D effect is activated, the volume control should be programmed to –6dB (10111 from Table 4) immediately after the 3D effect has been activated. Setting R3D = 20kΩ and C3D = 0.22µF allows the LM4859 to produce a pronounced 3D effect with a minimal increase in output noise. EXPOSED-DAP MOUNTING CONSIDERATIONS The LM4859’s exposed-DAP (die attach paddle) package (SP) provides a low thermal resistance between the die and the PCB to which the part is mounted and soldered. This allows rapid heat transfer from the die to the surrounding PCB copper area heatsink, copper traces, ground plane, and finally, surrounding air. The result is a low voltage audio power amplifier that produces 1.6W dissipation in a 4Ω load at ≤ 1% THD+N and over 1.8W in a 3Ω load at 10% THD+N. This high power is achieved through careful consideration of necessary thermal design. Failing to optimize thermal design may compromise the LM4859’s high power performance and activate unwanted, though necessary, thermal shutdown protection. The SP package must have its DAP soldered to a copper pad on the PCB. The DAP’s PCB copper pad is then, ideally, connected to a large plane of continuous unbroken copper. This plane forms a thermal mass, heat sink, and radiation area. Place the heat sink area on either outside plane in the case of a two-sided or multi-layer PCB. (The heat sink area can also be placed on an inner layer of a multi-layer board. The thermal resistance, however, will be higher.) Connect the DAP copper pad to the inner layer or backside copper heat sink area with 9 (3 X 3) (SP) vias. The via diameter should be 0.012in - 0.013in with a 1.27mm pitch. Ensure efficient thermal conductivity by plugging and tenting the vias with plating and solder mask, respectively. Best thermal performance is achieved with the largest practical copper heat sink area. If the heatsink and amplifier share the same PCB layer, a nominal 2in2 area is necessary for 5V operation with a 4Ω load. Heatsink areas not placed on the same PCB layer as the LM4859 should be 4in2 for the same supply voltage and load resistance. The last two area recommendations apply for 25˚C ambient temperature. Increase the area to compensate for ambient temperatures above 25˚C. In all circumstances and under all conditions, the junction temperature must be held below 150˚C to prevent activating the LM4859’s thermal shutdown protection. An example PCB layout for the exposed-DAP SP package is www.national.com 22 LM4859 Application Information (Continued) shown in the Demonstration Board Layout section. Further detailed and specific information concerning PCB layout and fabrication and mounting an SP (LLP) is found in National Semiconductor’s AN1187. PCB LAYOUT AND SUPPLY REGULATION CONSIDERATIONS FOR DRIVING 3Ω AND 4Ω LOADS Power dissipated by a load is a function of the voltage swing across the load and the load’s impedance. As load impedance decreases, load dissipation becomes increasingly dependent on the interconnect (PCB trace and wire) resistance between the amplifier output pins and the load’s connections. Residual trace resistance causes a voltage drop, which results in power dissipated in the trace and not in the load as desired. For example, 0.1Ω trace resistance reduces the output power dissipated by a 4Ω load from 1.6W to 1.5W. The problem of decreased load dissipation is exacerbated as load impedance decreases. Therefore, to maintain the highest load dissipation and widest output voltage swing, PCB traces that connect the output pins to a load must be as wide as possible. Poor power supply regulation adversely affects maximum output power. A poorly regulated supply’s output voltage decreases with increasing load current. Reduced supply voltage causes decreased headroom, output signal clipping, and reduced output power. Even with tightly regulated supplies, trace resistance creates the same effects as poor supply regulation. Therefore, making the power supply traces as wide as possible helps maintain full output voltage swing. BRIDGE CONFIGURATION EXPLANATION The LM4859 consists of two sets of bridged-tied amplifier pairs that drive the left loudspeaker (LLS) and the right loudspeaker (RLS). For this discussion, only the LLS bridgetied amplifier pair will be referred to. The LM4859 drives a load, such as a speaker, connected between outputs, LLS+ and LLS-. In the LLS amplifier block, the output of the amplifier that drives LLS- serves as the input to the unity gain inverting amplifier that drives LLS+. This results in both amplifiers producing signals identical in magnitude, but 180˚ out of phase. Taking advantage of this phase difference, a load is placed between LLS- and LLS+ and driven differentially (commonly referred to as ’bridge mode’). This results in a differential or BTL gain of: AVD = 2(Rf / Ri) = 2 (2) coupling capacitor that single supply, single-ended amplifiers require. Eliminating an output coupling capacitor in a typical single-ended configuration forces a single-supply amplifier’s half-supply bias voltage across the load. This increases internal IC power dissipation and may permanently damage loads such as speakers. POWER DISSIPATION Power dissipation is a major concern when designing a successful single-ended or bridged amplifier. A direct consequence of the increased power delivered to the load by a bridge amplifier is higher internal power dissipation. The LM4859 has 2 sets of bridged-tied amplifier pairs driving LLS and RLS. The maximum internal power dissipation operating in the bridge mode is twice that of a singleended amplifier. From Equation (3) and (4), assuming a 5V power supply and an 8Ω load, the maximum power dissipation for LLS and RLS is 634mW per channel. PDMAX-LLS = 4(VDD)2 / (2π2 RL): Bridged PDMAX-RLS = 4(VDD)2 / (2π2 RL): Bridged (3) (4) The LM4859 also has a pair of single-ended amplifiers driving LHP and RHP. The maximum internal power dissipation for ROUT and LOUT is given by equation (5) and (6). From Equations (5) and (6), assuming a 5V power supply and a 32Ω load, the maximum power dissipation for LOUT and ROUT is 40mW per channel. PDMAX-LHP = (VDD)2 / (2π2 RL): Single-ended PDMAX-RHP = (VDD)2 / (2π2 RL): Single-ended (5) (6) The maximum internal power dissipation of the LM4859 occurs during output modes 3, 8, and 13 when both loudspeaker and headphone amplifiers are simultaneously on; and is given by Equation (7). PDMAX-TOTAL = PDMAX-LLS + PDMAX-RLS + PDMAX-LHP + PDMAX-RHP (7) The maximum power dissipation point given by Equation (7) must not exceed the power dissipation given by Equation (8): PDMAX’ = (TJMAX - TA) / θJA (8) Both the feedback resistor, Rf, and the input resistor, Ri, are internally set. Bridge mode amplifiers are different from single-ended amplifiers that drive loads connected between a single amplifier’s output and ground. For a given supply voltage, bridge mode has a distinct advantage over the single-ended configuration: its differential output doubles the voltage swing across the load. Theoretically, this produces four times the output power when compared to a single-ended amplifier under the same conditions. This increase in attainable output power assumes that the amplifier is not current limited and that the output signal is not clipped. Another advantage of the differential bridge output is no net DC voltage across the load. This is accomplished by biasing LLS- and LLS+ outputs at half-supply. This eliminates the 23 The LM4859’s TJMAX = 150˚C. In the SP package, the LM4859’s θJA is 42˚C/W. At any given ambient temperature TA, use Equation (8) to find the maximum internal power dissipation supported by the IC packaging. Rearranging Equation (8) and substituting PDMAX-TOTAL for PDMAX’ results in Equation (9). This equation gives the maximum ambient temperature that still allows maximum stereo power dissipation without violating the LM4859’s maximum junction temperature. TA = TJMAX - PDMAX-TOTAL θJA (9) www.national.com LM4859 Application Information (Continued) For a typical application with a 5V power supply, stereo 8Ω loudspeaker load, and the stereo 32Ω headphone load, the maximum ambient temperature that allows maximum stereo power dissipation without exceeding the maximum junction temperature is approximately 93.4˚C for the SP package. TJMAX = PDMAX-TOTAL θJA + TA (10) limited frequency response reap little improvement; by using a large input capacitor. The internal input resistor (Ri) and the input capacitor (Ci) produce a high pass filter cutoff frequency that is found using Equation (13). fc = 1 / (2πRiCi) (11) Equation (10) gives the maximum junction temperature TJMAX. If the result violates the LM4859’s 150˚C, reduce the maximum junction temperature by reducing the power supply voltage or increasing the load resistance. Further allowance should be made for increased ambient temperatures. The above examples assume that a device is a surface mount part operating around the maximum power dissipation point. Since internal power dissipation is a function of output power, higher ambient temperatures are allowed as output power or duty cycle decreases. If the result of Equation (7) is greater than that of Equation (8), then decrease the supply voltage, increase the load impedance, or reduce the ambient temperature. If these measures are insufficient, a heat sink can be added to reduce θJA. The heat sink can be created using additional copper area around the package, with connections to the ground pin(s), supply pin and amplifier output pins. External, solder attached SMT heatsinks such as the Thermalloy 7106D can also improve power dissipation. When adding a heat sink, the θJA is the sum of θJC, θCS, and θSA. (θJC is the junction-to-case thermal impedance, θCS is the case-to-sink thermal impedance, and θSA is the sink-toambient thermal impedance.) Refer to the Typical Performance Characteristics curves for power dissipation information at lower output power levels. POWER SUPPLY BYPASSING As with any power amplifier, proper supply bypassing is critical for low noise performance and high power supply rejection. Applications that employ a 5V regulator typically use a 10µF in parallel with a 0.1µF filter capacitors to stabilize the regulator’s output, reduce noise on the supply line, and improve the supply’s transient response. However, their presence does not eliminate the need for a local 1.0µF tantalum bypass capacitance connected between the LM4859’s supply pins and ground. Keep the length of leads and traces that connect capacitors between the LM4859’s power supply pin and ground as short as possible. SELECTING EXTERNAL COMPONENTS Input Capacitor Value Selection Amplifying the lowest audio frequencies requires a high value input coupling capacitor (Ci in Figure 1). In many cases, however, the speakers used in portable systems, whether internal or external, have little ability to reproduce signals below 50Hz. Applications using speakers with this As an example when using a speaker with a low frequency limit of 50Hz and Ri = 20kΩ, Ci, using Equation (13) is 0.19µF. The 0.22µF Ci shown in Figure 4 allows the LM4859 to drive high efficiency, full range speaker whose response extends below 40Hz. Output Capacitor Value Selection Amplifying the lowest audio frequencies also requires the use of a high value output coupling capacitor (CO in Figure 1). A high value output capacitor can be expensive and may compromise space efficiency in portable design. The speaker load (RL) and the output capacitor (CO) form a high pass filter with a low cutoff frequency determined using Equation (14). fc = 1 / (2πRLCO) (12) When using a typical headphone load of RL = 32Ω with a low frequency limit of 50Hz, CO is 99µF. The 100µF CO shown in Figure 4 allows the LM4859 to drive a headphone whose frequency response extends below 50Hz. Bypass Capacitor Value Selection Besides minimizing the input capacitor size, careful consideration should be paid to value of CB, the capacitor connected to the BYPASS pin. Since CB determines how fast the LM4859 settles to quiescent operation, its value is critical when minimizing turn-on pops. The slower the LM4859’s outputs ramp to their quiescent DC voltage (nominally VDD/ 2), the smaller the turn-on pop. Choosing CB equal to 2.2µF along with a small value of Ci (in the range of 0.1µF to 0.39µF), produces a click-less and pop-less shutdown function. As discussed above, choosing Ci no larger than necessary for the desired bandwidth helps minimize clicks and pops. CB’s value should be in the range of 5 times to 10 times the value of Ci. This ensures that output transients are eliminated when the LM4859 transitions in and out of shutdown mode. Connecting a 2.2µF capacitor, CB, between the BYPASS pin and ground improves the internal bias voltage’s stability and improves the amplifier’s PSRR. The PSRR improvements increase as the bypass pin capacitor value increases. However, increasing the value of CB will increase wake-up time. The selection of bypass capacitor value, CB, depends on desired PSRR requirements, click and pop performance, wake-up time, system cost, and size constraints. www.national.com 24 LM4859 Application Information (Continued) 20106102 FIGURE 4. Reference Design Board Schematic 25 www.national.com LM4859 Demonstration Board Layout 20106162 20106159 Recommended SP PCB Layout: Silkscreen Layer Recommended SP PCB Layout: Top Layer 20106161 Recommended SP PCB Layout: Mid Layer 20106160 Recommended SP PCB Layout: Bottom Layer www.national.com 26 LM4859 Revision History Rev 1.1 Date 6/02/05 Description Added Modes 9 and 14 into Mode 4 (Conditions) for the Idd under Elect.Char tables 5V and 3V, then re-released D/S to the WEB (per Alvin Fok). (MC) Edited the micro SMD markings (per Alvin F.), then re-released D/S to the WEB. 1.2 06/06/06 27 www.national.com LM4859 Physical Dimensions inches (millimeters) unless otherwise noted 30 Bump TL Package Order Number LM4859TL NS Package Number TLA30CZA www.national.com 28 LM4859 Stereo 1.2W Audio Sub-system with 3D Enhancement Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 28 – Lead SP Package Order Number LM4859SP NS Package Number SPA28A National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. 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