LM48823TL

LM48823 Mono, Bridge-Tied Load, Ceramic Speaker Driver with I2C Volume Control and Reset LM48823 October 8, 2010 Mono, Bridge-Tied Load, Ceramic Speaker Driver with I2C Volume Control and Reset General Description The LM48823 is a single supply, mono, ceramic speaker driver with an integrated charge-pump, designed for portable devices, such as cell phones, where board space is at a premium. The LM48823 charge pump allows the device to deliver 5.4VRMS from a single 4.2V supply. The LM48823 features high power supply rejection ratio (PSRR), 93dB at 217Hz, allowing the device to operate in noisy environments without additional power supply conditioning. Flexible power supply requirements allow operation from 2.0V to 4.5V. The LM48823 features an active low reset input that reverts the device to its default state. Additionally, the LM48823 features a 32-step I2C volume control. The low power Shutdown mode reduces supply current consumption to 0.01µA. The LM48823’s superior click and pop suppression eliminates audible transients on power-up/down and during shutdown. The LM48823 is available in an ultra-small 16-bump micro SMD package (2mmx2mm). Key Specifications ■ Output Voltage at VDD = 4.2V, RL = 2.2µF + 15Ω THD+N ≤ 1% ■ Quiescent Power Supply Current at 4.2V 3.3mA (typ) 93dB (typ) 0.01μA (typ) 5.4VRMS (typ) ■ PSRR at 217Hz ■ Shutdown current Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Integrated Charge Pump Bridge-tied Load Output High PSRR I2C Volume and Mode Control Reset Input Advanced Click-and-Pop Suppression Low Supply Current Minimum external components Micro-power shutdown Available in space-saving 16-bump µSMD package Applications ■ ■ ■ ■ Cell phones Smart phones Portable media devices Notebook PCs Boomer® is a registered trademark of National Semiconductor Corporation. Tru-GND is a trademark of National Semiconductor Corporation. © 2010 National Semiconductor Corporation 300684 www.national.com LM48823 Typical Application 300684e1 FIGURE 1. Typical Audio Amplifier Application Circuit www.national.com 2 LM48823 Connection Diagrams TL Package 2mm x 2mm x 0.8mm 16–Bump micro SMD Marking 300684g7 Top View XY – Date Code TT – Lot Traceability G – Boomer Family K6 – LM48823TL 300684e0 Top View See NS Package Number TLA1611A Ordering Information Order Number LM48823TL LM48823TLX Package 16–Bump micro SMD 16–Bump micro SMD Package DWG # TLA1611A TLA1611A Transport Media 250 units on tape and reel 3000 units on tape and reel MSL Level 1 1 Green Status NOPB NOPB 3 www.national.com LM48823 TABLE 1. Bump Descriptions Pin Designator A1 A2 A3 A4 B1 B2 B3 B4 C1 C2 C3 C4 D1 D2 D3 D4 Pin Name SVDD SGND BYPASS INA OUTA OUTB RESET INB VSS SCL SDA I2CV DD Pin Function Signal Power Supply Signal Ground Amplifier Reference Bypass Amplifier Inverting input A Amplifier Inverting output A Amplifier Non-Inverting Output B Active Low Reset Input. Connect to VDD for normal operation. Toggle between VDD and GND to reset the device. Amplifier Non-Inverting Input B Charge Pump Output I2C Serial Clock Input I2C Serial Data Input I2C Supply Voltage Charge Pump Flying Capacitor Negative Terminal Power Ground Charge Pump Flying Capacitor Positive Terminal Power Supply C1N PGND C1P PVDD www.national.com 4 LM48823 Absolute Maximum Ratings (Note 1, Note 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (Note 1) Storage Temperature Input Voltage Power Dissipation (Note 3) ESD Rating (Note 4) ESD Rating (Note 5) 5.25V −65°C to +150°C −0.3V to VDD +0.3V Internally Limited 8kV 250V Junction Temperature Thermal Resistance  θJA (typ) - (TLA1611A) 150°C 63.2°C/W Operating Ratings Temperature Range TMIN ≤ TA ≤ TMAX Supply Voltage PVDD and SVDD I2CVDD −40°C ≤ TA ≤ +85°C 2.0V ≤ VDD ≤ 4.5V 1.8V ≤ I2CVDD ≤ 4.5V Audio Amplifier Electrical Characteristics VDD = 4.2V (Note 1, Note 2) The following specifications apply for AV = 6dB, RL = 2.2μF+15Ω, C1 = C2 = 2.2μF, f = 1kHz, unless otherwise specified. Limits apply for TA = 25°C. LM48823 Parameter Quiescent Power Supply Current Shutdown Current Differential Output Offset Voltage Logic High Input Threshold Conditions VIN = 0V, RL = ∞ Shutdown Enabled VIN = 0V RESET RESET Gain Minimum Gain Setting Maximum Gain Setting Maximum Gain Setting –70 24 9 80 7 11 64 96 Typical (Note 6) 3.3 0.01 0.5 Limits (Note 7) 4.3 1 3 1.4 0.4 Units (Limits) mA (max) µA (max) mV (max) V (min) V (max) dB dB kΩ (min) kΩ (max) kΩ (min) kΩ (max) VRMS VRMS % Symbol IDD ISD VOS VIH VIL AV RIN Input Resistance Minimum Gain Setting RL = 2.2μF+15Ω, THD+N = 1% f = 1kHz f = 5kHz VO = 4VRMS VO Output Voltage Total Harmonic Distortion + Noise Power Supply Rejection Ratio 5.4 3.1 0.015 THD+N VRIPPLE = 200mVP-P Sine, Inputs AC GND, CIN = 1μF, input referred PSRR f = 217Hz f = 1kHz POUT = 40mW, RL = 16Ω f = 1kHz AV = 4dB, Input Referred, A-weighted Filter 93 93 119 5.5 200 82 dB (min) dB dB μV μs SNR ∈OS TWU Signal-to-Noise-Ratio Output Noise Wake-Up Time 5 www.national.com LM48823 I2C Interface Characteristics VDD = 3.0V (Note 1, Note 2) The following specifications apply for AV = 6dB, RL = 2.2μF+15Ω, C1 = C2 = 2.2μF, f = 1kHz, unless otherwise specified. Limits apply for TA = 25°C. LM48823 Parameter SCL period SDA Setup Time SDA Stable Time Start Condition Time Stop Condition Time Logic High Input Threshold Logic Low Input Threshold Conditions Typical (Note 6) Limits (Note 7) 2.5 100 0 100 100 0.7 x I2CV DD Symbol t1 t2 t3 t4 t5 VIH VIL Units (Limits) μs (min) ns (min) ns (min) ns (min) ns (min) V (min) V (max) 0.3 x I2CVDD Note 1: :. “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All voltages are measured with respect to the ground pin, unless otherwise specified. Note 2: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed. Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature, TA. The maximum allowable power dissipation is PDMAX = (TJMAX - TA) / θJA or the number given in Absolute Maximum Ratings, whichever is lower. Note 4: Human body model, applicable std. JESD22-A114C. Note 5: Machine model, applicable std. JESD22-A115-A. Note 6: Typical values represent most likely parametric norms at TA = +25ºC, and at the Recommended Operation Conditions at the time of product characterization and are not guaranteed. Note 7: Datasheet min/max specification limits are guaranteed by test or statistical analysis. www.national.com 6 LM48823 Typical Performance Characteristics THD+N vs Frequency VDD = 3.6V THD+N vs Frequency VDD = 4.2V 300684g9 300684h0 THD+N vs Output Voltage AV = 6dB, ZL = 1μF+15Ω, f = 1kHz THD+N vs Output Voltage AV = 6dB, ZL = 2.2μF+15Ω, f = 1kHz 300684f2 300684f3 Output Voltage vs Frequency VDD = 4.2V, ZL = 1μF+15Ω,THD+N = 1% Output Voltage vs Frequency VDD = 4.2V, ZL = 2.2μF+15Ω,THD+N = 1% 300684f6 300684f7 7 www.national.com LM48823 Power Consumption vs Output Voltage VDD = 3.6V, ZL = 1μF+15Ω Power Consumption vs Output Voltage VDD = 3.6V, ZL = 2.2μF+15Ω 300684f8 300684f9 Power Consumption vs Output Voltage VDD = 4.2V, ZL = 1μF+15Ω Power Consumption vs Output Voltage VDD = 4.2V, ZL = 2.2μF+15Ω 300684g0 300684g1 Output Voltage vs Supply Voltage ZL = 1μF+15Ω, THD+N = 1% Output Voltage vs Supply Voltage ZL = 2.2μF+15Ω, THD+N = 1% 300684g2 300684g3 www.national.com 8 LM48823 PSRR vs Frequency VDD = 4.2V, VRIPPLE = 200mVP-P ZL = 1μF+15Ω, Input referred Supply Current vs Supply Voltage No Load 300684g5 300684g4 Shutdown Current vs Supply Voltage No Load 300684g6 9 www.national.com LM48823 Application Information I2C COMPATIBLE INTERFACE The LM48823 is controlled through an I2C compatible serial interface that consists of a serial data line (SDA) and a serial clock (SCL). The clock line is uni-directional. The data line is bi-directional (open drain). The LM48823 and the master can communicate at clock rates up to 400kHz. Figure 2 shows the I2C interface timing diagram. Data on the SDA line must be stable during the HIGH period of SCL. The LM48823 is a transmit/receive slave-only device, reliant upon the master to generate the SCL signal. Each transmission sequence is framed by a START condition and a STOP condition (Figure 3). Each data word, device address and data, transmitted over the bus is 8 bits long and is always followed by an acknowledge pulse (Figure 4). The LM48823 device address is 1110110. I2C BUS FORMAT The I2C bus format is shown in Figure 4. The START signal, the transition of SDA from HIGH to LOW while SCL is HIGH, is generated, alerting all devices on the bus that a device address is being written to the bus. The 7-bit device address is written to the bus, most significant bit (MSB) first, followed by the R/W bit. R/W = 0 indicates the master is writing to the slave device, R/W = 1 indicates the master wants to read data from the slave device. Set R/W = 0; the LM48823 is a WRITE-ONLY device and will not respond to the R/W = 1. The data is latched in on the rising edge of the clock. Each address bit must be stable while SCL is HIGH. After the last address bit is transmitted, the master device releases SDA, during which time, an acknowledge clock pulse is generated by the slave device. If the LM48823 receives the correct address, the device pulls the SDA line low, generating an acknowledge bit (ACK). Once the master device registers the ACK bit, the 8-bit register data word is sent. Each data bit should be stable while SCL is HIGH. After the 8-bit register data word is sent, the LM48823 sends another ACK bit. Following the acknowledgement of the register data word, the master issues a STOP bit, allowing SDA to go high while SCL is high. 30068467 FIGURE 2. I2C Timing Diagram 300684g8 FIGURE 3. Start and Stop Diagram www.national.com 10 LM48823 300684e2 FIGURE 4. Example Write Sequence TABLE 2. Device Address B7 Chip Address 1 B6 1 B5 1 B4 0 B3 1 B2 1 B1 0 B0 R/W 0 TABLE 3. Mode Control Registers Register Name Mode Control GENERAL AMPLIFIER FUNCTION The LM48823 is a ceramic speaker driver that utilizes National’s inverting charge pump technology to deliver over 15VP-P to a 2.2µF ceramic speaker while operating from a single 4.2V supply. The LM48823 features a unique input stage that converts two single-ended audio signals into a mono BTL output. This stereo to mono conversion is useful in applications where a stereo audio source is driving a single ceramic speaker, such as a ringer on a cellular phone. Connect INA and INB as shown in Figure 5 for the stereo-to-mono conversion. When the LM48823 is used with a single-ended mono audio source, connect both INA and INB to the audio source as shown in Figure 6. B7 VOL4 B6 VOL3 B5 VOL2 B4 VOL1 B3 VOL0 B2 0 B1 ENABLE_A B0 ENABLE_B 300684e4 FIGURE 5. Stereo to Mono Conversion Connection Example 300684e3 FIGURE 6. Mono Audio Source Connection Example 11 www.national.com LM48823 VOLUME CONTROL TABLE 4. Volume Control Volume Step 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VOL4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VOL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VOL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 VOL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VOL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Gain (dB) –70 –56 –46 –38 –32 –28 –24 –21 –18 –15 –12 –10 –8 –6 –4 –2 0 2 4 6 8 10 12 14 16 18 19 20 21 22 23 24 www.national.com 12 LM48823 SHUTDOWN FUNCTION The LM48823 features a low-power shutdown mode that disables the device, lowering the quiescent current to 0.01µA. Set bits B1 (ENABLE_A) and B2 (ENABLE_B) to 0 to disable the amplifiers and charge pump. Set both ENABLE_A and ENABLE_B to 1 for normal operation. Shutdown mode does not clear the I2C register. When re-enabled, the device returns to its previous volume setting. To clear the I2C register, either remove power from the device, or toggle RESET (see RESET section). RESET The LM48823 features an active low reset input. Driving RESET low clears the I2C register. Volume control is set to 00000 (-70dB) and both ENABLE_A and ENABLE_B are set to 0, disabling the device. While RESET is low, the LM48823 ignores any I2C data. After the device is reset, and RESET is driven high, the LM48823 remains in shutdown mode with the volume set to -70dB. Re-enable the device by writing to the I2C register. PROPER SELECTION OF EXTERNAL COMPONENTS Power Supply Bypassing/Filtering Proper power supply bypassing is critical for low noise performance and high PSRR. Place the supply bypass capacitors as close to the device as possible. Place a 1µF ceramic capacitor from VDD to GND. Additional bulk capacitance may be added as required. Bypass Capacitor Selection The BYPASS capacitor, CBYPASS, improves PSRR, noise rejection and output offset. For best results, use a capacitor of identical value to the input coupling capacitors Charge Pump Capacitor Selection Use low ESR ceramic capacitors (less than 100mΩ) for optimum performance. Charge Pump Flying Capacitor (C1) The flying capacitor (C1) affects the load regulation and output impedance of the charge pump. A C1 value that is too low results in a loss of current drive, leading to a loss of amplifier headroom. A higher valued C1 improves load regulation and lowers charge pump output impedance to an extent. Above 2.2µF, the RDS(ON) of the charge pump switches and the ESR of C1 and C2 dominate the output impedance. A lower value capacitor can be used in systems with low maximum output power requirements. Charge Pump Hold Capacitor (C2) The value and ESR of the hold capacitor (C2) directly affects the ripple on CPVSS. Increasing the value of C2 reduces output ripple. Decreasing the ESR of C2 reduces both output ripple and charge pump output impedance. A lower value capacitor can be used in systems with low maximum output power requirements. Input Capacitor Selection Input capacitors block the DC component of the audio signal, eliminating any conflict between the DC component of the audio source and the bias voltage of the LM48823. The input capacitors create a high-pass filter with the input resistors RIN. The -3dB point of the high pass filter is found using Equation (1) below. f = 1 / 2πRINCIN (Hz) (1) Where the value of R IN is given in the Electrical Characteristics Table. High pass filtering the audio signal helps protect the speakers. When the LM48823 is using a single-ended source, power supply noise on the ground is seen as an input signal. Setting the high-pass filter point above the power supply noise frequencies, 217Hz in a GSM phone, for example, filters out the noise such that it is not amplified and heard on the output. Capacitors with a tolerance of 10% or better are recommended for impedance matching and improved CMRR and PSRR. 13 www.national.com LM48823 PCB Layout Guidelines Minimize trace impedance of the power, ground and all output traces for optimum performance. Voltage loss due to trace resistance between the LM48823 and the load results in decreased output power and efficiency. Trace resistance between the power supply and ground has the same effect as a poorly regulated supply, increased ripple and reduced peak output power. Use wide traces for power supply inputs and amplifier outputs to minimize losses due to trace resistance, as well as route heat away from the device. Proper grounding improves audio performance, minimizes crosstalk between channels and prevents switching noise from interfering with the audio signal. Use of power and ground planes is recommended. Place all digital components and route digital signal traces as far as possible from analog components and traces. Do not run digital and analog traces in parallel on the same PCB layer. If digital and analog signal lines must cross either over or under each other, ensure that they cross in a perpendicular fashion. LM48823TL Demoboard Bill of Materials Designator C1, C2 C3 – C5 C6 C7, C8 JU1 – JU5 JU6, JU7 J1 LM4823TL Quantity 2 3 1 2 5 3 1 1 Description 2.2µF ±10% 10V X5R Ceramic Capacitor (603) Panasonic ECJ-1VB1A225K Murata GRM033R6OJ104KE19D 1µF ±10% 10V Tantalum Capacitor (402) AVX TACK105M010QTA 4.7µF ±10% 6.3V X5R Ceramic Capacitor (603) Panasonic ECJ-1VB0J475K Murata GRM188R6OJ475KE19D 0.1µF ±10% 6.3V X5R Ceramic Capacitor (201) Panasonic ECJZEB0J104K Murata GRM188R61A225KE34D 2 Pin Header 2 Pin Header 5-Pin I2C Header LM48823TL (16-Bump microSMD) www.national.com 14 Demo Board Schematic LM48823 15 300684e5 www.national.com FIGURE 7. LM48823 Demo Board Schematic LM48823 PC Board Layout 300684f0 300684f1 FIGURE 8: Top Silkscreen Layer FIGURE 9: Top Layer 300684e7 300684e8 FIGURE 10: Layer 2 FIGURE 11: Layer 3 300684e6 300684e9 FIGURE 12: Bottom Layer FIGURE 13: Bottom Silkscreen www.national.com 16 LM48823 Revision History Rev 1.0 1.01 1.02 Date 06/27/08 07/15/08 10/08/10 Initial release. Edited the Ordering Information table. Updated some Limits (under Gain) in the Volume Control table. Description 17 www.national.com LM48823 Physical Dimensions inches (millimeters) unless otherwise noted 16-Bump micro SMD Order Number LM48823TL NS Package Number TLA1611A X1 = 1.970± 0.03 X2 = 1.970 ± 0.03 X3 = 0.6 ± 0.075 www.national.com 18 LM48823 Notes 19 www.national.com LM48823 Mono, Bridge-Tied Load, Ceramic Speaker Driver with I2C Volume Control and Reset Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: www.national.com Products Amplifiers Audio Clock and Timing Data Converters Interface LVDS Power Management Switching Regulators LDOs LED Lighting Voltage References PowerWise® Solutions Temperature Sensors PLL/VCO www.national.com/amplifiers www.national.com/audio www.national.com/timing www.national.com/adc www.national.com/interface www.national.com/lvds www.national.com/power www.national.com/switchers www.national.com/ldo www.national.com/led www.national.com/vref www.national.com/powerwise WEBENCH® Tools App Notes Reference Designs Samples Eval Boards Packaging Green Compliance Distributors Quality and Reliability Feedback/Support Design Made Easy Design Support www.national.com/webench www.national.com/appnotes www.national.com/refdesigns www.national.com/samples www.national.com/evalboards www.national.com/packaging www.national.com/quality/green www.national.com/contacts www.national.com/quality www.national.com/feedback www.national.com/easy www.national.com/solutions www.national.com/milaero www.national.com/solarmagic www.national.com/training Applications & Markets Mil/Aero PowerWise® Design University Serial Digital Interface (SDI) www.national.com/sdi www.national.com/wireless www.national.com/tempsensors SolarMagic™ THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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