LM48824

LM48824 Class G Headphone Amplifier with I2C Volume Control LM48824 August 31, 2009 Class G Headphone Amplifier with I2C Volume Control General Description The LM48824 is a Class G, ground-referenced stereo headphone amplifier designed for portable devices. The LM48824 features National’s ground-referenced architecture, which eliminates the large DC blocking capacitors required by traditional headphone amplifiers, saving board space and minimizing system cost. The LM48824 takes advantage of National’s patent-pending Class G architecture offering power savings compared to a traditional Class AB headphone amplifier. Additionally, output noise is improved by common-mode sensing that corrects for any differences between the amplifier ground and the potential at the headphone return terminal, minimizing noise created by any ground mismatches. A high output impedance mode allows the LM48824's outputs to be driven by an external source without degrading the signal. Other features include flexible power supply requirements, differential inputs for improved noise rejection, a low power (2.5μA) shutdown mode, and a 32-step I2C volume control with mute function. The LM48824's superior click and pop suppression eliminates audible transients on power-up/down and during shutdown. The LM48824 is available in an ultra-small 16-bump, 0.4mm pitch micro SMD package (1.69mm x 1.69mm) Key Specifications ■ Quiescent Power Supply Current at 3.6V ■ Output Power/channel at VDD = 3.6V RL = 16Ω, THD+N ≤ 1% ■ Output Power/channel at VDD = 3.6V RL = 32Ω, THD+N ≤ 1% ■ PSRR at 217Hz ■ Shutdown current 0.9mA (typ) 37mW (typ) 29mW (typ) 100dB (typ) 2.5μA (typ) Features ■ Class G Power Savings ■ Ground Referenced Headphone Outputs – Eliminates ■ ■ ■ ■ ■ ■ ■ Output Coupling Capacitors Common-Mode Sense I2C Volume and Mode Control High Output Impedance in Shutdown Differential Inputs Advanced Click-and-Pop Suppression Low Supply Current Low THD mode option Applications ■ Mobile Phones, PDAs, MP3 Players ■ Portable Electronic Devices, Notebook PCs Simplified Block Diagram 30089221 Boomer® is a registered trademark of National Semiconductor Corporation. © 2009 National Semiconductor Corporation 300892 www.national.com LM48824 Typical Application 30089270 FIGURE 1. Typical Audio Amplifier Application Circuit www.national.com 2 LM48824 Connection Diagrams TM Package 1.7mm x 1.7mm x 0.6mm 16–Bump micro SMD Marking 30089217 Top View XY = Date code TT = Die traceability G = Boomer Family L6 = LM48824TM 30089220 Top View Order Number LM48824TM See NS Package Number TMD16DDA Ordering Information Order Number LM48824TM LM48824TMX Package 16 Bump micro SMD 16 Bump micro SMD Package DWG # TMD16DDA TMD16DDA Transport Media 250 units on tape and reel 3000 units on tape and reel MSL Level 1 1 Green Status NOPB NOPB 3 www.national.com LM48824 Bump Descriptions Bump A1 A2 A3 A4 B1 B2 B3 B4 C1 C2 C3 C4 D1 D2 D3 D4 Name SW VDD OUTL INLGND C1P HPVDD INL+ C1N HPVSS COM INR+ SDA SCL OUTR INRRegulator Switching Node Power Supply Left Channel Output Left Channel Inverting Input Ground Charge Pump Flying Capacitor Positive Terminal Amplifier Power Supply/Regulator Output Left Channel Non-Inverting Input Charge Pump Flying Capacitor Negative Terminal Charge Pump Output Common-mode Sense Input. Connect to headphone jack return Right Channel Non-Inverting Input I2C Serial Data Input I2C Serial Clock Input Right Channel Output Right Channel Inverting Input Pin Descriptions www.national.com 4 LM48824 Absolute Maximum Ratings (Note 1, Note 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (Note 1) Storage Temperature Input Voltage Power Dissipation (Note 3) ESD Rating (Note 4) ESD Rating (Note 5) ESD Rating (Note 6) Junction Temperature 6V −65°C to +150°C -0.3V to VDD + 0.3V Internally Limited 2000V 200V 500V 150°C Soldering Information Vapor Phase (60 sec.) Infrared (15 sec.) Thermal Resistance 215°C 220°C  θJA (TMA16DDA) 60°C/W Soldering Information See AN-1112 “Micro SMD Wafer Level Chip Scale package” Operating Ratings Temperature Range TMIN ≤ TA ≤ TMAX Supply Voltage (VDD) −40°C ≤ TA ≤ +85°C 2.4V ≤ VDD ≤ 5.5V Electrical Characteristics VDD = 3.6V Symbol Parameter (Note 1, Note 2) LM48824 Conditions Typical (Note 7) 0.9 1.55 1.8 2.5 Limit (Note 8) 1.3 Units (Limits) The following specifications apply for AV = 0dB, RL = 32Ω, f = 1kHz, unless otherwise specified. Limits apply to TA = 25°C. VIN = 0V, both channels active IDD Quiescent Power Supply Current RL = ∞ RL = ∞, Low THD mode PO = 100µW, two channels in phase, 3dB Crest Factor, RL = 32Ω + 15Ω PO = 100µW, two channels in phase, 3dB Crest Factor, RL = 32Ω + 15Ω, Low THD mode PO = 500µW, two channels in phase, 3dB Crest Factor RL = 32Ω + 15Ω IDD(OP) Operating Power Supply Current PO = 500µW, two channels in phase, 3dB Crest Factor RL = 32Ω + 15Ω, Low THD mode PO = 1mW, two channels in phase, 3dB Crest Factor, RL = 32Ω + 15Ω PO = 1mW, two channels in phase, 3dB Crest Factor, RL = 32Ω + 15Ω, Low THD mode ISD VOS TWU Shutdown Current Output Offset Voltage Wake Up Time Shutdown Enabled VSCL = VSDA = 1.8V VIN = 0V From Shutdown Minimum Gain Setting AV Gain Maximum Gain Setting AV(MUTE) RIN Mute Attenuation Input Resistance AV = 4dB AV = –59dB mA (max) mA mA (max) 2.2 mA 3.1 3.8 mA (max) 3.4 mA 4.1 4.9 mA (max) 4.4 mA 2.5 0.15 2 –59 4 –110 24 64 3.9 0.65 –58 –60 4.5 3.5 µA (max) mV (max) ms dB (max) dB (min) dB (max) dB (min) dB kΩ (min) kΩ (max) 20 80 5 www.national.com LM48824 LM48824 Symbol Parameter Conditions f = 1kHz, THD+N = 1% Two channels in phase RL= 16Ω f = 1kHz, THD+N = 1% Two channels in phase RL= 32Ω, THD+N = 1%, Two Channels in Phase RL = 16Ω VO Output Swing RL = 32Ω RL = 32Ω + 15Ω RL = 10kΩ f = 1kHz, Single Channel VO = 600mVRMS, RL = 16Ω VO = 600mVRMS, RL = 16Ω, Low THD Mode THD+N Total Harmonic Distortion + Noise VO = 800mVRMS, RL = 32Ω, VO = 800mVRMS, RL = 32Ω, Low THD Mode VO = 900mVRMS, RL = 32Ω+ 15Ω VO = 900mVRMS, RL = 32Ω+ 15Ω, Low THD Mode VRIPPLE = 200mVP-P, Inputs AC GND PSRR Power Supply Rejection Ratio CIN = 1μF, input referred, fRIPPLE = 217Hz fRIPPLE = 1kHz CMRR XTALK Common Mode Rejection Ratio Crosstalk VRIPPLE = 1VP-P, fRIPPLE = 217Hz RL ≥ 16Ω, PO = 5mW, f = 1kHz RL ≥ 10kΩ, VOUT = 1VRMS, f = 1kHz VOUT = 1VRMS, f = 1kHz SNR Signal-to-Noise Ratio VOUT = 1VRMS, f = 1kHz, Low THD Mode AV = 4dB, A-Weighted Filter ∈OS Output Noise AV = 4dB, A-weighted Filter, Low THD Mode Charge pump-only mode enabled ROUT Output Impedance f < 40kHz f = 6MHz f = 36MHz No Sustained Oscillations CL Maximum Capacitive Load with 5Ω series resistance with no series resistance VOUT Maximum Voltage Swing Voltage applied to amplifier outputs in charge pump-only mode 100 100 1.1 1.0 43 30 500 75 100 100 60 80 110 102 105 8 7 12 70 95 98 94 0.05 0.03 0.035 0.02 0.027 0.015 0.04 0.77 0.96 1.05 1.3 1.1 0.7 0.86 Typical (Note 7) 37 Limit (Note 8) 30 Units (Limits) mW (min) PO Output Power 29 23 mW (min) VRMS (min) VRMS (min) VRMS VRMS (min) % % % % %(max) % dB (min) dB dB dB (min) dB (min) dB (min) dB μV(max) μV kΩ (min) Ω (min) Ω (min) nF pF VRMS (min) www.national.com 6 LM48824 I2C Interface Characteristics VDD = 3.6V Symbol t1 t2 t3 t4 t5 VIH VIL Parameter SCL Period SDA Setup Time SDA Stable Time Start Condition Time Stop Condition Time Input High Voltage Input Low Voltage (Note 1, Note 2) LM48824 Units (Limits) μs (min) ns (min) ns (min) ns (min) ns (min) V (min) V (max) The following specifications apply for AV = 0dB, RL = 16Ω, f = 1kHz, unless otherwise specified. Limits apply to TA = 25°C. Conditions Typical (Note 7) Limit (Note 8) 2.5 250 250 250 250 1.2 0.6 Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All voltages are measured with respect to the ground pin, unless otherwise specified Note 2: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed. Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX , θJA, and the ambient temperature, TA. The maximum allowable power dissipation is PDMAX = (TJMAX - TA) / θJA or the number given in Absolute Maximum Ratings, whichever is lower. Note 4: Human body model, applicable std. JESD22-A114C. Note 5: Machine model, applicable std. JESD22-A115-A. Note 6: Charged Device Model, applicable std. JESD22-C101-C. Note 7: Typical values represent most likely parametric norms at TA = +25°C, and at the Recommended Operation Conditions at the time of product characterization and are not guaranteed. Note 8: Datasheet min/max specification limits are guaranteed by test or statistical analysis. 7 www.national.com LM48824 Typical Performance Characteristics THD+N vs Frequency VDD = 3.6V, RL = 16Ω, VO = 600VRMS Low THD Mode THD+N vs Frequency VDD = 3.6V, RL = 16Ω, VO = 600VRMS 300892c0 300892b9 THD+N vs Frequency VDD = 3.6V, RL = 32Ω, VO = 800VRMS Low THD Mode THD+N vs Frequency VDD = 3.6V, RL = 32Ω, VO = 800VRMS 300892c2 300892c1 THD+N vs Frequency VDD = 3.6V, RL = 47Ω, VO = 900VRMS Low THD Mode THD+N vs Frequency VDD = 3.6V, RL = 47Ω, VO = 900VRMS 30089225 30089224 www.national.com 8 LM48824 THD+N vs Output Voltage VDD = 3.6V, RL = 16Ω, f = 1kHz Low THD Mode THD+N vs Output Voltage VDD = 3.6V, RL = 16Ω, f = 1kHz 300892c6 300892c5 THD+N vs Output Voltage VDD = 3.6V, RL = 32Ω, f = 1kHz Low THD Mode THD+N vs Output Voltage VDD = 3.6V, RL = 32Ω, f = 1kHz 300892c8 300892c7 THD+N vs Output Voltage VDD = 3.6V, RL = 47Ω, f = 1kHz Low THD Mode THD+N vs Output Voltage VDD = 3.6V, RL = 47Ω, f = 1kHz 300892d0 300892c9 9 www.national.com LM48824 THD+N vs Output Power VDD = 3.6V, RL = 16Ω, f = 1kHz Low THD Mode THD+N vs Output Power VDD = 3.6V, RL = 16Ω, f = 1kHz 300892d2 300892d1 THD+N vs Output Power VDD = 3.6V, RL = 32Ω, f = 1kHz Low THD Mode THD+N vs Output Power VDD = 3.6V, RL = 32Ω, f = 1kHz 300892d4 300892d3 Power Dissipation vs Output Power VDD = 3.6V, RL = 16Ω, f = 1kHz Power Dissipation vs Output Power VDD = 3.6V, RL = 32Ω, f = 1kHz 300892d8 300892d9 www.national.com 10 LM48824 Power Dissipation vs Output Power VDD = 3.6V, RL = 47Ω, f = 1kHz Output Power vs Supply Voltage RL = 16Ω, f = 1kHz 300892e0 300892e2 Output Power vs Supply Voltage RL = 32Ω, f = 1kHz Output Power vs Supply Voltage RL = 47Ω, f = 1kHz 300892e3 300892e4 Supply Current vs Supply Voltage No Load CMRR vs Frequency VDD = 3.6V, VRIPPLE = 1VP-P RL = 32Ω 300892e6 300892h7 11 www.national.com LM48824 PSRR vs Frequency VDD = 3.6V, VRIPPLE = 200VP-P RL = 32Ω Crosstalk vs Frequency VDD = 3.6V, PO = 5mW RL = 32Ω 300892h8 300892h9 www.national.com 12 LM48824 Application Information I2C COMPATIBLE INTERFACE The LM48824 is controlled through an I2C compatible serial interface that consists of a serial data line (SDA) and a serial clock (SCL). The clock line is uni-directional. The data line is bi-directional (open drain). The LM48824 and the master can communicate at clock rates up to 400kHz. Figure 2 shows the I2C interface timing diagram. Data on the SDA line must be stable during the HIGH period of SCL. The LM48824 is a transmit/receive slave-only device, reliant upon the master to generate the SCL signal. Each transmission sequence is framed by a START condition and a STOP condition (Figure 3). Each data word, device address and data, transmitted over the bus is 8 bits long and is always followed by an acknowledge pulse (Figure 4). The LM48824 device address is 1100000. I2C BUS FORMAT The I2C bus format is shown in Figure 4. The START signal, the transition of SDA from HIGH to LOW while SCL is HIGH, is generated, alerting all devices on the bus that a device address is being written to the bus. The 7-bit device address is written to the bus, most significant bit (MSB) first, followed by the R/W bit (R/W = 0 indicates the master is writing to the LM48824, R/W = 1 indicates the master wants to read data from the LM48824). Data is latched into the device on the rising clock edge. Each address bit must be stable while SCL is HIGH. After the last address bit is transmitted, the master device releases SDA, during which time, an acknowledge clock pulse is generated by the slave device. If the LM48824 receives the correct address, the device pulls the SDA line low, generating an acknowledge bit (ACK). Once the master device registers the ACK bit, the 8-bit register address word is sent. Each data bit should be stable while SCL is HIGH. After the 8-bit register address is sent, the LM48824 sends another ACK bit. Following the acknowledgment of the register address, the 8-bit register data word is sent. Each data bit should be stable while SCL is HIGH. After the 8-bit register data is sent, the LM48824 sends another ACK bit. Following the acknowledgement of the register data word, the master issues a STOP bit, allowing SDA to go high while SCL is high. 30089201 FIGURE 2. I2C Timing Diagram 30089202 FIGURE 3. Start and Stop Diagram 13 www.national.com LM48824 30089214 FIGURE 4. I2C Write Cycle 30089269 FIGURE 5. Example I2C Read Cycle TABLE 1. Device Address B7 Device Address 1 B6 1 B5 0 B4 0 B3 0 B2 0 B1 0 B0 (R/W) X www.national.com 14 LM48824 TABLE 2. I2C Control Registers (Note 9) Register Address 0x01h 0x02h 0x03h Register Name MODE CONTROL VOLUME CONTROL OUTPUT CONTROL DEVICE INFORMATI ON (ReadOnly) B7 HPL_EN MUTE_L* 0 B6 HPR_EN MUTE_R* 0 B5 0 VOL4 0 B4 0 VOL3 0 B3 0 VOL2 LOW_THD B2 0 VOL1 0 B1 THRM VOL0 HiZ_L B0 SHDN 0 HiZ_R 0x04h 0 1 0 0 0 0 0 0 Note 9: * All registers default to 0 on initial power-up except SHDN, MUTE_L, MUTE_R bits default to 1 at power-up. TABLE 3. Mode Control Register Bit B0 B1 B6 B7 Name SHDN THRM (Read Only) HPR_EN HPL_EN Value 0 1 0 1 0 1 0 1 Device enabled Device disabled Thermal-protection inactive Thermal-protection active Right channel amplifier disabled Right channel amplifier enabled Left channel amplifier disabled Left channel amplifier enabled Description TABLE 4. Volume Control Register Bit B5:B1 B6 B7 Name VOL4:VOL0 MUTE_R MUTE_L 0 1 0 1 Value Description These bits set the volume level. See Table 5 (Volume Control). Right Channel Mute Disabled Right Channel Mute Enabled Left Channel Mute Disabled Left Channel Mute Enabled 15 www.national.com LM48824 TABLE 5. Volume Control Volume Step 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 VOL4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VOL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VOL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 VOL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VOL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 HP Gain (dB) -59 -55 -51 -47 -43 -39 -35 -31 -27 -25 -23 -21 -19 -17 -15 -13 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 TABLE 6. Output Control Register Bit B0 B1 B3 Name HiZ_R HiZ_L LOW_THD Value 0 1 0 1 0 1 Description Right channel high impedance mode disabled Right channel high impedance mode enabled Left channel high impedance mode disabled Left channel high impedance mode enabled LOW_THD mode disabled LOW_THD mode enabled, improves overall THD www.national.com 16 LM48824 GENERAL DEVICE FUNCTION The LM48824 integrates a high efficiency step down (buck) DC-DC switching regulator with a ground reference headphone amplifier. The switching regulator delivers a constant voltage from an input voltage ranging from 2.4V to 5.5V. The switching regulator uses a voltage-mode architecture with synchronous rectification, improving efficiency and reducing component count. The LM48824 headphone amplifier features National’s ground referenced architecture that eliminates the large DCblocking capacitors required at the outputs of traditional single-ended headphone amplifiers. A low-noise inverting charge pump creates a negative supply (HPVSS) from the positive supply voltage (VDD). The headphone amplifiers operate from these bipolar supplies, with the amplifier outputs biased about GND. Because there is no DC component on the output signals, the large DC-blocking, AC coupling capacitors (typically 220µF) are not necessary, conserving board space, reducing system cost, and improving frequency response. CLASS G OPERATION Class G is a modification of some other class of amplifier (normally Class B or Class AB) to increase efficiency and reduce power dissipation. Class G works off the fact that musical and voice signals have a high peak to mean ratio with most of the signal content at low levels. To decrease power dissipation, Class G has multiple voltage supplies. The LM48824 has two discrete voltage supplies at the output of the buck, 1.1V and 1.8V. When the output reached the threshold to switch to the higher voltage rails, the rails will switch from 1.1V to 1.8V. When the output falls below the required voltage rails for a set period of time, it will switch back to the lower rail until the next time the threshold is reached. Power dissipation is greatly reduced for typical musical or voice sources. The drawing below shows how a musical output may look. The green lines are the supply voltages at the output of the buck converter. 30089248 FIGURE 6. Class G Operation 17 www.national.com LM48824 DIFFERENTIAL AMPLIFIER EXPLANATION The LM48824 features a differential input stage, which offers improved noise rejection compared to a single-ended input amplifier. Because a differential input amplifier amplifies the difference between the two input signals, any component common to both signals is cancelled. SYNCHRONOUS RECTIFIER The buck converter in the LM48824 uses an internal NFET synchronous rectifier to reduce rectifier forward voltage drop and associated power loss. Synchronous rectification provides a significant improvement in efficiency whenever the output voltage is relative low compared to the voltage drop across an ordinary rectifier diode and eliminating the need for the diode. CURRENT LIMITING A current limit of the buck converter in the LM48824 allows the device to protect itself and external components during overload conditions. PFM OPERATION During PFM(Pulse-Frequency Modulation) operation, if the output voltage of the buck converter is below the ‘high’ PFM comparator threshold, the PMOS power switch is turned on. It remains on until the output voltage reaches the ‘high’ PFM threshold or the peak current exceeds the IPFM level set for PFM mode. The typical peak current in PFM mode is IPFM = 112mA + VDD/27Ω. Once the PMOS power switch is turned off, the NMOS power switch is turned on until the inductor current ramps to zero. When the NMOS zero-current condition is detected, the NMOS power switch is turned off. If the output voltage is below the ‘high’ PFM comparator threshold, the PMOS switch is again turned on and the cycle is repeated until the output reaches the desired level. Once the output reaches the ‘high’ PFM threshold, the NMOS switch is turned on briefly to ramp the inductor current to zero and then both output switches are turned off and the part enters an extremely low power mode. 30089205 FIGURE 7. PFM Operation SOFT START The buck converter has a soft-start circuit that limits in-rush current during start-up. During start-up the switch current limit is increased in steps. Soft start is activated only if global SHDN goes from 1 to 0 after VDD reaches 2.7V. Soft start is implemented by increasing switch current limit in steps of 70mA, 140mA, 280mA, and 750mA (typical switch current limit). The start-up time thereby depends on the output capacitor and load current of the buck converter. Typical start-up times with a 10uF output capacitor and 150mA load is 280us and with 5mA load is 240us. COMMON-MODE SENSE The LM48824 features a ground (common mode) sensing feature. In noisy applications, or where the headphone jack is used as a line out to other devices, noise pick up and ground imbalance can degrade audio quality. The LM48824 COM input senses and corrects any noise at the headphone return, or any ground imbalance between the headphone return and device ground, improving audio reproduction. Connect COM directly to the headphone return terminal of the headphone jack (Figure 8). No additional external components are required. Connect COM to GND if the common-mode sense feature is not in use. www.national.com 18 LM48824 30089206 FIGURE 8. COM Connection SHUTDOWN FUNCTION The LM48824 features individual amplifier shutdown control and a global device shutdown control. Bit B0 (SHDN) of the MODE CONTROL register controls the global shutdown for the entire device. Set SHDN = 1 to put the device into current-saving shutdown mode, and set SHDN = 0 for normal operation. SHDN defaults to 1 at power-up. Bit B7 (HPL_EN) and Bit B6 (HPR_EN) of the MODE CONTROL register (register address 0x01h) controls the left and right headphone amplifier shutdown respectively. Set HPL_EN = 0 to set the left channel headphone amplifier to shutdown and set HPL_EN = 1 to enable left channel operation. Set HPR_EN = 0 to set the right channel headphone amplifier to shutdown and set HPR_EN = 1 to enable right channel operation. The left and right channel amplifier shutdowns operate individually. The LM48824 has a shutdown time of 3ms to complete the internal shutdown sequence. After SHDN is set to 1, any new I2C commands should only be sent after the 3ms shutdown time to ensure proper operation of the device. MUTE FUNCTION The LM48824 features independent left and right channel mute functions. Bit B7 (MUTE_L) and Bit B6 (MUTE_R) of the VOLUME CONTROL register (register address 0x02h) controls the mute function of the left and right channels respectively. Set MUTE_L = 1 to mute the left channel and set the MUTE_R = 1 to mute the right channel. Set MUTE_L = 0 and MUTE_R = 0 to disable mute on the respective channels. MUTE_L and MUTE_R defaults to 1 at power-up. LOW THD+N MODE The LM48824 features a Low THD mode that reduces THD +N to improve audio qaulity. Set B3 (Low_THD) of the OUTPUT CONTROL register (register address 0x03h) to 1 to enable the Low THD mode. There is a quiescent and operating current increase in Low THD mode. See Electrical Characteristics table and Typical Performance Characteristics for reference. PROPER SELECTION OF EXTERNAL COMPONENTS INDUCTOR SELECTION There are two main considerations when choosing an inductor; the inductor saturation current and the inductor current ripple should be small enough to achieve the desired output voltage ripple. Different saturation current rating specifications are followed by different manufacturers so attention must be given to details. Saturation current ratings are typically specified at 25°C, ratings at the maximum ambient temperature of application should be requested from the manufacturer. Shielded capacitors are preferred since these capacitors radiate less noise. Inductors with low DCR should also be considered to minimize the efficiency. Inductor value involves trade-offs in performance. Larger inductors reduce inductor triple current, which typically means less output voltage ripple (for a given size of output capacitor). REGULATOR INPUT CAPACITOR SELECTION (C3) A ceramic input capacitor of 1µF, 6.3V is sufficient for most applications. Place the input capacitor as close as possible to the VDD pin of the device. A larger value may be used for improved input voltage filtering. Use X7R or X5R types; do not use Y5V. DC bias characteristics of ceramic capacitors must be considered when selecting case sizes like 0805 and 0603. REGULATOR OUTPUT CAPACITOR SELECTION (C4) A low ESR ceramic output capacitor of 10µF, 6.3V is sufficient for most applications. Use X7R or X5R types; do not use Y5V. DC bias characteristics of ceramic capacitors must be considered when selecting case sizes like 0805 and 0603. DC bias characteristics vary from manufacturer to manufacturer and dc bias curves should be requested from them as part of the capacitor selection process. CHARGE PUMP CAPACITOR SELECTION Use low ESR ceramic capacitors (less than 100mΩ) for optimum performance. CHARGE PUMP FLYING CAPACITOR (C1) The flying capacitor (C1) affects the load regulation and output impedance of the charge pump. A C1 value that is too low results in a loss of current drive, leading to a loss of amplifier headroom. A higher valued C1 improves load regulation and lowers charge pump output impedance to an extent. Above 2.2µF, the RDS(ON) of the charge pump switches and the ESR of C1 and C2 dominate the output impedance. A lower value capacitor can be used in systems with low maximum output power requirements. 19 www.national.com LM48824 CHARGE PUMP HOLD CAPACITOR (C2) The value and ESR of the hold capacitor (C2) directly affects the ripple on CPVSS. Increasing the value of C2 reduces output ripple. Decreasing the ESR of C2 reduces both output ripple and charge pump output impedance. A lower value capacitor can be used in systems with low maximum output power requirements. Amplifier Input Capacitor Selection Input capacitors may be required for some applications, or when the audio source is single-ended. Input capacitors block the DC component of the audio signal, eliminating any conflict between the DC component of the audio source and the bias voltage of the LM48824. The input capacitors create a highpass filter with the input resistors RIN. The -3dB point of the high-pass filter is found using Equation (1) below. f = 1 / 2πRINCIN (Hz) (1) Where the value of R IN is given in the Electrical Characteristics Table. High-pass filtering the audio signal can be beneficial for some applications. When the LM48824 is using a single-ended source, power supply noise on the ground is seen as an input signal. Setting the high-pass filter point above the power supply noise frequencies, 217Hz in a GSM phone, for example, filters out the noise such that it is not amplified and heard on the output. Capacitors with a tolerance of 10% or better are recommended for impedance matching and improved CMRR and PSRR. SINGLE-ENDED AUDIO AMPLIFIER CONFIGURATION The LM48824 is compatible with single-ended sources. Figure 9 shows the typical single-ended applications circuit. Input coupling capacitors are required for single-ended configuration. 30089250 FIGURE 9. Single-Ended Input Configuration www.national.com 20 LM48824 PCB LAYOUT CONFIGURATION TABLE 7. LM48824TM Demoboard Bill of Materials Designator C1 C2 C3, C8, C9 C4 – C7 R1, R2 L1 J1 J2 JU1 JU2 LM4822TM Quantity 1 1 3 4 2 1 1 1 1 1 1 Description 10µF ±10% 16V 500Ω Tantalum Capacitor (B Case) AVX TPSB106K016R0500 1μF ±10% 16V X5R Ceramic Capacitor (603) Panasonic ECJ-1VB1C105K 2.2μF ±10% 10V X5R Ceramic Capacitor (603) Panasonic ECJ-1VB1A225K 1μF ±10% 16V X7R Ceramic Capacitor (1206) Panasonic ECJ-3YB1C105K 5kΩ ±5% 1/10W Thick Film Resistor (603) Vishay CRCW06035R1KJNEA 3.3μH ± 30% 1.2A Inductor Murata LQM2MPN3R3NG0L Stereo Headphone Jack 16-Pin Boardmount Socket 3M 8516-4500JL 3 Pin Header 2 Pin Header LM48824TM (16-Bump microSMD) 21 www.national.com LM48824 www.national.com 300892h6 Demoboard Schematic 22 FIGURE 10. LM48824 Demoboard Schematic LM48824 300892h5 FIGURE 11. Top Silkscreen 300892h1 FIGURE 12. Top Layer 23 www.national.com LM48824 300892h2 FIGURE 13. Layer 2 (GND) 300892h3 FIGURE 14. Layer 3 (VDD) www.national.com 24 LM48824 300892h4 FIGURE 15. Bottom Layer 300892h0 FIGURE 16. Bottom Silkscreen 25 www.national.com LM48824 Revision History Rev 1.0 1.01 Date 08/06/09 08/31/09 Text edits. Description Initial released of the full datasheet. www.national.com 26 LM48824 Physical Dimensions inches (millimeters) unless otherwise noted 16 – Bump micro SMD Order Number LM48824TM NS Package Number TMD16DDA X1 = 1690μm X2 = 1690μm X3 = 600μm 27 www.national.com LM48824 Class G Headphone Amplifier with I2C Volume Control Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Amplifiers Audio Clock and Timing Data Converters Interface LVDS Power Management Switching Regulators LDOs LED Lighting Voltage Reference PowerWise® Solutions Temperature Sensors Wireless (PLL/VCO) www.national.com/amplifiers www.national.com/audio www.national.com/timing www.national.com/adc www.national.com/interface www.national.com/lvds www.national.com/power www.national.com/switchers www.national.com/ldo www.national.com/led www.national.com/vref www.national.com/powerwise WEBENCH® Tools App Notes Reference Designs Samples Eval Boards Packaging Green Compliance Distributors Quality and Reliability Feedback/Support Design Made Easy Solutions Mil/Aero PowerWise® Design University Design Support www.national.com/webench www.national.com/appnotes www.national.com/refdesigns www.national.com/samples www.national.com/evalboards www.national.com/packaging www.national.com/quality/green www.national.com/contacts www.national.com/quality www.national.com/feedback www.national.com/easy www.national.com/solutions www.national.com/milaero www.national.com/solarmagic www.national.com/training Serial Digital Interface (SDI) www.national.com/sdi www.national.com/wireless www.national.com/tempsensors SolarMagic™ THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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