LM49100

LM49100 Mono Class AB Audio Sub-System with a True-Ground Headphone Amplifier September 2007 LM49100 Mono Class AB Audio Sub-System with a True-Ground Headphone Amplifier General Description The LM49100 is a fully integrated audio subsystem capable of delivering 1.275W of continuous average power into a mono 8Ω bridged-tied load (BTL) with 1% THD+N and with a 5V power supply. The LM49100 also has a stereo true-ground headphone amplifier capable of 50mW per channel of continuous average power into a 32Ω single-ended (SE) loads with 1% THD+N. The LM49100 has three input channels. One pair of SE inputs can be used with a stereo signal. The other input channel is fully differential and may be used with a mono input signal. The LM49100 features a 32-step digital volume control and ten distinct output modes. The mixer, volume control, and device mode select are controlled through an I2C compatible interface. Thermal overload protection prevent the device from being damaged during fault conditions. Superior click and pop suppression eliminates audible transients on power-up/down and during shutdown. Key Specifications ■ Power Output at VDD = 5V:   Loudspeaker (LS): RL = 8Ω, THD+N ≤ 1%   Headphone (VDDHP = 2.8V): RL = 32Ω, THD+N ≤ 1% ■ Shutdown current 1.275W 50mW 0.01µA Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Mono and stereo inputs Thermal Overload Protection True-ground Headphone Drivers I2C Control Interface Input mute attenuation 2nd Stage headphone attenuator 32-step digital volume control 10 Operating Modes Minimum external components Click and Pop suppression Micro-power shutdown Available in space-saving 3mm x 3mm 25 bump GR package ■ RF Suppression Applications ■ ■ ■ ■ Mobile Phones PDAs Laptops Portable Electronics Boomer® is a registered trademark of National Semiconductor Corporation. © 2007 National Semiconductor Corporation 300015 www.national.com LM49100 Typical Application 300015o4 FIGURE 1. Typical Audio Amplifier Application Circuit www.national.com 2 LM49100 Connection Diagrams GR Package 3mm × 3mm × 1mm 300015o3 Top View Order Number LM49100GR See NS Package Number GRA25A GR Package Marking 300015f6 Top View XY — 2 Digit datecode TT — Lot traceability G — Boomer Family C9 — LM49100GR 3 www.national.com LM49100 Bump Descriptions Bump A1 A2 A3 A4 A5 B1 B2 B3 B4 B5 C1 C2 C3 C4 C5 D1 D2 D3 D4 D5 E1 E2 E3 E4 E5 Name VDDCP GNDCP MIN+ BYPASS RIN C1N C1P MINLIN LS− VSSCP VSSHP GND ADDR VDDLS HPL VDDHP VDD I2C SDA LS+ HPR VDDLS AGND GND SCL Description Positive Charge Pump Power Supply Charge Pump Ground Positive Mono Input Half-Supply Bypass Right Input Negative Terminal – Charge Pump Flying Capacitor Positive Terminal – Charge Pump Flying Capacitor Negative Mono Input Left Input Negative Loudspeaker Output Negative Charge Pump Power Supply Negative Headphone Power Supply Ground I2C Address Identification Loudspeaker Power Supply Left Headphone Output Positive Headphone Power Supply I2C Power Supply I2C Data Loudspeaker Output Positive Right Headphone Output Loudspeaker Power Supply Headphone Signal Ground (See Application Information section). Ground I2C Clock www.national.com 4 LM49100 Absolute Maximum Ratings (Notes 1, 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (Loudspeaker) Supply Voltage (Headphone) Storage Temperature Input Voltage Power Dissipation (Note 3) ESD Susceptibility (Note 4) ESD Susceptibility (Note 5) Junction Temperature 6V 3V −65°C to +150°C −0.3V to VDD + 0.3V Internally Limited 2000V 200V 150°C Thermal Resistance  θJA (GR) 50.2°C/W Operating Ratings Temperature Range TMIN ≤ TA ≤ TMAX Supply Voltage VDDLS Supply Voltage VDDHP I2C Voltage (VDDI2C ) 2.7V ≤ VDDLS ≤ 5.5V −40°C ≤ TA ≤ +85°C 2.4 V ≤ VDDHP ≤ 2.9V 1.7V ≤ VDDI2C ≤ 5.5V VDDHP ≤ VDDLS VDDI2C ≤ VDDLS The following specifications apply for all programmable gain set to 0 dB, CB = 4.7μF, RL (SP) = 8Ω, RL(HP) = 32Ω, f = 1 kHz unless otherwise specified. Limits apply for TA = 25°C. LM49100 Symbol Parameter Conditions Modes 1, 3, 5 VIN = 0V, No Load VDDLS = 3.0V Modes 2, 4, 6 VDDHP = 2.8V VIN = 0V, No Load Modes 7, 10, 14 VIN = 0V, No Load Modes 1, 3, 5 VIN = 0V, No Load IDD Supply Current VDDLS = 3.6V Modes 2, 4, 6 VDDHP = 2.8V VIN = 0V, No Load Modes 7, 10, 14 VIN = 0V, No Load Modes 1, 3, 5 VIN = 0V, No Load VDDLS = 5.0V Modes 2, 4, 6 VDDHP = 2.8V VIN = 0V, No Load Modes 7, 10, 14 VIN = 0V, No Load ISD Shutdown Supply Current Mode 0 VIN = 0V, Mode 7, Mono VIN = 0V, Mode 7, Headphone Gain = –24dB VOS Output Offset Voltage VIN = 0V, Mode 7, Headphone Gain = –18dB VIN = 0V, Mode 7, Headphone Gain = –12dB VIN = 0V, Mode 7, Headphone Gain = 0dB LS f = 1kHz RL = 8Ω 1% 10% RL = 16Ω 1% 10% RL = 32Ω 1% 10% Typical (Note 6) 2.9 3.4 4.8 2.9 3.5 4.8 3.1 3.6 5.0 0.01 6.0 2.2 2.4 3.2 7 425 525 49 69 35 44 15 1 25 5.5 4.3 5.4 7.4 Limit (Note 7) Units (Limits) mA mA mA mA (max) mA (max) mA (max) mA mA mA µA (max) mV (max) mV mV (max) mV mV (max) mW mW mW mW mW mW Electrical Characteristics VDDLS = 3.6V, VDDHP = 2.8V (Notes 1, 2) POUT Output Power VDDLS = 3.0V HP f = 1kHz 5 www.national.com LM49100 LM49100 Symbol Parameter Conditions RL = 8Ω 1% 10% RL = 16Ω 1% 10% RL = 32Ω 1% 10% RL = 8Ω 1% 10% RL = 16Ω 1% 10% RL = 32Ω 1% 10% Loudspeaker; Mode 1, RL = Total Harmonic Distortion + Noise 8Ω, POUT = 215mW Headphone; Mode 4, RL = 32Ω, POUT = 25mW Loudspeaker; Mode 1, RL = Total Harmonic Distortion + Noise 8Ω, POUT = 320mW Headphone; Mode 4, RL = 32Ω, POUT = 25mW Loudspeaker; Mode 1, RL = Total Harmonic Distortion + Noise 8Ω, POUT = 630mW Headphone; Mode 4, RL = 32Ω, POUT = 25mW Typical (Note 6) 640 790 49 72 50 62 1275 1575 49 72 53 62 46 Limit (Note 7) 600 Units (Limits) LS f = 1kHz mW (min) mW mW mW mW (min) mW mW mW mW mW mW mW POUT Output Power VDDLS = 3.6V HP f = 1kHz LS f = 1kHz POUT Output Power VDDLS = 5.0V HP f = 1kHz 0.05 % THD+N VDDLS = 3.0V f = 1kHz 0.02 % 0.05 % THD+N VDDLS = 3.6V f = 1kHz 0.02 % 0.035 % THD+N VDDLS = 5.0V f = 1kHz 0.02 % www.national.com 6 LM49100 LM49100 Symbol Parameter Conditions Typical (Note 6) Mode 2,10 Mode 4, 7 eN Noise A-weighted, 0 dB, inputs terminated to GND, output referred Mode 6, 14 Mode 1 Mode 3, 7, 10, 14 Mode 5 TON TOFF Turn-on Time Turn-off Time Maximum gain setting ZIN Input Impedance Maximum attenuation setting Stereo (Left and Right Channels) AV Volume Control Mono Input referred maximum attenuation Input referred maximum gain Input referred maximum attenuation Input referred maximum gain Headphone Mode 2, f = 217 Hz, VCM = 1 VPP,RL = 32Ω Loudspeaker Mode 1, f = 217 Hz, VCM = 1 VPP, RL = 8Ω LS, Mode 1 LS, Mode 3, 7, 10, 14 LS, Mode 5 PSRR Power Supply Rejection Ratio LS, Mode 7, 10, 14 HP, Mode 2, 10 HP, Mode 4, 7 HP, Mode 6, 14 HP, Mode 2, 10 HP, Mode 4, 7 HP, Mode 6, 14 110 −54 18 −60 12 64 58 12 13 16 Loudspeaker 14 23 27 26 1 12.5 10 15 90 130 –52 –56 17.5 18.5 –58 –62 11.5 12.5 Limit (Note 7) Units (Limits) Headphone µV µV µV µV µV µV ms ms kΩ (min) kΩ (max) kΩ (min) kΩ (max) dB (min) dB (max) dB (min) dB (max) dB (min) dB (max) dB (min) dB (max) dB dB CMRR Common Mode Rejection Ratio VRIPPLE = 200mVpp on VDD LS, output referred, inputs terminated to GND, f = 217Hz PSRR Power Supply Rejection Ratio 90 78 77 83 90 88 87 83 83 80 dB dB dB dB dB dB dB dB dB dB VRIPPLE = 200mVpp on VDD HP, output referred, inputs terminated to GND, f = 217Hz VRIPPLE = 200mVpp on VDD LS, output referred, inputs terminated to GND, f = 217Hz PSRR Power Supply Rejection Ratio VRIPPLE = 200mVpp on VDD HP, output referred, inputs terminated to GND, f = 217Hz PSRR Power Supply Rejection Ratio 7 www.national.com LM49100 I2C Symbol (Notes 2, 7) Parameter Conditions (Note 8) LM49100 Typical (Note 6) Limits (Note 7) 2.5 100 0 100 100 100 0.7xVDD I2C 0.3xVDDI2C Units (Limits) µs (min) ns (min) ns (min) ns (min) ns (min) ns (min) V (min) V (max) The following specifications apply for VDD = 5.0V and 3.3V, TA = 25°C, 2.2V ≤ VDDI2C ≤ 5.5V, unless otherwise specified. t1 t2 t3 t4 t5 t6 VIH VIL I2C Clock Period I2C Data Setup Time I2C Data Stable Time Start Condition Time Stop Condition Time I2C Data Hold Time I2C Input Voltage High I2C Input Voltage Low (Notes 2, 7) Parameter Conditions (Note 8) I2C Symbol The following specifications apply for VDD = 5.0V and 3.3V, TA = 25°C, 1.7V ≤ VDDI2C ≤ 2.2V, unless otherwise specified. LM49100 Typical (Note 6) t1 t2 t3 t4 t5 t6 VIH VIL I2C Clock Period I2C Data Setup Time I2C Data Stable Time Start Condition Time Stop Condition Time I2C Data Hold Time I2C Input Voltage High I2C Input Voltage Low Limits (Note 7) 2.5 250 0 250 250 250 0.7xVDDI2C 0.3xVDDI2C Units (Limits) µs (min) ns (min) ns (min) ns (min) ns (min) ns (min) V (min) V (max) Note 1: All voltages are measured with respect to the GND pin unless other wise specified. Note 2: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional but do not guarantee specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which guarantee specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not guaranteed for parameters where no limit is given, however, the typical value is a good indication of device performance. Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature, TA. The maximum allowable power dissipation is PDMAX = (TJMAX – TA)/ θJA or the number given in Absolute Maximum Ratings, whichever is lower. For the LM49100, see power derating currents for more information. Note 4: Human body model, 100 pF discharged through a 1.5kΩ resistor. Note 5: Machine Model, 220pF - 240pF discharged through all pins. Note 6: Typicals are measured at 25°C and represent the parametric norm. Note 7: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). Note 8: Please refer to Figure 3 (I2C Timing Diagram). www.national.com 8 LM49100 Typical Performance Characteristics THD+N vs Frequency VDD = 3.6V, RL = 8Ω, PO = 320mW BW = 22kHz, LS, Mode 1 THD+N vs Frequency VDD = 3.6V, RL = 32Ω, PO = 25mW HP, BW = 22kHz, Mode 4,7 300015o6 300015q1 THD+N vs Frequency VDD = 3V, RL = 8Ω, PO = 215mW BW = 22kHz, LS, Mode 1 THD+N vs Frequency VDD = 3V, RL = 32Ω, PO = 25mW BW = 22kHz, HP, Mode 4, 7 300015o8 300015q2 9 www.national.com LM49100 THD+N vs Frequency VDD = 5V, RL = 8Ω, PO = 630mW BW = 22kHz, Loudspeaker, Mode 1 THD+N vs Frequency VDD = 5V, RL = 32Ω, PO = 25mW BW = 22kHz, Headphone, Mode 4,7 300015p1 300015p2 THD+N vs Output Power RL = 32Ω, f = 1kHz BW = 22kHz, HP, Mode 4 THD+N vs Output Power RL = 8Ω, f = 1kHz BW = 22kHz, LS, Mode 1 300015q0 300015e7 Output Power vs Supply Voltage VDDHP = 2.8V, RL = 8Ω, f = 1kHz, LS Output Power vs Supply Voltage VDDHP = 2.8V, RL = 32Ω, f = 1kHz, HP 300015d8 300015p8 www.national.com 10 LM49100 Power Dissipation vs Output Power VDD = 3.6V, RL = 8Ω, f = 1kHz, Mode 1 Power Dissipation vs Output Power VDD = 3V, RL = 8Ω, f = 1kHz, Mode 1 300015p5 300015p6 Power Dissipation vs Output Power VDD = 5V, RL = 8Ω, f = 1kHz, Mode 1 Supply Current vs VDDLS VDDHP = 2.8V, Mode 1, 3, 5, No Load 30001564 300015p7 Supply Current vs VDDLS VDDHP = 2.8V, Mode 2, 4, 6, No Load Supply Current vs VDDLS VDDHP = 2.8V, Mode 7,10, 14, No Load 30001565 30001570 11 www.national.com LM49100 PSRR vs Frequency RL = 32Ω, VRIPPLE = 200mVPP on VDDHP VDDHP = 2.8V, CB = 4.7μF, Mode 2, 10, HP PSRR vs Frequency RL = 32Ω, VRIPPLE = 200mVPP on VDDHP VDDHP = 2.8V, CB = 4.7μF, Mode 4, 7, HP 300015k4 300015k5 PSRR vs Frequency RL = 32Ω, VRIPPLE = 200mVPP on VDDHP VDDHP = 2.8V, CB = 4.7μF, Mode 6, HP PSRR vs Frequency RL = 32Ω, VRIPPLE = 200mVPP on VDDLS VDDLS = 3.6V, CB = 4.7μF, Mode 2, 10, HP 300015k6 300015l0 PSRR vs Frequency RL = 32Ω, VRIPPLE = 200mVPP on VDDLS VDDLS = 3.6V, CB = 4.7μF, Mode 4, 7, HP PSRR vs Frequency RL = 32Ω, VRIPPLE = 200mVPP on VDDLS VDDLS = 3.6V, CB = 4.7μF, Mode 6, 14, HP 300015l1 300015l2 www.national.com 12 LM49100 PSRR vs Frequency RL = 8Ω, VRIPPLE = 200mVPP on VDDHP VDDHP = 2.8V, CB = 4.7μF, Mode 7, 10, 14, LS+HP PSRR vs Frequency RL = 8Ω, VRIPPLE = 200mVPP on VDDLS VDDLS = 3.6V, CB = 4.7μF, Mode 1, LS 300015m3 300015l6 PSRR vs Frequency RL = 8Ω, VRIPPLE = 200mVPP on VDDLS VDDLS = 3.6V, CB = 4.7μF, Mode 7, 10, 14, LS+HP PSRR vs Frequency RL = 8Ω, VRIPPLE = 200mVPP on VDDLS VDDLS = 3.6V, CB = 4.7μF, Mode 3, LS 300015m0 300015l7 PSRR vs Frequency RL = 8Ω, VRIPPLE = 200mVPP on VDDLS VDDLS = 3.6V, CB = 4.7μF, Mode 5, LS Crosstalk vs Frequency PO = 12mW, f = 1kHz, Mode 4, HP 30001525 300015l8 13 www.national.com LM49100 LM49100 Control Tables The LM49100 is controlled through an = 1). D7 Modes Control HP Volume (Gain) Control Mono Volume Control Left Volume (Gain) Control Right Volume (Gain) Control 0 0 1 1 1 I 2C TABLE 1. I2C Control Register Table compatible interface. The I2C chip address is 0xF8 (ADR pin = 0) or 0xFAh (ADDR pin D5 1 INPUT_MU TE 0 0 1 D4 1 0 MV4 LV4 RV4 D3 MC3 0 MV3 LV3 RV3 D2 MC2 HPR_SD MV2 LV2 RV2 D1 MC1 HPVC1 MV1 LV1 RV1 D0 MC0 HPVC0 MV0 LV0 RV0 D6 0 1 0 1 1 TABLE 2. Headphone Attenuation Control The following bits have added for extra headphone output attenuation: Gain Select 0 1 2 3 HPVC1 0 0 1 1 HPVC0 0 1 0 1 Gain, dB 0 −12 −18 −24 TABLE 3. Output Mode Selection Output Mode Number 0 1 2 3 4 5 6 7 10 14 MC3 0 0 0 0 0 0 0 0 1 1 MC2 0 0 0 0 1 1 1 1 0 1 MC1 0 0 1 1 0 0 1 1 1 1 MC0 0 1 0 1 0 1 0 1 0 0 Handsfree Mono Output SD 2 × GM × M SD 2 × (GL × L + GR × R) SD 2 × (GL × L + GR × R + GM × M) SD 2 × (GL × L + GR × R) 2 × (GL × L + GR × R) 2 × (GL × L + GR × R) Right HP Output SD SD GHP × (GM × M) SD GHP × (GR × R) SD GHP × (GR × R + GM × M) GHP × (GR × R) GHP × (GM × M) GHP × (GR × R + GM × M) Left HP Output SD SD GHP × (GM × M) SD GHP × (GL × L) SD GHP × (GL × L + GM × M) GHP × (GL × L) GHP × (GM × M) GHP × (GL × L + GM × M) GL— Left channel gain GR — Right channel gain GM — Mono channel gain GHP — Headphone Amplifier gain R — Right input signal L — Left input signal SD — Shutdown M — Mono input signal www.national.com 14 LM49100 TABLE 4. Mono/Stereo Left/Stereo Right Input Gain Control Volume Step MV4/LV4/RV4 MV3/LV3/RV3 MV2/LV2/RV2 MV1/LV1/RV1 MV0/LV0/RV0 R/L Gain, dB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 −54 −47 −40.5 −34.5 −30.0 −27 −24 −21 −18 −15 −13.5 −12 −10.5 −9 −7.5 −6 −4.5 −3 −1.5 0 1.5 3 4.5 6 7.5 9 10.5 12 13.5 15 16.5 18 MonoGain, dB −60 −53 −46.5 −40.5 −36 −33 −30 −27 −24 −21 −19.5 −18 −16.5 −15 −13.5 −12 −10.5 −9 −7.5 −6 −4.5 −3 −1.5 0 1.5 3 4.5 6 7.5 9 10.5 12 15 www.national.com LM49100 Application Information MINIMIZING CLICK AND POP To minimize the audible click and pop heard through a headphone, maximize the input signal through the corresponding volume (gain) control registers and adjust the output amplifier gain accordingly to achieve the user’s desired signal gain. For example, setting the output of the headphone amplifier to -24dB and setting the input volume control gain to 24dB will reduce the output offset from 7mV (typical) to 2.2mV (typical). This will reduce the audible click and pop noise significantly while maintaining a 0dB signal gain. SIGNAL GROUND NOISE The LM49100 has proprietary suppression circuitry, which provides an additional -50dB (typical) attenuation of the headphone ground noise and its incursion into the headphone. For optimum utilization of this feature the headphone jack ground should connect to the AGND (E3) bump. are of the form 111110X10 (binary), where X1 = 0, if ADDR pin is logic LOW; and X1 = 1, if ADDR pin is logic HIGH. If the I2C interface is used to address a number of chips in a system, the LM49100's chip address can be changed to avoid any possible address conflicts. The bus format for the I2C interface is shown in Figure 2. The bus format diagram is broken up into six major sections: The "start" signal is generated by lowering the data signal while the clock signal is HIGH. The start signal will alert all devices attached to the I2C bus to check the incoming address against their own address. The 8-bit chip address is sent next, most significant bit first. The data is latched in on the rising edge of the clock. Each address bit must be stable while the clock level is HIGH. After the last bit of the address bit is sent, the master releases the data line HIGH (through a pull-up resistor). Then the master sends an acknowledge clock pulse. If the LM49100 has received the address correctly, then it holds the data line LOW during the clock pulse. If the data line is not held LOW during the acknowledge clock pulse, then the master should abort the rest of the data transfer to the LM49100. The 8 bits of data are sent next, most significant bit first. Each data bit should be valid while the clock level is stable HIGH. After the data byte is sent, the master must check for another acknowledge to see if the LM49100 received the data. If the master has more data bytes to send to the LM49100, then the master can repeat the previous two steps until all data bytes have been sent. The "stop" signal ends the transfer. To signal "stop", the data signal goes HIGH while the clock signal is HIGH. The data line should be held HIGH when not in use. I2C INTERFACE POWER SUPPLY PIN (VDDI2C) The LM49100's I2C interface is powered up through theVDD I2C pin. The LM49100's I2C interface operates at a voltage level set by the VDD I2C pin which can be set independent to that of the main power supply pin VDD. This is ideal whenever logic levels for the I2C interface are dictated by a microcontroller or microprocessor that is operating at a lower supply voltage than the main battery of a portable system. 300015m9 I2C PIN DESCRIPTION SDA: This is the serial data input pin. SCL: This is the clock input pin. ADDR: This is the address select input pin. I2C COMPATIBLE INTERFACE The LM49100 uses a serial bus which conforms to the I2C protocol to control the chip's functions with two wires: clock (SCL) and data (SDA). The clock line is uni-directional. The data line is bi-directional (open-collector). The LM49100's I2C compatible interface supports standard (100kHz) and fast (400kHz) I2C modes. In this discussion, the master is the controlling microcontroller and the slave is the LM49100. The I2C address for the LM49100 is determined using the ADDR pin. The LM49100's two possible I2C chip addresses 300015d5 FIGURE 2. I2C Bus Format www.national.com 16 LM49100 300015d6 FIGURE 3. I2C Timing Diagram PCB LAYOUT AND SUPPLY REGULATION CONSIDERATIONS FOR DRIVING 8Ω LOAD Power dissipated by a load is a function of the voltage swing across the load and the load's impedance. As load impedance decreases, load dissipation becomes increasingly dependent on the interconnect (PCB trace and wire) resistance between the amplifier output pins and the load's connections. Residual trace resistance causes a voltage drop, which results in power dissipated in the trace and not in the load as desired. For example, 0.1Ω trace resistance reduces the output power dissipated by an 8Ω load from 158.3mW to 156.4mW. The problem of decreased load dissipation is exacerbated as load impedance decreases. Therefore, to maintain the highest load dissipation and widest output voltage swing, PCB traces that connect the output pins to a load must be as wide as possible. Poor power supply regulation adversely affects maximum output power. A poorly regulated supply's output voltage decreases with increasing load current. Reduced supply voltage causes decreased headroom, output signal clipping, and reduced output power. Even with tightly regulated supplies, trace resistance creates the same effects as poor supply regulation. Therefore, making the power supply traces as wide as possible helps maintain full output voltage swing. BRIDGE CONFIGURATION EXPLANATION The LM49100 drives a load, such as a loudspeaker, connected between outputs, LS+ and LS-. This results in both amplifiers producing signals identical in magnitude, but 180° out of phase. Taking advantage of this phase difference, a load is placed between LS- and LS+ and driven differentially (commonly referred to as ”bridge mode”). Bridge mode amplifiers are different from single-ended amplifiers that drive loads connected between a single amplifier's output and ground. For a given supply voltage, bridge mode has a distinct advantage over the single-ended configuration: its differential output doubles the voltage swing across the load. Theoretically, this produces four times the output power when compared to a single-ended amplifier under the same conditions. This increase in attainable output power assumes that the amplifier is not current limited and that the output signal is not clipped. Another advantage of the differential bridge output is no net DC voltage across the load. This is accomplished by biasing LS- and LS+ outputs at half-supply. This eliminates the coupling capacitor that single supply, single-ended amplifiers require. Eliminating an output coupling capacitor in a typical single-ended configuration forces a single-supply amplifier's half-supply bias voltage across the load. This increases internal IC power dissipation and may permanently damage loads such as loudspeakers. POWER DISSIPATION Power dissipation is a major concern when designing a successful single-ended or bridged amplifier. A direct consequence of the increased power delivered to the load by a bridge amplifier is higher internal power dissipation. The LM49100 has a pair of bridged-tied amplifiers driving a handsfree loudspeaker, LS. The maximum internal power dissipation operating in the bridge mode is twice that of a single-ended amplifier. From Equation (1), assuming a 5V power supply and an 8Ω load, the maximum MONO power dissipation is 634mW. PDMAX-LS = 4(VDD)2 / (2π2 RL): Bridge Mode (1) The LM49100 also has a pair of single-ended amplifiers driving stereo headphones, HPR and HPL. The maximum internal power dissipation for HPR and HPL is given by equation (2). Assuming a 2.8V power supply and a 32Ω load, the maximum power dissipation for LOUT and ROUT is 49mW, or 99mW total. PDMAX-HPL = 4(VDDHP)2 / (2π2 RL): Single-ended Mode (2) The maximum internal power dissipation of the LM49100 occurs when all three amplifiers pairs are simultaneously on; and is given by Equation (3). PDMAX-TOTAL = PDMAX-LS + PDMAX-HPL + PDMAX-HPR (3) The maximum power dissipation point given by Equation (3) must not exceed the power dissipation given by Equation (4): 17 www.national.com LM49100 PDMAX = (TJMAX - TA) / θJA (4) The LM49100's TJMAX = 150°C. In the GR package, the LM49100's θJA is 50.2°C/W. At any given ambient temperature TA, use Equation (4) to find the maximum internal power dissipation supported by the IC packaging. Rearranging Equation (4) and substituting PDMAX-TOTAL for PDMAX results in Equation (5). This equation gives the maximum ambient temperature that still allows maximum stereo power dissipation without violating the LM49100's maximum junction temperature. TA = TJMAX - PDMAX-TOTAL θJA (5) 1µF in parallel with a 0.1µF filter capacitors to stabilize the regulator's output, reduce noise on the supply line, and improve the supply's transient response. However, their presence does not eliminate the need for a local 4.7µF tantalum bypass capacitor and a parallel 0.1µF ceramic capacitor connected between the LM49100's supply pin and ground. Keep the length of leads and traces that connect capacitors between the LM49100's power supply pin and ground as short as possible. SELECTING EXTERNAL COMPONENTS Input Capacitor Value Selection Amplifying the lowest audio frequencies requires high value input coupling capacitor (CIN in Figure 1). A high value capacitor can be expensive and may compromise space efficiency in portable designs. In many cases, however, the loudspeakers used in portable systems, whether internal or external, have little ability to reproduce signals below 150Hz. Applications using loudspeakers and headphones with this limited frequency response reap little improvement by using large input capacitor. The internal input resistor (Ri), typical 12.5kΩ, and the input capacitor (CIN) produce a high pass filter cutoff frequency that is found using Equation (7). fc = 1 / (2πRiCIN) (7) For a typical application with a 5V power supply and an 8Ω load, the maximum ambient temperature that allows maximum mono power dissipation without exceeding the maximum junction temperature is approximately 114°C for the GR package. TJMAX = PDMAX-TOTAL θJA + TA (6) Equation (6) gives the maximum junction temperature TJMAX. If the result violates the LM49100's 150°C, reduce the maximum junction temperature by reducing the power supply voltage or increasing the load resistance. Further allowance should be made for increased ambient temperatures. The above examples assume that a device is a surface mount part operating around the maximum power dissipation point. Since internal power dissipation is a function of output power, higher ambient temperatures are allowed as output power or duty cycle decreases. If the result of Equation (3) is greater than that of Equation (4), then decrease the supply voltage, increase the load impedance, or reduce the ambient temperature. If these measures are insufficient, a heat sink can be added to reduce θJA. The heat sink can be created using additional copper area around the package, with connections to the ground pin(s), supply pin and amplifier output pins. POWER SUPPLY BYPASSING As with any power amplifier, proper supply bypassing is critical for low noise performance and high power supply rejection. Applications that employ a 5V regulator typically use a Bypass Capacitor Value Selection Besides minimizing the input capacitor size, careful consideration should be paid to value of CB, the capacitor connected to the BYPASS pin. Since CB determines how fast the LM49100 settles to quiescent operation, its value is critical when minimizing turn-on pops. Choosing CB equal to 2.2µF along with a small value of Ci (in the range of 0.1µF to 0.33µF), produces a click-less and pop-less shutdown function. As discussed above, choosing CIN no larger than necessary for the desired bandwidth helps minimize clicks and pops. CB's value should be in the range of 4 to 5 times the value of CIN . This ensures that output transients are eliminated when power is first applied or the LM49100 resumes operation after shutdown. www.national.com 18 LM49100 Demo Board Schematic 300015q3 19 www.national.com Demo Board Schematic LM49100 Demonstration Board Layout 300015f0 Signal 1 Layer 300015f1 Signal 2 Layer www.national.com 20 LM49100 300015f2 Top Layer 300015f3 Top Overlay 21 www.national.com LM49100 300015e8 Bottom Layer 300015e9 Bottom Overlay www.national.com 22 LM49100 Revision History Rev 1.0 1.1 1.2 1.3 1.4 1.5 Date 06/21/07 06/28/07 08/09/07 08/13/07 08/14/07 09/18/07 Initial release. Changed the mktg outline from TLA25XXX to GRA25A. Replaced some curves. Changed the f = 1kHz into f = 217Hz (PSRR) in the Electrical Characteristics table. Edited Table 1. Edited the schematic diagram. Description 23 www.national.com LM49100 Physical Dimensions inches (millimeters) unless otherwise noted Dimensions: X1 = X2 = 3 mm, X3 = 1 mm GR Package Order Number LM49100GR See NS Package Number GRA25A www.national.com 24 LM49100 Notes 25 www.national.com LM49100 Mono Class AB Audio Sub-System with a True-Ground Headphone Amplifier Notes THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. NATIONAL MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE ACCURACY OR COMPLETENESS OF THE CONTENTS OF THIS PUBLICATION AND RESERVES THE RIGHT TO MAKE CHANGES TO SPECIFICATIONS AND PRODUCT DESCRIPTIONS AT ANY TIME WITHOUT NOTICE. NO LICENSE, WHETHER EXPRESS, IMPLIED, ARISING BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. TESTING AND OTHER QUALITY CONTROLS ARE USED TO THE EXTENT NATIONAL DEEMS NECESSARY TO SUPPORT NATIONAL’S PRODUCT WARRANTY. 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