LM49120TLX

LM49120 Audio Sub-System with Mono Class AB Loudspeaker Amplifier and Stereo OCL/SE Headphone Amplifier July 15, 2008 LM49120 Audio Sub-System with Mono Class AB Loudspeaker Amplifier and Stereo OCL/SE Headphone Amplifier General Description The LM49120 is a compact audio subsystem designed for portable handheld applications such as cellular phones. The LM49120 combines a mono 1.3W speaker amplifier, stereo 85mW/ch output capacitorless headphone amplifier, 32 step volume control, and an input mixer/multiplexer into a single 16–bump micro SMD package. The LM49120 has three input channels: two single-ended stereo inputs and a differential mono input. Each input features a 32-step digital volume control. The headphone output stage features an 8 step (-18dB – 0dB) attenuator, while the speaker output stage has two selectable (0dB/+6dB) gain settings. The digital volume control and mode control are programmed through a two-wire I2C compatible interface.  Speaker:   RL = 8Ω, BTL, THD+N ≤ 1%  Headphone:   RL = 32Ω, OCL/SE, THD+N ≤ 1% 540mW (typ) 35mW (typ) Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ RF immunity Selectable OCL/SE headphone drivers 32 Step volume control Click and Pop suppression Independent speaker and headphone gain settings Minimum external components Thermal over load protection Micro-power shutdown Space saving 16–bump mciro SMD package Thermal shutdown protection Micro-power shutdown I2C Control Interface Key Specifications ■ Output power at VDD = 5V:  Speaker:   RL = 8Ω BTL, THD+N ≤ 1%  Headphone:   RL = 32Ω, SE, THD+N ≤ 1% ■ Output power at VDD = 3.6V:  Speaker:   RL = 8Ω, BTL, THD+N ≤ 1% ■ Output power at VDD = 3.3V: 632mW (typ) 1.3W (typ) 85mW (typ) Applications ■ Mobile Phones ■ PDAs ■ Portable Electronics Boomer® is a registered trademark of National Semiconductor Corporation. © 2008 National Semiconductor Corporation 300375 www.national.com LM49120 Typical Application 300375g1 FIGURE 1. Output Capacitor-less Configuration 300375n4 FIGURE 2. Single-Ended Configuration Note:The 6dB speaker gain applies only to the differential input path. www.national.com 2 LM49120 Connection Diagrams 16 Bump micro SMD Package 30037549 Top View XY - Date Code TT - Die Traceability G- Boomer K2 - LM49120TL 300375n2 Top View (Bump-Side Down) See NS Package Number TLA1611A Ordering Information Order Number LM49120TL LM49120TLX Package 16 Bump micro SMD 16 Bump micro SMD Package DWG # TLA1611A TLA1611A Transport Media 250 units on tape and reel 3000 units on tape and reel MSL Level 1 1 Green Status NOPB NOPB 3 www.national.com LM49120 Pin Descriptions Bump A1 A2 A3 A4 B1 B2 B3 B4 C1 C2 C3 C4 D1 D2 D3 D4 Name VOC VDD ROUT LOUT MONO_IN+ BYPASS LIN RIN MONO_INI2CVDD SCL SDA MONOGND VDD MONO+ Description Headphone Center Amplifier Output Headphone Power Supply Right Channel Headphone Output Left Channel Headphone Output Mono Non-inverting Input Bias Bypass Left Channel Input Right Channel Input Mono Inverting Input I2C Interface Power Supply I2C Clock Input I2C Data Input Loudspeaker Inverting Output Ground Power Supply Loudspeaker Non-inverting Output www.national.com 4 LM49120 Absolute Maximum Ratings (Notes 1, 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (Note 1) Storage Temperature Input Voltage Power Dissipation (Note 3) ESD Rating (Note 4) ESD Rating (Note 5) Junction Temperature 6.0V −65°C to +150°C −0.3 to VDD +0.3 Internally Limited 2000V 200V 150°C Solder Information Vapor Phase (60 sec.) Infrared (15 sec.) Thermal Resistance  θJA (typ) - TLA 215°C 220°C 62.3°C/W Operating Ratings Temperature Range Supply Voltage (VDD) Supply Voltage (I2CVDD) −40°C to 85°C 1.7V ≤ I2CVDD ≤ 5.5V 2.7V ≤ VDD ≤ 5.5V Electrical Characteristics 3.3V Symbol Parameter (Notes 1, 2) The following specifications apply for VDD = 3.3V, TA = 25°C, all volume controls set to 0dB, unless otherwise specified. LM49120 Conditions VIN = 0, No Load Output mode 5, 6, 7, 9, 10, 11, 13, 14, 15 OCL Headphone Output mode 5, 6, 7, 9, 10, 11, 13, 14, 15 SE Headphone IDD Supply Current Output mode 1, 2, 3 OCL Headphone Output mode 1, 2, 3 SE Headphone Output mode 4, 8, 12 OCL Headphone Output mode 4, 8, 12 SE Headphone ISD VOS Shutdown Current Output Offset Voltage Shutdown Mode 0 VIN = 0V, Output Mode 10, LS output VIN = 0V, Output Mode 10, HP output, (OCL), 0dB (HP Output Gain) LSOUT; RL = 8Ω THD+N = 1%; f = 1kHz, BTL, Mode 1 LOUT and ROUT; RL = 32Ω THD+N = 1%; f = 1kHz, OCL, Mode 8 MONOOUT f = 1kHz POUT = 250mW; RL = 8Ω, BTL, Mode 1 THD+N Total Harmonic Distortion + Noise LOUT and ROUT, f = 1kHz POUT = 12mW; RL = 32Ω, SE, Mode 8 LOUT and ROUT, f = 1kHz POUT = 12mW; RL = 32Ω, OCL, Mode 8 6.2 5.5 4.1 5.5 3.7 3.0 0.01 10 1.5 540 35 5 500 30 1 4.7 5.3 8.0 mA (max) mA mA (max) mA mA (max) mA µA mV mV (max) mW (min) mW (min) Typical (Note 6) Limits (Note 7) Units (Limits) PO Output Power 0.05 % 0.015 0.015 % % 5 www.national.com LM49120 LM49120 Symbol Parameter Conditions A-weighted, inputs terminated to GND, Output referred Speaker Amplifier; Mode 1 Speaker Amplifier; Mode 2 Speaker Amplifier; Mode 3 eOUT Output Noise Headphone Amplifier; SE, Mode 4 Headphone Amplifier; SE, Mode 8 Headphone Amplifier; SE, Mode 12 Headphone Amplifier; OCL, Mode 4 Headphone Amplifier; OCL, Mode 8 Headphone Amplifier; OCL, Mode 12 15 24 29 8 8 11 8 9 12 Typical (Note 6) Limits (Note 7) Units (Limits) μV μV μV μV μV μV μV μV μV VRIPPLE = 200mVPP; fRIPPLE = 217Hz, RL = 8Ω (Speaker); RL = 32Ω (Headphone) CB = 2.2µF, BTL All audio inputs terminated to GND; output referred Speaker Output; Speaker Output Gain 6dB Speaker Amplifier; Mode 1 Speaker Amplifier; Mode 2 Speaker Amplifier; Mode 3 Speaker Amplifier; Mode 1 Speaker Amplifier; Mode 2 Speaker Amplifier; Mode 3 Headphone Amplifier Output Headphone Amplifier; SE, Mode 4 Headphone Amplifier; SE, Mode 8 Headphone Amplifier; SE, Mode 12 Headphone Amplifier; OCL, Mode 4 Headphone Amplifier; OCL, Mode 8 Headphone Amplifier; OCL, Mode 12 VOL∈ Volume Control Step Size Error Maximum Attenuation VOLRANGE Digital Volume Control Range Maximum Gain Au(HP) HP (SE) Mute Attenuation MONO_IN Input Impedance LIN and RIN Input Impedance Output Mode 1, 2, 3 Maximum gain setting Maximum attenuation setting f = 217Hz, VCM = 1VPP, Speaker, BTL, Mode 1, RL = 8Ω Differential Input f = 217Hz, VCM = 1VPP, Headphone, OCL, Mode 4, RL = 32Ω Stereo Input 18 96 12.5 110 10 15 90 130 83 84 78 83 80 77 ±0.2 –86 –91 –81 17.4 18.6 dB dB dB dB dB dB dB dB (min) dB (max) dB (min) dB (max) dB kΩ (min) kΩ (max) kΩ (min) kΩ (max) 79 63 62 84 63 62 dB dB dB dB dB dB Speaker Amplifier Output; Speaker Output Gain 0dB PSRR Power Supply Rejection Ratio ZIN 61 dB CMRR Common-Mode Rejection Ratio 66 dB www.national.com 6 LM49120 LM49120 Symbol Parameter Conditions Headphone; POUT = 12mW f = 1kHz, OCL. Mode 8 Headphone; POUT = 12mW f = 1kHz, SE, Mode 8 CB = 4.7μF, OCL CB = 2.2μF, SE, Normal Turn On Mode Turn_On_Time = 1 CB = 2.2μF, OCL CB = 4.7μF, SE, Fast Turn On Mode Turn_On_Time = 0 Typical (Note 6) –60 –72 35 120 30 130 Limits (Note 7) Units (Limits) dB dB ms ms ms ms XTALK Crosstalk TWU Wake-Up Time from Shutdown Electrical Characteristics 5.0V Symbol Parameter (Notes 1, 2) The following specifications apply for VDD = 5.0V, TA = 25°C, all volume controls set to 0dB, unless otherwise specified. LM49120 Conditions VIN = 0, No Load Output mode 5, 6, 7, 9, 10, 11, 13, 14, 15 OCL Headphone Output mode 5, 6, 7, 9, 10, 11, 13, 14, 15 SE Headphone IDD Supply Current Output mode 1, 2, 3 OCL Headphone Output mode 1, 2, 3 SE Headphone Output mode 4, 8, 12 OCL Headphone Output mode 4, 8, 12 SE Headphone ISD VOS Shutdown Current Output Offset Voltage Shutdown Mode 0 VIN = 0V, Output Mode 10, LS output VIN = 0V, Output Mode 10, HP output, (OCL), 0dB (HP Output Gain) LS OUT; RL = 8Ω THD+N = 1%; f = 1kHz, BTL, Mode 1 LOUT and ROUT; RL = 32Ω THD+N = 1%; f = 1kHz, OCL, Mode 8 LSOUT f = 1kHz POUT = 250mW; RL = 8Ω, BTL, Mode 1 THD+N Total Harmonic Distortion + Noise LOUT and ROUT, f = 1kHz POUT = 12mW; RL = 32Ω, SE, Mode 8 LOUT and ROUT, f = 1kHz POUT = 12mW; RL = 32Ω, OCL, Mode 8 7.2 6.4 6.4 4.8 4.4 3.5 0.01 10 1.5 1.3 85 mA mA mA mA mA mA µA mV mV W mW Typical (Note 6) Limits (Note 7) Units (Limits) PO Output Power 0.05 % 0.015 0.015 % % 7 www.national.com LM49120 LM49120 Symbol Parameter Conditions A-weighted, inputs terminated to GND, Output referred Speaker Amplifier; Mode 1 Speaker Amplifier; Mode 2 Speaker Amplifier; Mode 3 eOUT Output Noise Headphone Amplifier; SE, Mode 4 Headphone Amplifier; SE, Mode 8 Headphone Amplifier; SE, Mode 12 Headphone Amplifier; OCL, Mode 4 Headphone Amplifier; OCL, Mode 8 Headphone Amplifier; OCL, Mode 12 VRIPPLE = 200mVPP; fRIPPLE = 217Hz, RL = 8Ω (Speaker); RL = 32Ω (Headphone) CB = 2.2µF, BTL All audio inputs terminated to GND; output referred Speaker Output; Speaker Output Gain 6dB Speaker Amplifier; Mode 1 Speaker Amplifier; Mode 2 Speaker Amplifier; Mode 3 PSRR Power Supply Rejection Ratio Speaker Amplifier; Mode 1 Speaker Amplifier; Mode 2 Speaker Amplifier; Mode 3 Headphone Amplifier Output Headphone Amplifier; SE, Mode 4 Headphone Amplifier; SE, Mode 8 Headphone Amplifier; SE, Mode 12 Headphone Amplifier; OCL, Mode 4 Headphone Amplifier; OCL, Mode 8 Headphone Amplifier; OCL, Mode 12 VOL∈ Volume Control Step Size Error Maximum Attenuation VOLRANGE Digital Volume Control Range Maximum Gain Au(HP) HP (SE) Mute Attenuation MONO_IN Input Impedance LIN and RIN Input Impedance Output Mode 1, 2, 3 Maximum gain setting Maximum attenuation setting f = 217Hz, VCM = 1VPP, Speaker, BTL, Mode 1, RL = 8Ω Differential Input f = 217Hz, VCM = 1VPP, Headphone, OCL, Mode 4, RL = 32Ω Stereo Input 18 96 12.5 110 75 75 72 75 75 72 ±0.2 –86 –91 –81 69 60 58 84 63 62 17 27 33 8 8 12 9 9 12 Typical (Note 6) Limits (Note 7) Units (Limits) μV μV μV μV μV μV μV μV μV dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB kΩ kΩ kΩ kΩ Speaker Amplifier Output; Speaker Output Gain 0dB ZIN 61 dB CMRR Common-Mode Rejection Ratio 66 dB www.national.com 8 LM49120 LM49120 Symbol Parameter Conditions Headphone; POUT = 12mW f = 1kHz, OCL, Mode 8 Headphone; POUT = 12mW f = 1kHz, SE, Mode 8 CB = 4.7μF, OCL CB = 2.2μF, SE, Normal Turn On Mode Turn_On_Time = 1 CB = 2.2μF, OCL CB = 4.7μF, SE, Fast Turn On Mode Turn_On_Time = 0 Typical (Note 6) –54 –72 28 151 25 168 Limits (Note 7) Units (Limits) dB dB ms ms ms ms XTALK Crosstalk TWU Wake-Up Time from Shutdown 9 www.national.com LM49120 I2C Timing Characteristics 2.2V ≤ I2C_VDD ≤ 5.5V, The following specifications apply for VDD = 5.0V and 3.3V, TA = 25°C, 2.2V ≤ Symbol t1 t2 t3 t4 t5 t6 VIH VIL Parameter I2C Clock Period I2C Data Setup Time I2C Data Stable Time Start Condition Time Stop Condition Time I2C Data Hold Time I2C Input Voltage High I2C Input Voltage Low Conditions (Notes 1, 2) DD I2C_V ≤ 5.5V, unless otherwise specified. LM49120 Typical Limits (Note 7) (Note 6) 2.5 100 0 100 100 100 0.7xI2CV DD Units (Limits) µs (min) ns (min) ns (min) ns (min) ns (min) ns (min) V (min) V (max) 0.3xI2CVDD (Notes 1, 2) LM49120 The following specifications apply for VDD = 5.0V and 3.3V, TA = 25°C, 1.7V ≤ I2C_VDD ≤ 2.2V, unless otherwise specified. Symbol t1 t2 t3 t4 t5 t6 VIH VIL Parameter I2C Clock Period I2C Data Setup Time I2C Data Stable Time Start Condition Time Stop Condition Time I2C Data Hold Time I2C Input Voltage High I2C Input Voltage Low Conditions Typical Limits (Note 7) (Note 6) 2.5 250 0 250 250 250 0.7xI2CVDD 0.3xI2CVDD Units (Limits) µs (min) ns (min) ns (min) ns (min) ns (min) ns (min) V (min) V (max) I2C Timing Characteristics 1.7V ≤ I2C_VDD ≤ 2.2V Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All voltages are measured with respect to the ground pin, unless otherwise specified. Note 2: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed. Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature, TA. The maximum allowable power dissipation is PDMAX = (TJMAX - TA) / θJA or the number given in Absolute Maximum Ratings, whichever is lower. Note 4: Human body model, applicable std. JESD22-A114C. Note 5: Machine model, applicable std. JESD22-A115-A. Note 6: Typical values represent most likely parametric norms at TA = +25ºC, and at the Recommended Operation Conditions at the time of product characterization and are not guaranteed. Note 7: Datasheet min/max specification limits are guaranteed by test or statistical analysis. www.national.com 10 LM49120 Typical Performance Characteristics Filter BW = 22kHz Crosstalk vs Frequency VDD = 3.3V, RL = 32Ω, PO = 12mW, f = 1kHz, Mode 8, OCL Crosstalk vs Frequency VDD = 3.3V, RL = 32Ω, PO = 12mW, f = 1kHz, Mode 8, SE 30037501 30037502 Crosstalk vs Frequency VDD = 5V, RL = 32Ω, PO = 30mW, f = 1kHz, Mode 8, OCL Crosstalk vs Frequency VDD = 5V, RL = 32Ω, PO = 30mW, f = 1kHz, Mode 8, SE 30037503 30037504 Output Power vs Supply Voltage VDD = 3.3V, RL = 32Ω f = 1kHz, Mode 8, OCL Output Power vs Supply Voltage VDD = 5V, RL = 8Ω f = 1kHz, Mode 1, Speaker 30037505 30037506 11 www.national.com LM49120 Power Dissipation vs Output Power VDD = 3.3V, RL = 32Ω f = 1kHz, Mode 8, OCL Power Dissipation vs Output Power VDD = 3.3V, RL = 8Ω f = 1kHz, Mode 1, Speaker 30037507 30037508 Power Dissipation vs Output Power VDD = 5V, RL = 32Ω f = 1kHz, Mode 8, OCL Power Dissipation vs Output Power VDD =5V, RL = 8Ω f = 1kHz, Mode 1, Speaker 30037509 30037510 Supply Current vs Supply Voltage VIN= GND, No load THD+N vs Frequency VDD = 3.3V, RL = 32Ω, PO = 12mW f = 22kHz, Mode 8, OCL 30037511 30037512 www.national.com 12 LM49120 THD+N vs Frequency VDD = 3.3V, RL = 32Ω, PO = 12mW f = 22kHz, Mode 8, SE THD+N vs Frequency VDD = 3.3V, RL = 64Ω, PO = 24mW f = 22kHz, Mode 4, BTL 30037513 30037514 THD+N vs Frequency VDD = 3.3V, RL = 8Ω, PO = 250mW f = 1kHz, Mode 1, Speaker THD+N vs Frequency VDD = 5V, RL = 32Ω, PO = 30mW f = 22kHz, Mode 8, OCL 30037515 30037516 THD+N vs Frequency VDD = 5V, RL = 32Ω, PO = 30mW f = 22kHz, Mode 8, SE THD+N vs Frequency VDD = 5V, RL = 64Ω, PO = 72mW f = 22kHz, Mode 4, BTL 30037517 30037518 13 www.national.com LM49120 THD+N vs Frequency VDD = 5V, RL = 8Ω, PO = 500mW f = 1kHz, Mode 1, Speaker THD+N vs Output Power VDD = 3.3V, RL = 32Ω f = 1kHz, Mode 8, OCL 30037519 30037520 THD+N vs Output Power VDD = 3.3V, RL = 32Ω f = 1kHz, Mode 8, SE THD+N vs Output Power VDD = 3.3V, RL = 64Ω f = 1kHz, Mode 4, BTL 30037521 30037522 THD+N vs Output Power VDD = 3.3V, RL = 8Ω f = 1kHz, Mode 1, Speaker THD+N vs Output Power VDD = 5V, RL = 32Ω f = 1kHz, Mode 8, OCL 30037523 30037524 www.national.com 14 LM49120 THD+N vs Output Power VDD = 5V, RL = 32Ω f = 1kHz, Mode 8, SE THD+N vs Output Power VDD = 5V, RL = 64Ω f = 1kHz, Mode 4, BTL 30037525 30037526 THD+N vs Output Power VDD = 5V, RL = 8Ω f = 1kHz, Mode 1, Speaker PSRR vs Frequency VDD = 3.3V, RL = 8Ω, CBYP = 2.2μF VRIPPLE = 200mVP-P, MODE 1 30037527 30037531 PSRR vs Frequency VDD = 3.3V, RL = 8Ω, CBYP = 4.7μF VRIPPLE = 200mVP-P, MODE 1 PSRR vs Frequency VDD = 3.3V, RL = 32Ω, CBYP = 2.2μF VRIPPLE = 200mVP-P, MODE 8, OCL 30037532 30037533 15 www.national.com LM49120 PSRR vs Frequency VDD = 3.3V, RL = 32Ω, CBYP = 2.2μF VRIPPLE = 200mVP-P, MODE 8, SE PSRR vs Frequency VDD = 3.3V, RL = 32Ω, CBYP = 4.7μF VRIPPLE = 200mVP-P, MODE 8, OCL 30037534 30037535 PSRR vs Frequency VDD = 3.3V, RL = 32Ω, CBYP = 2.2μF VRIPPLE = 200mVP-P, MODE 4, BTL PSRR vs Frequency VDD = 3.3V, RL = 64Ω, CBYP = 4.7μF VRIPPLE = 200mVP-P, MODE 4, BTL 30037536 30037537 PSRR vs Frequency VDD = 3.3V, RL = 8Ω, CBYP = 2.2μF VRIPPLE = 200mVP-P, MODE 1 PSRR vs Frequency VDD = 5V, RL = 8Ω, CBYP = 4.7μF VRIPPLE = 200mVP-P, MODE 1 30037538 30037539 www.national.com 16 LM49120 PSRR vs Frequency VDD = 5V, RL = 32Ω, CBYP = 2.2μF VRIPPLE = 200mVP-P, MODE 8, OCL PSRR vs Frequency VDD = 5V, RL = 32Ω, CBYP = 2.2μF VRIPPLE = 200mVP-P, MODE 8, SE 30037540 30037541 PSRR vs Frequency VDD = 5V, RL = 64Ω, CBYP = 4.7μF VRIPPLE = 200mVP-P, MODE 4, BTL PSRR vs Frequency VDD = 5V, RL = 32Ω, CBYP = 4.7μF VRIPPLE = 200mVP-P, MODE 8, SE 30037542 30037543 17 www.national.com LM49120 Application Information I2C COMPATIBLE INTERFACE The LM49120 is controlled through an I2C compatible serial interface that consists of a serial data line (SDA) and a serial clock (SCL). The clock line is uni-directional. The data line is bi-directional (open drain). The LM49120 and the master can communicate at clock rates up to 400kHz. Figure 3 shows the I2C interface timing diagram. Data on the SDA line must be stable during the HIGH period of SCL. The LM49120 is a transmit/receive slave-only device, reliant upon the master to generate the SCL signal. Each transmission sequence is framed by a START condition and a STOP condition (Figure 4). Each data word, device address and data, transmitted over the bus is 8 bits long and is always followed by an acknowledge pulse (Figure 5). The LM49120 device address is 1111100. I2C BUS FORMAT The I2C bus format is shown in Figure 5. The START signal, the transition of SDA from HIGH to LOW while SCL is HIGH, is generated, alerting all devices on the bus that a device address is being written to the bus. The 7-bit device address is written to the bus, most significant bit (MSB) first, followed by the R/W bit. R/W = 0 indicates the master is writing to the slave device, R/W = 1 indicates the master wants to read data from the slave device. Set R/ W = 0; the LM49120 is a WRITE-ONLY device and will not respond the R/W = 1. The data is latched in on the rising edge of the clock. Each address bit must be stable while SCL is HIGH. After the last address bit is transmitted, the master device releases SDA, during which time, an acknowledge clock pulse is generated by the slave device. If the LM49120 receives the correct address, the device pulls the SDA line low, generating and acknowledge bit (ACK). Once the master device registers the ACK bit, the 8-bit register data word is sent. Each data bit should be stable while SCL is HIGH. After the 8-bit register data word is sent, the LM49120 sends another ACK bit. Following the acknowledgement of the register data word, the master issues a STOP bit, allowing SDA to go high while SCL is high. 30037550 FIGURE 3. I2C Timing Diagram 30037551 FIGURE 4. Start and Stop Diagram www.national.com 18 LM49120 30037552 FIGURE 5. Example Write Sequence TABLE 1. Device Address B7 Device Address 1 B6 1 B5 1 B4 1 B3 1 B2 0 B1 0 B0 (R/W) 0 TABLE 2. Control Registers B7 Shutdown Control Output Mode Control Output Gain Control Mono Input Volume Control Left Input Volume Control Right Input Volume Control 0 0 1 1 1 1 B6 0 1 0 0 1 1 B5 0 0 0 1 0 1 B4 OCL/SE 0 0 MG4 LG4 RG4 B3 HP/BTL MC3 LS_GAIN MG3 LG3 RG3 B2 SD_I2CVDD MC2 HP_GAIN2 MG2 LG2 RG2 B1 Turn_On _Time MC1 HP_GAIN1 MG1 LG1 RG1 B0 PWR_On MC0 HP_GAIN0 MG0 LG0 RG0 TABLE 3. Shutdown Control Register Bit B4 B3 Name OSC/SE HP/BTL Value 0 1 0 1 0 1 B1 B0 TURN_ON_TIME PWR_ON 0 1 0 1 Description Single-Ended headphone mode (Capacitively Coupled) Output Capacitor-less (OCL) headphone mode Single-ended stereo headphone output mode Mono, BTL output mode. I2CVDD acts as an active low RESET input. If I2CVDD drops below 1.1V, the device is reset and the I2C registers are restored to their default state. Normal Operation. I2CVDD voltage does not reset the device Fast turn on time (120ms) Normal turn on time (130ms) Device Disabled Device Enabled B2 SD_I2CVDD 19 www.national.com LM49120 TABLE 4. Output Mode Control (HP/BTL = 0) Output Mode Number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 MC3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 MC2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 MC1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 MC0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 LS Output SD GM x M 2 x (GL x L + GR x R) 2 x (GL x L + GR x R) + GM x M SD GM x M 2 x (GL x L + GR x R) 2 x (GL x L + GR x R) + GM x M SD GM x M 2 x (GL x L + GR x R) 2 x (GL x L + GR x R) + GM x M SD GM x M 2 x (GL x L + GR x R) 2 x (GL x L + GR x R) + GM x M HP R Output SD Mute Mute Mute GM x M/2 GM x M/2 GM x M/2 GM x M/2 GR x R GR x R GR x R GR x R GR x R + GM x M/2 GR x R + GM x M/2 GR x R + GM x M/2 GR x R + GM x M/2 HP L Output SD Mute Mute Mute GM x M/2 GM x M/2 GM x M/2 GM x M/2 GL x L GL x L GL x L GL x L GL x L + GM x M/2 GL x L + GM x M/2 GL x L + GM x M/2 GL x L + GM x M/2 M: Mono Differential Input R: Right In L: Left In SD: Shutdown GM: Mono Volume Control Gain GR: Right Stereo Volume Control Gain GL: Left Stereo Volume Control Gain www.national.com 20 LM49120 TABLE 5. Output Mode Control (HP/BTL = 1) Output Mode Number 4 5 6 7 12 13 14 15 MC3 0 0 0 0 1 1 1 1 MC2 1 1 1 1 1 1 1 1 MC1 0 0 1 1 0 0 1 1 MC0 0 1 0 1 0 1 0 1 LS Output SD GM x M 2 x (GL x L + GR x R) 2 x (GL x L + GR x R) + GP x P SD GM x M 2 x (GL x L + GR x R) 2 x (GL x L + GR x R) + GM x M HP R Output GM x M+/2 GM x M+/2 GM x M+/2 GM x M+/2 GR x R + GM x M+/2 GR x R + GM x M+/2 GR x R + GM x M+/2 GR x R + GM x M+/2 HP L Output GM x M-/2 GM x M-/2 GM x M-/2 GM x M-/2 GL x L + GM x M-/2 GL x L + GM x M-/2 GL x L + GM x M-/2 GL x L + GM x M-/2 21 www.national.com LM49120 TABLE 6. Volume Control Table Volume Step 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 _G4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 _G3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 _G2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 _G1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 _G0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Gain (dB) Mute –46.50 –40.50 –34.50 –30.00 –27.00 –24.00 –21.00 –18.00 –15.00 –13.50 –12.00 –10.50 –9.00 –7.50 –6.00 –4.50 –3.00 –1.50 0.00 1.50 3.00 4.50 6.00 7.50 9.00 10.50 12.00 13.50 15.00 16.50 18.00 TABLE 7. Output Gain Control (Headphone) HP_GAIN2 0 0 0 0 1 1 1 1 HP_GAIN1 0 0 1 1 0 0 1 1 HP_GAIN0 0 1 0 1 0 1 0 1 GAIN (dB) 0 –1.2 –2.5 –4.0 –6.0 –8.5 –12 –18 www.national.com 22 LM49120 TABLE 8. Output Gain Control (Loudspeaker) Bit LS_GAIN Value 0 1 Gain (dB) Differential Input 0 +6 Gain (dB) Single-Ended Input +6 +12 BRIDGE CONFIGURATION EXPLAINED The LM49120 loudspeaker amplifier is designed to drive a load differentially, a configuration commonly referred to as a bridge-tied load (BTL). The BTL configuration differs from the single-ended configuration, where one side of the load is connected to ground. A BTL amplifier offers advantages over a single-ended device. By driving the load differentially, the output voltage is doubled, compared to a single-ended amplifier under similar conditions. This doubling of the output voltage leads to a quadrupling of the output power, for example, the theoretical maximum output power for a single-ended amplifier driving 8Ω and operating from a 5V supply is 390mW, while the theoretical maximum output power for a BTL amplifier operating under the same conditions is 1.56W. Since the amplifier outputs are both biased about VDD/2, there is no net DC voltage across the load, eliminating the DC blocking capacitors required by single-ended, single-supply amplifiers. Headphone Amplifier The LM49120 headphone amplifier features two different operating modes, output capacitor-less (OCL) and single-ended (SE) capacitor coupled mode. The OCL architecture eliminates the bulky, expensive output coupling capacitors required by traditional headphone amplifiers. In OCL mode, the LM49120 headphone section uses three amplifiers. Two amplifiers drive the headphones, while the third (VOC) is set to the internally generated bias voltage (typically VDD/2). The third amplifier is connected to the return terminal of the headphone jack (Figure 1). In this configuration, the signal side of the headphone is biased to VDD/2, the return is biased to VDD/2, thus there is no net DC voltage across the headphone, eliminating the need for an output coupling capacitor. Removing the output coupling capacitors from the headphone signal path reduces component count, reducing system cost and board space consumption, as well as improving low frequency performance. In OCL mode, the headphone return sleeve is biased to VDD/2. When driving headphones, the voltage on the return sleeve is not an issue. However, if the headphone output is used as a line out, the VDD/2 can conflict with the GND potential that the line-in would expect on the return sleeve. When the return of the headphone jack is connected to GND the VOC amplifier of the LM49120 detects an output short circuit condition and is disabled, preventing damage to the LM49120, and allowing the headphone return to be biased at GND. Single-Ended, Capacitor Coupled Mode In single-ended mode, the VOC amplifier is disabled, and the headphone outputs are coupled to the jack through series capacitors, allowing the headphone return to be connected to GND (Figure 2). In SE mode, the LM49120 requires output coupling capacitors to block the DC component of the amplifier output, preventing DC current from flowing to the load. The output capacitor and speaker impedance form a high pass filter with a -3dB roll-off determined by: f–3dB = 1 / 2πRLCO (Hz) (1) Where RL is the headphone impedance, and C O is the value of the output coupling capacitor. Choose CO such that f-3dB is well below the lowest frequency of interest. Setting f-3dB too high results in poor low frequency performance. Select capacitor dielectric types with low ESR to minimize signal loss due to capacitor series resistance and maximize power transfer to the load. Headphone Amplifier BTL Mode The LM49120 headphone amplifiers feature a BTL mode where the two headphone outputs, LOUT and ROUT are configured to drive a mono speaker differentially. In BTL mode, the amplifier accepts audio signals from either the differential MONO inputs, or the single-ended stereo inputs, and converts them to a mono BTL output. However, if the stereo inputs are 180° out of phase, no audio will be present at the amplifier outputs. Bit B3 (HP/BTL) in the Shutdown Control Register determines the headphone output mode. Set HP/ BTL = 0 for stereo headphone mode, set HP/BTL = 1 for BTL mode. Input Mixer/Multiplexer The LM49120 includes a comprehensive mixer multiplexer controlled through the I2C interface. The mixer/multiplexer allows any input combination to appear on any output of the LM49120. Multiple input paths can be selected simultaneously. Under these conditions, the selected inputs are mixed together and output on the selected channel. Tables 4 and 5 show how the input signals are mixed together for each possible input selection. Audio Amplifier Gain Setting Each channel of the LM49120 has two separate gain stages. Each input stage features a 32-step volume control with a range of -46dB to +18dB (Table 6). The loudspeaker output stage has two additional gain settings: 0dB and +6dB (Table 8) when the differential MONO input is selected, and +6dB and +12dB when the single-ended stereo inputs are selected. The headphone gain is not affected by the input mode. Each headphone output stage has 8 gain settings (Table 7). This allows for a maximum separation of 22dB between the speaker and headphone outputs when both are active. Calculate the total gain of the given signal path as follows: AVOL + AVOS = AVTOTAL (dB) (2) Where AVOL is the volume control level, AVOS is the output stage gain setting, and AVTOTAL is the total gain for the signal path. 23 www.national.com LM49120 POWER DISSIPATION Power dissipation is a major concern when designing a successful single-ended or bridged amplifier. A direct consequence of the increased power delivered to the load by a bridge amplifier is higher internal power dissipation. The LM49120 has a pair of bridged-tied amplifiers driving a handsfree speaker, MONO. The maximum internal power dissipation operating in the bridge mode is twice that of a single-ended amplifier. From Equation (2), assuming a 5V power supply and an 8Ω load, the maximum MONO power dissipation is 633mW. PDMAX-SPKROUT = 4(VDD)2 / (2π2 RL): Bridge Mode (3) The LM49120 also has a pair of single-ended amplifiers driving stereo headphones, ROUT and LOUT. The maximum internal power dissipation for ROUT and LOUT is given by equation (3) and (4). From Equations (3) and (4), assuming a 5V power supply and a 32Ω load, the maximum power dissipation for LOUT and ROUT is 40mW, or 80mW total. PDMAX-LOUT = (VDD)2 / (2π2 RL): Single-ended Mode PDMAX-ROUT = (VDD)2 / (2π2 RL): Single-ended Mode (4) maximum junction temperature by reducing the power supply voltage or increasing the load resistance. Further allowance should be made for increased ambient temperatures. The above examples assume that a device is a surface mount part operating around the maximum power dissipation point. Since internal power dissipation is a function of output power, higher ambient temperatures are allowed as output power or duty cycle decreases. If the result of Equation (5) is greater than that of Equation (6), then decrease the supply voltage, increase the load impedance, or reduce the ambient temperature. If these measures are insufficient, a heat sink can be added to reduce θJA. The heat sink can be created using additional copper area around the package, with connections to the ground pin(s), supply pin and amplifier output pins. External, solder attached SMT heatsinks such as the Thermalloy 7106D can also improve power dissipation. When adding a heat sink, the θJA is the sum of θJC, θCS, and θSA. (θJC is the junction-to-case thermal impedance, θCS is the case-to-sink thermal impedance, and θSA is the sink-to-ambient thermal impedance). Refer to the Typical Performance Characteristics curves for power dissipation information at lower output power levels. PROPER SELECTION OF EXTERNAL COMPONENTS Power Supply Bypassing/Filtering Proper power supply bypassing is critical for low noise performance and high PSRR. Place the supply bypass capacitors as close to the device as possible. Place a 1μF ceramic capacitor from VDD to GND. Additional bulk capacitance may be added as required. Input Capacitor Selection Input capacitors may be required for some applications, or when the audio source is single-ended. Input capacitors block the DC component of the audio signal, eliminating any conflict between the DC component of the audio source and the bias voltage of the LM49120. The input capacitors create a highpass filter with the input resistors RIN. The -3dB point of the high pass filter is found using Equation (3) below. f = 1 / (2πRINCIN) (Hz) (10) (5) The maximum internal power dissipation of the LM49120 occurs when all three amplifiers pairs are simultaneously on; and is given by Equation (5). PDMAX-TOTAL = PDMAX-SPKROUT + PDMAX-LOUT + PDMAX-ROUT (6) The maximum power dissipation point given by Equation (5) must not exceed the power dissipation given by Equation (6): PDMAX = (TJMAX - TA) / θJA (7) The LM49120's TJMAX = 150°C. In the SQ package, the LM49120's θJA is 46°C/W. At any given ambient temperature TA, use Equation (6) to find the maximum internal power dissipation supported by the IC packaging. Rearranging Equation (6) and substituting PDMAX-TOTAL for PDMAX' results in Equation (7). This equation gives the maximum ambient temperature that still allows maximum stereo power dissipation without violating the LM49120's maximum junction temperature. TA = TJMAX - PDMAX-TOTAL θJA (8) For a typical application with a 5V power supply and an 8Ω load, the maximum ambient temperature that allows maximum mono power dissipation without exceeding the maximum junction temperature is approximately 121°C for the SQ package. TJMAX = PDMAX-TOTAL θJA + TA (9) Where the value of R IN is given in the Electrical Characteristics Table. High pass filtering the audio signal helps protect the speakers. When the LM49120 is using a single-ended source, power supply noise on the ground is seen as an input signal. Setting the high-pass filter point above the power supply noise frequencies, 217Hz in a GSM phone, for example, filters out the noise such that it is not amplified and heard on the output. Capacitors with a tolerance of 10% or better are recommended for impedance matching and improved CMRR and PSRR. Bias Capacitor Selection The LM49120 internally generates a VDD/2 common-mode bias voltage. The BIAS capacitor CBIAS, improves PSRR and THD+N by reducing noise at the BIAS node. Use a 2.2µF ceramic placed as close to the device as possible. Equation (8) gives the maximum junction temperature TJMAX. If the result violates the LM49120's 150°C, reduce the www.national.com 24 LM49120 PCB LAYOUT GUIDELINES Minimize trace impedance of the power, ground and all output traces for optimum performance. Voltage loss due to trace resistance between the LM49120 and the load results in decreased output power and efficiency. Trace resistance between the power supply and ground has the same effect as a poorly regulated supply, increased ripple and reduced peak output power. Use wide traces for power supply inputs and amplifier outputs to minimize losses due to trace resistance, as well as route heat away from the device. Proper grounding improves audio performance, minimizes crosstalk between channels and prevents digital noise from interfering with the audio signal. Use of power and ground planes is recommended. Place all digital components and route digital signal traces as far as possible from analog components and traces. Do not run digital and analog traces in parallel on the same PCB layer. If digital and analog signal lines must cross either over or under each other, ensure that they cross in a perpendicular fashion. Revision History Rev 1.0 1.01 Date 06/26/08 07/15/08 Initial release. Edited the Ordering Information table. Description 25 www.national.com LM49120 Physical Dimensions inches (millimeters) unless otherwise noted 16 – Bump micro SMD Package Order Number LM49120TL NS Package Number TLA00016 X1 = 2000μm±30m, X2 = 2000μm±30μm, X3 = 600μm www.national.com 26 LM49120 Notes 27 www.national.com Audio Sub-System with Mono Class AB Loudspeaker Amplifier and Stereo OCL/SE Headphone Amplifier Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Amplifiers Audio Clock Conditioners Data Converters Displays Ethernet Interface LVDS Power Management Switching Regulators LDOs LED Lighting PowerWise Serial Digital Interface (SDI) Temperature Sensors Wireless (PLL/VCO) www.national.com/amplifiers www.national.com/audio www.national.com/timing www.national.com/adc www.national.com/displays www.national.com/ethernet www.national.com/interface www.national.com/lvds www.national.com/power www.national.com/switchers www.national.com/ldo www.national.com/led www.national.com/powerwise www.national.com/sdi www.national.com/tempsensors www.national.com/wireless WEBENCH Analog University App Notes Distributors Green Compliance Packaging Design Support www.national.com/webench www.national.com/AU www.national.com/appnotes www.national.com/contacts www.national.com/quality/green www.national.com/packaging www.national.com/quality www.national.com/refdesigns www.national.com/feedback Quality and Reliability Reference Designs Feedback THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. NATIONAL MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE ACCURACY OR COMPLETENESS OF THE CONTENTS OF THIS PUBLICATION AND RESERVES THE RIGHT TO MAKE CHANGES TO SPECIFICATIONS AND PRODUCT DESCRIPTIONS AT ANY TIME WITHOUT NOTICE. NO LICENSE, WHETHER EXPRESS, IMPLIED, ARISING BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. TESTING AND OTHER QUALITY CONTROLS ARE USED TO THE EXTENT NATIONAL DEEMS NECESSARY TO SUPPORT NATIONAL’S PRODUCT WARRANTY. EXCEPT WHERE MANDATED BY GOVERNMENT REQUIREMENTS, TESTING OF ALL PARAMETERS OF EACH PRODUCT IS NOT NECESSARILY PERFORMED. NATIONAL ASSUMES NO LIABILITY FOR APPLICATIONS ASSISTANCE OR BUYER PRODUCT DESIGN. BUYERS ARE RESPONSIBLE FOR THEIR PRODUCTS AND APPLICATIONS USING NATIONAL COMPONENTS. PRIOR TO USING OR DISTRIBUTING ANY PRODUCTS THAT INCLUDE NATIONAL COMPONENTS, BUYERS SHOULD PROVIDE ADEQUATE DESIGN, TESTING AND OPERATING SAFEGUARDS. EXCEPT AS PROVIDED IN NATIONAL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NATIONAL ASSUMES NO LIABILITY WHATSOEVER, AND NATIONAL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO THE SALE AND/OR USE OF NATIONAL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE CHIEF EXECUTIVE OFFICER AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness. National Semiconductor and the National Semiconductor logo are registered trademarks of National Semiconductor Corporation. All other brand or product names may be trademarks or registered trademarks of their respective holders. LM49120 Copyright© 2008 National Semiconductor Corporation For the most current product information visit us at www.national.com National Semiconductor Americas Technical Support Center Email: support@nsc.com Tel: 1-800-272-9959 www.national.com National Semiconductor Europe Technical Support Center Email: europe.support@nsc.com German Tel: +49 (0) 180 5010 771 English Tel: +44 (0) 870 850 4288 National Semiconductor Asia Pacific Technical Support Center Email: ap.support@nsc.com National Semiconductor Japan Technical Support Center Email: jpn.feedback@nsc.com