LM4930

LM4930 Audio Subsystem with Stereo Headphone & Mono Speaker Amplifiers September 2004 LM4930 Audio Subsystem with Stereo Headphone & Mono Speaker Amplifiers General Description The LM4930 is an integrated audio subsystem that supports voice and digital audio functions. The LM4930 includes a high quality I2S input stereo DAC, a voice band codec, a stereo headphone amplifier and a high-power mono speaker amplifier. It is primarily designed for demanding applications in mobile phones and other portable devices. The LM4930 features an I2S serial interface for full range audio, a 16-bit PCM bi-directional serial interface for the voice band codec and an two-wire interface for control. The full range music path features an SNR of 86dB with a 16-bit 48kHz input. The stereo DAC can also be used while the voice codec is in use. The headphone amplifier delivers 25mWRMS to a 32Ω single-ended stereo load with less than 0.5% distortion (THD+N) when AVDD = 3V. The mono speaker amplifier delivers up to 330mW into an 8Ω load with less than 1% distortion when AVDD = 3V. The LM4930 employs advanced techniques to reduce power consumption, to reduce controller overhead and to eliminate click and pop. Boomer audio power amplifiers were designed specifically to provide high quality output power with a minimal amount of external components. It is, therefore, ideally suited for mobile phone and other low voltage applications where minimal power consumption is a primary requirement. Key Specifications j PLS j PLS OUT at AVDD = 5.0V, 8Ω 1W (typ) 330mW (typ) 25mW (typ) 2.6V to 4.5V 2.6V to 5.5V 2µA (typ) 50dB (typ) at AVDD = 3.0V, 8Ω at AVDD = 3.0V, 32Ω 1% THD+N OUT 1% THD+N j PH/P OUT 0.5% THD+N j Supply voltage range DVDD (Note 8) AVDD (Note 8) j Total shutdown current j PSRR at 217Hz, AVDD = 3V Features 16-bit resolution 48kHz stereo DAC 16-bit resolution 8kHz voice codec I2S digital audio data serial interface Two-wire serial control interface PCM voice audio data serial interface 25mW/channel stereo headphone amplifier 330mW mono 8Ω amplifier (at AVDD = 3.0V) 32-step volume control for audio output amplifiers No snubber networks or bootstrap capacitors are required by the headphone or hands-free amplifiers n Digital sidetone generation with adjustable attenuation n Gain controllable headphone amp, mono BTL amp, mic preamp n Available in the 36–bump micro SMD and 44–lead LLP packages n n n n n n n n n Applications n Mobile Phones n Mobile/low power audio appliances n PDAs Boomer ® is a registered trademark of National Semiconductor Corporation. © 2004 National Semiconductor Corporation DS200720 www.national.com LM4930 Typical Application 20072003 FIGURE 1. Typical I2S + Voice codec application circuit for mobile phones www.national.com 2 LM4930 Connection Diagrams 36-Bump micro SMD micro SMD Marking 20072056 Top View X - Date Code T - Die Traceability G - Boomer Family B6 - LM4930ITL 20072002 Top View Order Number LM4930ITL See NS Package Number MKT - TLA36KRA 44 – Lead LLP 44 – Lead LLP Marking 20072087 Top View N - National Logo U - Wafer Fab Code Z - Assembly Plant Code XY - Two Digit Date Code TT - Die Run Code L4930LQ - LM4930LQ 20072086 Top View Order Number LM4930LQ See NS Package Number MKT - LQA44A 3 www.national.com LM4930 Pin Descriptions A1 A2 A3 A4 A5 A6 B1 B2 B3 B4 B5 B6 C1 C2 C3 C4 C5 C6 D1 D2 D3 D4 D5 D6 E1 E2 E3 MIC_P MIC_N AVDD_MIC DAC_REF SDA SCL AGND_MIC MIC_BIAS MIC_REF ADDR PCM_SDI PCM_CLK AVDD_HP NC BYPASS PCM_SYNC I2S_DATA DGND_D HP_L HP_R HPSENSE_IN PCM_SDO I2S_CLK DVDD_D AGND_HP LSHPSENSE_OUT Microphone positive differential input Microphone negative differential input Analog Vdd for microphone preamp D/A converter reference voltage Two-wire control interface serial data pin Two-wire control interface serial clock pin Analog ground for microphone preamp Microphone bias supply output (2V) Internal fixed-reference bypass capacitor decoupling pin Control bus address select pin PCM serial data in PCM Serial clock pin Analog Vdd for headphone amplifier No Connect Half-supply bypass capacitor decoupling pin PCM Frame sync pin I2S serial data input Digital ground Headphone amplifier connection (Left) Headphone amplifier connection (Right) Connection for sense pin of headphone jack PCM serial data out I2S serial bit clock Digital Vdd Analog ground for headphone amplifier Loudspeaker amplifier BTL negative out (-) Logic output pin to indicate headphone connection status. Outputs logic high when HPSENSE_IN is high and outputs logic low when HPSENSE_IN is low. See Figure 5 for suggested application circuit LM4930 mode status indicator pin I2S word select Negative feedback source for external crystal MCLK Analog ground for loudspeaker amplifier Loudspeaker amplifier BTL positive out (+) Analog VDD for loudspeaker amplifier Digital ground Digital VDD 12.288MHz or 24.576MHz Master Clock from crystal (via XTAL OUT) or external source E4 E5 E6 F1 F2 F3 F4 F5 F6 IRQ I2S_WS XTAL_OUT AGND_LS LS+ AVDD_LS DGND_X DVDD_X MCLK/XTAL_IN www.national.com 4 LM4930 System Control Registers The LM4930 is controlled with a two-wire serial interface. This interface is used to configure the operating mode, digital interfaces, and delta-sigma modulators. The LM4930 is controlled by writing information into a series of write-only registers, each with its own unique 7 bit address. The following registers are programmable: BASIC CONFIG REGISTER This register is used to configure the I2S and PCM interfaces as well as the 48kHz DAC module. The 7 bit address for the BASICCONFIG register is XX10000. (X = 0 if ADDR is set to logic 0) (X = 1 if ADDR is set to logic 1) BASIC CONFIGURATION (XX1000). BIT RESET Address 3:0 15 0 Register MODE 14 0 13 0 (Set = logic 1, Clear = logic 0) 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Description The LM4930 can be placed in one of several modes that dictate the basic operation. When a new mode is selected the LM4930 will change operation silently and will re-configure the power management profile automatically. The modes are described as follows: (Note 14) Mode 0000 0001 0010 0011 0100 0101 0110 0111 Mono Speaker Amplifier Source None None Voice None Voice Audio (L+R) None Audio (L+R) Headphone Left Source None None None Voice Voice None Audio (Left) Audio (Left) Headphone Right Comment Source None None None Voice Voice None Audio (Right) Audio (Right) Powerdown mode Standby mode Mono speaker mode Headphone call mode Conference call mode L+R mixed to mono speaker Headphone stereo audio L+R mixed to mono speaker + stereo headphone audio Mixed Mode Mixed mode Mixed Mode 1000 1001 1010 4 5 6 7 8:9 10 11 12 13 14 15 SOFT_RESET PCM_LONG PCM_COMPANDED PCM_LAW PCM_SYNC_MODE PCM_ALWAYS_ON I2S_M/S I2S_RES RSVD RSVD RSVD Audio (Left) Voice + Audio (Left) Voice Voice Voice Audio (Left) Voice Voice Audio (Left) Resets the LM4930, excluding the control registers If set the PCM interface uses a long frame sync. (Note 12) If set the 8 MSBs are presumed to be companded data and the 8 LSBs are ignored. (Note 12) If set, the companded G711 data is set to be A-law, else µ-law is assumed (Note 12) Sets 1 (00h), 2 (01h) or 4(10h) 16 bit frames per sync. The PCM_SDO pin is tri-stated during the latter frames. (Note 12) This bit should be set if another codec is using the PCM bus. When set, the LM4930 will drive the clock and sync signals in all modes except Powerdown (Note 12) I2S master or slave select. If set then I2S = master. Cleared = slave I2S resolution select. If set then 32 bits per frame. If cleared then 16 bits per frame RESERVED (Note 13) RESERVED (Note 13) RESERVED (Note 13) 5 www.national.com LM4930 System Control Registers (Continued) VOICE/TEST CONFIG REGISTERS This register configures the voiceband codec, sidetone attenuation, and selected control functions. The 7 bit address for the VOICE TESTCONFIG register is XX10001. (X = 0 if ADDR is set to logic 0) (X = 1 if ADDR is set to logic 1) VOICETESTCONFIG (XX10001). BIT RESET Address 0 4:1 15 0 Register CLASS 14 0 0 (Set = logic 1, Clear = logic 0) 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 13 Description If set, configures the chip for use with an external class D or linear amplifier and turns the BTL speaker output into a buffer. (Note 12) 4:1 0000 0001 0010 0011 0100 0101 0110 0111 Sidetone Attenuation Mute -30dB -27dB -24dB -21dB -18dB -15dB -12dB 4:1 1000 1001 1010 1011 1100 1101 1110 1111 Sidetone Attenuation -9dB -6dB -3dB 0dB Mute Mute Mute Mute SIDESTONE_ATTEN Programs the attenuation of the digital sidetone. Attenuation is set as follows: 5 AUTOSIDE This feature is included for use with the mono speaker in hands-free applications where sidetones may not be desirable. If set, the sidetone is always muted in modes when voice is played on the mono speaker (0010, 0100, 1001, and 1010), otherwise the sidetone is present at whatever level is set in the attenuation conrol register If set, allows for the use of a 24.576MHz crystal. Default setting is for 12.288MHz crystal. (Note 12) Disables the zero crossing detect in the stereo DAC to guarantee immediate mode changes rather than waiting for a zero cross. (Note 11) RESERVED (Note 13) Set to accomodate different bypass capacitor values to give correct turn-off delay and click/pop performance. Value is set as follows: (Note 12) 10:11 00 01 10 11 Delay 25ms 50ms 85ms RESERVED Bypass Capacitor Size 0.1µF 0.39µF 1µF RESERVED 6 7 8:9 10:11 CLOCK_DIV ZXD_DISABLE RSVD CAP_SIZE 12 13 14 15 ZXDS_SLOW MUTE_LS MUTE_HP MUTE_MIC If set, this forces the stereo DAC outputs to wait for a zero crossing before powering down If set, mutes the loudspeaker amplifier in any mode where it is not already muted If set, mutes the headphone amplifier in any mode where it is not already muted If set, mutes the microphone preamp www.national.com 6 LM4930 System Control Registers (Continued) GAIN CONFIG REGISTERS This register is used to control the gain of the headphone amplifier, the loudspeaker amplifier, and the microphone preamplifier. The 7 bit address for the GAINCONFIG register is XX10010. (X = 0 if ADDR is set to logic 0) (X = 1 if ADDR is set to logic 1) GAINCONFIG (XX10010). BIT RESET Address 4:0 15 0 Register LOUDSPKR_GAIN 14 0 (Set = logic 1, Clear = logic 0) 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Description Programs the gain of the loudspeaker amplifier. Gain is set as follows: 4:0 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 Loudspeaker Gain -34.5dB -33dB -31.5dB -30dB -28.5dB -27dB -25.5dB -24dB -22.5dB -21dB -19.5dB -18dB -16.5dB -15dB -13.5dB -12dB Headphone Gain -46dB -45dB -43.5dB -42db -40.5dB -39dB -37.5dB -36dB -34.5dB -33dB -31.5dB -30dB -28.5dB -27dB -25.5dB -24dB 4:0 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 9:5 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 Loudspeaker Gain -10.5dB -9dB -7.5dB -6dB -4.5dB -3dB -1.5dB 0dB 1.5dB 3dB 4.5dB 6dB 7.5dB 9dB 10.5dB 12dB Headphone Gain -22.5dB -21dB -19.5dB -18dB -16.5dB -15dB -13.5dB -12dB -10.5dB -9dB -7.5dB -6dB -4.5dB -3dB -1.5dB 0dB 9:5 HP_GAIN Programs the gain of the headphone amplifier. Gain is set as follows: 9:5 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 13:10 MIC_GAIN Programs the gain of the microphone amplifier. Gain is set as follows: 7 www.national.com LM4930 System Control Registers 13:10 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 15:14 RSVD (Continued) GAIN CONFIG REGISTERS (Continued) Mic Preamp Gain 17dB 19dB 21dB 23dB 25dB 27dB 29dB 31dB 33dB 35dB 37dB 39dB 41dB 43dB 45dB 47dB RESERVED (Note 13) www.national.com 8 LM4930 Timing Diagrams 20072009 FIGURE 2. Two-wire control Interface Timing Diagram 20072008 FIGURE 3. PCM Receive Timing Diagram 20072007 FIGURE 4. I2S Transmit Timing Diagram 9 www.national.com LM4930 Absolute Maximum Ratings (Notes 1, 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Analog Supply Voltage Digital Storage Supply Voltage Storage temperature Power Dissipation (Note 3) ESD Susceptibility Human Body Model (Note 4) Machine Model (Note 5) Junction temperature 2000V 200V 150˚C 6.0V 6.0V -65˚C to +150˚C Internally Limited Thermal Resistance θJA - TLA36KRA θJA - LQA44A (Note 17) 105˚C/W 27˚C/W Operating Ratings (Note 3) Temperature Range TMIN ≤ TA ≤ TMAX Supply Voltage DVDD (Note 8) AVDD (Note 8) 2.6V - 4.5V 2.6V - 5.5V −30˚C ≤ TA ≤ +85˚C Electrical Characteristics DVDD = 3.3V, AVDD = 5V, RLHP = 32Ω, RLHF = 8Ω (Notes 1, 2, 8) The following specifications apply for the circuit shown in Figure 1, unless otherwise specified. Limits apply for TA= 25˚C. Symbol Parameter Conditions LM4930 Typical (Note 6) Limits (Notes 7, 15) Units (Limits) fMCLK = 12.288MHz Output Mode = "0010" Output Mode = "0011" Output Mode = "0100" DIDD Digital Power Supply Current Output Mode = "0101" Output Mode = "0110" Output Mode = "0111" Output Mode = "1000" Output Mode = "1001" Output Mode = "1010" fMCLK = 12.288MHz; No Load Output Mode = "0010" Output Mode = "0011" Output Mode = "0100" AIDD Analog Power Supply Quiescent Current Output Mode = "0101" Output Mode = "0110" Output Mode = "0111" Output Mode = "1000" Output Mode = "1001" Output Mode = "1010" DISD AISD DIST AIST VFS_LS VFS_HP Digital Powerdown Current Analog Powerdown Current Digital Standby Current Analog Standby Current Full-Scale Output Voltage (Mono speaker amplifier) Full-Scale Output Voltage (Headphone amplifier) fMCLK = 12.288MHz Output Mode = "0000" Powerdown Mode fMCLK = 12.288MHz Output Mode = "0000" Powerdown Mode fMCLK = 12.288MHz Output Mode = "0001" Standby Mode fMCLK = 12.288MHz Output Mode = "0001" Standby Mode CLASS = 0; 0dB gain setting; 8Ω BTL load (Note 10) 0dB gain setting; 32Ω Stereo Load (Note 10) 7.0 6.3 8.0 8.2 7.4 8.7 9.5 1 14 7 mA (max) µA (max) 2 4.4 4.9 8 mA (max) 1 1.4 230 2.5 2.5 2 2 1000 µA (max) mA (max) µA (max) VP-P VP-P www.national.com 10 LM4930 Electrical Characteristics DVDD = 3.3V, AVDD = 5V, RLHP = 32Ω, RLHF = 8Ω (Notes 1, 2, 8) (Continued) The following specifications apply for the circuit shown in Figure 1, unless otherwise specified. Limits apply for TA= 25˚C. Symbol Parameter Conditions LM4930 Typical (Note 6) Limits (Notes 7, 15) Units (Limits) VMIC_BIAS Mic Bias Voltage THD+N Headphone Amplifier Total Harmonic Motion Distortion + Noise Headphone Amplifier Output Power Mono Speaker Amplifier Output Power Power Supply Rejection Ratio fIN = 1 kHz, POUT = 7.5mW; 32Ω Stereo Load THD+N = 0.5%, fOUT = 1kHz THD+N = 1%, fOUT = 1kHz CBYPASS = 1.0µF CDAC_REF = 1.0µF VRIPPLE = 200mVP-P @ 217Hz, MIC_P, MIC_N terminated with 10Ω to ground Signal = Vo at f = 1kHz @1% THD+N, 32Ω Stereo Load; Noise = digital zero, A-weighted, 0dB gain setting Signal = Vo at f = 1kHz @1% THD+N, 32Ω Stereo Load; Noise = digital zero, A-weighted; 0dB gain setting 2.0 0.07 V % POHP POLS PSRR 27 1 55 20 mW (min) W 45 dB (min) SNR (Voice) SNR (Music) DR (Voice) DR (Music) SNRADC Signal-to-Noise Ratio (Voice DAC Path) Signal-to-Noise Ratio (Music Audio Path) 72 dB 86 dB Dynamic Range (Voice DAC Path) Signal = Vo at f = 1kHz @1% THD+N, 32Ω Stereo Load; Noise for -60dBFS digital input; A-weighted; 0dB gain setting Dynamic Range (Music Audio Path) Signal-to-Noise Ratio (Voice ADC Path) Signal = Vo at f=1kHz @1% THD+N, 32Ω Stereo Load; Noise for -60dBFS digital input; A-weighted, 0dB gain setting Reference signal = 0dBFS MIC_P, MIC_N terminated with 10Ω to ground; A-weighted; 47dB MIC preamp gain setting Reference signal = 0dBFS Noise for -60dBFS digital input; A-weighted; 47dB MIC preamp gain setting fS = 48kHz, fIN = 1kHz sinewave at -3dBFS 17dB MIC Preamp gain setting 300Hz - 3.3kHz through head-phone output. 300Hz - 3.3kHz through head-phone output. -3dB Point Above 4kHz Upper -3dB Point 72 dB 86 dB 75 dB DRADC Dynamic Range (Voice ADC Path) 75 dB XTALK VMIC-IN RVDAC RVADC PBVDAC Stereo Channel-to-Channel Crosstalk Maximum Differential MIC Input Voltage Voice DAC Ripple Voice ADC Ripple Voice DAC Passband 75 570 +/-0.15 +/-0.25 3.46 72 3.47 +/-0.2 +/-0.3 dB mVP-P dB (max) dB (max) kHz dB kHz SBAVDAC Voice DAC Stopband Attenuation UPBVADC Voice ADC Upper Passband Cutoff Frequency. 11 www.national.com LM4930 Electrical Characteristics DVDD = 3.3V, AVDD = 5V, RLHP = 32Ω, RLHF = 8Ω (Notes 1, 2, 8) (Continued) The following specifications apply for the circuit shown in Figure 1, unless otherwise specified. Limits apply for TA= 25˚C. Symbol Parameter Conditions LM4930 Typical (Note 6) Limits (Notes 7, 15) Units (Limits) LPBVADC Voice ADC Lower Passband Cutoff Frequency. SBAVADC Voice ADC Stopband Attenuation SBANOTCH Voice ADC Notch Attenuation RDAC PBDAC SBADAC DRDAC Audio DAC Ripple Audio DAC Passband Width Audio DAC Stopband Attenuation Audio DAC Dynamic Range Digital Filter Section Audio DAC SNR Digital Filter Section Stereo Channel-to-Channel Gain Mismatch Digital Input: Logic Low Voltage Level Digital Input: Logic High Voltage Level Volume Control Range (Headphone amplifiers) Volume Control Range (Mono speaker amplifier) Volume Control Step Size (Output amplifiers) Volume Control Range (Microphone Preamp) Volume Control Step Size (Microphone Preamp) Side Tone Attenuation Range Side Tone Attenuation Step Size fMCLK MCLK frequency MCLK Duty Cycle fCONV fCLKSCL tRISESCL tFALLSCL tSDAH tSDAS Sampling Clock Frequency (Note 9) SCL_CLK Frequency SCL_CLK, SCL_DATA Rise Time SCL_CLK, SDA_DATA Fall Time SDA_DATA Hold Time SDA_DATA Setup Time Lower -3dB Point Above 4kHz Centered on 55Hz, figure gives worst case attenuation for 50Hz & 60Hz. 20Hz - 20kHz through head-phone output. -3dB point Above 24kHz Signal = VO at f = 1kHz @ 1% THD+N; f = 1kHz; Noise for -60dBFS digital input; 0dB gain; A-weighted Signal = VO at f = 1kHz @ 1% THD+N; f = 1kHz; Noise for -60dBFS digital input; 0dB gain; A-weighted 0.230 65 58 +/-0.1 22.7 76 97 +/-0.2 kHz dB dB dB (max) kHz dB dB SNRDAC 97 dB ∆ACH-CH VIL VIH 0.3 0.4 1.4 Maximum Attenuation Minimum Attenuation Minimum Gain Maximum Gain -46.5 0 -34.5 12 1.5 Minimum Gain Maximum Gain 17 47 2 Maximum Attenuation Minimum Attenuation CLOCK_DIV = 0 CLOCK_DIV = 1 -30 0 3 12.288 24.576 50 48 400 300 300 500 500 40 60 dB V V dB dB dB dB dB dB dB dB dB dB dB MHz MHz % (min) % (max) kHz kHz ns ns ns ns www.national.com 12 LM4930 Electrical Characteristics DVDD = 3.3V, AVDD = 5V, RLHP = 32Ω, RLHF = 8Ω (Notes 1, 2, 8) (Continued) The following specifications apply for the circuit shown in Figure 1, unless otherwise specified. Limits apply for TA= 25˚C. Symbol Parameter Conditions LM4930 Typical (Note 6) Limits (Notes 7, 15) Units (Limits) fCLKPCM PCM_CLK Frequency PCM_SYNC_MODE = 00 PCM_SYNC_MODE = 01 PCM_SYNC_MODE = 10 128 256 512 50 40 60 kHz PCM_CLK Duty Cycle fCLKI2S I2S_CLK Frequency I2S_CLK Duty Cycle I2S_RES = 0 I2S_RES = 1 % (min) % (max) MHz 1.536 3.072 50 40 60 % (min) % (max) Electrical Characteristics DVDD = 3V, AVDD = 3V, RLHP = 32Ω, RLHF = 8Ω (Notes 1, 2, 3) The following specifications apply for the circuit shown in Figure 1, unless otherwise specified. Limits apply for TA= 25˚C. Symbol Parameter Conditions LM4930 Typical (Note 6) Limits (Notes 7, 15) Units (Limits) fMCLK = 12.288MHz Output Mode = "0010" Output Mode = "0011" Output Mode = "0100" DIDD Digital Power Supply Current Output Mode = "0101" Output Mode = "0110" Output Mode = "0111" Output Mode = "1000" Output Mode = "1001" Output Mode = "1010" fMCLK = 12.288MHz; No Load Output Mode = "0010" Output Mode = "0011" Output Mode = "0100" AIDD Analog Power Supply Quiescent Current Output Mode = "0101" Output Mode = "0110" Output Mode = "0111" Output Mode = "1000" Output Mode = "1001" Output Mode = "1010" DISD AISD DIST Digital Powerdown Current Analog Powerdown Current Digital Standby Current fMCLK = 12.288MHz Output Mode = "0000" Powerdown Mode fMCLK = 12.288MHz Output Mode = "0000" Powerdown Mode fMCLK = 12.288MHz Output Mode = "0001" Standby Mode 5.8 5.1 6.5 6.4 5.8 7.0 7.5 1 12 7 mA (max) µA (max) 1.6 3.8 4.2 7 mA (max) 0.6 1.1 1.5 1.7 µA (max) mA (max) 13 www.national.com LM4930 Electrical Characteristics DVDD = 3V, AVDD = 3V, RLHP = 32Ω, RLHF = 8Ω (Notes 1, 2, 3) (Continued) The following specifications apply for the circuit shown in Figure 1, unless otherwise specified. Limits apply for TA= 25˚C. Symbol Parameter Conditions LM4930 Typical (Note 6) Limits (Notes 7, 15) Units (Limits) AIST VFS_LS VFS_HP Analog Standby Current Full-Scale Output Voltage (Mono speaker amplifier) Full-Scale Output Voltage (Headphone amplifier) Headphone Amplifier Total Harmonic Distortion + Noise Headphone Amplifier Output Power Mono Speaker Amplifier Output Power Power Supply Rejection Ratio fMCLK = 12.288MHz Output Mode = "0001" Standby Mode CLASS = 0; 0dB gain setting; 8Ω BTL load (Note 10) 0dB gain setting; 32Ω Stereo Load (Note 10) fIN = 1kHz, POUT = 7.5mW THD+N = 0.5%, fOUT = 1kHz THD+N = 1%, fOUT = 1kHz CBYPASS = 1.0µF CDAC_REF = 1.0µF VRIPPLE = 200mVP-P @ 217Hz Signal = Vo at f = 1kHz @1% THD+N, 32Ω Stereo Load; Noise = digital zero, A-weighted; 0dB gain setting Signal = Vo at f = 1kHz @1% THD+N, 32Ω Stereo Load; Noise = digital zero, A-weighted; 0dB gain setting 100 2.5 2.5 2 0.07 25 330 50 300 µA (max) VP-P VP-P V % VMIC_BIAS Mic Bias Voltage THD+N POHP POLS PSRR 15 270 42 mW (min) mW (min) dB (min) SNR (Voice) SNR (Music) DR (Voice) DR (Music) SNRADC Signal-to-Noise Ratio (Voice DAC Path) Signal-to-Noise Ratio (Music Audio Path) 72 dB 86 dB Dynamic Range (Voice DAC Path) Signal = Vo at f = 1kHz @1% THD+N, 32Ω Stereo Load; Noise for -60dBFS digital input; A-weighted, 0dB gain setting Dynamic Range (Music Audio Path) Signal-to-Noise Ratio (Voice ADC Path) Signal = Vo at f=1kHz @1% THD+N, 32Ω Stereo Load; Noise for -60dBFS digital input; A-weighted, 0dB gain setting Reference signal = 0dBFS MIC_P, MIC_N terminated with 10Ω to ground; A-weighted; 47dB MIC preamp gain setting Reference signal = 0dBFS Noise for -60dBFS digital input; A-weighted; 47dB MIC preamp gain setting fS = 48kHz, fIN = 1kHz sinewave at -3dBFS 17dB MIC Preamp gain setting 300Hz - 3.3kHz through head-phone output. 300Hz - 3.3kHz through head-phone output. -3dB Point 72 dB 86 dB 75 dB DRADC Dynamic Range (Voice ADC Path) 75 dB XTALK VMIC-IN RVDAC RVADC PBVDAC Stereo Channel-to-Channel Crosstalk Maximum Differential MIC Input Voltage Voice DAC Ripple Voice ADC Ripple Voice DAC Passband 73 570 +/-0.15 +/-0.25 3.46 +/-0.2 +/-0.3 dB mVP-P dB (max) dB (max) kHz www.national.com 14 LM4930 Electrical Characteristics DVDD = 3V, AVDD = 3V, RLHP = 32Ω, RLHF = 8Ω (Notes 1, 2, 3) (Continued) The following specifications apply for the circuit shown in Figure 1, unless otherwise specified. Limits apply for TA= 25˚C. Symbol Parameter Conditions LM4930 Typical (Note 6) Limits (Notes 7, 15) Units (Limits) SBAVDAC Voice DAC Stopband Attenuation UPBVADC Voice ADC Upper Passband Cutoff Frequency. LPBVADC Voice ADC Lower Passband Cutoff Frequency. SBAVADC Voice ADC Stopband Attenuation SBANOTCH Voice ADC Notch Attenuation RDAC PBDAC SBADAC DRDAC Audio DAC Ripple Audio DAC Passband Width Audio DAC Stopband Attenuation Audio DAC Dynamic Range Digital Filter Section Audio DAC SNR Digital Filter Section Stereo Channel-to-Channel Gain Mismatch Digital Input: Logic Low Voltage Level Digital Input: Logic High Voltage Level Volume Control Range (Headphone amplifiers) Volume Control Range (Mono speaker amplifier) Volume Control Step Size (Output amplifiers) Volume Control Range (Microphone Preamp) Volume Control Step Size (Microphone Preamp) Side Tone Attenuation Range Side Tone Attenuation Step Size fMCLK MCLK frequency Above 4kHz Upper -3dB Point Lower -3dB Point Above 4kHz Centered on 55Hz, figure gives worst case attenuation for 50Hz & 60Hz. 20Hz - 20kHz through head-phone output. -3dB point Above 24kHz Signal = VO at f = 1kHz @ 1% THD+N; f = 1kHz; Noise for -60dBFS digital input; 0dB gain; A-weighted Signal = VO at f = 1kHz @ 1% THD+N; f = 1kHz; Noise for -60dBFS digital input; 0dB gain; A-weighted 72 3.47 0.230 65 58 +/-0.1 22.7 76 97 +/-0.2 dB kHz kHz dB dB dB (max) kHz dB dB SNRDAC 97 dB ∆ACH-CH VIL VIH 0.3 0.4 1.4 Maximum Attenuation Minimum Attenuation Minimum Gain Maximum Gain -46.5 0 -34.5 12 1.5 Minimum Gain Maximum Gain 17 47 2 Maximum Attenuation Minimum Attenuation CLOCK_DIV = 0 CLOCK_DIV = 1 -30 0 3 12.288 24.576 50 (Note 9) 48 400 300 300 500 40 60 dB V V dB dB dB dB dB dB dB dB dB dB MHz MHz % (min) % (max) kHz kHz ns ns ns MCLK Duty Cycle fCONV fCLKSCL tRISESCL tFALLSCL tSDAH Sampling Clock Frequency SCL_CLK Frequency SCL_CLK, SCL_DATA Rise Time SCL_CLK, SDA_DATA Fall Time SDA_DATA Hold Time 15 www.national.com LM4930 Electrical Characteristics DVDD = 3V, AVDD = 3V, RLHP = 32Ω, RLHF = 8Ω (Notes 1, 2, 3) (Continued) The following specifications apply for the circuit shown in Figure 1, unless otherwise specified. Limits apply for TA= 25˚C. Symbol Parameter Conditions LM4930 Typical (Note 6) Limits (Notes 7, 15) Units (Limits) tSDAS fCLKPCM SDA_DATA Setup Time PCM_CLK Frequency PCM_SYNC_MODE = 00 PCM_SYNC_MODE = 01 PCM_SYNC_MODE = 10 500 128 256 512 50 I2S_RES = 0 I2S_RES = 1 1.536 3.072 50 40 60 40 60 ns kHz kHz kHz % (min) % (max) MHz MHz % (min) % (max) PCM_CLK Duty Cycle fCLKI2S I2S_CLK Frequency I2S_CLK Duty Cycle Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional but do not guarantee specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which guarantee specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not guaranteed for parameters where no limit is given, however, the typical value is a good indication of device performance. Note 2: All voltages are measured with respect to the relevant GND pin unless otherwise specified. Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX ,θJA, and the ambient temperature, TA. The maximum allowable power dissipation is PDMAX = (TJMAX – TA) / θJA or the number given in Absolute Maximum Ratings, whichever is lower. For the LM4930, see power derating currents for more information. Note 4: Human body model: 100pF discharged through a 1.5kΩ resistor. Note 5: Machine model: 220pF - 240pF discharged through all pins. Note 6: Typicals are measured at 25˚C and represent the parametric norm. Note 7: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). Note 8: Best operation is achieved by maintaining 3.0V ≤ AVDD ≤ 5.0 and 3.0V ≤ DVDD ≤ 3.6V. AVDD must be equal to or greater than DVDD. for proper operation. Note 9: The sampling clock frequency is equal to the master clock frequency divided by 256. (fconv = fMCLK/256) Note 10: This value represents the 0dB output level of the given amplifier for the given analog supply voltage. Gain values given in the GAINCONFIG register are relative to these full-scale values for each output amplifier. Note 11: To ensure a successful transistion into Powerdown Mode, ZXD_DISABLE must be set whenever there is no audio input signal present. Note 12: It is recommended to alter this bit only while the part is in Powerdown Mode. Note 13: Reserved bits should be set to zero when programming the associated register. Note 14: With the exception of Standby Mode, rapid switching between modes should be avoided. Rapid switching between modes will not ensure that the desired mode will be activated. Note 15: Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. Note 16: 0dBm0 = -3dBFS for the PCM voice codec and 0dBm0 = -1dBFS for the I2S DAC, unless otherwise specified. Note 17: The given θA is for an LM4930 packaged in an LQA44A with the Exposed-DAP soldered to an exposed 2in2 area of 1oz printed circuit board copper with 16 thermal vias as described in National AN-1187. www.national.com 16 LM4930 Typical Performance Characteristics MIC PreAmp + ADC Frequency Response (MIC Gain = 17dB) (Note 16) MIC PreAmp + ADC Frequency Response Zoom (MIC Gain = 17dB) 20072015 20072016 MIC PreAmp + ADC Frequency Response (MIC Gain = 47dB) MIC PreAmp + ADC Frequency Response Zoom (MIC Gain = 47dB) 20072017 20072018 MIC PreAmp + ADC Frequency Response High Cutoff (MIC Gain = 17dB) MIC PreAmp + ADC Frequency Response High Cutoff (MIC Gain = 47dB) 20072019 20072020 17 www.national.com LM4930 Typical Performance Characteristics MIC PreAmp + ADC Frequency Response Low Cutoff (MIC Gain = 17dB) (Note 16) (Continued) MIC PreAmp + ADC Frequency Response Low Cutoff (MIC Gain = 47dB) 20072021 20072022 ADC THD+N vs MIC Input Voltage (MIC Gain = 17dB) ADC THD+N vs MIC Input Voltage (MIC Gain = 47dB) 20072023 20072024 MIC PreAmp + ADC PSRR vs Frequency Top Trace = 47dB MIC Gain, Bottom Trace = 17dB MIC Gain Headphone Sense In Hysteresis Loop (AVDD = 3V) 20072026 20072027 www.national.com 18 LM4930 Typical Performance Characteristics Headphone Sense In Hysteresis Loop (AVDD = 5V) (Note 16) (Continued) I2S DAC Frequency Response ( Handsfree Output) 20072028 20072029 I2S DAC Frequency Response Zoom (Handsfree Output) I2S DAC Frequency Response Zoom (Headphone Output) 20072030 20072031 I2S DAC Frequency Response Zoom (Headphone Output) THD+N vs I2S Input Voltage (Handsfree Output, 0dB Handsfree Gain) 20072032 20072038 19 www.national.com LM4930 Typical Performance Characteristics THD+N vs I2S Input Voltage (Headphone Output, 0dB Headphone Gain) (Note 16) (Continued) I2S DAC Crosstalk (Top Trace = Left to Right, Bottom Trace = Right to Left) 20072039 20072040 MIC Bias Dropout Voltage vs MIC Bias Current PCM DAC Frequency Response (Handsfree Output) 20072041 20072055 PCM DAC Frequency Response Zoom (Handsfree Output) PCM DAC Frequency Response (Headphone Output) 20072050 20072049 www.national.com 20 LM4930 Typical Performance Characteristics PCM DAC Frequency Response Zoom (Headphone Output) (Note 16) (Continued) THD+N vs PCM Input Voltage (Handsfree Output, 0dB Handsfree Gain) 20072051 20072052 THD+N vs PCM Input Voltage (Headphone Output, 0dB Headphone Gain) Crosstalk (AVDD = 5V and AVDD = 3V, Headphone Output) 20072053 200720F9 PSRR vs Frequency (AVDD = 3V, RL = 16Ω, Headphone Output) PSRR vs Frequency (AVDD = 3V, RL = 32Ω, Headphone Output) 200720G0 200720G1 21 www.national.com LM4930 Typical Performance Characteristics PSRR vs Frequency (AVDD = 3V, RL = 8Ω, Handsfree Output) (Note 16) (Continued) PSRR vs Frequency (AVDD = 5V, RL = 16Ω, Headphone Output) 200720G2 200720G3 PSRR vs Frequency (AVDD = 5V, RL = 32Ω, Headphone Output) PSRR vs Frequency (AVDD = 5V, RL = 8Ω, Handsfree Output) 200720G4 200720G5 (AVDD THD+N vs Frequency = 3V, RL = 8Ω, PO = 150mW, Handsfree Output) THD+N vs Frequency (AVDD = 5V and AVDD = 3V, RL = 16Ω, PO = 15mW, Headphone Output) 200720G7 20072001 www.national.com 22 LM4930 Typical Performance Characteristics THD+N vs Frequency (AVDD = 5V and AVDD = 3V, RL = 32Ω, PO = 7.5mW, Headphone Output) (Note 16) (Continued) THD+N vs Frequency (AVDD = 5V, RL = 8Ω, PO = 250mW, Handsfree Output) 200720G8 20072025 THD+N vs Output Power AVDD = 3V, RL = 16Ω, f = 1kHz, Headphone Output) THD+N vs Output Power (AVDD = 3V, RL = 8Ω, f = 1kHz, Handsfree Output) 200720H0 20072033 THD+N vs Output Power (AVDD = 5V and AVDD = 3V, RL = 32Ω, f = 1kHz, Headphone Output) THD+N vs Output Power (AVDD = 5V and AVDD = 3V, RL = 16Ω, f = 1kHz, Headphone Output) 200720H3 200720H4 23 www.national.com LM4930 Typical Performance Characteristics (Note 16) (Continued) THD+N vs Output Power (AVDD = 5V, RL = 8Ω, f = 1kHz, Handsfree Output) 20072034 Application Information REFERENCE DESIGN BOARD AND LAYOUT LM4930ITL Board Layout 20072014 FIGURE 5. LM4930ITL Demo Board Schematic www.national.com 24 LM4930 Application Information (Continued) 20072006 FIGURE 6. LM4930ITL Demo Board Composite View 20072005 FIGURE 7. LM4930ITL Demo Board Silkscreen 25 www.national.com LM4930 Application Information (Continued) 20072004 FIGURE 8. LM4930ITL Demo Board Top Layer 20072013 FIGURE 9. LM4930ITL Demo Board Bottom Layer www.national.com 26 LM4930 Application Information (Continued) 20072012 FIGURE 10. LM4930ITL Demo Board Inner Layer 1 20072011 FIGURE 11. LM4930ITL Demo Board Inner Layer 2 27 www.national.com LM4930 Application Information (Continued) 20072010 FIGURE 12. Pin Markings for LM4930ITL demo board BILL OF MATERIALS FOR LM4930 LM4930 Demo Board Bill Of Materials Comment 1k 2k 20k 100k 1M 22pF 0.01µF cer 0.1µF cer 1µF 220µF CRYSTAL Footprint 0805 0805 0805 0805 0805 1210 1210 1210 1210 7243 7243 Designators R6, R7 R2, R3 R1 R5 R4 C6, C7 C16, C17 C14, C15 C1, C2, C3, C4, C5, C10, C11, C12, C13 C8, C9 Y1 PHONE JACK STEREO SW STEREO HEADPHONE JACK (3.5MM) J8 www.national.com 28 LM4930 Application Information Pin 1 2 3 4 5 6 (Continued) Two-wire control Interface (J1) Function DVDD SCL DGND NC DGND SDA PCM Interface (P4, P3, P1, P2) Header P1 P2 P3 P4 I2S Interface (J2) Pin 1 2 3 4 5 6 7 8 9 10 MIC Jack Pin 1 2 3 Misc Jumpers and Headers DVDD/DGND (J10) Pin 1 2 Misc Jumpers and Headers AVDD/AGND (J9) Pin 1 2 Misc Jumpers and Headers MCLK/XTAL_IN (P5) Pin 29 Function PCM_SDI PCM_CLK PCM_SYNC PCM_SDO Function MCLK I2S-CLK I2S-DATA I2S-WS DGND DGND DGND DGND DGND DGND Function AGND MICMIC+ Function DGND AVDD Function AGND AVDD Function www.national.com LM4930 Application Information 1 2 (Continued) Misc Jumpers and Headers MCLK/XTAL_IN (P5) (Continued) DGND MCLK/XTAL_IN ADR SELECT (S1) Jumper IN = LOW Control interface responds to addresses 001000b (BASICCONFIG), 0010001b (VOICETESTCONFIG)), and 0010010b (GAINCONFIG) Jumper OUT = HIGH Control interface responds to addresses 111000b (BASICCONFIG), 1110001b (VOICETESTCONFIG)), and 1110010b (GAINCONFIG) HP Sense Out (J6) Pin 1 2 IRQ (J4) Pin 1 2 Onboard MCLK Select (S2) Jumper IN = Onboard MCLK Jumper OUT = External MCLK LM4930ITL DEMO BOARD OPERATION The LM4930ITL demo board is a complete evaluation platform, designed to give easy access to the control pins of the part and comprise all the necessary external passive components. Besides the separate analog (J9) and digital (J10) supply connectors, the board features seven other major input and control blocks: a two wire interface bus (J1) for the control lines, a PCM interface bus (P1-P4) for voiceband digital audio, an I2S interface bus (J2) for full-range digital audio, an analog mic jack input (J3) for connection to an external microphone, a BTL mono output (J7) for connection to an external speaker, a stereo headphone output (J8), and an external MCLK input (P5) for use in place of the crystal on the demoboard. Two-wire Interface Bus (J1) This is the main control bus for the LM4930. It is a two-wire interface with an SDA line (data) and SCL line (clock). Each transmission from the baseband controller to the LM4930 is given MSB first and must follow the timing intervals given in the Electrical Characteristics section of the datasheet to create the start and stop conditions for a proper transmission. The start condition is detected if SCL is high on the falling edge of SDA. The stop condition is detected if SCL is high on the rising edge of SDA. Repeated start signals are handled correctly. Data is then transmitted as shown in Figure 2. After the start condition has been achieved the chip address is sent, followed by a set write bit, wait for ack (SDA will be pulled low by LM4930), data bits 15-8, wait for ACK (SDA will be pulled low by LM4930), data bits 7-0, wait for ACK (SDA will be pulled low by LM4930)and finally the stop condition is given. www.national.com 30 Function AGND HPSense_Out Function DGND IRQ This same sequence follows for any control bus transmission to the LM4930. The chip address is hardwire selected by the ADR Select pin which may be jumpered high or low with its application at S1 on the demo board. The chip address is then given as a combination of the identifying bits for the LM4930 plus the 2-bit address of the desired control register (00b = BasicConfig, 01b = VoicetestConfig, 10b = GainConfig). Acceptable addresses are shown here in Table 1. Table 1. LM4930 Control Bus Addresses Address Bits ADR = 0 6 0 0 0 1 1 1 5 0 0 0 1 1 1 4 1 1 1 1 1 1 3 0 0 0 0 0 0 2 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 Register Address ADR = 1 Data is sampled only if the address is in range and the R/W bit is clear. Data for each register is given in the System Control Registers section of the datasheet. National Semiconductor also features a special control board for quick evaluation of the LM4930 demo board with your PC. This is a serial control interface board, complete with header com- LM4930 Application Information (Continued) patible with the interface header (J1) on the LM4930 board. This also features demonstration software to allow for complete control and evaluation of the various modes and functions of the LM4930 through the bus. Pullup resistors are required to achieve reliable operation. 750Ω pullup resistors on the SDA and SCL lines achieves best results when used with National’s parallel-to-serial interface board. Lower value pullup resistors will decrease the rise and fall times on the bus which will in turn decrease susceptibility to bus noise that may cause a false trigger. The cost comes at extra current use. Control bus reliability will thus depend largely on bus noise and may vary from design to design. Low noise is critical for reliable operation. PCM Bus Interface (P1, P2, P3, P4) PCM_SDO (P4), PCM_SYNC (P3), PCM_SDI (P1), and PCM_CLK (P2) form the PCM interface bus for simple communication with most baseband ICs with voiceband communications and follow the PCM-1900 communications standard. The PCM interface features frame lengths of 16, 32, or 64 bits, A-law and u-law companding, linear mode, short or long frame sync, an energy-saving power down mode, and master only operation. The PCM bus does not support a slave mode. It operates as a master only. Thus PCM_SYNC and PCM_CLK are solely generated by the LM4930. PCM_SYNC is the word sync line for the bus. It operates at a fixed frequency of 8kHz and may be set in the BASICCONFIG register (bit 5 PCM_LONG) for short or long frame sync. A short frame sync is 1 PCM_CLK cycle (PCM_LONG=0), a long frame sync is 2 PCM_CLK cycles long (PCM_LONG=1). A long sync pulse is also delayed one clock cycle relative to a short sync pulse. This is illustrated in Figure 3. PCM_CLK is the bit clock for the bus. It’s frequency depends on the number of 16-bit frames per sync pulse and can be 128kHz, 256kHz, 512kHz. The other two lines, PCM_SDO and PCM_SDI, are for serial data out and serial data in, respectively. The type of data may also be set in the BASICCONFIG register by bits 6 and 7. Bit 6 controls whether the data is linear or companded. If set to 1, the 8 MSBs are presumed to be companded data and the 8 LSBs are ignored. If cleared to 0, the data is treated as 2’s complement PCM data. Bit 7 controls which PCM law is used if Bit 6 is set for companded (G711) data. If set to 1, the companded data is assumed to be A-law. If cleared to 0, the companded data is treated as µ-law. Bits 8:9 of the BASICCONFIG register set the PCM_SYNC_MODE settings. This controls the number of 16 bit frames per sync pulse. The feature allows the LM4930 to function harmoniously with other devices or channels on the PCM bus by adjusting the number of 16 bit frames per sync pulse to 1 (00b), 2 (01b), or 4 (10b). The LM4930 will transmit PCM data in the first frame and then tri-state the PCM_SDO pin on later frames. In addition, the LM4930 provides control to allow the PCM_CLK and PCM_SYNC clocks to continue functioning even when the LM4930 is in Standby mode. By setting bit 10 of the BASICCONFIG register to 1 PCM_ALWAYS_ON is enabled and the LM4930 will continue to drive the PCM clock and sync lines when in Standby mode. This bit should be set if another codec is using the PCM bus. Powerdown mode will disable these outputs. I2S Interface Bus (J2) The I2S standard provides a uni-directional serial interface designed specifically for digital audio. For the LM4930, the interface provides access to a 48kHz, 16 bit full-range stereo audio DAC. This interface uses a three port system of clock (I2S_CLK), data (I2S_DATA), and word (I2S_WS). The clock and word lines can be either master or slave as set by bit 11 in the BASICCONFIG register. A bit clock (I2S_CLK) at 32 or 64 times the sample frequency is established by the I2S system master and a word select (I2S_WS) line is driven at a frequency equal to the sampling rate of the audio data, in this case 48kHz. The word line is registered to change on the negative edge of the bit clock. The serial data (I2S_DATA) is sent MSB first, again registered on the negative edge of the bit clock, delayed by 1 bit clock cycle relative to the changing of the word line (typical I2S format - see Figure 4). The resolution of the I2S interface may be set by modifying the I2S_RES bit (bit 12) in the BASICCONFIG register. If set to 1, the LM4930 operates at 32 bits per frame (3.072MHz). If cleared to 0, then 16 bits per frame is selected (1.536MHz). This has a corresponding effect on the bit clock. The I2S Interface Bus also provides for an additional MCLK connection to an external device from the LM4930 demo board. This may be used in conjunction with National Semiconductors SPDIF- > I2S Conversion Board for quick evaluation. This board features a connection header that interfaces with pins 1-5 of the I2S Interface Bus. Pins 6-10 are provided as digital ground references for the case of discrete connections. MCLK/XTAL_IN (P5) This is the input for an external Master Clock. The jumper at S2 must be removed (disconnecting the onboard crystal from the circuit) when using an external Master Clock. BTL Mono Out (J7) This is the mono speaker output, designed for use with an 8 ohm speaker. The outputs are driven in bridge-tied-load (BTL) mode, so both sides have signal. Outputs are normally biased at one half AVDD when the LM4930 is in active mode. Additionally, if the CLASS bit is set to 1 in the VOICETESTCONFIG register (bit 0) the BTL mono output is internally configured as a buffer amplifier designed for use with an external class D amp. Stereo Headphone Out (J8) This is the stereo headphone output. Each channel is singleended, with 220uF DC blocking capacitors mounted on the demo board. The jack features a typical stereo headphone pinout. A headphone sense pin is provided at J6. This pin provides a clean logic high or low output to indicate the presence of headphones in the headphone jack. A common application circuit for this is given in the Reference Board Schematic shown in Figure 5. In this application HPSENSE_IN is pulled low by the 1k ohm resistor when no headphone is present. This gives a corresponding logic low output on the HPSENSE_OUT pin. When a headphone is placed in the jack the 1k ohm pull-down is disconnected and a 100k ohm pull-up resistor creates a high voltage condition on HPSENSE_IN. This in turn creates a logic high on HPSENSE_OUT. This output may be used to reliably drive an external microcontroller with headphone status. 31 www.national.com LM4930 Application Information MIC Jack (J3) (Continued) L+R Mixed to Mono Speaker + Stereo Headphone Audio (0111b) Part is active. All analog outputs are biased. Full-range audio from the 16bit/48kHz audio DAC is sent discretely to the stereo headphone jack and also mixed together and sent to the mono speaker out. Mixed Mode (1000b) Part is active. All analog outputs are biased. This provides one channel (the left channel) of full range audio to the mono speaker out. Audio from the voiceband codec is then sent to the stereo headphones, the same on each channel. Mixed Mode (1001b) Part is active. All analog outputs are biased. Mixed voiceband and full-range audio (left channel only) is sent to the mono speaker out. Audio from the voiceband codec only is sent to the stereo headphones, the same on each channel. Mixed Mode (1010b) Part is active. All analog outputs are biased. Audio from the voiceband codec is sent to the mono speaker out. The left channel only of the full range audio is then sent to both the left and right channels of the stereo headphone out. REGISTERS The LM4930 starts on power-up with all registers cleared in Powerdown mode. Powerdown mode is the recommended time to make setup changes to the digital interfaces (PCM bus, I2S bus). Although the configuration registers can be changed in any mode, changes made during Standby or Powerdown prevent unwanted audio artifacts that may occur during rapid mode changes with the outputs active. The LM4930 also features a soft reset. This reset is enabled by setting bit 4 of the BASICCONFIG register. The VOICETESTCONFIG register is used to set various configuration parameters on the voiceband and full-range audio codecs. SIDETONE_ATTEN (bits 4:1) refers to the level of signal from the MIC input that is fed back into the analog audio output path (commonly used in headphone applications and killed in hands-free applications). Setting the AUTOSIDE bit (bit 5) automatically mutes the sidetone in voice over mono speaker modes so feedback isn’t an issue. Quick mute functions are also located in this register, with bits 13:15 muting the mono speaker amp, the headphone amp, and the mic preamp respectively. This register also has a CLOCK_DIV bit (bit 6) which, if set, allows for the use of a 24.576MHz clock instead of the default 12.288MHz. The GAINCONFIG register is used to control the gain of the mono speaker amp , the headphone amp, and the mic preamp. This allows flexible mono speaker gains from -34.5dB to +12dB in 1.5dB steps, headphone amp gains of -46.5dB to 0dB in 1.5dB steps, and mic preamp gains of 17dB to 47dB in 2dB steps. Gain levels may be modified in any mode, but may wait for a zero cross detect in the DAC to eliminate volume control artifacts. This wait for zero cross may be disabled by setting the ZXD_DISABLE bit (bit 7) in the VOICETESTCONFIG register to allow immediate changes. ANALOG INPUTS AND OUTPUTS The LM4930 features an analog mono BTL output for connection to an 8Ω external speaker. This output can provide up to 1W of power into an 8Ω load with a 5V analog supply. 32 This jack is for connection to an external microphone like the kind typically found in mobile phones. Pin 1 is GND, pin 2 is the negative input pin, and pin 3 is the positive pin, with phantom voltage supplied by MIC_BIAS on the LM4930. IRQ (J4) This pin provides simple status updates from the LM4930 to an external microcontroller if desired. IRQ is logic high when the LM4930 is in a stable state and changes to low when changing modes. This can also be useful for simple software/driver development to monitor mode changes, or as a simple debugging tool. BASIC OPERATION The LM4930 is a highly integrated audio subsystem with many different operating modes available. These modes may be controlled in the BASICCONFIG register in bits 3:0. These mode settings are shown in the BASICCONFIG register table and are described here below: Powerdown Mode (0000b) Part is powered down, analog outputs are not biased. This is a minimum current mode. All part features are shut down. Standby Mode (0001b) The LM4930 is powered down, but outputs are still biased at one half AVDD. This comes at some current cost, but provides a much faster turn-on time with zero "click and pop" transients on the headphone out. Standby mode can be toggled into and out of rapidly and is ideal for saving power whenever continuous audio is not a requirement. All other part functions are suspended unless PCM_ALWAYS_ON (bit 10 in BASICCONFIG register) is enabled, in which case PCM_CLK and PCM_SYNC will continue to function. Mono Speaker Mode (0010b) Part is active. All analog outputs are biased. Audio from the voiceband codec is routed to the mono speaker out. Stereo headphone out is silent. Headphone Call Mode (0011b) Part is active. All analog outputs are biased. Audio from voiceband codec is routed to the stereo headphones. Both left and right channels are the same. Mono speaker out is silent. Conference Call Mode (0100b) Part is active. All analog outputs are biased. Audio from the voiceband codec is routed to the mono speaker out and to the stereo headphones. L+R Mixed to Mono Speaker (0101b) Part is active. All analog outputs are biased. Full-range audio from the 16bit/48kHz audio DAC is mixed together and routed to the mono speaker out. Stereo headphones are silent. Headphone Stereo Audio (0110b) Part is active. All analog outputs are biased. Full-range audio from the 16bit/48kHz audio DAC is sent to the stereo headphone jack. Each channel is heard discretely. The mono speaker is silent. www.national.com LM4930 Application Information (Continued) A single-ended stereo headphone output is also featured, providing up to 30mW of power per channel into 32Ω with a 5V analog supply. A Headphone Sense output is provided on J6 for connection to an external controller. This pin goes high when a hea- phone is present (when used as shown in Figure 5) and will function in all modes independent of other operations the LM4930 may be currently processing. The MIC Jack input (J3) provides for a low level analog input. Pin 3 provides the power to the MIC and the positive input of the LM4930. Gain for the MIC preamp is set in the GAINCONFIG register. 33 www.national.com LM4930 Physical Dimensions inches (millimeters) unless otherwise noted 36-Bump micro SMD Order Number LM4930ITL NS Package Number TLA36KRA X1 = 3.230 ± 0.03mm X2 = 3.408 ± 0.03 X3 = 0.600 ± 0.075 www.national.com 34 LM4930 Audio Subsystem with Stereo Headphone & Mono Speaker Amplifiers Physical Dimensions inches (millimeters) unless otherwise noted (Continued) LLP Package Order Number LM4930LQ NS Package Number LQA44A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. BANNED SUBSTANCE COMPLIANCE National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2. National Semiconductor Americas Customer Support Center Email: new.feedback@nsc.com Tel: 1-800-272-9959 www.national.com National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Support Center Email: ap.support@nsc.com National Semiconductor Japan Customer Support Center Fax: 81-3-5639-7507 Email: jpn.feedback@nsc.com Tel: 81-3-5639-7560 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.