LM49321

LM49321 Audio Sub-System with Stereo DAC, Mono Class AB Loudspeaker Amplifier, OCL/SE Stereo Headphone Output and RF Suppression LM49321 August 31, 2009 Audio Sub-System with Stereo DAC, Mono Class AB Loudspeaker Amplifier, OCL/SE Stereo Headphone Output and RF Suppression General Description The LM49321 is an integrated audio sub-system designed for mono voice, stereo music cell phones connecting to base band processors with mono differential analog voice paths. Operating on a 3.3V supply, it combines a mono speaker amplifier delivering 520mW into an 8Ω load, a stereo headphone amplifier delivering 36mW per channel into a 32Ω load, and a mono earpiece amplifier delivering 55mW into a 32Ω load. The headphone amplifier can be configured for output capacitor-less (OCL) or single-ended (SE) mode. It integrates the audio amplifiers, volume control, mixer, and power management control all into a single package. In addition, the LM49321 routes and mixes the single-ended stereo and differential mono inputs into multiple distinct output modes. The LM49321 features an I2S serial interface for full range audio and an I2C or SPI compatible interface for control. The full range music path features an SNR of 85dB with up to 192kHz playback. Boomer audio power amplifiers are designed specifically to provide high quality output power with a minimal amount of external components. Key Specifications ■ POUT LS, 8Ω, 3.3V, 1% THD+N ■ POUT HP, 32Ω, 3.3V, 1% THD+N ■ POUT Mono Earpiece, 32Ω 1% THD+N 55mW (typ) 0.6µA (typ) 85dB (typ) 520mW (typ) 36mW (typ) ■ Shutdown current ■ SNR (DAC + Amplifier) Features ■ ■ ■ ■ ■ ■ ■ ■ 18-bit stereo DAC with up to 192kHz sampling rate Multiple distinct output modes Mono class AB speaker amplifier Stereo OCL/SE headphone amplifier Mono earpiece amplifier Differential mono analog input Single-ended analog inputs Independent loudspeaker, headphone and mono earpiece volume controls ■ I2C/SPI (selectable) compatible interface ■ Ultra low shutdown current ■ Click and Pop Suppression circuit Applications ■ ■ ■ ■ Cell Phones PDAs Laptop computers Portable devices Boomer® is a registered trademark of National Semiconductor Corporation. © 2009 National Semiconductor Corporation 300618 www.national.com LM49321 Block Diagram 30061832 FIGURE 1A: Typical Audio Amplifier Subsystem Application circuit with Output Capacitor-less (OCL) Headphone configuration www.national.com 2 LM49321 30061833 FIGURE 1B: Typical Audio Amplifier Subsystem Application circuit with Cap-C`oupled single-ended (SE) Headphone configuration 3 www.national.com LM49321 Connection Diagrams 36 – Bump Micro SMD 36 – Bump Micro SMD Top Marking Drawing 30061858 Top View (Bump Side Down) Order Number LM49321RL See NS Package Number RLA36LVA 30061802 Top View XY — 2 Digit Date Code TT — Die Traceability G — Boomer Family K9 — LM49321RL www.national.com 4 LM49321 Pin Descriptions Pin A1 A2 A3 A4 A5 A6 B1 B2 B3 B4 B5 B6 C1 C2 C3 C4 C5 C6 D1 D2 D3 D4 D5 D6 E1 E2 E3 E4 E5 E6 F1 F2 F3 F4 F5 F6 Pin Name DGND MCLK I2S_WS SDA/SDI DVDD I/O_VDD PLL_VDD I2S_SDATA I2S_CLK GPIO I2C_VDD SDL/SCK PLL_GND PLL_OUT PLL_IN ADDR/ENB BYPASS AVDD AGND AGND NC MODE RHP CHP DIFFLIN RIN NC LHP AGND DIFF+ EPEP+ LSAVDD LS+ A A A A A A A A O P I O O O P O D A A A A A I O O I I I Digital/ Analog D D D D D D D D D D D D D D D D A A A A I/O, Power P I I/O I/O P P P I I/O O P I P O I I I P P P Description DIGITAL GND MASTER CLOCK I2S WORD SELECT I2C SDA OR SPI SDI DIGITAL SUPPLY VOLTAGE I/O SUPPLY VOLTAGE PLL SUPPLY VOLTAGE I2S SERIAL DATA INPUT I2S CLOCK SIGNAL TEST PIN (MUST BE LEFT FLOATING) I2C SUPPLY VOLTAGE I2C_SCL OR SPI_SCK PHASE LOCK LOOP GROUND PHASE LOCK LOOP FILTER OUTPUT PLL FILTER INPUT I2C ADDRESS OR SPI ENB DEPENDING ON MODE HALF-SUPPLY BYPASS ANALOG SUPPLY VOLTAGE ANALOG GROUND ANALOG GROUND NO CONNECT (MUST BE LEFT FLOATING) SELECTS BETWEEN I2C OR SPI CONTROL RIGHT HEADPHONE OUTPUT HEADPHONE CENTER PIN OUTPUT (1/2 VDD or GND) ANALOG NEGATIVE DIFFERENTIAL INPUT ANALOG LEFT CHANNEL INPUT ANALOG RIGHT CHANNEL INPUT NO CONNECT (MUST BE LEFT FLOATING) LEFT HEADPHONE OUTPUT ANALOG GROUND ANALOG POSITIVE DIFFERENTIAL INPUT MONO EARPIECE- OUTPUT MONO EARPIECE+ OUTPUT LOUDSPEAKER OUTPUTANALOG SUPPLY VOLTAGE LOUDSPEAKER OUTPUT+ 5 www.national.com LM49321 Absolute Maximum Ratings (Note 1, Note 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Analog Supply Voltage (Note 1) Digital Supply Voltage (Note 1) Storage Temperature Input Voltage Power Dissipation (Note 3) ESD Ratings (Note 4) ESD Ratings (Note 5) Junction Temperature (TJMAX) Thermal Resistance 6.0V 6.0V -65°C to +150°C -0.3V to VDD +0.3V Internally Limited 2000V 200V 150°C  θJA (RLA36) 100°C/W Soldering Information See AN-1279 “Microfill Wafer Level Underfilled Chip Scale package.” Operating Ratings Temperature Range TMIN ≤ TA ≤ TMAX Supply Voltage (Note 1, Note 2) −40°C ≤ TA ≤ +85°C 2.7V ≤ AVDD ≤ 5.5V 1.7V ≤ I2C_VDD ≤ 4.0V 1.7V ≤ I/O_VDD ≤ 4.0V 2.7V ≤ DVDD ≤ 4.0V Audio Amplifier Electrical Characteristics AVDD = 3.0V, DVDD = 3.0V (Note 1, Note 2) The following specifications apply for the circuit shown in Figure 1 with all programmable gain set at 0dB, unless otherwise specified. Limits apply for TA = 25°C. LM49321 Symbol Parameter Conditions VIN = 0, No Load All Amps On + DAC, OCL (Note 10) Headphone Mode Only, OCL, DAC off Headphone Mode Only, OCL, DAC Off STEREO_OUTPUT_ONLY = 1, STEREO_INPUT_ONLY = 1 IDD Supply Current Headphone Mode only OCL, DAC On, OSR = 64, DAC_INPUT_ONLY = 1 STEREO_OUTPUT_ONLY = 1 Mono Loudspeaker Mode Only (Note 11) Mono Earpiece Speaker Mode Only MONO_ONLY = 1 (register 01h) MONO_ONLY = 0 DAC Off, All Amps On (OCL) (Note 10) ISD PO VFS DAC Shutdown Current Output Power Full Scale DAC Output Speaker; PO = 200mW; f = 1kHz, 8Ω BTL THD+N Total Harmonic Distortion+Noise Headphone; PO = 10mW; f = 1kHz, 32Ω SE Earpiece; PO = 20mW; f = 1kHz, 32Ω BTL Speaker VOS ∈O PSRR Offset Voltage Output Noise Power Supply Rejection Ratio Earpiece Headphone (OCL) A-weighted; 0dB gain f = 217Hz; VRIPPLE = 200mVP-P CB = 2.2μF 6 Typical (Note 6) 13 4.6 4 Limits (Note 7) 18 6.25 5.5 Units (Limits) mA (max) mA (max) mA 7.5 6.5 3.7 3.3 10 0.6 420 27 45 2.4 0.04 0.01 0.04 10 8 8 Table 1 Table 2 10 11.5 5 13.5 1 370 24 40 mA (max) mA (max) mA (max) mA mA (max) μA (max) mW (min) mW (min) mW (min) VRMS % % % (Note 8) Speaker; THD = 1%; f = 1kHz, 8Ω BTL Headphone; THD = 1%; f = 1kHz, 32Ω SE Earpiece; THD = 1%; f = 1kHz, 32Ω BTL 55 50 15 mV (max) mV (max) mV (max) www.national.com LM49321 LM49321 Symbol XTALK TWU CMRR Crosstalk Wake-Up Time Common-Mode Rejection Ratio Parameter Conditions Headphone; PO = 10mW, f = 1kHz; OCL CB = 2.2μF, CD_6 = 0 CB = 2.2μF, CD_6 = 1 f = 217Hz, VRMS = 200mVPP Typical (Note 6) –60 35 85 56 Limits (Note 7) Units (Limits) dB ms ms dB (Note 1, Note Audio Amplifier Electrical Characteristics AVDD = 5.0V, DVDD = 3.3V 2) The following specifications apply for the circuit shown in Figure 1 with all programmable gain set at 0dB, unless otherwise specified. Limits apply for TA = 25°C. LM49321 Symbol Parameter Conditions VIN = 0, No Load All Amps On + DAC, OCL (Note 10) Headphone Mode Only, OCL, DAC Off Headphone Mode Only, OCL, DAC Off STEREO_OUTPUT_ONLY = 1, STEREO_INPUT_ONLY = 1 Headphone Mode Only, OCL, DAC On, OSR = 64, DAC_INPUT_ONLY = 1 STEREO_OUTPUT_ONLY = 1 Mono Loudspeaker Mode Only (Note 10) Mono Earpiece Mode Only (Note 10) DAC Off, All Amps On (OCL) (Note 10) ISD Shutdown Current (Note 8) Speaker; THD = 1%; f = 1kHz, 8Ω BTL PO Output Power Headphone; THD = 1%; f = 1kHz, 32Ω SE Earpiece; THD = 1%; f = 1kHz, 32Ω BTL VFS DAC Full Scale DAC Output Speaker; PO = 500mW; f = 1kHz, 8Ω BTL THD+N Total Harmonic Distortion + Noise Headphone; PO = 30mW; f = 1kHz, 32Ω SE Earpiece; PO = 40mW; f = 1kHz, 32Ω BTL Speaker VOS ∈O PSRR XTALK TWU Offset Voltage Output Noise Power Supply Rejection Ratio Crosstalk Wake-Up Time Earpiece HP (OCL) A-weighted; 0dB gain; f = 217Hz; Vripple = 200mVP-P CB = 2.2μF Headphone; PO= 15mW, f = 1kHz; OCL CB = 2.2μF, CD_6 = 0 CB = 2.2μF, CD_6 = 1 Typical (Note 6) 17.5 5.8 5.5 Limits (Note 7) Units (Limits) mA (max) mA (max) mA IDD Supply Current 9.5 11.6 5 12.9 1.6 1.25 80 175 2.4 0.03 0.01 0.04 10 8 8 Table 1 Table 3 –56 45 130 mA mA mA mA μA mW mW mW VRMS % % % mV mV mV dB ms ms 7 www.national.com LM49321 Volume Control Electrical Characteristics (Note 1, Note 2) The following specifications apply for 3.0V ≤ AVDD ≤ 5.0V and 2.7V ≤ DVDD ≤ 4.0V, unless otherwise specified. Limits apply for TA = 25°C. LM49321 Symbol Parameter Conditions Typical (Note 6) –6 15 –12 9 –56 +5 0.3 VIN = 1VRMS, Gain = 0dB with load, Headphone –90 23 18 28 Limits (Note 7) –7 –5 15.5 14.5 –13 –11 9.5 8.5 –59 –53 4.5 5.5 Units (Limits) dB (min) dB (max) dB (max) dB (min) dB (min) dB (max) dB (max) dB (min) dB (min) dB (max) dB (min) dB (max) dB dB kΩ (min) kΩ (max) Stereo Analog Inputs Pre-Amp Gain Setting Range PGR Differential Mono Analog Input PreAmp Gain Setting Range minimum gain setting maximum gain setting minimum gain setting maximum gain setting minimum gain setting maximum gain setting VCR Output Volume Control for Loudspeaker, Headphone Output, or Earpiece Output Stereo Channel to Channel Gain Mismatch Mute Attenuation DIFF+, DIFF-, LIN and RIN Input Impedance ΔACH-CH AMUTE RINPUT Digital Section Electrical Characteristics (Note 1, Note 2) The following specifications apply for 3.0V ≤ AVDD ≤ 5.0V and 2.7V ≤ DVDD ≤ 4.0V, unless otherwise specified. Limits apply for TA = 25°C. LM49321 Symbol Parameter Conditions Mode 0, DVDD = 3.0V No MCLK fMCLK = 12MHz, DVDD = 3.0V ALL MODES EXCEPT 0 fMCLK = 12MHz, DVDD = 3.0V 20Hz - 20kHz through headphone output -3dB point Above 24kHz DC - 20kHz, –60dBFS; AES17 Standard 0.01 5.3 4.8 +/-0.1 22.6 76 Table 4 6.5 6 μA mA (max) mA (max) dB kHz dB dB dB dB 10 26 1000 250 250 8 Typical (Note 6) Limits (Note 7) Units (Limits) DISD DIDD PLLIDD RDAC PBDAC SBADAC DRDAC SNR SNRDAC PLL fIN Digital Shutdown Current Digital Power Supply Current PLL Quiescent Current Audio DAC Ripple Audio DAC Passband width Audio DAC Stop band Attenuation Audio DAC Dynamic Range Audio DAC-AMP Signal to Noise Ratio Internal DAC SNR Audio DAC (Typical numbers are with 6.144MHz audio clock and 48kHz sampling frequency A-Weighted, Signal = VO at 0dBFS, f = 1kHz Table 4 Noise = digital zero, A-weighted A-weighted (Note 9) 95 Input Frequency on MCLK pin 12 MHz SPI/I2C (1.7V ≤ I2C_VDD ≤ 2.2V) fSPI tSPISETD tSPISETENB www.national.com Maximum SPI Frequency SPI Data Setup Time SPI ENB Setup Time kHz (max) ns (max) ns (max) LM49321 LM49321 Symbol tSPIHOLDD tSPIHOLDENB tSPICL tSPICH fCLKI2C tI2CHOLD tI2CSET VIH VIL Parameter SPI Data Hold Time SPI ENB Hold Time SPI Clock Low Time SPI Clock High Time I2C_CLK Frequency Setup Time I2C_VDD 0 I2C_DATA Hold Time I2C_DATA Conditions Typical (Note 6) Limits (Note 7) 250 250 500 500 400 250 250 0.7 x I2C_VDD 0.25 x I2C_VDD 4000 100 100 100 100 125 125 400 100 100 I2C_VDD 0 0.7 x I2C_VDD 0.3 x I2C_VDD 6144 12288 40 60 0.75 x I/O_VDD 0.25 x I/O_VDD 1536 3072 50 6144 12288 40 60 0.7 x I/O_VDD 0.3 x I/O_VDD Units (Limits) ns (max) ns (max) ns (max) ns (max) kHz (max) ns (max) ns (max) V (min) V (max) I2C/SPI Input High Voltage I2C/SPI Input Low Voltage SPI/I2C (2.2V ≤ I2C_VDD ≤ 4.0V) fSPI tSPISETD tSPISETENB tSPIHOLDD tSPIHOLENB tSPICL tSPICH fCLKI2C tI2CHOLD tI2CSET VIH VIL Maximum SPI Frequency SPI Data Setup Time SPI ENB Setup Time SPI Data Hold Time SPI ENB Hold Time SPI Clock Low Time SPI Clock High Time I2C_CLK Frequency I2C_DATA Hold Time I2C_DATA Setup Time I2C/SPI Input High Voltage I2C/SPI Input Low Voltage kHz (max) ns (max) ns (max) ns (max) ns (max) ns (max) ns (max) kHz (max) ns (max) ns (max) V (min) V (max) I2S (1.7V ≤ I/O_VDD ≤ 2.7V) I2S_CLK Frequency fCLKI2S I2S_WS Duty Cycle VIH VIL Digital Input High Voltage Digital Input Low Voltage I2S_RESOLUTION = 1 I2S_RESOLUTION = 0 1536 3072 50 kHz (max) kHz (max) % (min) % (max) V (min) V (max) I2S (2.7V ≤ I/O_VDD ≤ 4.0V) I2S_CLK Frequency fCLKI2S I2S_WS Duty Cycle VIH VIL Digital Input High Voltage Digital Input Low Voltage I2S_RESOLUTION = 1 I2S_RESOLUTION = 0 kHz (max) kHz (max) % % V (min) V (max) 9 www.national.com LM49321 Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum RatingsRatings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All voltages are measured with respect to the ground pin, unless otherwise specified. Note 2: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed. Note 3: Maximum allowable power dissipation is PDMAX = (TJMAX - TA) / θJA or the number given in Absolute Maximum Ratings, whichever is lower. Note 4: Human body model, applicable std. JESD22-A114C. Note 5: Machine model, applicable std. JESD22-A115-A. Note 6: Typical values represent most likely parametric norms at TA = +25ºC, and at the Recommended Operation Conditions at the time of product characterization and are not guaranteed. Note 7: Datasheet min/max specification limits are guaranteed by test or statistical analysis. Note 8: Shutdown current is measured in a normal room environment. Note 9: Internal DAC only with DAC modes 00 and 01. Note 10: Enabling mono bit (MONO_ONLY in Output Control Register 01h) will save 400μA (typ) form specified current. www.national.com 10 LM49321 TABLE 1. Output Noise Output Noise AVDD = 5.0V and AVDD = 3.0V. All gains set to 0dB. Units in μV, A-weighted, Inputs terminated to ground. MODE 1 2 3 4 5 6 7 EP 22 22 22 68 38 29 38 LS 22 22 22 88 48 34 48 TABLE 2. PSRR AVDD = 3.0V PSRR AVDD = 3.0V, fRIPPLE = 217Hz; VRIPPLEe = 200mVP-P; CB = 2.2μF; All gains set to 0dB.. MODE 1 2 3 4 5 6 7 EP(Typ) 69 69 69 63 69 69 69 LS (Typ) 76 76 76 62 68 70 68 67 LS (Limit) HP (Typ) 72 72 72 55 61 64 61 TABLE 3. PSRR AVDD = 5.0V PSRR AVDD = 5.0V, fRIPPLE = 217Hz; VRIPPLE = 200mVP-P; CB = 2.2μF; All gains set to 0dB, MODE 1 2 3 4 5 6 7 EP (Typ) 68 68 68 68 68 69 68 LS (Typ) 72 72 72 66 69 72 69 TABLE 4. Dynamic Range and SNR Dynamic Range and SNR. 3.0V ≤ AVDD ≤ 5.0V. All programmable gain set to 0dB. Units in dB. DR (Typ) LS HP EP 95 95 97 SNR (Typ) 85 85 85 Units dB dB dB HP (Typ) 71 71 71 69 70 71 70 Units dB dB dB dB dB dB dB 68 HP (Limit) Units dB dB dB dB dB dB dB HP OCL 8 8 8 46 24 18 24 Units μV μV μV μV μV μV μV 11 www.national.com LM49321 System Control The LM49321 is controlled via either a two wire I2C compatible interface or three wire SPI interface, selectable with the MODE pin. This interface is used to configure the operating mode, interfaces, data converters, mixers and amplifiers. The LM49321 is controlled by writing 8 bit data into a series of write-only registers, the device is always a slave for both type of interfaces. THREE WIRE, SPI INTERFACE (MODE = 1) Three Wire Mode Write Bus Transaction 30061859 Three Wire Mode Write Bus Timing 30061860 Three Wire Mode Write Bus When the part is configured as an SPI device and the enable (ENB) line is lowered the serial data on SDI is clocked in on the rising edge of the SCK line. The protocol used is 16bit, MSB first. The upper 8 bits (15:8) are used to select an address within the device, the lower 8 bits (7:0) contain the updated data for this register. TWO WIRE I2C COMPATIBLE INTERFACE (MODE = 0) Two Wire Mode Write Bus Transaction 300618j6 Two Wire Mode Write Bus Timing 30061862 Two Wire Mode Write Bus www.national.com 12 LM49321 When the part is configured as an I2C device then the LM49321 will respond to one of two addresses, according to the ADDR input. If ADDR is low then the address portion of the I2C transaction should be set to write to 0010000. When ADDR is high then the address input should be set to write to 1110000. TABLE 5. Chip Address A7 Chip Address ADR = 0 ADR = 1 0 0 0 A6 EC 0 1 A5 EC 0 1 A4 1 1 1 A3 0 0 0 A2 0 0 0 A1 0 0 0 A0 0 0 0 EC — Externally configured by ADR pin 13 www.national.com LM49321 TABLE 6. Control Registers D7 0 DAC_INPUT_ ONLY 0 0 0 0 0 ANA_R_GAIN DAC_R_GAIN R_DIV 0 PLL_N PLL_N_MOD 0 MUTE_R I2C_FAST MUTE_L I2S_MODE PLL_P DAC_MODE I2S_ RESOLUTION I2S_MASTER_ SLAVE 0 0 0 0 0 0 CUST_COMP DITHER_ALW_ON DITHER_OFF 0 0 PLL_M PLL_ ENABLE DAC_L_GAIN AUDIO _CLK_SEL HP_R_VOL ANA_L_GAIN MONO_L_GAIN PLL_INPUT FAST_ CLOCK HP_L_VOL 0 0 0 LS_VOL 0 0 EP_VOL STEREO_INPUT_ ONLY HP_R_ OUTPUT HP_L_ OUTPUT LS_ OUTPUT CD_6 0 OCL MODE_CONTROL MONO_ OUTPUT D6 D5 D4 D3 D2 D1 D0 Address Register www.national.com 00h MODE_CONTROL 01h 0 0 0 0 0 0 0 0 0 0 0 0 0 OUTPUT_ CONTROL STEREO_ MONO_ONLY OUT_ONLY 02h EP_VOL 03h LS_VOL 04h RESERVED 05h HP_L_VOL 06h HP_R_VOL 07h ANALOG_INPUT _GAIN 08h ANALOG_DAC _GAIN 09h CLOCKS 0Ah PLL_M 0Bh 0Ch PLL_N_MOD VCO_FAST DITHER_LEVEL DITHER_LEVEL 14 0Dh PLL_P 0Eh DAC_SET UP 0Fh INTERFACE 10h COMPENSATION _C OEFF0_LSB COMPENSATION _C OEFF0_MSB COMPENSATION _C OEFF1_LSB COMPENSATION _C OEFF1_MSB COMPENSATION _C OEFF2_LSB COMPENSATION _C OEFF2_MSB 11h 12h 13h 14h 15h Note: All registers default to 0 on initial power-up. LM49321 Mixer Control Registers TABLE 7. Mode Control Register (00h) This register is used to control the different mixer modes that the LM49321 supports. Bits 3:0 Field Description Loudspeaker SD M AL+AR M+AL+AR DL+DR DL+DR+AL+AR M+DL+DR+AL +AR M+DL+DR Headphone Left SD M AL M+AL DL DL+AL M+DL+AL M+DL Headphone Right SD M AR M+AR DR DR+AR M+DR+AR M+DR MODE This sets the different mixer output modes. _CONTROL MODE_CONTROL Mode Mono Earpiece 0000 1001 1010 1011 1100 1101 1110 1111 4 OCL 0 1 2 3 4 5 6 7 OCL 0 1 SD — Shutdown M — Mono Differential Input AL — Analog Left Channel AR — Analog Right Channel DL — I2S DAC Left Channel DR — I2S DAC Right Channel Note: Power-On Default Mode is Mode 0 SD M AL+AR M+AL+AR DL+DR DL+DR+AL+AR M+DL+DR+AL +AR M+DL+DR This sets the headphone output to use output capacitor-less configuration. Headphone output configuration Cap-coupled Single-ended Mode (SE) Output capacitor-less (OCL) TABLE 8. Output Control (01h) This register is used to control the different output configurations. Bits 0 Field EP_OUTPUT EP_OUTPUT 0 1 1 LS_OUTPUT LS_OUTPUT 0 1 2 HP_L_OUTPUT This enables the Headphone left output. HP_L_OUTPUT 0 1 3 HP_R_OUTPUT HP_R_OUTPUT 0 1 Status Headphone left output off. If OCL=1, output is in mute. Headphone left output on Status Headphone right output off. If OCL=1, output is in mute. Headphone right output on Description This enables the Mono Earpiece output. Status Mono earpice output off Mono earpice output on Status Loudspeaker output off Loudspeaker output on This enables the Mono Loudspeaker output. This enables the Headphone right output. 15 www.national.com LM49321 Bits 4 Field STEREO_INPUT_ONLY Description This enables the analog left (AL) and analog right (AR) and disables all other inputs. STEREO_INPUT_ONLY 0 1 Status Normal Enables AL and AR inputs only Status Normal Enables DL and DR inputs only 5 DAC_INPUT_ONLY This enables the DAC left (DL) and analog right (DR) and disables all other inputs. DAC_INPUT_ONLY 0 1 6 MONO_ONLY This enables mono earpiece (EP) and loudspeaker (LS) outputs MUX and disables the headphone outputs MUX. Enabling this mode can save up to 400µA of current. MONO_ONLY 0 1 Status Normal Enable mono earpiece and loudspeaker outputs MUX 7 STEREO_OUTPUT_ONLY This enables the headphone output MUX only and disables all other output MUX’s. Enabling this mode can save up to 200µA of current. STEREO_OUTPUT_ONLY 0 1 Status Normal Enables the headphone output MUX www.national.com 16 LM49321 Volume Control Registers TABLE 9. Volume Control Register EP_VOL (02h), LS_VOL (03h), HP_L_VOL (05h), HP_R_VOL (06h) These registers are used to control output volume control levels for Earpiece, Loudspeaker and Headphone. Bits 4:0 Field EP_VOL LS_VOL HP_L_VOL HP_R_VOL Description This programs the Earpiece, Loudspeaker and Headphone volume level. VOL 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 Level (dB) MUTE –56 –52 –48 –45 –42 –39 –36 –33 –30 –28 –26 –24 –22 –20 –18 –16 –14 –12 –10 –8 –6 –4 –3 –2 –1 0 1 2 3 4 5 17 www.national.com LM49321 TABLE 10. Analog Left and Right Input Control (07h) This register is used to control input gain for left and right analog inputs. Bits 2:0 Field ANA_L_GAIN ANA_L_GAIN 000 001 010 011 100 101 110 111 5:3 ANA_R_GAIN This program the analog Right input gain. ANA_R_GAIN 000 001 010 011 100 101 110 111 TABLE 11. Mono and DAC Input Gain Control (08h) This register is sued to control input gain for Mono, DAC left and right inputs. Bits 2:0 Field MONO_IN_GAIN Description This program the mono input gain. MONO_IN_GAIN 000 001 010 011 100 101 110 111 4:3 DAC_L_GAIN This program the DAC left input gain. DAC_L_GAIN 00 01 10 11 6:5 DAC_R_GAIN DAC_R_GAIN 00 01 10 11 Level (dB) –3 0 3 6 Level (dB) –3 0 3 6 Level (dB) –12 –9 –6 –3 0 3 6 9 Level (dB) –6 –3 0 3 6 9 12 15 Description This program the analog left input gain. Level (dB) –6 –3 0 3 6 9 12 15 This program the DAC Right input gain. www.national.com 18 LM49321 Clock Configuration Register This register is used to control the multiplexers and clock R divider in the clock module. TABLE 12. CLOCK (09h) Bits 0 Register FAST_CLOCK If set master clock is divided by two. FAST_CLOCK 0 1 1 PLL_INPUT Programs the PLL input multiplexer to select: PLL_INPUT 0 1 2 AUDIO_CLK_SEL Selects which clock is passed to the audio sub-system DAC_CLK_SEL 0 1 3 7:4 PLL_ENABLE R_DIV If set enables the PLL. (MODES 4–7 only) Programs the R divider R_DIV 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Divide Value 1 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 DAC Sub-system Input Source PLL Input PLL Output PLL Input Source MCLK I2S Input Clock MCLK Frequency Normal Divided by 2 Description 19 www.national.com LM49321 30061853 By default the stereo DAC operates at 250*fs, i.e. 12.000MHz (at the clock generator input clock) for 48kHz data. It is expected that the PLL be used to drive the audio system unless a 12.000MHz master clock is supplied. The PLL can also use the I2S clock input as a source. In this case, the audio DAC uses the clock from the output of the PLL. Common Clock Settings for the DAC The DAC can work in 4 modes, each with different oversampling rates, 125,128,64 & 32. In normal operation 125x oversampling provides for the simplest clocking solution as it will work from 12.000MHz (common in most systems with Bluetooth or USB) at 48kHz exactly. The other modes are useful if data is being provided to the DAC from an uncontrollable isochronous source (such as a CD player, DAB, or other external digital source) rather than being decoded from memory. In this case the PLL can be used to derive a clock for the DAC from the I2S clock. The DAC oversampling rate can be changed to allow simpler clocking strategies, this is controlled in the DAC SETUP register but the oversampling rates are as follows: TABLE 13. DAC MODE 00 01 10 11 Over sampling Ratio Used 125 128 64 32 The following table describes the clock required at the clock generator input for various clock sample rates in the different DAC modes: TABLE 14. Fs (kHz) 8 8 11.025 11.025 12 12 16 16 22.05 22.05 DAC Oversampling Ratio 125 128 125 128 125 128 125 128 125 128 Required CLock at DAC Clock Generator Input (MHz) 2 2.048 2.75625 2.8224 3 3.072 4 4.096 5.5125 5.6448 www.national.com 20 LM49321 Fs (kHz) 24 24 32 32 44.1 44.1 48 48 88.2 96 176.4 192 DAC Oversampling Ratio 125 128 125 128 125 128 125 128 64 64 32 32 Required CLock at DAC Clock Generator Input (MHz) 6 6.144 8 8.192 11.025 11.2896 12 12.288 11.2896 12.288 22.5792 24.576 Methods for producing these clock frequencies are described in the PLL section. The R divider can be used when the master clock is exactly 12.00 MHz in order to generate different sample rates. The Table below shows different sample rates supported from 12.00MHz by using only the R divider and disabling the PLL. In this way we can save power and the clock jitter will be low. TABLE 15. R_DIV 11 9 7 5 4 3 2 0 Divide Value 6 5 4 3 2.5 2 1.5 1 DAC Clock Generator Input Frequency 2 2.4 3 4 4.8 6 8 12 Sample Rate Supported 8 9.6 12 16 19.2 24 32 48 The R divider can also be used along with the P divider in order to create the clock needed to support low sample rates. PLL Configuration Registers PLL M DIVIDER CONFIGURATION REGISTER This register is used to control the input divider of the PLL. TABLE 16. PLL_M (0Ah) Bits 6:0 Register PLL_M Description Programs the PLL input divider to select: PLL_M 0000000 0000001 0000010 0000011 0000100 ... 1111110 Divide Ratio Divider Off 1 1.5 2 2.5 ... 63.5 NOTES: The M divider should be set such that the output of the divider is between 0.5 and 5MHz. See the PLL setup section for details. The division of the M divider is derived from PLL_M as such: M = (PLL_M+1) / 2 21 www.national.com LM49321 PLL N DIVIDER CONFIGURATION REGISTER This register is used to control PLL N divider. TABLE 17. PLL_N (0Bh) Bits 7:0 Register PLL_N PLL_N 00000000 00000001 →00001010 00001011 00001100 ... 11111000 11111001 Description Programs the PLL feedback divider: Divide Ratio Divider Off 10 11 12 ... 248 249 NOTES: The N divider should be set such that the output of the divider is between 0.5 and 5MHz. See the PLL setup section for details. The N divider should never be set so that (Fin/M) * N > 55MHz (or 80MHz if FAST_VCO is set in the PLL_N_MOD register). The non-sigma-delta division of the N divider is derived from the PLL_N as such: N = PLL_N Fin /M is often referred to as Fcomp (Frequency of Comparison) or Fref (Reference Frequency). In this document, Fcomp is used. PLL P DIVIDER CONFIGURATION REGISTER This register is used to control the PLL's P divider. TABLE 18. PLL_P Bits 3:0 Register PLL_P 0000 0001 0010 0011 ... 1101 1110 1111 Description Programs the PLL input divider to select: Divider Off 1 1.5 2 –> 2.5 7 7.5 8 NOTES: The output of this divider should be either 12 or 24MHz in USB mode or 11.2896MHz, 12.288MHz or 24.576MHz in non-USB modes. The division of the P divider is derived from PLL_P as such: P = (PLL_P+1) / 2 PLL N MODULATOR AND DITHER SELECT CONFIGURATION REGISTER This register is used to control the Fractional component of the PLL. TABLE 19. PLL_N_MOD (0Ch) Bits 4:0 Register PLL_N_MOD PLL_N_MOD 00000 00001 00010 → 11110 Description This programs the PLL N Modulator's fractional component: Fractional Addition 0/32 1/32 2/32 → 30/32 www.national.com 22 LM49321 Bits 6:5 Register DITHER_LEVEL DITHER_LEVEL 00 01 10 Description Allows control over the dither used by the N Modulator DAC Sub-system Input Source Medium (32) Small (16) Large (48) Maximum FVCO 40–55MHz 7 VCO_FAST If set the VCO maximum and minimum frequencies are raised: VCO_FAST 0 NOTES: The complete N divider is a fractional divider as such: N = PLL_N + (PLL_N_MOD/32) If the modulus input is zero, then the N divider is simply an integer N divider. The output from the PLL is determined by the following formula: Fout = (Fin * N) / (M * P) Please see over for more details on the PLL and common settings. 23 www.national.com LM49321 Further Notes on PLL Programming The sigma-delta PLL is designed to drive audio circuits requiring accurate clock frequencies of up to 25MHz with frequency errors noise-shaped away from the audio band. The 5 bits of modulus control provide exact synchronization of 48kHz and 44.1kHz sample rates from any common clock source when the oversampling rate of the audio system is 125fs. In systems where 128x oversampling must be used (for example with an isochronous I2S data stream) a clock synchronous to the sample rate should be used as input to the PLL (typically the I2S clock). If no isochronous source is available then the PLL can be used to obtain a clock that is accurate to within typical crystal tolerances of the real sample rate. 30061863 TABLE 20. Example Of PLL Settings For 48Khz Sample Rates f_in (MHz) 11 12 12.288 13 14.4 16.2 16.8 19.2 19.44 19.68 19.8 fsamp (kHz) 48 48 48 48 48 48 48 48 48 48 48 M 11 5 4 13 9 27 14 13 27 20.5 16.5 N 60 25 19.53125 60 37.5 100 50 40.625 100 62.5 50 P 5 5 5 5 5 5 5 5 6 5 5 PLL_M 21 9 7 25 17 53 27 25 53 40 32 PLL_N 60 25 19 60 37 100 50 40 100 62 50 PLL_N_MOD 0 0 17 0 16 0 0 20 0 16 0 PLL_P 9 9 9 9 9 9 9 9 11 9 9 f_out (MHz) 12 12 12 12 12 12 12 12 12 12 12 TABLE 21. Example PLL Settings For 44.1Khz Sample Rates f_in (MHz) 11 11.2896 12 13 14.4 16.2 16.8 19.2 19.44 19.68 19.8 fsamp (kHz) 44.1 44.1 44.1 44.1 44.1 44.1 44.1 44.1 44.1 44.1 44.1 M 11 8 5 13 12 9 17 16 13.5 20.5 11 N 55.125 39.0625 22.96875 55.125 45.9375 30.625 55.78125 45.9375 38.28125 45.9375 30.625 P 5 5 5 5 5 5 5 5 5 4 5 PLL_M 21 15 9 25 23 17 33 31 26 40 21 PLL_N 55 39 22 55 45 30 55 45 38 45 30 PLL_N_MOD 4 2 31 4 30 20 25 30 9 30 20 PLL_P 9 9 9 9 9 9 9 9 9 7 9 f_out (MHz) 11.025000 11.025000 11.025000 11.025000 11.025000 11.025000 11.025000 11.025000 11.025000 11.025000 11.025000 These tables cover the most common applications, obtaining clocks for sample rates such as 22.05kHz and 192kHz should be done by changing the P divider value or the R divider in the clock configuration diagram. www.national.com 24 LM49321 If the user needs to obtain a clock unrelated to those described above, the following method is advised. An example of obtaining 11.2896 from 12.000MHz is shown below. Choose a small range of P so that the VCO frequency is swept between 45 and 55MHz (or 60-80MHz if VCOFAST is used). Remembering that the P divider can divide by half integers. So for P = 4.0 → 7.0 sweep the M inputs from 2.5 → 24. The most accurate N and N_MOD can be calculated by: N = FLOOR(((Fout/Fin)*(P*M)),1) N_MOD = ROUND(32*((((Fout)/Fin)*(P*M)-N),0) This shows that setting M = 11.5, N = 75 N_MOD = 47 P = 7 gives a comparison frequency of just over 1MHz, a VCO frequency of just under 80MHz (so VCO_FAST must be set) and an output frequency of 11.289596 which gives a sample rate of 44.099985443kHz, or accurate to 0.33 ppm. Care must be taken when synchronization of isochronous data is not possible, i.e. when the PLL has to be used in the above mode. The I2S should be master on the LM49321 so that the data source can support appropriate SRC as required. This method should only be used with data being read on demand to eliminate sample rate mismatch problems. Where a system clock exists at an integer multiple of the required DAC clock rate it is preferable to use this rather than the PLL. The LM49321 is designed to work in 8,12,16,24,32, and 48kHz modes from a 12MHz clock without the use of the PLL. This saves power and reduces clock jitter. DAC Setup Register This register is used to configure the basic operation of the stereo DAC. TABLE 22. DAC_SETUP (0Eh)   Bits 1:0 Register DAC_MODE Description The DAC used in the LM49321 can operate in one of 4 oversampling modes. The modes are described as follows: DAC_MODE Oversampling Rate 125 128 64 32 Typical fS 48KHz 44.1KHz 48KHz 96KHz 192KHz MCLK Required 12.000MHz (USB Mode) 11.2896MHz 12.288MHz 12.288MHz 24.576MHz 00 01 10 11 2 3 4 5 6 MUTE_L MUTE_R DITHER_OFF DITHER ALWAYS_ON CUST_COMP Mutes the left DAC channel on the next zero crossing. Mutes the right DAC channel on the next zero crossing. If set the dither in DAC is disabled. If set the dither in DAC is enabled all the time. If set the DAC frequency response can be programmed manually via a 5 tap FIR “compensation” filter. This can be used to enhance the frequency response of small loudspeakers or provide a crude tone control. The compensation Coefficients can be set by using registers 10h to 15h. 25 www.national.com LM49321 Interface Control Register This register is used to control the I2S and I2C compatible interface on the chip. TABLE 23. INTERFACE (0Fh) Bits 0 Field I2S_MASTER_SLAVE Description This enables I2S in master or slave mode. I2S_MASTER_SLAVE Comments LM49321 acts as a slave where both I2S clock and word select are configured as inputs. LM49321 acts as a master for I2S, so both I2S clock and I2S word select are configured as outputs. 0 1 1 I2S_RESOLUTION This set the I2S resolution and affects the I2S Interface in master mode. In slave mode the I2S Interface can support any I2 S compatible resolution. In master mode the I2S resolution also depends on the DAC mode as the note below explains. I2S_RESOLUTION 0 1 Comments I2S resolution is set to 16 bits. I2S resolution is set to 32 bits. Comments I2S interface is configured in normal I2S mode timing. I2S is configured in left justified mode timing. Comments I2C speed gets its default value of a maximum of 400kHz. This enables the I2C to run in fast mode with an I2C clock up to 3.4MHz. 2 I2S_MODE This set the I2S mode timing. I2S_MODE 0 1 3 I2C_FAST This set the I2C Clock speed. I2C_FAST 0 1 NOTES: The master I2S format depends on the DAC mode. In USB mode the number of bits per word is 25 (i.e. 2.4MHz for a 48kHz sample rate). The duty cycle is 40/60. In non-USB modes the format is 32 or 16 bits per word, depending on I2S_RESOLUTION and the duty cycle is always 50-50. In slave mode it will decode any I2S compatible data stream. www.national.com 26 LM49321 30061827 I2S Mode Timing 30061828 Left Justified Mode Timing 27 www.national.com LM49321 FIR Compensation Filter Configuration Registers These registers are used to configure the DAC’s FIR compensation filter. Three 16 bit coefficients are required and must be programmed via the I2C/SPI Interface in bytes as follows: TABLE 24. COMP_COEFF (10h → 15h) Address 10h 11h 12h 13h 14h 15h Register COMP_COEFF0_LSB COMP_COEFF0_MSB COMP_COEFF1_LSB COMP_COEFF1_MSB COMP_COEFF2_LSB COMP_COEFF2_MSB Description Bits [7:0] of the 1st and 5th FIR tap (C0 and C4) Bits [15:8] of the 1st and 5th FIR tap (C0 and C4) Bits [7:0] of the 2nd and 4th FIR tap (C1 and C3) Bits [15:8] of the 2nd and 4th FIR tap (C1 and C3) Bits [7:0] of the 3rd FIR tap (C2) Bits [15:8] of the 3rd FIR tap (C2) NOTES: The filter must be phase linear to ensure the data keeps the correct stereo imaging so the second half of the FIR filter must be the reverse of the 1st half. 30061855 If the CUST_COMP option in register 0Eh is not set the FIR filter will use its default values for a linear response from the DAC into the analog mixer, these values are: DAC_OSR 00 01, 10, 11 C0, C4 434 61 C1, C3 –2291 –371 C2 26984 25699 If using 96 or 192kHz data then the custom compensation may be required to obtain flat frequency responses above 24kHz. The total power of any custom filter must not exceed that of the above examples or the filters within the DAC will clip. The coefficient must be programmed in 2’s complement. www.national.com 28 LM49321 Typical Performance Characteristics THD+N vs Frequency AVDD = 3.0V, EP Out, RL = 32Ω, PO = 20mW THD+N vs Frequency AVDD = 3.0V, HP Out, RL = 16Ω, PO = 20mW 30061864 30061865 THD+N vs Frequency AVDD = 3.0V, LS Out, RL = 8Ω, PO = 200mW THD+N vs Frequency AVDD = 5.0V, EP, RL = 32Ω, PO = 40mW 30061866 30061867 THD+N vs Frequency AVDD = 5.0V, HP Out, RL = 16Ω, PO = 60mW THD+N vs Frequency AVDD = 5.0V, HP Out, RL = 32Ω, PO = 30mW 30061869 30061870 29 www.national.com LM49321 THD+N vs Frequency AVDD = 5.0V, LS Out, RL = 8Ω, PO = 500mW THD+N vs Output Power AVDD = 3.0V, EP Out, RL = 16Ω, f = 1kHz 30061871 30061872 THD+N vs Output Power AVDD = 3.0V, EP Out, RL = 32Ω, f = 1kHz THD+N vs Output Power AVDD = 3.0V, HP Out, RL = 16Ω, f = 1kHz 30061873 30061876 THD+N vs Output Power AVDD = 3.0V, HP Out, RL = 32Ω, f = 1kHz THD+N vs Output Power AVDD = 3.0V, LS Out, RL = 8Ω, f = 1kHz 30061877 30061819 www.national.com 30 LM49321 THD+N vs Output Power AVDD = 5.0V, EP Out, RL = 16Ω, f = 1kHz THD+N vs Output Power AVDD = 5.0V, EP Out, RL = 32Ω, f = 1kHz 30061878 30061879 THD+N vs Output Power AVDD = 5.0V, HP Out, RL = 16Ω, f = 1kHz THD+N vs Output Power AVDD = 5.0V, HP Out, RL = 32Ω, f = 1kHz 30061880 30061881 THD+N vs Output Power AVDD = 5.0V, LS Out, RL = 8Ω, f = 1kHz THD+N vs I2S Level EP Out 30061882 30061883 31 www.national.com LM49321 THD+N vs I2S Level HP Out THD+N vs I2S Level LS Out 30061884 30061885 PSRR vs Frequency AVDD = 3.0V, EP Out Mode 1 PSRR vs Frequency AVDD = 3.0V, EP Out Mode 4 30061886 30061887 PSRR vs Frequency AVDD = 3.0V, HP Out Mode 2 PSRR vs Frequency AVDD = 3.0V, HP Out Mode 4 30061888 30061889 www.national.com 32 LM49321 PSRR vs Frequency AVDD = 3.0V, LS Out Mode 2 PSRR vs Frequency AVDD = 3.0V, LS Out Mode 4 30061890 30061891 PSRR vs Frequency AVDD = 5.0V, HP Out Mode 2 PSRR vs Frequency AVDD = 5.0V, HP Out Mode 4 30061892 30061893 PSRR vs Frequency AVDD = 5.0V, LS Out Mode 4 PSRR vs Frequency AVDD = 5.0V, LS Out Mode 2 30061894 30061895 33 www.national.com LM49321 Output Power vs Supply Voltage EP Out , RL = 32Ω, 1% THD+N Output Power vs Supply Voltage HP Out , RL = 32Ω, 1% THD+N 30061896 30061897 Output Power vs Supply Voltage LS Out , RL = 8Ω, 1% THD+N 30061898 www.national.com 34 LM49321 Application Information I2S The LM49321 supports both master and slave I2S transmission at either 16 or 32 bits per word at clock rates up to 3.072MHz (48kHz stereo, 32bit). The basic format is shown below: 30061807 FIGURE 1. MONO ONLY SETTING The LM49321 may be restricted to mono amplification only by setting MONO_ONLY in Output Control register 0x01h to 1. This may save an additional 400μA from IDD. LM49321 DEMOBOARD OPERATION BOARD LAYOUT DIGITAL SUPPLIES JP14 — Digital Power DVDD JP10 — I/O Power IOVDD JP13 — PLL Supply PLLVDD JP16 — USB Board Supply BBVDD JP15 — I2CVDD All supplies may be set independently. All digital ground is common. Jumpers may be used to connect all the digital supplies together. S9 – connects VDD_PLL to VDD_D S10 – connects VDD_D to VDD_IO S11 – connects VDD_IO to VDD_I2C S12 – connects VDD_I2C to Analog VDD S17 – connects BB_VDD to USB3.3V (from USB board) S19 – connects VDD_D to USB3.3V (from USB board) S20 – connects VDD_D to SPDIF receiver chip ANALOG SUPPLY JP11 — Analog Supply  S12 — connects Analog VDD with Digital VDD (I2C_VDD)  S16 — connects Analog Ground with Digital Ground  S21 — connects Analog VDD to SPDIF receiver chip INPUTS Analog Inputs JP2 — Mono Differential Input JP6 — Left Input JP7 — Right Input Digital Inputs JP19 — Digital Interface  Pin 1 — MCLK  Pin 2 — I2S_CLK  Pin 3 — I2S_SDI 35  Pin 4 — I2S_WS JP20 — Toslink SPDIF Input JP21 — Coaxial SPDIF Input Coaxial and Toslink inputs may be toggled between by use of S25. Only one may be used at a time. Must be used in conjunction with on-board SPDIF receiver chip. OUTPUTS JP5 — BTL Loudspeaker Output JP1 — Left Headphone Output (Single-Ended or OCL) JP3 — Right Headphone Output (Single-Ended or OCL) P1 — Stereo Headphone Jack (Same as JP1, JP2, SingleEnded or OCL) JP12 — Mono BTL Earpiece Output CONTROL INTERFACE X1, X2 – USB Control Bus for I2C/SPI X1 Pin 9 – Mode Select (SPI or I2C) X2 Pin 1 – SDA Pin 3 – SCL Pin 15 – ADDR/END Pin 14 – USB5V Pin 16 – USB3.3V Pin 16 – USB GND MISCELLANEOUS I2S BUS SELECT S23, S24, S26, S27 – I2S Bus select. Toggles between onboard and external I2S (whether on-board SPDIF receiver is used). All jumpers must be set the same. Jumpers on top two pins selects external bus (JP19). Jumpers on bottom two pins selects on-board SPDIF receiver output. HEADPHONE OUTPUT CONFIGURATION Jumpers S1, S2, S3, and S4 are used to configure the headphone outputs for either cap-coupled outputs or output capacitorless (OCL) mode in addition to the register control internal to the LM49321 for this feature. Jumpers S1 and S3 bypass the output DC blocking capacitors when OCL mode www.national.com LM49321 is required. S2 connects the center amplifier HPCOUT to the headphone ring when in OCL mode. S4 connects the center ring to GND when cap-coupled mode is desired. S4 must be removed for OCL mode to function properly. Jumper settings for each mode: OCL S1 = ON S2 = ON S3 = ON S4 = OFF Cap-Coupled S1 = OFF S2 = OFF S3 = OFF S4 = ON PLL FILTER CONFIGURATION The LM49321 demo board comes with a simple filter setup by connecting jumpers S5 and S6. Removing these and connecting jumpers S7 and S8 will allow for an alternate PLL filter configuration to be used at R2 and C23. ON-BOARD SPDIF RECEIVER The SPDIF receiver present on the LM49321 demo board allows quick demonstration of the capabilities of the LM49321 by using the common SPDIF output found on most CD/DVD players today. There are some limitations in its useage, as the receiver will not work with digital supplies of less than 3.0V and analog supplies of less than 4V. This means low analog supply voltage testing of the LM49321 must be done on the external digital bus. The choice of using on-board or external digital bus is made usign jumpers S23, S24, S26, and S27 as described above. S25 selects whether the Toslink or Coaxial SPDIF input is used. The top two pins connects the toslink, the bottom two connect the coaxial input. Power on the digital side is routed through S20 (connecting to the other digital supplies), while on the analog side it is interrupted by S21. Both jumpers must be in place for the receiver to function. The part is already configured for I2S standard outputs. Jumper S28 allows the DATA output to be pulled either high or low. Default is high (jumper on right two pins). It may be necessary to quickly toggle S29 to reset the receiver and start it working upon initial power up. A quick short across S29 should clear this condition. LM49321 I2C/SPI INTERFACE SOFTWARE Convenient graphical user interface software is available for demonstration purposes of the LM49321. It allows for either SPI or I2C control via either USB or parallel port connections to a Windows computer. Control options include all mode and output settings, volume controls, PLL and DAC setup, FIR setting and on-the-fly adjustment by an easy to use graphical interface. An advanced option is also present to allow direct, register-level commands. Software is available from www.national.com and is compatible with Windows operating systems of Windows 98 or more (with USB support) with the latest .NET updates from Microsoft. www.national.com 36 LM49321 Demonstration Board Schematic 30061803 37 Complete Board Schematic www.national.com LM49321 www.national.com 300618k6 38 Enlarged Board Schematic Part 1 of 2 LM49321 39 300618k7 www.national.com Enlarged Board Schematic Part 2 of 2 LM49321 Revision History Rev 1.0 1.01 1.02 Date 09/10/08 09/23/08 08/31/09 Initial release. Text edits. Edited the package drawing and the top markings. Description www.national.com 40 LM49321 Physical Dimensions inches (millimeters) unless otherwise noted 36-Bump micro SMD Order Number LM49321RL NS Package Number RLA36LVA X1 = 3255±30μm, X2 = 3510±30μm, X3 = 650±75μm 41 www.national.com LM49321 Audio Sub-System with Stereo DAC, Mono Class AB Loudspeaker Amplifier, OCL/SE Stereo Headphone Output and RF Suppression Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Amplifiers Audio Clock and Timing Data Converters Interface LVDS Power Management Switching Regulators LDOs LED Lighting Voltage Reference PowerWise® Solutions Temperature Sensors Wireless (PLL/VCO) www.national.com/amplifiers www.national.com/audio www.national.com/timing www.national.com/adc www.national.com/interface www.national.com/lvds www.national.com/power www.national.com/switchers www.national.com/ldo www.national.com/led www.national.com/vref www.national.com/powerwise WEBENCH® Tools App Notes Reference Designs Samples Eval Boards Packaging Green Compliance Distributors Quality and Reliability Feedback/Support Design Made Easy Solutions Mil/Aero PowerWise® Design University Design Support www.national.com/webench www.national.com/appnotes www.national.com/refdesigns www.national.com/samples www.national.com/evalboards www.national.com/packaging www.national.com/quality/green www.national.com/contacts www.national.com/quality www.national.com/feedback www.national.com/easy www.national.com/solutions www.national.com/milaero www.national.com/solarmagic www.national.com/training Serial Digital Interface (SDI) www.national.com/sdi www.national.com/wireless www.national.com/tempsensors SolarMagic™ THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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