LM4934

LM4934 3D Audio Sub-System with Stereo Speaker, OCL/SE Stereo Headphone, Earpiece and Mono Line Level Outputs February 2006 LM4934 3D Audio Sub-System with Stereo Speaker, OCL/SE Stereo Headphone, Earpiece and Mono Line Level Outputs General Description The LM4934 is an integrated audio sub-system designed for stereo cell phone applications. Operating on a 3.3V supply, it combines a stereo speaker amplifier delivering 520mW per channel into an 8Ω load, a stereo headphone amplifier delivering 36mW per channel into a 32Ω load, a mono earpiece amplifier delivering 55mW into a 32Ω load, and a line output for an external powered handsfree speaker. It integrates the audio amplifiers, volume control, mixer, power management control, and National 3D enhancement all into a single package. In addition, the LM4934 routes and mixes the stereo and mono inputs into multiple distinct output modes. The LM4934 features an I2S serial interface for full range audio and an I2C/SPI compatible interface for control. Boomer audio power amplifiers are designed specifically to provide high quality output power with a minimal amount of external components. Key Specifications j POUT, Stereo BTL, 8Ω, 3.3V, 1% THD+N j POUT HP, 32Ω, 3.3V, 1% THD+N j POUT Mono Earpiece, 32Ω, 3.3V, 520mW (typ) 36mW (typ) 55mW (typ) 0.6µA (typ) 95dB (typ) 1% THD+N j Shutdown current j DAC SNR Features n n n n n n n n n n n 18-bit stereo DAC Multiple distinct output modes Stereo speaker amplifier Stereo headphone amplifier Mono earpiece amplifier Mono Line Output for external handsfree carkit Independent Left, Right, headphone and Mono speaker volume controls National 3D enhancement with programmable effect level I2C/SPI (selectable) compatible interface Ultra low shutdown current Click and Pop Suppression circuit Applications n Cell Phones n PDAs Boomer ® is a registered trademark of National Semiconductor Corporation. © 2006 National Semiconductor Corporation DS201669 www.national.com LM4934 Block Diagram 20166949 FIGURE 1. Audio Sub-System Block Diagram with OCL HP Outputs 201669J7 FIGURE 2. Audio Sub-System with SE HP Outputs www.national.com 2 LM4934 Connection Diagrams 42-Bump Micro SMDxt 20166958 Top View (Bump Side Down) Order Number LM4934RL See NS Package Number RLA42 Top Marking Drawing 201669B7 Top View XY — 2 Digit Date Code TT — Traceability G — Boomer Family G9 — LM4934RL I — Pin 1 Marking Pin Descriptions PIN A1 A2 A3 A4 A5 A6 B1 B2 B3 B4 B5 B6 C1 C2 C3 C4 C5 C6 PIN NAME DGND MCLK I2S_WS GPIO ADDR/ENB DVDD PLLVDD I2S_SDI I2S_CLK MODE I2C_VDD VDDIO PLL_IN PLL_OUT PLLGND SDA/SDI SCL/SCK AVDD D/A D D D D D D D D D D D D D D D D D A I/O P I I/O O I P P I I/O I P P I O P I/O I P DESCRIPTION DIGITAL GROUND MASTER CLOCK I2S WORD SELECT TEST PIN (MUST BE LEFT FLOATING) I2C_ADDR OR SPI_ENB DEPENDING ON I2C or SPI MODE SELECT DIGITAL SUPPLY VOLTAGE PLL SUPPLY VOLTAGE I2S SERIAL DATA INPUT I2S CLOCK SIGNAL SELECTS BETWEEN SPI AND I2C CONTROL INTERFACE I2C SUPPLY VOLTAGE I/O SUPPLY VOLTAGE PLL FILTER INPUT PLL FILTER OUTPUT PLL GND I2C SDA OR SPI SDI I2C_SCL OR SPI_SCK ANALOG SUPPLY VOLTAGE 3 www.national.com LM4934 Pin Descriptions D1 D2 D3 D4 D5 D6 E1 E2 E3 E4 E5 E6 F1 F2 F3 F4 F5 F6 G1 G2 G3 G4 G5 G6 AGND RIN NC BYPASS LINEOUT RHP EPMIN LIN R3DOUT LHP CHP AGND EP+ L3DIN L3DOUT R3DIN AGND LLSAVDD LLS+ RLSAVDD RLS+ (Continued) A A A A A A A A A A A A A A A A A A A A A A A A I O O O I I I O O P O I I I P O P O O P O P I ANALOG GROUND RIGHT ANALOG IN NO CONNECT HALF-SUPPLY BYPASS MONO LINE OUT RIGHT HEADPHONE OUTPUT MONO EARPIECE OUTMONO ANALOG IN LEFT ANALOG IN RIGHT CHANNEL 3D OUTPUT LEFT HEADPHONE OUTPUT HEADPHONE CENTER PIN OUTPUT (1/2 VDD) ANALOG GND MONO EARPIECE OUT+ LEFT CHANNEL 3D INPUT LEFT CHANNEL 3D OUTPUT RIGHT CHANNEL 3D INPUT ANALOG GND LEFT SPEAKER OUTANALOG SUPPLY VOLTAGE LEFT SPEAKER OUT+ RIGHT SPEAKER OUTANALOG SUPPLY VOLTAGE RIGHT SPEAKER OUT+ www.national.com 4 LM4934 Absolute Maximum Ratings (Notes 1, 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Analog Supply Voltage Digital Supply Voltage Storage Temperature Input Voltage Power Dissipation (Note 3) ESD Susceptibility (Note 4) ESD Susceptibility(Note 5) Junction Temperature Thermal Resistance 6.0V 6.0V -65˚C to +150˚C -0.3V to VDD +0.3V Internally Limited 2000V 200V 150˚C θJA (RLA42) See AN-1279 61˚C/W Operating Ratings Temperature Range TMIN ≤ TA ≤ TMAX Supply Voltage 2.7V ≤ AVDD ≤ 5.5V 2.7V ≤ DVDD ≤ 4.0V 2.4V ≤ I2CVDD ≤ 4.0V −40˚C ≤ TA ≤ +85˚C Audio Amplifier Electrical Characteristics AVDD = 3.0V, DVDD = 3.0V (Notes 1, 2) The following specifications apply for the circuit shown in Figure 1 with all programmable gain set at 0dB, unless otherwise specified. Limits apply for TA = 25˚C. Symbol Parameter Conditions LM4934 Typical (Note 6) Limits (Notes 7, 8) 26.5 8 19.5 8 22 2 370 24 40 Units (Limits) VIN = 0, No Load All Amps On + DAC, OCL IDD Supply Current Headphone Mode Only, OCL Stereo Speaker Mode Only Mono Speaker Mode Only DAC Off, All Amps On, OCL ISD Shutdown Current Speaker; THD = 1%; f = 1kHz, 8Ω BTL PO Output Power Headphone; THD = 1%; f = 1kHz, 32Ω SE Earpiece; THD = 1%; f = 1kHz, 32Ω BTL VFS DAC Full Scale DAC Output Speaker; PO = 200mW; f = 1kHz, 8Ω BTL THD+N Total Harmonic Distortion Headphone; PO = 10mW; f = 1kHz, 32Ω SE Earpiece; PO = 20mW; f = 1kHz, 32Ω BTL Line Out; VO = 1Vrms; f = 1kHz, 10kΩ SE Speaker VOS ∈O PSRR Offset Voltage Output Noise Power Supply Rejection Ratio Earpiece HP (OCL) A = weighted; 0dB gain; See Table 1 f = 217Hz; Vripple = 200mVP-P CB = 2.2µF; See Table 2 18.5 5.6 12 5.9 14.6 0.6 420 27 45 2.4 0.04 0.01 0.04 0.004 8 8 8 Table 1 mA (max) mA (max) mA (max) mA (max) mA (max) µA (max) mW (min) mW (min) mW (min) Vpp % % % % 55 50 40 mV (max) mV (max) mV Table 2 5 www.national.com LM4934 Audio Amplifier Electrical Characteristics AVDD = 3.0V, DVDD = 3.0V (Notes 1, 2) (Continued) The following specifications apply for the circuit shown in Figure 1 with all programmable gain set at 0dB, unless otherwise specified. Limits apply for TA = 25˚C. Symbol Parameter Conditions LM4934 Typical (Note 6) Limits (Notes 7, 8) Units (Limits) Loudspeaker; PO= 200mW f = 1kHz Xtalk Crosstalk Headphone; PO= 10mW f = 1kHz; SE Headphone; PO= 10mW f = 1kHz; OCL TWU Wake-Up Time CB = 2.2µF, CD6 = 0 CB = 2.2µF, CD6 = 1 –84 –85 –60 35 85 dB dB dB ms ms Audio Amplifier Electrical Characteristics AVDD = 5.0V, DVDD = 3.3V (Notes 1, 2) The following specifications apply for the circuit shown in Figure 1 with all programmable gain set at 0dB, unless otherwise specified. Limits apply for TA = 25˚C. Symbol Parameter Conditions LM4934 Typical (Note 6) Limits (Notes 7, 8) Units (Limits) VIN = 0, No Load All Amps On - DAC IDD Supply Current Headphone Mode Only Stereo Speaker Mode Only Mono Speaker Mode Only DAC Off, All Amps On ISD Shutdown Current Speaker; THD = 1%; f = 1kHz, 8Ω BTL PO Output Power Headphone; THD = 1%; f = 1kHz, 32Ω SE Earpiece; THD = 1%; f = 1kHz, 32Ω BTL VFS DAC Full Scale DAC Output Speaker; PO = 500mW; f = 1kHz, 8Ω BTL THD+N Total Harmonic Distortion Headphone; PO = 30mW; f = 1kHz, 32Ω SE Earpiece; PO = 40mW; f = 1kHz, 32Ω BTL; CD4 = 0 Line Out; VO = 1Vrms; f = 1kHz, 10kΩ SE Speaker VOS ∈O Offset Voltage Output Noise Earpiece HP (OCL) A = weighted; 0dB gain; See Table 1 24 5.8 17 7 19 1.6 1.2 80 175 2.4 0.03 0.01 0.04 0.003 8 8 8 Table 1 mA (max) mA mA mA mA µA W mW mW Vpp % % % % mV mV mV www.national.com 6 LM4934 Audio Amplifier Electrical Characteristics AVDD = 5.0V, DVDD = 3.3V (Notes 1, 2) (Continued) The following specifications apply for the circuit shown in Figure 1 with all programmable gain set at 0dB, unless otherwise specified. Limits apply for TA = 25˚C. Symbol Parameter Conditions LM4934 Typical (Note 6) Limits (Notes 7, 8) Units (Limits) PSRR Power Supply Rejection Ratio f = 217Hz; Vripple = 200mVP-P CB = 2.2µF; See Table 3 Loudspeaker; PO= 400mW f = 1kHz Table 3 –86 –56 –80 45 130 dB dB dB ms ms Xtalk Crosstalk Headphone; PO= 15mW f = 1kHz; OCL Headphone; PO= 15mW f = 1kHz, SE TWU Wake-Up Time CB = 2.2µF, CD6 = 0 CB = 2.2µF, CD6 = 1 Volume Control Electrical Characteristics (Notes 1, 2) The following specifications apply for 3V ≤ AVDD ≤ 5V and 2.7V ≤ DVDD ≤ 4.0V, unless otherwise specified. Limits apply for TA = 25˚C. Symbol Parameter Conditions LM4934 Typical (Note 6) Limits (Notes 7, 8) –6.5 –5.5 15.5 14.5 –56.5 –55.5 4.5 5.5 Units (Limits) PGR Stereo or Mono Analog Inputs PreAmp Gain Setting Range minimum gain setting maximum gain setting minimum gain setting, Vol = 00001 maximum gain setting –6 15 –56 5 0.3 dB (min) dB (max) dB (max) dB (min) dB (min) dB (max) dB (min) dB (max) dB VCR Output Volume Control for Stereo Speakers, Headphone Output, or Mono Output Range Stereo Channel to Channel Gain Mismatch ∆ACH-CH AMUTE Mute Attenuation Vin = 1Vrms, Gain = 0dB with load, Vol = 00000 Headphone Line Out < -90 < -90 23 18 28 dB dB kΩ (min) kΩ (max) RINPUT MIN, LIN and RIN Input Impedance 7 www.national.com LM4934 Digital Section Electrical Characteristics (Notes 1, 2) The following specifications apply for 3V ≤ AVDD ≤ 5V and 2.7V ≤ DVDD ≤ 4.0V, unless otherwise specified. Limits apply for TA = 25˚C. Symbol Parameter Conditions LM4934 Typical (Note 6) Limits (Notes 7, 8) Units (Limits) DISD DIDD PLLIDD RDAC PBDAC SBADAC DRDAC Digital Shutdown Current Digital Power Supply Current PLL Quiescent Current Audio DAC Ripple Audio DAC Passband width Audio DAC Stop band Attenuation Audio DAC Dynamic Range Audio DAC-AMP Signal to Noise Ratio Mode 0, DVDD = 3.0V No MCLK fMCLK = 12MHz, DVDD = 3.0V ALL MODES EXCEPT 0 fMCLK = 12MHz, DVDD = 3.0V 20Hz - 20kHz through headphone output -3dB point Above 24kHz DC - 20kHz, –60dBFS; AES17 Standard See Table 4 A-Weighted, Signal = VO at 0dBFS, f = 1kHz Noise = digital zero, A-weighted, See Table 4 A-weighted (Note 10) 5.3 4.8 +/-0.1 22.6 76 Table 4 8 6 mA mA dB kHz dB dB 0.01 1 µA Audio DAC (Typical numbers are with 6.144MHz audio clock and 48kHz sampling frequency SNR Table 4 dB SNRDAC PLL fIN SPI/I2C fSPI tSPISETD tSPISETENB tSPIHOLDD tSPIHOLDENB tSPICL tSPICH fCLKI2C tI2CHOLD tI2CSET VIH VIL I2S fCLKI2S Internal DAC SNR 95 10 26 4000 100 100 100 100 125 125 400 100 100 I2CVDD 0 0.7 x I2CVDD 0.3 x I2CVDD 6144 12288 40 0.7 x DVDD 0.3 x DVDD dB Input Frequency on MCLK pin 12 MHz Maximum SPI Frequency SPI Data Setup Time SPI ENB Setup Time SPI Data Hold Time SPI ENB Hold Time SPI Clock Low Time SPI Clock High Time I2C_CLK Frequency I2C_DATA Hold Time I C_DATA Setup Time I2C/SPI Input High Voltage I2C/SPI Input Low Voltage 2 kHz (max) ns (max) ns (max) ns (max) ns (max) ns (max) ns (max) kHz (max) ns (max) ns (max) V (min) V (max) I2S_CLK Frequency I2S_WS Duty Cycle I2S_RES = 0 I2S_RES = 1 1536 3072 50 kHz (max) % V (min) V (max) VIH VIL Digital Input High Voltage Digital Input Low Voltage Note 1: All voltages are measured with respect to the GND pin unless otherwise specified. www.national.com 8 LM4934 Note 2: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional but do not guarantee specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which guarantee specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not guaranteed for parameters where no limit is given, however, the typical value is a good indication of device performance. Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX ,θJA, and the ambient temperature, TA. The maximum allowable power dissipation is PDMAX = (TJMAX – TA) / θ JA or the number given in Absolute Maximum Ratings, whichever is lower. Note 4: Human body model: 100pF discharged through a 1.5kΩ resistor. Note 5: Machine model: 220pF - 240pF discharged through all pins. Note 6: Typicals are measured at 25˚C and represent the parametric norm. Note 7: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). Note 8: Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. Note 9: Shutdown current is measured in a normal room environment. Note 10: Internal DAC only with DAC modes 00 and 01. TABLE 1. Output Noise Output Noise AVDD = 5V and AVDD = 3V. All gains set to 0dB. Units in µV. A - weighted MODE 1 2 3 4 5 6 7 EP 22 22 22 68 38 29 38 LS 22 22 22 88 48 34 48 HP OCL or SE 11 11 11 46 24 18 24 Lineout 9 9 9 35 20 15 20 Units µV µV µV µV µV µV µV TABLE 2. PSRR AVDD = 3V PSRR AVDD = 3V. f = 217Hz; Vripple = 200mVp-p; CB = 2.2µF. MODE EP (Typ) 69 69 69 63 69 69 69 LS (Typ) 71 71 71 62 68 70 68 67 LS (Limit) HP OCL or SE (Typ) 72 72 72 55 61 64 61 68 HP OCL or SE (Limit) Lineout (Typ) 70 70 70 68 69 70 69 Units 1 2 3 4 5 6 7 dB dB dB dB dB dB dB TABLE 3. PSRR AVDD = 5V PSRR AVDD = 5V. All gains set to 0dB. f = 217Hz; Vripple = 200mVp-p; CB = 2.2µF MODE 1 2 3 4 5 6 7 EP (Typ) 68 68 68 68 68 69 68 LS (Typ) 72 72 72 66 69 72 69 HP OCL or SE (Typ) 71 71 71 69 70 71 70 Lineout (Typ) 70 70 70 70 70 71 70 Units dB dB dB dB dB dB dB TABLE 4. Dynamic Range and SNR Dynamic Range and SNR. 3V ≤ AVDD ≤ 5V. All programmable gain set to 0dB. Units in dB. DR (Typ) LS Lineout 95 100 SNR (Typ) 85 87 Units dB dB 9 www.national.com LM4934 TABLE 4. Dynamic Range and SNR (Continued) Dynamic Range and SNR. 3V ≤ AVDD ≤ 5V. All programmable gain set to 0dB. Units in dB. DR (Typ) HP EP 95 97 SNR (Typ) 85 87 Units dB dB www.national.com 10 LM4934 System Control The LM4934 is controlled via either a three wire SPI or a two wire I2C compatible interface, selectable with the MODE pin. When MODE is cleared the device is in I2C mode, when MODE is set the device is in SPI mode. This interface is used to configure the operating mode, interfaces, data converters, mixers and amplifiers. The LM4934 is controlled by writing 8 bit data into a series of write-only registers, the device is always a slave for both type of interfaces. THREE WIRE, SPI INTERFACE (MODE = 1) Three Wire Mode Write Bus Transaction 20166959 Three Wire Mode Write Bus Timing 20166960 FIGURE 3. Three Wire Mode Write Bus When the part is configured as an SPI device and the enable (ENB) line is lowered the serial data on SDI is clocked in on the rising edge of the SCK line. The protocol used is 16bit, MSB first. The upper 8 bits (15:8) are used to select an address within the device, the lower 8 bits (7:0) contain the updated data for this register. TWO WIRE I2C COMPATIBLE INTERFACE (MODE = 0) Two Wire Mode Write Bus Transaction 201669J6 Two Wire Mode Write Bus Timing 20166962 FIGURE 4. Two Wire Mode Write Bus 11 www.national.com LM4934 System Control (Continued) When the part is configured as an I2C device then the LM4934 will respond to one of two addresses, according to the ADDR input. If ADDR is low then the address portion of the I2C transaction should be set to write to 0010000. When ADDR is high then the address input should be set to write to 1110000. TABLE 5. Chip Address A6 Chip Address ADR = 0 ADR = 1 EC 0 1 A5 EC 0 1 A4 1 1 1 A3 0 0 0 A2 0 0 0 A1 0 0 0 A0 0 0 0 EC — Externally configured by ADR pin www.national.com 12 System Control TABLE 6. Control Registers D7 0 0 0 3D_LEVEL_1 3D_LEVEL_0 LS_L_VOL_4 LS_L_VOL_3 LS_L_VOL_2 0 MONO_VOL_4 MONO_VOL_3 MONO_VOL_2 0 HP_R_ OUTPUT LS_L_VOL_1 HP_L_ OUTPUT LS_R_ OUTPUT LS_L_ OUTPUT MONO_ OUTPUT CD_6 0 OCL CD_3 CD_2 CD_1 CD_0 LINEOUT_ OUTPUT LS_L_VOL_0 D6 D5 D4 D3 D2 D1 D0 (Continued) Address Register 00h Mode Control 01h Output Control 02h 0 Mono Volume Control 0 MONO_VOL_1 MONO_VOL_0 03h Loud Speaker LeftVolume and 3D Gain 0 3D_MODE 3D_ENABLE LS_R_VOL_4 LS_R_VOL_3 LS_R_VOL_2 04h Loud Speaker RightVolume and 3D Control 0 0 0 DIG_R_ GAIN_1 R_DIV_2 PLL_M_6 PLL_N_6 PLL_DITH_LEV_0 0 DITHER_ALW_ON 0 COMP0_5 COMP0_13 COMP1_5 0 DITHER_OFF 0 COMP0_4 COMP0_12 COMP1_4 PLL_N_5 PLL_N_4 PLL_N_MOD_4 PLL_M_5 PLL_M_4 R_DIV_1 R_DIV_0 DIG_R_ GAIN_0 DIG_L_ GAIN_1 DIG_L_ GAIN_0 PLL_ ENABLE PLL_M_3 PLL_N_3 0 0 0 HP_R_VOL_4 HP_R_VOL_3 0 0 HP_L_VOL_4 HP_L_VOL_3 HP_L_VOL_2 HP_R_VOL_2 LS_R_VOL_1 LS_R_VOL_0 05h Headphone Left Volume Control HP_L_VOL_1 HP_R_VOL_1 HP_L_VOL_0 HP_R_VOL_0 06h Headphone Right Volume Control ANA_R_ GAIN_2 ANA_R_ GAIN_1 ANA_R_ GAIN_0 07h LM4934 13 Analog R & L Input Gain Control ANA_L_ GAIN_2 MONO_IN_ GAIN_2 AUDIO _CLK_SEL PLL_M_2 PLL_N_2 ANA_L _GAIN_1 MONO_IN_ GAIN_1 PLL_INPUT PLL_M_1 PLL_N_1 ANA_L _GAIN_0 MONO_IN_ GAIN_0 FAST_ CLOCK PLL_M_0 PLL_N_0 08h R_DIV_3 0 PLL_N_7 VCO_FAST PLL_DITH_LEV_1 0 0 0 COMP0_6 0 CUST_COMP 0 Analog Mono & DAC 0 Input Gain Control 09h Clock Configu ration 0Ah PLL M Divider 0Bh PLL N Divider 0Ch PLL N_MOD Divider and Dither Level PLL_N_MOD_3 PLL_N_MOD_2 PLL_P_3 MUTE_R I2C_FAST COMP0_3 COMP0_11 COMP1_3 PLL_P_2 MUTE_L I2S_MODE COMP0_2 COMP0_10 COMP1_2 PLL_N_MOD_1 PLL_N_MOD_0 PLL_P_1 I2S_RESOL COMP0_1 COMP0_9 COMP1_1 PLL_P_0 DAC_MODE_1 DAC_MODE_0 I2S_M/S COMP0_0 COMP0_8 COMP1_0 0Dh PLL_P Divider 0Eh DAC Setup 0Fh Interface 10h COMPENSATION _C COMP0_7 OEFF0_LSB 11h COMP1_6 COMPENSATION _C COMP0_15 COMP0_14 OEFF0_MSB www.national.com 12h COMPENSATION _C COMP1_7 OEFF1_LSB LM4934 System Control TABLE 6. Control Registers (Continued) D7 COMP1_13 COMP2_5 COMP2_13 RESERVED RESERVED RESERVED RESERVED COMP2_12 COMP2_11 COMP2_10 COMP2_4 COMP2_3 COMP2_2 COMP2_1 COMP2_9 RESERVED COMP1_12 COMP1_11 COMP1_10 COMP1_9 D6 D5 D4 D3 D2 D1 D0 (Continued) www.national.com Address Register 13h COMP2_6 COMPENSATION _C COMP1_15 COMP1_14 OEFF1_MSB COMP1_8 COMP2_0 COMP2_8 RESERVED 14h COMPENSATION _C COMP2_7 OEFF2_LSB 15h RESERVED RESERVED COMPENSATION _C COMP2_15 COMP2_14 OEFF2_MSB 16h TEST_ REGISTER Note: All registers default to 0 on initial power-up. 14 LM4934 System Controls TABLE 7. Stereo or Mono, Left or Right Volume Control MONO_VOL_4, LS_L_VOL_4, LS_R_VOL_4, HP_L_VOL_4, HP_R_VOL_4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 MONO_VOL_3, LS_L_VOL_3, LS_R_VOL_3, HP_L_VOL_3, HP_R_VOL_3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 MONO_VOL_2, LS_L_VOL_2, LS_R_VOL_2, HP_L_VOL_2, HP_R_VOL_2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 MONO_VOL_1, LS_L_VOL_1, LS_R_VOL_1, HP_L_VOL_1, HP_R_VOL_1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 MONO_VOL_0, LS_L_VOL_0, LS_R_VOL_0, HP_L_VOL_0, HP_R_VOL_0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Gain (dB) Mute –56 –52 –48 –45 –42 –39 –36 –33 –30 –28 –26 –24 –22 –20 –18 –16 –14 –12 –10 –8 –6 –4 –3 –2 –1 0 +1 +2 +3 +4 +5 15 www.national.com LM4934 System Controls Mode 0 1 2 3 4 5 6 7 CD3 0 1 1 1 1 1 1 1 CD2 0 0 0 0 1 1 1 1 (Continued) TABLE 8. Mixer Code Control CD1 0 0 1 1 0 0 1 1 CD0 0 1 0 1 0 1 0 1 Mono Lineout SD M AL+AR M+AL+AR DL+DR DL+DR+ AL+AR M+DL+AL+ DR+AR M+DL+DR Mono Earpiece SD M AL+AR M+AL+AR DL+DR DL+DR+ AL+AR LoudLoud- Headphone Speaker L Speaker R L SD M AL M+AL DL DL+AL SD M AR M+AR DR DR+AR SD M AL M+AL DL DL+AL Headphone R SD M AR M+AR DR DR+AR M+DR+AR M+DR M+DL+AL+ M+DL+AL M+DR+AR M+DL+AL DR+AR M+DL+DR M+DL M+DR M+DL SD — Shutdown M — Mono Input AL — Analog Left Channel AR — Analog Right Channel DL — I2S DAC Left Channel DR — I2S DAC Right Channel MUTE — Mute Note: Power-On Default Mode is Mode 0 www.national.com 16 LM4934 System Controls Loudspeaker Left Channel (Continued) TABLE 9. Output Control (01h) LS_L_OUTPUT = 1 Output On LS_R_OUTPUT = 1 Output On HP_L_OUTPUT = 1 Output On HP_R_OUTPUT = 1 Output On MONO_OUTPUT = 1 Output On LINEOUT_OUTPUT = 1 Output On OCL = 1 LS_L_OUTPUT = 0 Output Off LS_R_OUTPUT = 0 Output Off HP_L_OUTPUT = 0 OCL = 1, Output Mute OCL = 0, Output Mute Loudspeaker Right Channel Headphone Left Channel Headphone Right Channel HP_R_OUTPUT = 0 OCL = 1, Output Mute OCL = 0, Output Mute Mono Speaker Output MONO_OUTPUT = 0 Output Off LINEOUT_OUTPUT = 0 Output Mute OCL = 0 Headphone Output Set to Cap-coupled Lineout Headphone Output Mode Headphone Output set to Capless (CHP = 1/2 AVDD) CD3 = 1 Outputs Toggled Via Register Control All Outputs CD3 = 0 All Outputs Off TABLE 10. National 3D Enhancement Level Select (03h) 3D_LEVEL_1 0 0 1 1 3D_LEVEL_0 0 1 0 1 TABLE 11. National 3D Mode Control (04h) 3D_MODE 0 1 3D type 1: ROUT = Ri - G * LOUT3D, LOUT = Li - G * ROUT3D 3D type 2: ROUT = −Ri - G * LOUT3D, LOUT = Li + G * ROUT3D Ri = Right Input Li = Left Input G = 3D gain level (Mix Ratio) ROUT3D = Ri through the high-pass filter R3D and C3D LOUT3D = Li through the high-pass filter R3D and C3D MIX RATIO 25% 40% 55% 70% MODE 3D type 1 3D type 2 17 www.national.com LM4934 System Controls MONO_IN_GAIN_2 ANA_L_GAIN_2 ANA_R_GAIN_2 0 0 0 0 1 1 1 1 (Continued) TABLE 12. Analog Input Amplifier Gain Select MONO_IN_GAIN_1 ANA_L_GAIN_1 ANA_R_GAIN_1 0 0 1 1 0 0 1 1 TABLE 13. DAC Gain Select MONO_IN_GAIN_0 ANA_L_GAIN_0 ANA_R_GAIN_0 0 1 0 1 0 1 0 1 Input Gain Setting –6dB –3dB 0dB 3dB 6dB 9dB 12dB 15dB DIG_L_GAIN_1 DIG_R_GAIN_1 0 0 1 1 DIG_L_GAIN_1 DIG_R_GAIN_1 0 1 0 1 Input Gain Setting –3dB 0dB 3dB 6dB PLL Configuration Registers PLL M DIVIDER CONFIGURATION REGISTER This register is used to control the input divider of the PLL. PLL_M (0Ah) (Set = logic 1, Clear = logic 0) Bits 6:0 Register PLL_M Description Programs the PLL input divider to select: PLL_M 0 1 2 3 4 ... 126 127 NOTES: The M divider should be set such that the output of the divider is between 0.5 and 5MHz. See the PLL setup section for details. The divider of the M divider is derived from PLL_M as such: M = (PLL_M+1) / 2 Divide Ratio Divider Off 1 1.5 2 2.5 3→ 63.5 64 www.national.com 18 LM4934 PLL Configuration Registers PLL N DIVIDER CONFIGURATION REGISTER This register is used to control PLL N divider. (Continued) PLL_N (0Bh) (Set = logic 1, Clear = logic 0) Bits 7:0 Register PLL_N PLL_N 0 1 → 10 11 12 ... 248 249 250 → 255 Description Programs the PLL feedback divider: Divide Ratio Divider Off 10 11 12 ... 248 249 250 NOTES: The divider should be set such that the output of the divider is between 0.5 and 5MHz. See the PLL setup section for details. The N divider should never be set so that (Fin/M) * N > 55MHz (or 80MHz if FAST_VCO is set in the PLL_N_MOD register). The non-sigma-delta division of the N divider is derived from the PLL_N as such: N = PLL_N Fin /M is often referred to as Fcomp (Frequency of Comparison) or Fref (Reference Frequency). In this document, Fcomp is used. PLL P DIVIDER CONFIGURATION REGISTER This register is used to control the PLL’s P divider. PLL_P (0Dh) (Set = logic 1, Clear = logic 0) Bits 3:0 Register PLL_P PLL_P 0 1 2 3 ... 13 14 15 NOTES: The division of the P divider is derived from PLL_P as such: P = (PLL_P+1) / 2 Description Programs the PLL input divider to select: Divide Ratio Divider Off 1 1.5 2 – > 2.5 7 7.5 8 19 www.national.com LM4934 PLL Configuration Registers (Continued) PLL N MODULATOR AND DITHER SELECT CONFIGURATION REGISTER This register is used to control the Fractional component of the PLL. PLL_N_MOD (0Ch) (Set = logic 1, Clear = logic 0) Bits 4:0 Register PLL_N_MOD PLL_N_MOD 0 1 → 30 2 31 6:5 DITHER_LEVEL DITHER_LEVEL 00 01 10 11 7 FAST_VCO FAST_VCO 0 1 Description This programs the PLL N Modulator’s fractional component: Fractional Addition 0/32 1/32 2/32 → 30/32 31/32 DAC Sub-system Input Source Medium (32) Small (16) Large (48) Off Maximum FVCO 40–55MHz 55–80MHz Allows control over the dither used by the N Modulator If set the VCO maximum and minimum frequencies are raised: NOTES: The complete N divider is a fractional divider as such: N = PLL_N + (PLL_N_MOD/32) If the modulus input is zero, then the N divider is simply an integer N divider. The output from the PLL is determined by the following formula: Fout = (Fin * N) / (M * P) Please see over for more details on the PLL and common settings. www.national.com 20 LM4934 Further Notes on PLL Programming The sigma-delta PLL is designed to drive audio circuits requiring accurate clock frequencies of up to 25MHz with frequency errors noise-shaped away from the audio band. The 5 bits of modulus control provide exact synchronization of 48kHz and 44.1kHz sample rates from any common clock source when the oversampling rate of the audio system is 125fs. In systems where 128x oversampling must be used (for example with an isochronous I2S data stream) a clock synchronous to the sample rate should be used as input to the PLL (typically the I2S clock). If no isochronous source is available then the PLL can be used to obtain a clock that is accurate to within typical crystal tolerances of the real sample rate. 20166963 Example Of Pll Settings For 48Khz Sample Rates f_in (MHz) 11 12 12.288 13 14.4 16.2 16.8 19.2 19.44 19.68 19.8 fsamp (kHz) 48 48 48 48 48 48 48 48 48 48 48 M 11 5 4 13 9 27 14 13 27 20.5 16.5 N 60 25 19.53125 60 37.5 100 50 40.625 100 62.5 50 P 5 5 5 5 5 5 5 5 6 5 5 PLL_M 21 9 7 25 17 53 27 25 53 40 32 PLL_N 60 25 19 60 37 100 50 40 100 62 50 PLL_N_MOD 0 0 17 0 16 0 0 20 0 16 0 PLL_P 9 9 9 9 9 9 9 9 11 9 9 f_out (MHz) 12 12 12 12 12 12 12 12 12 12 12 Example Pll Settings For 44.1Khz Sample Rates f_in (MHz) 11 11.2896 12 13 14.4 16.2 16.8 19.2 19.44 19.68 19.8 fsamp (kHz) 44.1 44.1 44.1 44.1 44.1 44.1 44.1 44.1 44.1 44.1 44.1 8 5 13 12 9 17 16 13.5 20.5 11 M 11 N 55.125 39.0625 22.96875 55.125 45.9375 30.625 55.78125 45.9375 38.28125 45.9375 30.625 P 5 5 5 5 5 5 5 5 5 4 5 PLL_M 21 15 9 25 23 17 33 31 26 40 21 PLL_N 55 39 22 55 45 30 55 45 38 45 30 PLL_N_MOD 4 2 31 4 30 20 25 30 9 30 20 PLL_P 9 9 9 9 9 9 9 9 9 7 9 f_out (MHz) 11.025000 11.025000 11.025000 11.025000 11.025000 11.025000 11.025000 11.025000 11.025000 11.025000 11.025000 These tables cover the most common applications, obtaining clocks for sample rates such as 22.05kHz and 192kHz should be done by changing the P divider value or the R divider in the clock configuration diagram. If the user needs to obtain a clock unrelated to those described above, the following method is advised. An example of obtaining 11.2896 from 12.000MHz is shown below. 21 www.national.com LM4934 Further Notes on PLL Programming (Continued) Choose a small range of P so that the VCO frequency is swept between 45 and 55MHz (or 60-80MHz if VCOFAST is used). Remembering that the P divider can divide by half integers. So for P = 4.0 → 7.0 sweep the M inputs from 2.5 → 24. The most accurate N and N_MOD can be calculated by: N = FLOOR(((Fout/Fin)*(P*M)),1) N_MOD = ROUND(32*((((Fout)/Fin)*(P*M)-N),0) This shows that setting M = 11.5, N = 75 N_MOD = 47 P = 7 gives a comparison frequency of just over 1MHz, a VCO frequency of just under 80MHz (so VCO_FAST must be set) and an output frequency of 11.289596 which gives a sample rate of 44.099985443kHz, or accurate to 0.33 ppm. Care must be taken when synchronization of isochronous data is not possible, i.e. when the PLL has to be used in the above mode. The I2S should be master on the LM4934 so that the data source can support appropriate SRC as required. This method should only be used with data being read on demand to eliminate sample rate mismatch problems. Where a system clock exists at an integer multiple of the required DAC clock rate it is preferable to use this rather than the PLL. The LM4934 is designed to work in 8,12,16,24,32, and 48kHz modes from a 12MHz clock without the use of the PLL. This saves power and reduces clock jitter. Clock Configuration Register This register is used to control the multiplexers and clock R divider in the clock module. CLOCK (09h) (Set = logic 1, Clear = logic 0) Bits 0 Register FAST_CLOCK 0 1 1 PLL_INPUT PLL_INPUT 0 1 DAC_CLK_SEL 2 AUDIO_CLK_SEL 0 1 3 7:4 PLL_ENABLE R_DIV R_DIV 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Programs the R divider Divide Value 1 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 FAST_CLOCK Description If set master clock is divided by two. MCLK Frequency Normal Divided by 2 PLL Input Source MCLK I2S Input Clock DAC Sub-system Input Source PLL Input PLL Output Programs the PLL input multiplexer to select: Selects which clock is passed to the audio sub-system If set enables the PLL. (MODES 4–7 only) www.national.com 22 LM4934 Clock Configuration Register (Continued) 20166953 By default the stereo DAC operates at 250*fs, i.e. 12.000MHz (at the clock generator input clock) for 48kHz data. It is expected that the PLL be used to drive the audio system unless a 12.000MHz master clock is supplied. The PLL can also use the I2S clock input as a source. In this case, the audio DAC uses the clock from the output of the PLL. Common Clock Settings for the DAC The DAC can work in 4 modes, each with different oversampling rates, 125,128,64 & 32. In normal operation 125x oversampling provides for the simplest clocking solution as it will work from 12.000MHz (common in most systems with Bluetooth or USB) at 48kHz exactly. The other modes are useful if data is being provided to the DAC from an uncontrollable isochronous source (such as a CD player, DAB, or other external digital source) rather than being decoded from memory. In this case the PLL can be used to derive a clock for the DAC from the I2S clock. The DAC oversampling rate can be changed to allow simpler clocking strategies, this is controlled in the DAC SETUP register but the oversampling rates are as follows: DAC MODE 00 01 10 11 Oversampling Ratio Used 125 128 64 32 The following table describes the clock required at the clock generator input for various clock sample rates in the different DAC modes: Fs (kHz) 8 8 11.025 11.025 12 12 16 16 22.05 22.05 24 24 32 32 DAC Oversampling Ratio 125 128 125 128 125 128 125 128 125 128 125 128 125 128 Required CLock at DAC Clock Generator Input (MHz) 2 2.048 2.75625 2.8224 3 3.072 4 4.096 5.5125 5.6448 6 6.144 8 8.192 23 www.national.com LM4934 Common Clock Settings for the DAC Fs (kHz) 44.1 44.1 48 48 88.2 96 176.4 192 DAC Oversampling Ratio 125 128 125 128 64 64 32 32 (Continued) Required CLock at DAC Clock Generator Input (MHz) 11.025 11.2896 12 12.288 11.2896 12.288 22.5792 24.576 Methods for producing these clock frequencies are described in the PLL section. The R divider can be used when the master clock is exactly 12.00 MHz in order to generate different sample rates. The Table below shows different sample rates supported from 12.00MHz by using only the R divider and disabling the PLL. In this way we can save power and the clock jitter will be low. R_DIV 11 9 7 5 4 3 2 0 Divide Value 6 5 4 3 2.5 2 1.5 1 DAC Clock Generator Input Frequency < MHz > 2 2.4 3 4 4.8 6 8 12 Sample Rate Supported < KHz > 8 9.6 12 16 19.2 24 32 48 The R divider can also be used along with the P divider in order to create the clock needed to support low sample rates. DAC Setup Register This register is used to configure the basic operation of the stereo DAC. DAC_SETUP (0Eh) Bits 1:0 (Set = logic 1, Clear = logic 0) Description The DAC used in the LM4934 can operate in one of 4 oversampling modes. The modes are described as follows: DAC_MODE 00 01 10 11 Oversampling Rate 125 128 64 32 Typical FS 48KHz 44.1KHz 48KHz 96KHz 192KHz Clock Required 12.000MHz (USB Mode) 11.2896MHz 12.288MHz 12.288MHz 24.576MHz Register DAC_MODE 2 3 4 5 6 MUTE_L MUTE_R DITHER_OFF DITHER ALWAYS_ON CUST_COMP Mutes the left DAC channel on the next zero crossing. Mutes the right DAC channel on the next zero crossing. If set the dither in DAC is disabled. If set the dither in DAC is enabled all the time. If set the DAC frequency response can be programmed manually via a 5 tap FIR “compensation” filter. This can be used to enhance the frequency response of small loudspeakers or provide a crude tone control. The compensation Coefficients can be set by using registers 10h to 15h. www.national.com 24 LM4934 Interface Control Register This register is used to control the I2S and I2C compatible interface on the chip. INTERFACE (0Fh) (Set = logic 1, Clear = logic 0) Bits 0 Register I2S_MASTER_SLAVE Description If set the LM4934 acts as a master for I2S, so both I2S clock and I2S word select are configured as outputs. If cleared the LM4934 acts as a slave where both I2S clock and word select are configured as inputs. If set the I2S resolution is set to 32 bits. If clear, resolution is set to 16 bits. This bit only affects the I2S Interface in master mode. In slave mode the I2S Interface can support any I2S compatible resolution. In master mode the I2S resolution also depends on the DAC mode as the note below explains. If set the I2S is configured in left justified mode timing. If clear, the I2S interface is configured in normal I2S mode timing. If set enables the I2C to run in fast mode with an I2C clock up to 3.4MHz. If clear the I2C speed gets its default value of a maximum of 400kHz 1 I2S_RESOLUTION 2 I2S_MODE 3 I2C_FAST NOTES: The master I2S format depends on the DAC mode. In USB mode the number of bits per word is 25 (i.e. 2.4MHz for a 48kHz sample rate). The duty cycle is 40/60. In non-USB modes the format is 32 or 16 bits per word, depending on I2S_RESOLTION and the duty cycle is always 50-50. In slave mode it will decode any I2S compatible data stream. 201669A9 I2S Mode Timing 25 www.national.com LM4934 Interface Control Register (Continued) 201669B0 Left Justified Mode Timing FIR Compensation Filter Configuration Registers These registers are used to configure the DAC’s FIR compensation filter. Three 16 bit coefficients are required and must be programmed via the I2C/SPI Interface in bytes as follows: COMP_COEFF (10h → 15h) (Set = logic 1, Clear = logic 0) Address 10h 11h 12h 13h 14h 15h Register COMP_COEFF0_LSB COMP_COEFF0_MSB COMP_COEFF1_LSB COMP_COEFF1_MSB COMP_COEFF2_LSB COMP_COEFF2_MSB Description Bits [7:0] of the 1st and 5th FIR tap (C0 and C4) Bits [15:8] of the 1st and 5th FIR tap (C0 and C4) Bits [7:0] of the 2nd and 4th FIR tap (C1 and C3) Bits [15:8] of the 2nd and 4th FIR tap (C1 and C3) Bits [7:0] of the 3rd FIR tap (C2) Bits [15:8] of the 3rd FIR tap (C2) NOTES: The filter must be phase linear to ensure the data keeps the correct stereo imaging so the second half of the FIR filter must be the reverse of the 1st half. 20166955 If the CUST_COMP option in register 0Eh is not set the FIR filter will use its default values for a linear response from the DAC into the analog mixer, these values are: DAC_OSR 00 01, 10, 11 C0, C4 68 112 C1, C3 –412 –580 C2 28526 27551 If using 96 or 192kHz data then the custom compensation may be required to obtain flat frequency responses above 24kHz. The total power of any custom filter must not exceed www.national.com 26 that of the above examples or the filters within the DAC will clip. The coefficient must be programmed in 2’s complement. LM4934 Typical Performance Characteristics THD+N vs Frequency 3V Lineout, RL = 10kΩ, VO = 850mV THD+N vs Frequency 3V EP Out, RL = 32Ω, PO = 20mW 20166920 20166921 THD+N vs Frequency 3V HP Out, RL = 16Ω, PO = 20mW THD+N vs Frequency 3V LS Out, RL = 8Ω, PO = 200mW 20166922 20166923 THD+N vs Frequency 5V EP, RL = 32Ω, PO = 40mW THD+N vs Frequency 5V HP Out, RL = 16Ω, PO = 60mW 20166924 20166926 27 www.national.com LM4934 Typical Performance Characteristics THD+N vs Frequency 5V HP Out, RL = 32Ω, PO = 30mW (Continued) THD+N vs Frequency 5V LS Out, RL = 8Ω, PO = 500mW 20166929 20166930 THD+N vs Output Power 3V EP Out, RL = 16Ω, f = 1kHz THD+N vs Output Power 3V EP Out, RL = 32Ω, f = 1kHz 201669J8 201669J9 THD+N vs Output Power 3V HP Out, RL = 16Ω, f = 1kHz THD+N vs Output Power 3V HP Out, RL = 32Ω, f = 1kHz 201669K0 201669K1 www.national.com 28 LM4934 Typical Performance Characteristics THD+N vs Output Power 3V LS Out, RL = 8Ω, f = 1kHz (Continued) THD+N vs Output Power 5V EP Out, RL = 16Ω, f = 1kHz 20166975 201669K2 THD+N vs Output Power 5V EP Out, RL = 32Ω, f = 1kHz THD+N vs Output Power 5V HP Out, RL = 16Ω, f = 1kHz 201669K3 201669K4 THD+N vs Output Power 5V HP Out, RL = 32Ω, f = 1kHz THD+N vs Output Power 5V LS Out, RL = 8Ω, f = 1kHz 201669K5 201669I9 29 www.national.com LM4934 Typical Performance Characteristics THD+N vs I2S Level EP Out (Continued) THD+N vs I2S Level HP Out 201669B1 201669B2 THD+N vs I2S Level Line Out THD+N vs I2S Level LS Out 201669B3 201669B4 PSRR vs Frequency 3V EP Out Mode 1 PSRR vs Frequency 3V EP Out Mode 4 20166904 20166905 www.national.com 30 LM4934 Typical Performance Characteristics PSRR vs Frequency 3V HP Out Mode 2 (Continued) PSRR vs Frequency 3V HP Out Mode 4 20166906 20166908 PSRR vs Frequency 3V Line Out Mode 1 PSRR vs Frequency 3V Line Out Mode 4 20166909 20166910 PSRR vs Frequency 3V LS Out Mode 2 PSRR vs Frequency 3V LS Out Mode 4 20166911 20166912 31 www.national.com LM4934 Typical Performance Characteristics PSRR vs Frequency 5V HP Out Mode 2 (Continued) PSRR vs Frequency 5V HP Out Mode 4 20166913 20166914 PSRR vs Frequency 5V Line Out Mode 1 PSRR vs Frequency 5V Line Out Mode 4 20166915 20166916 PSRR vs Frequency 5V LS Out Mode 4 PSRR vs Frequency 5V LS Out Mode 2 20166917 20166918 www.national.com 32 LM4934 Typical Performance Characteristics XTalk vs Frequency 5V HP Out Mode 2, RL = 32Ω, 1VRMS, SE (Continued) XTalk vs Frequency 5V LS Out Mode 2, RL = 8Ω, 1VRMS 201669B5 201669B6 Output Power vs Supply Voltage EP Out, RL = 32Ω, 1% THD+N Output Power vs Supply Voltage HP Out, RL = 32Ω, 1% THD+N 201669J0 201669J1 Output Power vs Supply Voltage LS Out, RL = 8Ω, 1% THD+N 201669J2 33 www.national.com LM4934 Application Information I 2S The LM4934 supports both master and slave I2S transmission at either 16 or 32 bits per word at clock rates up to 3.072MHz (48kHz stereo, 32bit). The basic format is shown below: 20166907 FIGURE 5. NATIONAL SEMICONDUCTOR 3D AUDIO ENHANCEMENT The LM4934 utilizes a programmable gain version of National Semiconductor’s 3D audio enhancement circuit. This allows 3D gain only (not frequency response) to be controlled via I2C/SPI in the National 3D Enhancement Level Select registers (3D1 and 3D0). Also, this circuit uses the same 3D path for both the headphone and stereo loudspeaker outputs, so the 3D effect remains constant when switching from headphone to stereo loudspeaker outputs unless changed in the registers. An added benefit of this is that the gain of the original signal is unaffected when 3D is turned on/off. 3D gain is established internally with R3D (approximately 30kΩ) and externally with C3D. Typical values for C3D are around 0.22µF, but may varied for altered 3D response. Gain Considerations When using the mixer and 2,3,4, or 5 channels are summed into the stereo output (headphone or speaker), the gain of each individual input is automatically reduced by 1/N, where N is the number of channels being summed. This has the effect of maintaining the total signal output level for different modes (i.e.; when LIN and RIN are summed for a mono output, gain for RIN and LIN will each be reduced by 6dB). This is not true for mono output modes, like EP and lineout. For these cases, stereo inputs are treated as one input with a –6dB gain for each input before summing this with a mono input. An example of relative output levels for each mode is given below: Mode 1 2 3 4 5 6 7 Mono Out M (AL/2)+(AR+2) [M+(AL/2)+(AR/2)]/2 (DL/2)+(DR/2) [(AL/2)+(AR/2)+(DL/2)+(DR/2)]/2 [M+(AL/2)+(AR/2)+(DL/2)+(DR/2)]/2 [M+(DL/2)+(DR/2)]/2 Stereo R Out M AR (M+AR)/2 DR (AR+DR)/2 (M+AR+DR)/3 (M+DR)/2 Stereo L Out M AL (M+AL)/2 DL (AL+DL)/2 (M+AL+DL)/3 (M+DL)/2 LM4934 DEMOBOARD OPERATION BOARD LAYOUT DIGITAL SUPPLIES JP14 — Digital Power DVDD JP14 — I/O Power IOVDD JP14 — PLL Supply PLLVDD JP14 — USB Board Supply BBVDD JP14 — I2C VDD All supplies may be set independently. All digital ground is common. Jumpers may be used to connect all the digital supplies together. S9 – connects VDD_PLL to VDD_D S10 – connects VDD_D to VDD_IO S11 – connects VDD_IO to VDD_I2C www.national.com 34 LM4934 Application Information S12 – connects VDD_I2C to Analog VDD (Continued) S17 – connects BB_VDD to USB3.3V (from USB board) S19 – connects VDD_D to USB3.3V (from USB board) S20 – connects VDD_D to SPDIF receiver chip ANALOG SUPPLY JP11 — Analog Supply S12 — connects Analog VDD with Digital VDD (I2C_VDD) S16 — connects Analog Ground with Digital Ground S21 — connects Analog VDD to SPDIF receiver chip INPUTS Analog Inputs JP2 — Mono Input JP6 — Left Input JP7 — Right Input Digital Inputs JP19 — Digital Interface Pin 1 — MCLK Pin 2 — I2S_CLK Pin 3 — I2S_SDI Pin 4 — I2S_WS JP20 — Toslink SPDIF Input JP21 — Coaxial SPDIF Input Coaxial and Toslink inputs may be toggled between by use of S25. Only one may be used at a time. Must be used in conjunction with on-board SPDIF receiver chip. OUTPUTS JP4 — Right BTL Loudspeaker Output JP5 — Left BTL Loudspeaker Output JP1 — Left Headphone Output (Single-Ended or OCL) JP3 — Right Headphone Output (Single-Ended or OCL) P1 — Stereo Headphone Jack (Same as JP1, JP2, Single-Ended or OCL) JP12 — Mono BTL Earpiece Output JP8 — Single-Ended Line Level Output CONTROL INTERFACE X1, X2 – USB Control Bus for I2C/SPI X1 Pin 9 – Mode Select (SPI or I2C) X2 Pin Pin Pin Pin Pin Pin 1 – SDA 3 – SCL 15 – ADDR/END 14 – USB5V 16 – USB3.3V 16 – USB GND 35 www.national.com LM4934 Application Information MISCELLANEOUS (Continued) I2S BUS SELECT S23, S24, S26, S27 – I2S Bus select. Toggles between on-board and external I2S (whether on-board SPDIF receiver is used). All jumpers must be set the same. Jumpers on top two pins selects external bus (JP19). Jumpers on bottom two pins selects on-board SPDIF receiver output. HEADPHONE OUTPUT CONFIGURATION Jumpers S1, S2, S3, and S4 are used to configure the headphone outputs for either cap-coupled outputs or output capacitorless (OCL) mode in addition to the register control internal to the LM4934 for this feature. Jumpers S1 and S3 bypass the output DC blocking capacitors when OCL mode is required. S2 connects the center amplifer HPCOUT to the headphone ring when in OCL mode. S4 connects the center ring to GND when cap-coupled mode is desired. S4 must be removed for OCL mode to function properly. Jumper settings for each mode: OCL S1 = ON S2 = ON S3 = ON S4 = OFF Cap-Coupled S1 = OFF S2 = OFF S3 = OFF S4 = ON PLL FILTER CONFIGURATION The LM4934 demo board comes with a simple filter setup by connecting jumpers S5 and S6. Removing these and connecting jumpers S7 and S8 will allow for an alternate PLL filter configuration to be used at R2 and C23. ON-BOARD SPDIF RECEIVER The SPDIF receiver present on the LM4934 demo board allows quick demonstration of the capabilities of the LM4934 by using the common SPDIF output found on most CD/DVD players today. There are some limitations in its useage, as the receiver will not work with digital supplies of less than 3V and analog supplies of less than 4V. This means low analog supply voltage testing of the LM4934 must be done on the external digital bus. The choice of using on-board or external digital bus is made usign jumpers S23, S24, S26, and S27 as described above. S25 selects whether the Toslink or Coaxial SPDIF input is used. The top two pins connects the toslink, the bottom two connect the coaxial input. Power on the digital side is routed through S20 (connecting to the other digital supplies), while on the analog side it is interrupted by S21. Both jumpers must be in place for the receiver to function. The part is already configured for I2S standard outputs. Jumper S28 allows the DATA output to be pulled either high or low. Default is high (jumper on right two pins). It may be necessary to quickly toggle S29 to reset the receiver and start it working upon initial power up.. A quick short across S29 should clear this condition. LM4934 I2C/SPI INTERFACE SOFTWARE Convenient graphical user interface software is available for demonstration purposes of the LM4934. It allows for either SPI or I2C control via either USB or parallel port connections to a Windows computer. Control options include all mode and output settings, volume controls, PLL and DAC setup, FIR setting and on-the-fly adjustment by an easy to use graphical interface. An advanced option is also present to allow direct, register-level commands. Software is available from www.national.com and is compatible with Windows operating systems of Windows 98 or more (with USB support) with the latest .NET updates from Microsoft. www.national.com 36 Demonstration Board Schematic LM4934 37 20166956 www.national.com LM4934 Revision History Rev 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 Date 9/22/05 9/27/05 10/6/05 10/11/05 10/12/05 10/13/05 10/19/05 10/21/05 10/24/06 11/10/05 Description Started D/S by copying LM4931 (DS201009). Did major edits. Input some text/Typical/Limits on the EC tables. Added table 1, 2, and 3. Input some text edits also. Input more edits. First WEB release of the D/S. D/S was taken out of the WEB per Daniel. Text edits and curves. Added K6 (by Diane T.), will release to the per Daniel. Fixed typos, then released to the WEB. Added the internal DAC SNR (with 95dB typ) under Key Spec and into the Digital EC table. Added the SNR DAC, then re-webd per Daniel. Removed the WL package and replaced it with the RL. Removed the WL package and replaced it with the RL package (per Veronica and Daniel A.), then released D/S to the WEB. Edited 20166956 (board schem, changed WL to RL), X1, X2,and X3 values. Switched the labels of B3 and B2 on the Demo Board Schematic (pg 37) per Daniel. 2.0 2.1 2.2 11/15/05 12/14/05 12/19/05 2.3 2.4 1/19/06 2/13/06 www.national.com 38 LM4934 3D Audio Sub-System with Stereo Speaker, OCL/SE Stereo Headphone, Earpiece and Mono Line Level Outputs Physical Dimensions inches (millimeters) unless otherwise noted 42-Bump micro SMDxt Order Number LM4934RL NS Package Number RLA42MPA X1 = 3.245 ± 0.030mm, X2 = 3.796 ± 0.030mm, X3 = 0.650 ± 0.075mm National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. 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