LM49370

LM49370 Audio Sub-System with an Ultra Low EMI, Spread Spectrum, Class D Loudspeaker Amplifier, a Dual-Mode Stereo Headphone Amplifier, and a Dedicated PCM Interface for Bluetooth Transceivers February 2007 LM49370 Audio Sub-System with an Ultra Low EMI, Spread Spectrum, Class D Loudspeaker Amplifier, a Dual-Mode Stereo Headphone Amplifier, and a Dedicated PCM Interface for Bluetooth Transceivers 1.0 General Description The LM49370 is an integrated audio subsystem that supports both analog and digital audio functions. The LM49370 includes a high quality stereo DAC, a mono ADC, a stereo headphone amplifier, which supports output cap-less (OCL) or AC-coupled (SE) modes of operation, a mono earpiece amplifier, and an ultra-low EMI spread spectrum Class D loudspeaker amplifier. It is designed for demanding applications in mobile phones and other portable devices. The LM49370 features a bi-directional I2S interface and a bidirectional PCM interface for full range audio on either interface. The LM49370 utilizes an I2C or SPI compatible interface for control. The stereo DAC path features an SNR of 85 dB with an 18-bit 48 kHz input. In SE mode the headphone amplifier delivers at least 33 mWRMS to a 32Ω single-ended stereo load with less than 1% distortion (THD+N) when A_VDD = 3.3V. The mono earpiece amplifier delivers at least 115mWRMS to a 32Ω bridged-tied load with less than 1% distortion (THD+N) when A_VDD = 3.3V. The mono speaker amplifier delivers up to 490mW into an 8Ω load with less than 1% distortion when LS_VDD = 3.3V and up to 1.2W when LS_VDD = 5.0V. The LM49370 employs advanced techniques to reduce power consumption, to reduce controller overhead, to speed development time, and to eliminate click and pop. Boomer audio power amplifiers were designed specifically to provide high quality output power with a minimal amount of external components. It is therefore ideally suited for mobile phone and other low voltage applications where minimal power consumption, PCB area and cost are primary requirements. ■ ■ ■ ■ SNRLS (AUX IN to Loudspeaker) SNRDAC (Stereo DAC to AUXOUT) SNRADC (Mono ADC from Cell Phone In) SNRHP (Aux In to Headphones) 90 dB (typ) 85 dB (typ) 90 dB (typ) 98 dB (typ) 4.0 Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Spread Spectrum Class D architecture reduces EMI Mono Class D 8Ω amplifier, 490 mW at 3.3V OCL or AC-coupled headphone operation 33mW stereo headphone amplifier at 3.3V 115 mW earpiece amplifier at 3.3V 18-bit stereo DAC 16-bit mono ADC 8 kHz to 192 kHz stereo audio playback 8 kHz to 48 kHz mono recording Bidirectional I2S compatible audio interface Bidirectional PCM compatible audio interface for Bluetooth transceivers I2S-PCM Bridge with sample rate conversion Sigma-Delta PLL for operation from any clock at any sample rate Digital 3D Stereo Enhancement FIR filter programmability for simple tone control Low power clock network operation if a 12 MHz or 13 MHz system clock is available Read/write I2C or SPI compatible control interface Automatic headphone & microphone detection Support for internal and external microphones Automatic gain control for microphone input Differential audio I/O for external cellphone module Mono differential auxiliary output Stereo auxiliary inputs Differential microphone input for internal microphone Flexible audio routing from input to output 32 Step volume control for mixers in 1.5 dB steps 16 Step volume control for microphone in 2 dB steps Programmable sidetone attenuation in 3 dB steps Two configurable GPIO ports Multi-function IRQ output Micro-power shutdown mode Available in the 4 x 4 mm 49 bump micro SMDxt package 2.0 Applications ■ ■ ■ ■ ■ Smart phones Mobile Phones and Multimedia Terminals PDAs, Internet Appliances and Portable Gaming Portable DVD/CD/AAC/MP3 Players Digital Cameras/Camcorders 3.0 Key Specifications ■ ■ ■ ■ ■ ■ ■ PHP (AC-COUP) (A_VDD = 3.3V, 32Ω, 1% THD) PHP (OCL) (A_VDD = 3.3V, 32Ω, 1% THD) PLS ( LS_VDD = 5V, 8Ω, 1% THD) PLS (LS_VDD = 4.2V, 8Ω, 1% THD) PLS (LS_VDD = 3.3V, 8Ω, 1% THD) Shutdown Current PSRRLS (217 Hz, LS_VDD = 3.3V) 33 mW 31 mW 1.2 W 900 mW 490 mW 0.8 µA 70 dB Boomer® is a registered trademark of National Semiconductor Corporation. © 2007 National Semiconductor Corporation 201917 www.national.com LM49370 5.0 LM49370 Overview 20191724 FIGURE 1. Conceptual Schematic www.national.com 2 LM49370 6.0 Typical Application 20191723 FIGURE 2. Example Application in Multimedia Mobile Phone 3 www.national.com LM49370 Table of Contents 1.0 General Description ......................................................................................................................... 2.0 Applications .................................................................................................................................... 3.0 Key Specifications ........................................................................................................................... 4.0 Features ........................................................................................................................................ 5.0 LM49370 Overview .......................................................................................................................... 6.0 Typical Application ........................................................................................................................... 7.0 Connection Diagrams ....................................................................................................................... 7.1 PIN TYPE DEFINITIONS ................................................................................................................ 8.0 Absolute Maximum Ratings .............................................................................................................. 9.0 Operating Ratings ........................................................................................................................... 10.0 Electrical Characteristics (Notes 1, 2) Unless otherwise stated PLL_VDD = 3.3V, D_VDD = 3.3V, BB_VDD = 1.8V, 11.0 System Control ............................................................................................................................ 11.1 I2C SIGNALS ............................................................................................................................ 11.2 I2C DATA VALIDITY .................................................................................................................. 11.3 I2C START AND STOP CONDITIONS .......................................................................................... 11.4 TRANSFERRING DATA ............................................................................................................. 11.5 I2C TIMING PARAMETERS ....................................................................................................... 12.0 Status & Control Registers ............................................................................................................ 12.1 BASIC CONFIGURATION REGISTER ......................................................................................... 12.2 CLOCKS CONFIGURATION REGISTER ...................................................................................... 12.3 LM49370 CLOCK NETWORK ..................................................................................................... 12.4 COMMON CLOCK SETTINGS FOR THE DAC & ADC ................................................................... 12.5 PLL M DIVIDER CONFIGURATION REGISTER ............................................................................ 12.6 PLL N DIVIDER CONFIGURATION REGISTER ............................................................................ 12.7 PLL P DIVIDER CONFIGURATION REGISTER ............................................................................ 12.8 PLL N MODULUS CONFIGURATION REGISTER ......................................................................... 12.9 FURTHER NOTES ON PLL PROGRAMMING ............................................................................... 12.10 ADC_1 CONFIGURATION REGISTER ....................................................................................... 12.11 ADC_2 CONFIGURATION REGISTER ....................................................................................... 12.12 AGC_1 CONFIGURATION REGISTER ...................................................................................... 12.13 AGC_2 CONFIGURATION REGISTER ...................................................................................... 12.14 AGC_3 CONFIGURATION REGISTER ...................................................................................... 12.15 AGC OVERVIEW ..................................................................................................................... 12.16 MIC_1 CONFIGURATION REGISTER ........................................................................................ 12.17 MIC_2 CONFIGURATION REGISTER ........................................................................................ 12.18 SIDETONE ATTENUATION REGISTER ..................................................................................... 12.19 CP_INPUT CONFIGURATION REGISTER ................................................................................. 12.20 AUX_LEFT CONFIGURATION REGISTER ................................................................................. 12.21 AUX_RIGHT CONFIGURATION REGISTER ............................................................................... 12.22 DAC CONFIGURATION REGISTER .......................................................................................... 12.23 CP_OUTPUT CONFIGURATION REGISTER .............................................................................. 12.24 AUX_OUTPUT CONFIGURATION REGISTER ............................................................................ 12.25 LS_OUTPUT CONFIGURATION REGISTER .............................................................................. 12.26 HP_OUTPUT CONFIGURATION REGISTER .............................................................................. 12.27 EP_OUTPUT CONFIGURATION REGISTER .............................................................................. 12.28 DETECT CONFIGURATION REGISTER .................................................................................... 12.29 HEADSET DETECT OVERVIEW ............................................................................................... 12.30 STATUS REGISTER ................................................................................................................ 12.31 3D CONFIGURATION REGISTER ............................................................................................. 12.32 I2S PORT MODE CONFIGURATION REGISTER ........................................................................ 12.33 I2S PORT CLOCK CONFIGURATION REGISTER ....................................................................... 12.34 DIGITAL AUDIO DATA FORMATS ............................................................................................. 12.35 PCM PORT MODE CONFIGURATION REGISTER ...................................................................... 12.36 PCM PORT CLOCK CONFIGURATION REGISTER ..................................................................... 12.37 SRC CONFIGURATION REGISTER .......................................................................................... 12.38 GPIO CONFIGURATION REGISTER ......................................................................................... 12.39 DAC PATH COMPENSATION FIR CONFIGURATION REGISTERS .............................................. 13.0 Typical Performance Characteristics .............................................................................................. 14.0 LM49370 Demonstration Board Schematic Diagram ......................................................................... 15.0 Demoboard PCB Layout ............................................................................................................... 16.0 Revision History .......................................................................................................................... 17.0 Physical Dimensions .................................................................................................................... www.national.com 4 1 1 1 1 2 3 5 7 8 8 A_VDD = 3.3V, LS_VDD = 3.3V. The following specifications apply for the circuit shown in Figure 2 unless otherwise stated. Limits apply for 25°C. .............................................................................................................................. 8 14 14 14 14 14 16 18 19 20 21 22 23 24 25 26 27 30 31 32 33 34 35 36 37 38 38 39 39 40 41 41 41 42 42 43 44 47 48 49 50 51 52 53 54 56 56 58 91 92 98 99 LM49370 7.0 Connection Diagrams 49 Bump micro SMDxt 49 Bump micro SMDxt Marking 201917q7 Top View XY — Date Code TT — Die Traceability G — Boomer I3 — LM49370RL 201917p3 Top View (Bump Side Down) Order Number LM49370RL See NS Package Number RLA49UUA 5 www.national.com LM49370 Pin Descriptions Pin A1 A2 A3 A4 A5 A6 A7 B1 B2 B3 B4 B6 B7 C1 C2 C3 C4 C5 C6 C7 D1 D2 D3 D4 D5 D6 D7 E1 E2 E3 E4 E5 E6 E7 F1 F2 F3 F4 F5 F6 F7 G1 G2 G3 G4 G5 Pin Name EP_NEG A_VDD INT_MIC_POS PCM_SDO PCM_CLK PCM_SYNC PCM_SDI A_VSS EP_POS INT_MIC_NEG BYPASS PLL_FILT PLL_VDD HP_R EXT_BIAS INT_BIAS AUX_R GPIO_2 SDA SCL HP_L VREF_FLT EXT_MIC SPI_MODE GPIO_1 BB_VDD D_VDD HP_VMID MIC_DET AUX_L CPI_NEG IRQ I2S_SDO I2S_SDI HP_VMID_FB LS_VDD CPI_POS CPO_NEG AUX_OUT_NEG I2S_WS I2S_CLK LS_NEG LS_VSS LS_POS CPO_POS AUX_OUT_POS Type Analog Supply Analog Digital Digital Digital Digital Supply Analog Analog Analog Digital Analog Supply Analog Analog Analog Analog Digital Digital Digital Analog Analog Analog Digital Digital Supply Supply Analog Analog Analog Analog Digital Digital Digital Analog Supply Analog Analog Analog Digital Digital Analog Supply Analog Analog Analog Direction Output Input Input Output Inout Inout Input Input Output Input Input Input Input Input Output Output Output Input Inout Inout Input Output Inout Input Input Inout Input Input Inout Input Input Input Output Output Input Input Input Input Output Output Inout Inout Output Input Output Output Output Earpiece negative output Headphone and mixer VDD Internal microphone positive input PCM Serial Data Output PCM clock signal PCM sync signal PCM Serial Data Input Headphone and mixer ground Earpiece positive output Internal microphone negative input A_VDD/2 filter point If SPI_MODE = 1, then this pin becomes CS. Filter point for PLL VCO input PLL VDD Headphone Right Output External microphone supply (2.0/2.5/2.8/3.3V) Internal microphone supply (2.0/2.5/2.8/3.3V) Right Analog Input General Purpose I/O 2 Control Data, I2C_SDA or SPI_SDA Control Clock, I2C_SCL or SPI_SCL Headphone Left Output Filter point for the microphone power supply External microphone input Control mode select 1 = SPI, 0 = I2C General Purpose I/O 1 Baseband VDD for the digital I/Os Digital VDD Virtual Ground for Headphones in OCL mode, otherwise 1st headset detection input Headset insertion/removal and microphone presence detection input. Left Analog Input Cell Phone analog input negative Interrupt request signal (NOT open drain) I2S Serial Data Out I2S Serial Data Input VMID Feedback in OCL mode, otherwise a 2nd headset detection input Loudspeaker VDD Cell Phone analog input positive Cell Phone analog output negative Auxiliary analog output negative I2S Word Select Signal (can be master or slave) I2S Clock Signal (can be master or slave) Loudspeaker negative output Loudspeaker ground Loudspeaker positive output Cell Phone analog output positive Auxiliary analog output positive Description B5 TEST_MODE/CS www.national.com 6 LM49370 Pin G6 G7 Pin Name D_VSS MCLK Type Supply Digital Direction Input Input Digital ground Input clock from 0.5 MHz to 30 MHz Description 7.1 PIN TYPE DEFINITIONS Analog Input— A pin that is used by the analog and is never driven by the device. Supplies are part of this classification. Analog Output— A pin that is driven by the device and should not be driven by external sources. Analog Inout— A pin that is typically used for filtering a DC signal within the device, Passive components can be connected to these pins. Digital Input— Digital Output— Digital Inout— A pin that is used by the digital but is never driven. A pin that is driven by the device and should not be driven by another device to avoid contention. A pin that is either open drain (I2C_SDA) or a bidirectional CMOS in/out. In the later case the direction is selected by a control register within the LM49370. 7 www.national.com LM49370 8.0 Absolute Maximum Ratings (Notes 1, 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Analog Supply Voltage (A_VDD & LS_VDD) Digital Supply Voltage  (BB_VDD & D_VDD & PLL_VDD) Storage Temperature Power Dissipation (Note 3) ESD Susceptibility Human Body Model (Note 4) Machine Model (Note 5) 6.0V 6.0V −65°C to +150°C Internally Limited 2500V 200V Junction Temperature Thermal Resistance  θJA – RLA49 (soldered down to PCB with 2in2 1oz. copper plane) Soldering Information 150°C 60°C/W 9.0 Operating Ratings Temperature Range Supply Voltage D_VDD/PLL_VDD BB_VDD LS_VDD/A_VDD −40°C to +85°C 2.5V to 4.5V 1.8V to 4.5V 2.5V to 5.5V 10.0 Electrical Characteristics (Notes 1, 2) Unless otherwise stated PLL_VDD = 3.3V, D_VDD = 3.3V, BB_VDD = 1.8V, A_VDD = 3.3V, LS_VDD = 3.3V. The following specifications apply for the circuit shown in Figure 2 unless otherwise stated. Limits apply for 25°C. LM49370 Symbol Parameter Conditions Typical (Note 6) Limit (Notes 7, 11) 2.2 1.8 1.2 1.2 Units POWER DISD DIST AISD AIST Digital Shutdown Current Digital Standby Current Analog Shutdown Current Analog Standby Current Chip Mode '00', fMCLK = 13MHz Chip Mode '01', fMCLK = 13MHz Chip Mode '00' Chip Mode '01' Chip Mode '10', fMCLK = 12MHz, fS = 48kHz, DAC on; PLL off Chip Mode '10', fMCLK = 13MHz, fPLLOUT = 12MHz, fS = 48kHz; DAC + PLL on Chip Mode '10', HP On, SE mode, DAC inputs selected Digital Playback Mode Analog Active Current Chip Mode '10', HP On, OCL mode, DAC inputs selected Chip Mode '10', LS On, DAC inputs selected Analog Playback Mode Digital Active Current Chip Mode '10', fMCLK = 13MHz, DAC +ADC + PLL off Chip Mode '10', HP On, SE mode, AUX inputs selected Analog Playback Mode Analog Active Current Chip Mode '10', HP On, OCL mode, AUX inputs selected Chip Mode '10', LS On, AUX inputs selected CODEC Mode Digital Active Current CODEC Mode Analog Active Current Voice Module Mode Digital Active Current Voice Module Mode Analog Active Current www.national.com 0.7 0.9 0.1 0.1 7.9 µA (max) mA(max) µA(max) µA (max) mA Digital Playback Mode Digital Active Current 12.5 14.5 mA(max) 9.0 9.4 11.5 0.9 5.9 6.3 8.4 2.7 11.2 0.9 7.4 13.5 13.5 15.5 1.8 9.5 9.7 12 3.5 15.5 1.8 11 mA(max) mA(max) mA(max) mA(max) mA(max) mA(max) mA(max) mA(max) mA(max) mA(max) mA(max) Chip Mode '10', fMCLK = 13MHz, fS = 8kHz, DAC +ADC on; PLL Off Chip Mode '10', EP On, DAC inputs selected Chip Mode '10', fMCLK = 13MHz, DAC +ADC + PLL off Chip Mode '10', EP + CPOUT on, CPIN input selected 8 LM49370 LM49370 Symbol Parameter Conditions Typical (Note 6) Limit (Notes 7, 11) Units LOUDSPEAKER AMPLIFIER 8Ω load, LS_VDD = 5V PLS Max Loudspeaker Power 8Ω load, LS_VDD = 4.2V 8Ω load, LS_VDD = 3.3V LSTHD+N LSEFF Loudspeaker Harmonic Distortion Efficiency 8Ω load, LS_VDD = 3.3V, PO = 400mW 0 dB Input MCLK = 12.000 MHz AUX inputs terminated CBYPASS = 1.0 µF VRIPPLE = 200 mVP-P fRIPPLE = 217 Hz From 0 dB Analog AUX input, A-weighted A-weighted 1.2 0.9 0.5 0.04 84 0.43 W W W (min) % % PSRRLS Power Supply Rejection Ration (Loudspeaker) Signal to Noise Ratio Output Noise Loudspeaker Offset Voltage 70 dB SNRLS eN VOS 90 62 12 80 dB(min) µV mV mW (min) mW mW mW mW mW HEADPHONE AMPLIFIER 32Ω load, 3.3V, SE 16Ω load, 3.3V, SE PHP Headphone Power 32Ω load, 3.3V, OCL, VCM = 1.5V 32Ω load, 3.3V, OCL, VCM = 1.2V 16Ω load, 3.3V, OCL, VCM = 1.5V 16Ω load, 3.3V, OCL, VCM = 1.2V AUX inputs terminated CBYPASS = 1.0 µF VRIPPLE = 200 mVP-P fRIPPLE = 217 Hz SE Mode OCL Mode VCM = 1.2V OCL Mode VCM = 1.5V From 0dB Analog AUX input A-weighted SE Mode SNRHP Signal to Noise Ratio OCL Mode VCM = 1.2V OCL Mode VCM = 1.5V HPTHD+N eN ΔACH-CH XTALK VOS Headphone Harmonic Distortion Output Noise Stereo Channel-to-Channel Gain Mismatch Stereo Crosstalk Offset Voltage SE Mode OCL Mode 32Ω load, 3.3V, PO = 7.5mW A-weighted 98 97 96 0.05 12 0.3 61 71 8 dB dB dB % µV dB dB dB mV 60 68 65 55 dB dB(min) dB 33 52 31 20 50 32 25 PSRRHP Power Supply Rejection Ratio (Headphones) EARPIECE AMPLIFIER 9 www.national.com LM49370 LM49370 Symbol Parameter Conditions Typical (Note 6) 115 150 Limit (Notes 7, 11) 100 Units PEP Earpiece Power 32Ω load, 3.3V 16Ω load, 3.3V mW (min) mW PSRREP Power Supply Rejection Ratio (Earpiece) Signal to Noise Ratio Earpiece Harmonic Distortion Output Noise Offset Voltage Total Harmonic Distortion + Noise CP_IN terminated CBYPASS = 1.0 µF VRIPPLE = 200 mVP-P FRIPPLE = 217 Hz From 0dB Analog AUX input, A-weighted 32Ω load, 3.3V, PO = 50mW A-weighted 76 dB SNREP EPTHD+N eN VOS THD+N 93 0.04 41 8 dB % µV mV % AUXOUT AMPLIFIER VO = 1VRMS, 5kΩ load CP_IN terminated CBYPASS = 1.0μF VRIPPLE = 200mVPP fRIPPLE = 217Hz VO = 1VRMS, 5kΩ load CBYPASS = 1.0μF VRIPPLE = 200mVPP fRIPPLE = 217Hz 0.02 PSRR Power Supply Rejection Ratio 86 dB CP_OUT AMPLIFIER THD+N PSRR MONO ADC RADC PBADC SBAADC SNRADC ADCLEVEL STEREO DAC RDAC PBDAC SBADAC SNRDAC DRDAC DACLEVEL PLL FIN I2S/PCM fS = 48kHz; 16 bit mode fI2SCLK I2S CLK Frequency fS = 48kHz; 25 bit mode fS = 8kHz; 16 bit mode fS = 8kHz; 25 bit mode 1.536 2.4 0.256 0.4 MHz MHz MHz MHz Input Frequency Range Min Max 0.5 30 MHz MHz DAC Ripple DAC Passband DAC Stopband Attenuation DAC Signal to Noise Ratio DAC Dynamic Range DAC Full Scale Output Level A-weighted, AUXOUT 0.1 20 70 85 96 1 dB kHz dB dB dB VRMS ADC Ripple ADC Passband Lower (HPF Mode 1), fS = 8 kHz Upper ADC Stopband Attenuation ADC Signal to Noise Ratio ADC Full Scale Input Level Above Passband HPF Notch, 50 Hz/60 Hz (worst case) From CPI, A-weighted ±0.25 300 3470 60 58 90 1 dB Hz Hz dB dB dB VRMS Total Harmonic Distortion + Noise Power Supply Rejection Ratio 0.02 86 % dB www.national.com 10 LM49370 LM49370 Symbol Parameter Conditions Typical (Note 6) 0.768 1.2 0.128 0.2 40 60 50 Refer to Pg. 16 for more details Refer to Pg. 16 for more details 100 300 100 100 100 100 500 500 Minimum Gain w/ AUX_BOOST OFF VCRAUX AUX Volume Control Range Maximum Gain w/ AUX_BOOST OFF Minimum Gain w/ AUX_BOOST ON Maximum Gain w/ AUX_BOOST ON Minimum Gain w/ DAC_BOOST OFF VCRDAC DAC Volume Control Range Maximum Gain w/ DAC_BOOST OFF Minimum Gain w/ DAC_BOOST ON Maximum Gain w/ DAC_BOOST ON VCRCPIN VCRMIC VCRSIDE SSAUX SSDAC SSCPIN SSMIC SSSIDE CPIN Volume Control Range MIC Volume Control Range SIDETONE Volume Control Range AUX VCR Stepsize DAC VCR Stepsize CPIN VCR Stepsize MIC VCR Stepsize SIDETONE VCR Stepsize Minimum Gain from AUX input, BOOST OFF Loudspeaker Audio Path Gain Maximum Gain from AUX input, BOOST OFF Minimum Gain from CPI input Maximum Gain from CPI input Minimum Gain Maximum Gain Minimum Gain Maximum Gain Minimum Gain Maximum Gain –46.5 0 –34.5 12 –46.5 0 –34.5 12 –34.5 12 6 36 –30 0 1.5 1.5 1.5 2 3 –34.5 12 –22.5 24 Limit (Notes 7, 11) Units fS = 48kHz; 16 bit mode fPCMCLK PCM CLK Frequency fS = 48kHz; 25 bit mode fS = 8kHz; 16 bit mode fS = 8kHz; 25 bit mode DCI2S_CLK DCI2S_WS I2C TI2CSET TI2CHOLD SPI TSPISETENB TSPIHOLD-ENB TSPISETD TSPIHOLDD TSPICL TSPICH Enable Setup Time Enable Hold Time Data Setup Time Data Hold Time Clock Low Time Clock High Time I2C Data Setup Time I2C Data Hold Time I2S_CLK Duty Cycle I2S_WS Duty Cycle Min Max MHz MHz MHz MHz % (min) % (max) % ns (min) ns (min) ns (min) ns (min) ns (min) ns (min) ns (min) ns (min) dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB VOLUME CONTROL AUDIO PATH GAIN W/ STEREO (bit 6 of 0x00h) ENABLED (AUX_L & AUX_R signals identical and selected onto mixer) 11 www.national.com LM49370 LM49370 Symbol Parameter Conditions Typical (Note 6) –52.5 –6 –40.5 6 –30 0 –40.5 6 –28.5 18 –18 12 –46.5 0 –34.5 12 –46.5 0 6 36 Limit (Notes 7, 11) Units Minimum Gain from AUX input, BOOST OFF Maximum Gain from AUX input, BOOST OFF Headphone Audio Path Gain Minimum Gain from CPI input Maximum Gain from CPI input Minimum Gain from MIC input using SIDETONE path w/ VCRMIC gain = 6dB Maximum Gain from MIC input using SIDETONE path w/ VCRMIC gain = 6dB Minimum Gain from AUX input, BOOST OFF Maximum Gain from AUX input, BOOST OFF Earpiece Audio Path Gain Minimum Gain from CPI input Maximum Gain from CPI input Minimum Gain from MIC input using SIDETONE path w/ VCRMIC gain = 6dB Maximum Gain from MIC input using SIDETONE path w/ VCRMIC gain = 6dB Minimum Gain from AUX input, BOOST OFF AUXOUT Audio Path Gain Maximum Gain from AUX input, BOOST OFF Minimum Gain from CPI input Maximum Gain from CPI input Minimum Gain from AUX input, BOOST OFF CPOUT Audio Path Gain Maximum Gain from AUX input, BOOST OFF Minimum Gain from MIC input Maximum Gain from MIC input dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB www.national.com 12 LM49370 LM49370 Symbol Parameter Conditions Typical (Note 6) Limit (Notes 7, 11) Units Total DC Power Dissipation DAC (fS = 48kHz) and HP ON Digital Playback Mode Power Dissipation fMCLK = 12MHz, PLL OFF fMCLK = 13MHz, PLL ON fPLLOUT = 12MHz AUX Inputs selected and HP ON fMCLK = 13MHz, PLL OFF PCM DAC (fS = 8kHz) + ADC (fS = 8kHz) and EP ON fMCLK = 13MHz, PLL OFF CP IN selected. EP and CPOUT ON fMCLK = 13MHz, PLL OFF 27 mW 46 mW 22 mW 56 71 mW mW Analog Playback Mode Power Dissipation VOICE CODEC Mode Power Dissipation VOICE Module Mode Power Dissipation Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional but do not guarantee specific performance limits. Characteristics state DC and AC electrical specifications under particular test conditions which guarantee specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not guaranteed for parameters where no limit is given, however, the typical value is a good indication of device performance. Note 2: All voltages are measured with respect to the relevant VSS pin unless otherwise specified. All grounds should be coupled as close as possible to the device. Note 3: The maximum power dissipation must be de-rated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature, TA. The maximum allowable power dissipation is PDMAX = (TJMAX – TA)/ θJA or the number given in Absolute Maximum Ratings, whichever is lower. Note 4: Human body model: 100pF discharged through a 1.5kΩ resistor. Note 5: Machine model: 220pF – 240pF discharged through all pins. Note 6: Typical values are measured at 25°C and represent the parametric norm. Note 7: Limits are guaranteed to Nationals AOQL (Average Outgoing Quality Level). Note 8: Best operation is achieved by maintaining 3.0V < A_VDD < 5.0 and 3.0V < D_VDD < 3.6V and A_VDD > D_VDD. Note 9: Digital shutdown current is measured with system clock set for PLL output while the PLL is disabled. Note 10: Disabling or bypassing the PLL will usually result in an improvement in noise measurements. Note 11: Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. 13 www.national.com LM49370 11.0 System Control Method 1. I2C Compatible Interface 11.1 I2C SIGNALS In I2C mode the LM49370 pin SCL is used for the I2C clock SCL and the pin SDA is used for the I2C data signal SDA. Both these signals need a pull-up resistor according to I2C specification. The I2C slave address for LM49370 is 00110102. 11.2 I2C DATA VALIDITY The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of the data line can only be changed when SCL is LOW. 201917q1 I2C Signals: Data Validity 11.3 I2C START AND STOP CONDITIONS START and STOP bits classify the beginning and the end of the I2C session. START condition is defined as SDA signal transitioning from HIGH to LOW while SCL line is HIGH. STOP condition is defined as the SDA transitioning from LOW to HIGH while SCL is HIGH. The I2C master always generates START and STOP bits. The I2C bus is considered to be busy after START condition and free after STOP condition. During data transmission, I2C master can generate repeated START conditions. First START and repeated START conditions are equivalent, function-wise. 201917q2 11.4 TRANSFERRING DATA Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first. Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDA line during the 9th clock pulse, signifying an acknowledge. A receiver which has been addressed must generate an acknowledge after each byte has been received. After the START condition, the I2C master sends a chip address. This address is seven bits long followed by an eight bit which is a data direction bit (R/W). The LM49370 address is 00110102. For the eighth bit, a “0” indicates a WRITE and a “1” indicates a READ. The second byte selects the register to which the data will be written. The third byte contains data to write to the selected register. www.national.com 14 LM49370 201917q3 I2C Chip Address Register changes take an effect at the SCL rising edge during the last ACK from slave. 201917q5 w = write (SDA = “0”) r = read (SDA = “1”) ack = acknowledge (SDA pulled down by slave) rs = repeated start Example I2C Write Cycle 15 www.national.com LM49370 When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in the Read Cycle waveform. 201917q6 Example I2C Read Cycle 201917p9 I2C Timing Diagram 11.5 I2C TIMING PARAMETERS Symbol 1 2 3 4 5 5 6 7 8 9 10 Cb Parameter Min Hold Time (repeated) START Condition Clock Low Time Clock High Time Setup Time for a Repeated START Condition Data Hold Time (Output direction, delay generated by LM49370) Data Hold Time (Input direction, delay generated by the Master) Data Setup Time Rise Time of SDA and SCL Fall Time of SDA and SCL Set-up Time for STOP condition Bus Free Time between a STOP and a START Condition Capacitive Load for Each Bus Line 0.6 1.3 600 600 300 0 100 20+0.1Cb 15+0.1Cb 600 1.3 10 200 300 300 900 900 Limit Max µs µs ns ns ns ns ns ns ns ns µs pF Units NOTE: Data guaranteed by design www.national.com 16 LM49370 Method 2. SPI/Microwire Control/3–wire Control The LM49370 can be controlled via a three wire interface consisting of a clock, data and an active low chip_select. To use this control method connect SPI_MODE to BB_VDD and use TEST_MODE/CS as the chip_select as follows: 20191706 FIGURE 3. SPI Write Transaction If the application requires read access to the register set; for example to determine the cause of an interrupt request, the GPIO2 pin can be configured as an SPI format serial data output by setting the GPIO_SEL in the GPIO configuration register (0x1Ah) to SPI_SDO. To perform a read rather than a write to a particular address the MSB of the register address field is set to a 1, this effectively mirrors the contents of the register field to read-only locations above 0x80h: 20191707 FIGURE 4. SPI Read Transaction Three Wire Mode Write Bus Timing 20191709 FIGURE 5. SPI Timing 17 www.national.com LM49370 12.0 Status & Control Registers TABLE 1. Register Map (The default value of all I2C registers is 0x00h) Addre ss Register 7 6 DAC_ MODE FORCERQ VCOFATS PLLTEST NGZXDD HPF_MODE Q_DIV PLL_CLK_SEL SAMPLE_RATE RIGHT PEAKTIME NG_ENB AGC_TARGET AGC_MAX_GAIN AGC_HOLD_TIME SE_DIFF MUTE BTNTYPE PREAMP_GAIN MIC_BIAS_VOLTAGE SIDETONE_ATTEN MUTE AUX_DAC AUX_DAC USAXLVL MUTE MUTE DACMUTE BOOST BOOST BOOST MICGATE MUTE MUTE MUTE OCL STEREO MUTE MUTE HS_DBNC_TIME GPIN1 CUST_COM ATTENUATE P WORD_ ORDER ALAW/ μLAW GPIN2 FREQ WS_MS TEMP BTN LEVEL STEREO REVERSE CLKSRCE I2S_MODE LEFT LEFT CPI_LEVEL AUX_LEFT_LEVEL AUX_RIGHT_LEVEL DAC_LEVEL LEFT LEFT LEFT RIGHT RIGHT TEMP_INT MIC RIGHT RIGHT RIGHT CPI CPI BTN_INT STEREO MODE INENB CLKSCE CLK_MS INENB MIC CPI CPI SIDE SIDE DET_INT HEADSET 3DENB OUTENB CLK_MS OUTENB VCMVOLT BTN_DEBOUNCE_TIME ADC_CLK_SEL LEFT 5 CAP_SIZE R_DIV PLL_M PLL_N PLL_P PLL_N_MOD CPI MIC ADCMUTE ADC_MOD E AGC_ENB 4 3 OSC_ENB 2 PLL_ENB 1 CHP_MODE DAC_CLK_SEL 0 0x00h BASIC 0x01h CLOCKS 0x02h PLL_M 0x03h PLL_N 0x04h PLL_P 0x05h PLL_MOD 0x06h ADC_1 0x07h ADC_2 0x08h AGC_1 0x09h AGC_2 0x0Ah AGC_3 0x0Bh MIC_1 0x0Ch MIC_2 0x0Dh SIDETONE 0x0Eh CP_INPUT 0x0Fh AUX_LEFT 0x10h AUX_RIGHT 0x11h DAC 0x12h CP_OUTPUT 0x13h AUX OUTPUT 0x14h LS_OUTPUT 0x15h HP_OUTPUT 0x16h EP_OUTPUT 0x17h DETECT 0x18h STATUS 0x19h 3D 0x1Ah I2SMODE 0x1Bh I2SCLOCK 0x1Ch PCMMODE 0x1Dh PCMCLOCK 0x1Eh BRIDGE 0x1Fh GPIO 0x20h CMP_0_LSB 0x21h CMP_0_0SB 0x22h CMP_1_LSB 0x23h CMP_1_MSB 0x24h CMP_2_LSB 0x25h CMP_2_MSB NOISE_GATE_THRESHOLD AGC_TIGH T INT_EXT AGC_DECAY AGC_ATTACK I2S_WS_GEN_MODE PCM_SYNC__WIDTH COMPAND SDO_ LSB_HZ MONO_ SUM_SEL I2S_CLOCK_GEN_MODE SYNC_MS PCM_SYNC_GEN_MODE MONO_SUM_MODE DAC_SRC_ MODE ADC_SRC_ MODE DAC_TX_SEL GPIO_2_SEL CMP_0_LSB CMP_0_MSB CMP_1_LSB CMP_1_MSB CMP_2_LSB CMP_2_MSB PCM_CLOCKGEN MODE I2S_TX_SEL GPIO_1_SEL PCM_ TX_SEL www.national.com 18 LM49370 12.1 BASIC CONFIGURATION REGISTER This register is used to control the basic function of the chip. TABLE 2. BASIC (0x00h) Bits 1:0 Field CHIP_MODE Description The LM49370 can be placed in one of four modes which dictate its basic operation. When a new mode is selected the LM49370 will change operation silently and will re-configure the power management profile automatically. The modes are described as follows: CHIP MODE 002 012 102 112 2 3 PLL_ENABLE USE_OSC This enables the PLL. If set the power management and control circuits will assume that no external clock is available and will resort to using an on-chip oscillator for headset detection and analog power management functions such as click and pop. The PLL, ADC, and DAC are not wired to use this low quality clock. This bit must be cleared for the part to be fully turned off power-down mode. This programs the extra delays required to stabilize once charge/discharge is complete, based on the size of the bypass capacitor. CAP_SIZE 002 012 102 112 7:6 DAC_MODE Bypass Capacitor Size 0.1 µF 1 µF 2.2 µF 4.7 µF Turn-off/on time 45 ms/75 ms 45 ms/140 ms 45 ms/260 ms 45 ms/500 ms Audio System Off Off On On Typical Application Power-down Mode Stand-by mode with headset event detection Active without headset event detection Active with headset event detection 5:4 CAP_SIZE The DAC can operate in one of four modes. If an “fs*2∧N” audio clock is available, then the DAC can be run in a slightly lower power mode. If such a clock is not available, the PLL can be used to generate a suitable clock. DAC MODE 002 012 102 112 DAC OSR 125 128 64 32 Typical Application 48kHz Playback from 12.000MHz 48kHz Playback from 12.288MHz 96kHz Playback from 12.288MHz 192kHz Playback from 24.576MHz For reliable headset / push button detection the following bits should be defined before enabling the headset detection system by setting bit 0 of CHIP_MODE: The OCL-bit (Cap / Capless headphone interface; bit 6 of HP_OUTPUT (0x15h)) The headset insert/removal debounce settings (bits 6:3 of DETECT (0x17h)) The BTN_TYPE-bit (Parallel / Series push button type; bit 3 MIC_2 register (0x0Ch)) The parallel push button debounce settings (bits 5:4 of MIC_2 register (0x0Ch)) All register fields controlling the audio system should be defined before setting bit 1 of CHIP_MODE and should not be altered while the audio sub-system is active. If the analog or digital levels are below −12dB then it is not necessary to set the stereo bit allowing greater output levels to be obtained for such signals. 19 www.national.com LM49370 12.2 CLOCKS CONFIGURATION REGISTER This register is used to control the clocks throughout the chip. TABLE 3. CLOCKS (0x01h) Bits 1:0 Field DAC_CLK DAC_CLK 002 002 102 112 7:2 R_DIV This programs the R divider. R_DIV 0 1 2 3 4 5 6 7 8 9 10 11 12 13 to 61 62 63 Divide Value Bypass Bypass 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 to 31 31.5 32 Description This selects the clock to be used by the audio DAC system. DAC Input Source MCLK PLL_OUTPUT I2S_CLK_IN PCM_CLK_IN www.national.com 20 LM49370 12.3 LM49370 CLOCK NETWORK The audio ADC operates at 125*fs ( or 128*fs), so it requires a 1.000 MHz (or 1.024MHz) clock to sample at 8 kHz (at point C as marked on the following diagram). If the stereo DAC is running at 125*fs (or128*fs), it requires a 12.000MHz (or 12.288MHz) clock (at point B) for 48 kHz data. It is expected that the PLL is used to drive the audio system operating at 125*fs unless a 12.000 MHz master clock is supplied or the sample rate is always a multiple of 8 kHz. In this case the PLL can be bypassed to reduce power, with clock division being performed by the Q and R dividers instead. The PLL can also be bypassed if the system is running at 128*fs and a 12.288MHz master clock is supplied and the sample rate is a multiple of 8kHz. The PLL can also use the I2S clock input as a source. In this case, the audio DAC uses the clock from the output of the PLL and the audio ADC either uses the PLL output divided by 2*FS(DAC)/FS(ADC) or a system clock divided by Q, this allows n*8 kHz recording and 44.1 kHz playback. MCLK must be less than or equal to 30 MHz. I2S_CLK and PCM_CLK should be below 6.144MHz. When operating at 125*fs, the LM49370 is designed to work from a 12.000 MHz or 11.025 MHz clock at point A. When operating at 128*fs, the LM49370 is designed to work from a 12.288MHz or 11.2896 MHz clock at point A. This is used to drive the power management and control logic. Performance may not meet the electrical specifications if the frequency at this point deviates significantly beyond this range. 20191710 FIGURE 6. LM49370 Clock Network 21 www.national.com LM49370 12.4 COMMON CLOCK SETTINGS FOR THE DAC & ADC When DAC_MODE = '00' (bits 7:6 of (0x00h)), the DAC has an over sampling ratio of 125 but requires a 250*fs clock at point B. This allows a simple clocking solution as it will work from 12.000 MHz (common in most systems with Bluetooth or USB) at 48 kHz exactly, the following table describes the clock required at point B for various clock sample rates in the different DAC modes: TABLE 4. Common DAC Clock Frequencies DAC Sample Rate (kHz) 8 11.025 12 16 22.05 24 32 44.1 48 Clock Required at B (OSR = 125) 2 MHz 2.75625 MHz 3 MHz 4 MHz 5.5125 MHz 6 MHz 8 MHz 11.025 MHz 12 MHz Clock Required at B (OSR = 128) 2.048 MHz 2.8224 MHz 3.072 MHz 4.096 MHz 5.6448 MHz 6.144 MHz 8.192 MHz 11.2896 MHz 12.288 MHz Note: When DAC_MODE = '01' with the I2S or PCM interface operating as master, the stereo DAC operates at half the frequency of the clock at point B. This divided by two DAC clock is used as the source clock for the audio port. The over sampling ratio of the ADC is set by ADC MODE (bit 0 of 0x07h)). The table below shows the required clock frequency at point C for the different ADC modes. TABLE 5. Common ADC Clock Frequencies ADC Sample Rate (kHz) 8 11.025 12 16 22.05 24 Clock Required at C (OSR = 125) 1 MHz 1.378125 MHz 1.5 MHz 2 MHz 2.75625 MHz 3 MHz Clock Required at C (OSR = 128) 1.024 MHz 1.4112 MHz 1.536 MHz 2.048 MHz 2.8224 MHz 3.072 MHz Methods for producing these clock frequencies are described in the PLL Section. www.national.com 22 LM49370 12.5 PLL M DIVIDER CONFIGURATION REGISTER This register is used to control the input section of the PLL. (Note 12) TABLE 6. PLL_M (0x02h) Bits 0 6:0 Field RSVD PLL_M PLL_M 0 1 2 3 4 ... 126 127 7 FORCERQ Description RESERVED Input Divider Value No Divided Clock 1 1.5 2 2.5 3 to 63 63.5 64 If set, the R and Q divider are enabled and the DAC and ADC clocks are propagated. This allows operation of the I2S and PCM interfaces without the ADC or DAC being enabled, for example to act as a bridge or a clock master. The M divider should be set such that the output of the divider is between 0.5 MHz and 5 MHz. The division of the M divider is derived from PLL_M such that: M = (PLL_M + 1) / 2 Note 12: See Further Notes on PLL Programming for more detail. 23 www.national.com LM49370 12.6 PLL N DIVIDER CONFIGURATION REGISTER This register is used to control the feedback divider of the PLL. (Note 13) TABLE 7. PLL_N (0x03h) Bits 7:0 Field PLL_N PLL_N 0 to 10 11 12 13 14 … 249 250 to 255 Description This programs the PLL feedback divider as follows: Feedback Divider Value 10 11 12 13 14 … 249 250 The N divider should be set such that the output of the divider is between 0.5 MHz and 5 MHz. (Fin/M)*N will be the target resting VCO frequency, FVCO. The N divider should be set such that 40 MHz < (Fin/M)*N < 60 MHz. Fin/M is often referred to as Fcomp (comparison frequency) or Fref (reference frequency), in this document Fcomp is used. The integer division of the N divider is derived from PLL_N such that: For 9 < PLL_N < 251: N = PLL_N Note 13: See Further Notes on PLL Programming for further details. www.national.com 24 LM49370 12.7 PLL P DIVIDER CONFIGURATION REGISTER This register is used to control the output divider of the PLL. (Note 14) TABLE 8. PLL_P (0x04h) Bits 3:0 Field PLL_P PLL_P 0 1 2 3 4 ... 14 15 6:4 Q_DIV This programs the Q Divider Q_DIV 0002 0012 0102 0112 1002 1012 1102 1112 7 FAST_VCO This programs the PLL VCO range: FAST_VCO 0 1 The division of the P divider is derived from PLL_P such that: P = PLL_P + 1 Note 14: See Further Notes on PLL Programming for more details. Description This programs the PLL output divider as follows: Output Divider Value No Divided Clock 1 1.5 2 2.5 3 to 7 7.5 8 Divide Value 2 3 4 6 8 10 12 13 PLL VCO Range 40 to 60MHz 60 to 80MHz 25 www.national.com LM49370 12.8 PLL N MODULUS CONFIGURATION REGISTER This register is used to control the modulation applied to the feedback divider of the PLL. (Note 15) TABLE 9. PLL_N_MOD (0x05h) Bits 4:0 Field PLL_N_MOD PLL_N_MOD 0 1 2 to 30 31 6:5 PLL_CLK_SEL This selects the clock to be used as input for the audio PLL. PLL_INPUT_CLK 002 012 102 112 7 RSVD Reserved. MCLK I2S_CLK_IN PCM_CLK_IN — Description This programs the PLL N divider's fractional component: Fractional Addition 0/32 1/32 2/32 to 30/32 31/32 The complete N divider is a fractional divider as such: N = PLL_N + PLL_N_MOD/32 If the modulus input is zero then the N divider is simply an integer N divider. The output from the PLL is determined by the following formula: Fout = (Fin*N)/(M*P) Note 15: See Further Notes on PLL Programming for more details. www.national.com 26 LM49370 12.9 FURTHER NOTES ON PLL PROGRAMMING The sigma-delta PLL Is designed to drive audio circuits requiring accurate clock frequencies of up to 30MHz with frequency errors noise-shaped away from the audio band. The 5 bits of modulus control provide exact synchronization of 48kHz and 44.1kHz sample rates from any common system clock. In systems where an isochronous I2S data stream is the source of data to the DAC a clock synchronous to the sample rate should be used as input to the PLL (typically the I2S clock). If no isochronous source is available, then the PLL can be used to obtain a clock that is accurate to within 1Hz of the correct sample rate although this is highly unlikely to be a problem. 201917r0 FIGURE 7. PLL Overview TABLE 10. Example PLL Settings for 48 kHz and 44.1 kHz Sample Rates in DAC MODE 00 Fin (MHz) 11 12.288 13 14.4 16.2 16.8 19.2 19.44 19.68 19.8 11 11.2896 12 13 14.4 16.2 16.8 19.2 19.44 19.68 19.8 Fs (kHz) 48 48 48 48 48 48 48 48 48 48 44.1 44.1 44.1 44.1 44.1 44.1 44.1 44.1 44.1 44.1 44.1 M 11 4 13 9 27 14 13 27 20.5 16.5 11 8 5 13 12 9 17 16 13.5 20.5 11 N 60 19.53125 60 37.5 100 50 40.625 100 62.5 50 55.125 39.0625 22.96875 55.125 45.9375 30.625 55.78125 45.9375 38.28125 45.9375 30.625 P 5 5 5 5 5 5 5 6 5 5 5 5 5 5 5 5 5 5 5 44 5 PLL_M 21 7 25 17 53 27 25 53 40 32 21 15 9 25 23 17 33 31 26 40 21 PLL_N 60 19 60 37 100 50 40 100 62 50 55 39 22 55 45 9 30 45 38 45 30 PLL_N_MOD 0 17 0 16 0 0 20 0 16 0 4 2 31 4 30 20 25 30 9 30 20 PLL_P 9 9 9 9 9 9 9 11 9 9 9 9 9 9 9 9 9 9 9 7 9 Fout (MHz) 12 12 12 12 12 12 12 12 12 12 11.025 11.025 11.025 11.025 11.025 11.025 11.025 11.025 11.025 11.025 11.025 27 www.national.com LM49370 TABLE 11. Example PLL Settings for 48 kHz and 44.1 kHz Sample Rates in DAC MODE 01 Fin (MHz) 12 13 14.4 16.2 16.8 19.2 19.44 19.68 19.8 12 13 14.4 16.2 16.8 19.2 19.44 19.68 19.8 Fs (kHz) 48 48 48 48 48 48 48 48 48 44.1 44.1 44.1 44.1 44.1 44.1 44.1 44.1 44.1 M 12.5 26.5 37.5 37.5 12.53 12.5 40.5 20.5 37.5 35.5 37 37.5 47.5 12.5 12.5 37.5 44.5 48 N 64 112.71875 128 128 32 32 128 64 128 133.59375 144.59375 147 182.0625 42 36.75 98 114.875 136.84375 P 5 4.5 4 4.5 3.5 4 58 5 5.5 4 4.5 5 5.5 5 5 4.5 4.5 5 PLL_M 24 52 74 74 24 24 80 40 74 70 73 74 94 24 24 74 88 95 PLL_N 64 112 128 128 32 32 128 64 128 133 144 147 182 42 36 98 114 136 PLL_N_MOD 0 23 0 0 0 0 0 0 0 19 19 0 2 0 24 0 28 27 PLL_P 9 8 7 8 6 7 9 9 10 7 8 9 10 9 9 9 8 9 Fout (MHz) 12.288 12.288 12.288 12.288 12.288 12.288 12.288 12.288 12.288 11.2896 11.2896 11.2896 11.2896 11.2896 11.2896 11.2896 11.2896 11.2896 www.national.com 28 LM49370 These tables cover the most common applications, obtaining clocks for derivative sample rates such as 22.05 kHz should be done by increasing the P divider value or using the R/Q dividers. An example of obtaining 12.000 MHz from 1.536 MHz is shown below (this is typical for deriving DAC clocks from I2S datastreams). Choose a small range of P so that the VCO frequency is swept between 40 MHz and 60 MHz (or 60–80 MHz if VCOFAST is used). Remembering that the P divider can divide by half integers, for a 12 MHz output, this gives possible P values of 3, 3.5, 4, 4.5, or 5. The M divider should be set such that the comparison frequency (Fcomp) is between 0.5 and 5 MHz. This gives possible M values of 1, 1.5, 2, 2.5, or 3. The most accurate N and N_MOD can be calculated by sweeping the P and M inputs of the following formulas: N = FLOOR(((Fout/Fin)*(P*M)),1) N_MOD = ROUND(32*((((Fout)/Fin)*(P*M)-N),0) This shows that setting M = 1, N = 39+1/16, P = 5 (i.e. PLL_M = 0, PLL_N = 39, PLL_N_MOD = 2, & PLL_P = 4) gives a comparison frequency of 1.536MHz, a VCO frequency of 60 MHz and an output frequency of 12.000 MHz. The same settings can be used to get 11.025 from 1.4112 MHz for 44.1 kHz sample rates. Care must be taken when synchronization of isochronous data is not possible, i.e. when the PLL has to be used but an exact frequency match cannot be found. The I2S should be master on the LM49370 so that the data source can support appropriate SRC as required. This method should only be used with data being read on demand to eliminate sample rate mismatch problems. Where a system clock exists at an integer multiple of the required ADC or DAC clock rate it is preferable to use this rather than the PLL. The LM49370 is designed to work in 8, 12, 16, 24, 48 kHz modes from a 12 MHz clock and 8 kHz modes from a 13 MHz clock without the use of the PLL. This saves power and reduces clock jitter which can affect SNR. 29 www.national.com LM49370 12.10 ADC_1 CONFIGURATION REGISTER This register is used to control the LM49370's audio ADC. TABLE 12. ADC_1 (0x06h) Bits 0 1 2 3 5:4 Field MIC_SELECT CPI_SELECT LEFT_SELECT ADC_SAMPLE_ RATE Description If set the microphone preamp output is added to the ADC input signal. If set the cell phone input is added to the ADC input signal. If set the left stereo bus is added to the ADC input signal. This programs the closest expected sample rate of the mono ADC, which is a variable required by the AGC algorithm whenever the AGC is in use. This does not set the sample rate of the mono ADC. ADC_SAMPLE_RATE 002 012 102 112 7:6 HPF_MODE This sets the HPF of the ADC HPF-MODE 002 012 HPF Response No HPF FS = 8 kHz, −0.5 dB @ 300 Hz, Notch @ 55 Hz FS = 12 kHz, −0.5 dB @ 450 Hz, Notch @ 82 Hz FS = 16 kHz, −0.5 dB @ 600 Hz, Notch @ 110 Hz FS = 8 kHz, −0.5 dB @ 150 Hz, Notch @ 27 Hz FS = 12 kHz, −0.5 dB @ 225 Hz, Notch @ 41 Hz FS = 16 kHz, −0.5 dB @ 300 Hz, Notch @ 55 Hz No HPF Sample Rate 8 kHz 12 kHz 16 kHz 24 kHz RIGHT_SELECT If set the right stereo bus is added to the ADC input signal. 102 112 www.national.com 30 LM49370 12.11 ADC_2 CONFIGURATION REGISTER This register is used to control the LM49370's audio ADC. TABLE 13. ADC_2 (0x07h) Bit s 0 Field ADC_MODE This sets the oversampling ratio of the ADC MODE 0 1 1 ADC_MUTE If set, the analog inputs to the ADC are muted. ADC OSR 125fs 128fs Description 4:2 AGC_FRAME_TIME This sets the frame time to be used by the AGC algorithm. In a given frame, the AGC's peak detector determines the peak value of the incoming microphone audio signal and compares this value to the target value of the AGC defined by AGC_TARGET (bits [3:1] of register (0x08h)) in order to adjust the microphone preamplifier's gain accordingly. AGC_FRAME_TIME basically sets the sample rate of the AGC to adjust for a wide variety of speech patterns. (Note 16) AGC_FRAME_TIME 0002 0012 0102 0112 1002 1012 1102 1112 6:5 ADC_CLK This selects the clock to be used by the audio ADC system. ADC_CLK 002 012 102 112 7 NGZXDD Source MCLK PLL_OUTPUT I2S_CLK_IN PCM_CLK_IN Time (ms) 96 128 192 256 384 512 768 1000 If set, the noise gate will not wait for a zero crossing before mute/unmuting. This bit should be set if the ADC's HPF is disabled and if there is a large DC or low frequency component at the ADC input. NGZXDD 0 1 Result Noise Gate operates on ZXD events Noise Gate operates on frame boundaries Note 16: Refer to the AGC overview for further detail. 31 www.national.com LM49370 12.12 AGC_1 CONFIGURATION REGISTER This register is used to control the LM49370's Automatic Gain Control. (Note 17) TABLE 14. AGC_1 (0x08h) Bit s 0 3:1 Field AGC_ENABLE AGC_TARGET Description If set, the AGC controls the analog microphone preamplifier gain into the system. This feature is useful for microphone signals that are routed to the ADC. This programs the target level of the AGC. This will depend on the expected transients and desired headroom. Refer to AGC_TIGHT (bit 7 of 0x09h) for more detail. AGC_TARGET 0002 0012 0102 0112 1002 1012 1102 1112 4 7:5 Target Level −6 dB −8 dB −10 dB −12 dB −14 dB −16 dB −18 dB −20 dB NOISE_GATE_ON If set, signals below the noise gate threshold are muted.The noise gate is only activated after a set period of signal absence. NOISE_ GATE_ THRES This field sets the expected background noise level relative to the peak signal level. The sole presence of signals below this level will not result in an AGC gain change of the input and will be gated from the ADC output if the NOISE_GATE_ON is set. This level must be set even if the noise gate is not in use as it is required by the AGC algorithm. NOISE_GATE_THRES 0002 0012 0102 0112 1002 1012 1102 1112 Level −72 dB −66 dB −60 dB −54 dB −48 dB −42 dB −36 dB −30 dB Note 17: See the AGC overview. www.national.com 32 LM49370 12.13 AGC_2 CONFIGURATION REGISTER This register is used to control the LM49370's Automatic Gain Control. TABLE 15. AGC_2 (0x09h) Bits 3:0 Field AGC_MAX_GAIN 00002 00012 00102 00112 01002 to 11002 11012 11102 11112 6:4 AGC_DECAY AGC_DECAY 0002 0012 0102 0112 1002 1012 1102 1112 7 AGC_TIGHT AGC_TIGHT = 0 AGC_TARGET 0002 0012 0102 0112 1002 1012 1102 1112 AGC_TIGHT = 1 0002 0012 0102 0112 1002 1012 1102 1112 Min Level −6 dB −8 dB −10 dB −12 dB −14 dB −16 dB −18 dB −20 dB −6 dB −8 dB −10 dB −12 dB −14 dB −16 dB −18 dB −20 dB Description Max Preamplifier Gain 6 dB 8 dB 10 dB 12 dB 14 dB to 30 dB 32 dB 34 dB 36 dB Step Time (ms) 32 64 128 256 512 1024 2048 4096 Max Level −3 dB −4 dB −5 dB −6 dB −7 dB −8 dB −9 dB −10 dB −3 dB −5 dB −7 dB −9 dB −11 dB −13 dB −15 dB −17 dB AGC_MAX_GAIN This programs the maximum gain that the AGC algorithm can apply to the microphone preamplifier. This programs the speed at which the AGC will increase gains if it detects the input level is a quiet signal. If set, the AGC algorithm controls the microphone preamplifier more exactly. (Note 18) Note 18: The AGC can be used to control the analog path of the microphone to the output stages or to optimize the microphone path for recording on the ADC. When the analog path is used this bit should be set to ensure the target is tightly adhered to. If the ADC is the only destination of the microphone or the desired analog mixer level is line level then AGC_TIGHT should be cleared, allowing greater dynamic rage of the recorded signal. For further details see the AGC overview. 33 www.national.com LM49370 12.14 AGC_3 CONFIGURATION REGISTER This register is used to control the LM49370's Automatic Gain Control. (Note 19) TABLE 16. AGC_3 (0x0Ah) Bits 4:0 Field Description AGC_HOLDTIME This programs the amount of delay before the AGC algorithm begins to adjust the gain of the microphone preamplifier. AGC_HOLDTIME 000002 000012 000102 000112 001002 to 111002 111012 111102 111112 No. of speech segments 0 1 2 3 4 to 28 29 30 31 Step Time (ms) 32 64 128 256 512 1024 2048 4096 7:5 AGC_ATTACK This programs the speed at which the AGC will reduce gains if it detects the input level is too large. AGC_ATTACK 0002 0012 0102 0112 1002 1012 1102 1112 Note 19: See the AGC overview. www.national.com 34 LM49370 12.15 AGC OVERVIEW The Automatic Gain Control (AGC) system can be used to optimize the dynamic range of the ADC for voice data when the level of the source is unknown. A target level for the output is set so that any transients on the input won’t clip during normal operation. The AGC circuit then compares the output of the ADC to this level and increases or decreases the gain of the microphone preamplifier to compensate. If the audio from the microphone is to be output digitally through the ADC then the full dynamic range of the ADC can be used automatically. If the output is through the analog mixer then the ADC is used to monitor the microphone level. In this case, the analog dynamic range is less important than the absolute level, so AGC_TIGHT should be set to tie transients closely to the target level. To ensure that the system doesn’t reduce the quality of the speech by constantly modulating the microphone preamplifier gain, the ADC output is passed through an envelope detector. This frames the output of the ADC into time segments roughly equal to the phonemes found in speech (AGC_FRAME_TIME). To calculate this, the circuit must also know the sample rate of the data from the ADC (ADC_SAMPLERATE). If after a programmable number of these segments (AGC_HOLDTIME), the level is consistently below target, the gain will be increased at a programmable rate (AGC_DECAY). If the signal ever exceeds the target level (AGC_TARGET) then the gain of the microphone is reduced immediately at a programmable rate (AGC_ATTACK). This is demonstrated below: 20191712 AGC Operation Example The signal in the above example starts with a small analog input which, after the hold time has timed out, triggers a rise in the gain ((1) → (2)). After some time the real analog input increases and it reaches the threshold for a gain reduction which decreases the gain at a faster rate ((2) → (3)) to allow the elimination of typical popping noises. Only ADC outputs that are considered signal (rather than noise) are used to adjust the microphone preamplifier gain. The signal to noise ratio of the expected input signal is set by NOISE_GATE_THRESHOLD. In some situations it is preferable to remove audio considered to be consisting solely of background noise from the audio output; for example conference calls. This can be done by setting NOISE_GATE_ON. This does not affect the performance of the AGC algorithm. The AGC algorithm should not be used where very large background noise is present. If the type of input data, application and microphone is known then the AGC will typically not be required for good performance, it is intended for use with inputs with a large dynamic range or unknown nominal level. When setting NOISE_GATE_THRESHOLD be aware that in some mobile phone scenarios the ADC SNR will be dictated by the microphone performance rather than the ADC or the signal. Gain changes to the microphone are performed on zero crossings. To eliminate DC offsets, wind noise, and pop sounds from the output of the ADC, the ADC's HPF should always be enabled. 35 www.national.com LM49370 12.16 MIC_1 CONFIGURATION REGISTER This register is used to control the microphone configuration. TABLE 17. MIC_1 (0x0Bh) Bits 3:0 Field PREAMP_GAIN PREAMP_GAIN 00002 00012 00102 00112 01002 to 11002 11012 11102 11112 4 5 6 MIC_MUTE INT_SE_DIFF INT_EXT If set, the microphone preamplifier is muted. If set, the internal microphone is assumed to be single ended and the negative connection is connected to the ADC common mode point internally. This allows a single-ended internal microphone to be used. If set, the single ended external microphone is used and the negative microphone input is grounded internally, otherwise internal microphone operation is assumed. (Note 20) Description This programs the gain applied to the microphone preamplifier if the AGC is not in use. Gain 6 dB 8 dB 10 dB 12 dB 14 dB to 30 dB 32 dB 34 dB 36 dB Note 20: On changing INT_EXT from internal to external note that the dc blocking cap will not be charged so some time should be taken (300 ms for a 1 µF cap) between the detection of an external headset and the switching of the output stages and ADC to that input to allow the DC points on either side of this cap to stabilize. This can be accomplished by deselecting the microphone input from the audio outputs and ADC until the DC points stabilize. An active MIC path to CPOUT or the ADC may result in the microphone DC blocking caps causing audio pops under the following situations: 1) Switching between internal and external microphone operation while in chip modes '10' or '11'. 2) Toggling in and out of powerdown/standby modes. 3) Toggling between chip modes '10' and '11' whenever external microphone operation is selected. 4) The insertion/removal of a headset while in chip modes '10' or '11' whenever external microphone operation is selected. To avoid these potential pop issues, it is recommended to deselect the microphone input from CPOUT and ADC until the DC points stabilize. www.national.com 36 LM49370 12.17 MIC_2 CONFIGURATION REGISTER This register is used to control the microphone configuration. TABLE 18. MIC_2 (0x0Ch) Bits 0 Field OCL_ VCM_ VOLTAGE Description This selects the voltage used as virtual ground (HP_VMID pin) in OCL mode. This will depend on the available supply and the power output requirements of the headphone amplifiers. OCL_VCM_VOLTAGE 0 1 2:1 MIC_ BIAS_ VOLTAGE Voltage 1.2V 1.5V This selects the voltage as a reference to the internal and external microphones. Only one bias pin is driven at once depending on the INT_EXT bit setting found in the MIC_1 (0x0Bh) register. MIC_BIAS_VOLTAGE should be set to '11' only if A_VDD > 3.4V. In OCL mode, MIC_BIAS_VOLTAGE = '00' (EXT_BIAS = 2.0V) should not be used to generate the EXT_BIAS supply for a cellular headset external microphone. Please refer to Table 19 for more detail. MIC_BIAS_VOLTAGE 002 012 102 112 EXT_BIAS/INT_BIAS 2.0V 2.5V 2.8V 3.3V 3 BUTTON_TYPE If set, the LM49370 assumes that the button (if used) in the headset is in series (series push button) with the microphone, opening the circuit when pressed. The default is for the button to be in parallel (parallel push button), shorting out the microphone when pressed. This sets the time used for debouncing the pushing of the button on a headset with a parallel push button. BUTTON_DEBOUNCE_TIME 002 012 102 112 Time (ms) 0 8 16 32 5:4 BUTTON_ DEBOUNCE_ TIME In OCL mode there is a trade-off between the external microphone supply voltage (EXT_MIC_BIAS - OCL_VCM_ VOLTAGE) and the maximum output power possible from the headphones. A lower OCL_VCM_VOLTAGE gives a higher microphone supply voltage but a lower maximum output power from the headphone amplifiers due to the lower OCL_VCM_VOLTAGE - A_VSS. TABLE 19. External MIC Supply Voltages in OCL Mode Available A_VDD > 3.4V 2.9V to 3.4V 2.8V to 2.9V 2.7V to 2.8V Recommended EXT_MIC_BIAS 3.3V 2.8V 2.5V 2.5V Supply to Microphone OCL_VCM_VOLT = 1.5V 1.8V 1.3V 1.0V OCL_VCM_VOLT = 1.2V 2.1V 1.6V 1.3V 1.3V 37 www.national.com LM49370 12.18 SIDETONE ATTENUATION REGISTER This register is used to control the analog sidetone attenuation. (Note 21) TABLE 20. SIDETONE (0x0Dh) Bits 3:0 Field SIDETONE_ ATTEN SIDETONE_ATTEN 00002 00012 00102 00112 01002 01012 to 10102 10112 to 11112 Description This programs the attenuation applied to the microphone preamp output to produce a sidetone signal. Attenuation -Inf −30 dB −27 dB −24 dB −21 dB −18 dB to −3 dB 0 dB Note 21: An active SIDETONE path to an audio output may result in the microphone DC blocking caps causing audio pops under the following situations: 1) Switching between internal and external microphone operation while in chip modes '10' or '11'. 2) Toggling in and out of powerdown/standby modes. 3) Toggling between chip modes '10' and '11' whenever external microphone operation is selected. 4) The insertion/removal of a headset while in chip modes '10' or '11' whenever external microphone operation is selected. To avoid potential pop noises, it is recommended to set SIDETONE_ATTEN to '0000' until DC points have stabilized whenever the SIDETONE path is used. 12.19 CP_INPUT CONFIGURATION REGISTER This register is used to control the differential cell phone input. TABLE 21. CP_INPUT (0x0Eh) Bits 4:0 Field CPI_LEVEL CPI_LEVEL 000002 000012 000102 000112 00100 to 111002 111012 111102 111112 5 CPI_MUTE If set, the CPI input is muted at source. Description This programs the gain/attenuation applied to the cell phone input. Level −34.5 dB −33 dB −31.5 dB −30 dB −28.5 dB to +7.5 dB +9 dB +10.5 dB +12 dB www.national.com 38 LM49370 12.20 AUX_LEFT CONFIGURATION REGISTER This register is used to control the left aux analog input. TABLE 22. AUX_LEFT (0x0Fh) Bits 4:0 Field AUX_ LEFT_ LEVEL AUX_LEFT_LEVEL 000002 000012 000102 000112 00100 to 111002 111012 111102 111112 5 AUX_ LEFT_ BOOST AUX_L_MUTE Description This programs the gain/attenuation applied to the AUX LEFT analog input to the mixer. (Note 22) Level (With Boost) −34.5 dB −33 dB −31.5 dB −30 dB −28.5 dB to +7.5 dB +9 dB +10.5 dB +12 dB Level (Without Boost) −46.5 dB −45 dB −43.5 dB −42 dB −40.5 dB to −4.5 dB −3 dB −1.5 dB 0 dB If set, the gain of the AUX_LEFT input to the mixer is increased by 12 dB (see above). 6 7 If set, the AUX LEFT input is muted. AUX_OR_DAC_L If set, the AUX LEFT input is passed to the mixer, the default is for the DAC LEFT output to be passed to the mixer. Note 22: The recommended mixer level is 1V RMS. The auxiliary analog inputs can be boosted by 12 dB if enough headroom is available. Clipping may occur if the analog power supply is insufficient to cater for the required gain. 12.21 AUX_RIGHT CONFIGURATION REGISTER This register is used to control the right aux analog input. TABLE 23. AUX_RIGHT (0x10h) Bits 4:0 Field AUX_ RIGHT_ LEVEL AUX_RIGHT_LEVEL 000002 000012 000102 000112 00100 to 111002 111012 111102 111112 5 6 7 AUX_ RIGHT_BOOST AUX_R_MUTE Description This programs the gain/attenuation applied to the AUX RIGHT analog input to the mixer. (Note 23) Level (With Boost) −34.5 dB −33 dB −31.5 dB −30 dB −28.5 dB to +7.5 dB +9 dB +10.5 dB +12 dB Level (Without Boost) −46.5 dB −45 dB −43.5 dB −42 dB −40.5 dB to −4.5 dB −3 dB −1.5 dB 0 dB If set, the gain of the AUX_RIGHT input to the mixer is increased by 12 dB (see above). If set, the AUX RIGHT input is muted. AUX_OR_DAC_R If set, the AUX RIGHT input is passed to the mixer, the default is for the DAC RIGHT output to be passed to the mixer. Note 23: The recommended mixer level is 1V RMS. The auxiliary analog inputs can be boosted by 12 dB if enough headroom is available. Clipping may occur if the analog power supply is insufficient to cater for the required gain. 39 www.national.com LM49370 12.22 DAC CONFIGURATION REGISTER This register is used to control the DAC levels to the mixer. TABLE 24. DAC (0x11h) Bits 4:0 Field DAC_LEVEL DAC_LEVEL 000002 000012 000102 000112 00100 to 111002 111012 111102 111112 5 6 7 DAC_BOOST DAC_MUTE USE_AUX_ LEVELS Description This programs the gain/attenuation applied to the DAC input to the mixer. (Note 24) Level (With Boost) −34.5 dB −33 dB −31.5 dB −30 dB −28.5 dB to +7.5 dB +9 dB +10.5 dB +12 dB Level (Without Boost) −46.5 dB −45 dB −43.5 dB −42 dB −40.5 dB to −4.5 dB −3 dB −1.5 dB 0 dB If set, the gain of the DAC inputs to the mixer is increased by 12dB (see above). If set, the stereo DAC input is muted on the next zero crossing. If set, the gain of the DAC inputs is controlled by the AUX_LEFT and AUX_RIGHT registers, allowing a stereo balance to be applied. Note 24: The output from the DAC is 1V RMS for a full scale digital input. This can be boosted by 12 dB if enough headroom is available. Clipping may occur if the analog power supply is insufficient to cater for the required gain. www.national.com 40 LM49370 12.23 CP_OUTPUT CONFIGURATION REGISTER This register is used to control the differential cell phone output. (Note 25) TABLE 25. CP_OUTPUT (0x12h) Bit s 0 1 2 3 4 Field MIC_SELECT RIGHT_SELECT LEFT_SELECT CPO_MUTE Description If set, the microphone channel of the mixer is added to the CP_OUT output signal. If set, the right channel of the mixer is added to the CP_OUT output signal. If set, the left channel of the mixer is added to the CP_OUT output signal. If set, the CPOUT output is muted. MIC_NOISE_GAT If this is set and NOISE_GATE_ON (register 0x08h) is enabled, the MIC to CPO path will be gated if the E signal is determined to be noise by the AGC (that is, if the signal is below the set noise threshold). Note 25: The gain of cell phone output amplifier is 0 dB. 12.24 AUX_OUTPUT CONFIGURATION REGISTER This register is used to control the differential auxiliary output. (Note 26) TABLE 26. AUX_OUTPUT (0x13h) Bits 0 1 2 3 Field CPI_SELECT LEFT_SELECT AUX_MUTE Description If set, the cell phone input channel of the mixer is added to the AUX_OUT output signal. If set, the left channel of the mixer is added to the AUX_OUT output signal. If set, the AUX_OUT output is muted. RIGHT_SELECT If set, the right channel of the mixer is added to the AUX_OUT output signal. Note 26: The gain of the auxiliary output amplifier is 0 dB. If a second (external) loudspeaker amplifier is to be used its gain should be set to 12 dB to match the onboard loudspeaker amplifier gain. 12.25 LS_OUTPUT CONFIGURATION REGISTER This register is used to control the loudspeaker output. (Note 27) TABLE 27. LS_OUTPUT (0x14h) Bits 0 1 2 3 4 Field CPI_SELECT LEFT_SELECT LS_MUTE RSVD Description If set, the cell phone input channel of the mixer is added to the loudspeaker output signal. If set, the left channel of the mixer is added to the loudspeaker output signal. If set, the loudspeaker output is muted. Reserved. RIGHT_SELECT If set, the right channel of the mixer is added to the loudspeaker output signal. Note 27: The gain of the loudspeaker output amplifier is 12 dB. 41 www.national.com LM49370 12.26 HP_OUTPUT CONFIGURATION REGISTER This register is used to control the stereo headphone output. (Note 28) TABLE 28. HP_OUTPUT (0x15h) Bits 0 1 2 Field CPI_SELECT RIGHT_SELECT Description If set, the cell phone input channel of the mixer is added to both of the headphone output signals. If set, the right channel of the mixer is added to the headphone output. If the STEREO bit (0x00h) is set, the right channel is added to the right headphone output signal only. If the STEREO bit (0x00h) is cleared, it is added to both the right and left headphone output signals. If set, the left channel of the mixer is added to the headphone output. If the STEREO bit (0x00h) is set, the left channel is added to the left headphone output signal only. If the STEREO bit (0x00h) is cleared, it is added to both the right and left headphone output signals. If set, the headphone output is muted. If set, the mixers assume that the signals on the left and right internal busses are highly correlated and when these signals are combined their levels are reduced by 6dB to allow enough headroom for them to be summed. If set, the part is placed in OCL (Output Capacitor Less) mode. SIDETONE_SELECT If set, the sidetone channel of the mixer is added to both of the headphone output signals. 3 LEFT_SELECT 4 5 HP_MUTE STEREO 6 OCL Note 28: The gain of the headphone output amplifier is –6 dB for the cell phone input channel and sidetone channel of the mixer. When the STEREO bit (0x00h) is set, headphone output amplifier gain is –6 dB for the left and right channel. When the STEREO bit (0x00h) is cleared, the headphone output amplifier gain is –12 dB for the left and right channel (to allow enough headroom for adding them and routing them to both headphone amplifiers). 12.27 EP_OUTPUT CONFIGURATION REGISTER This register is used to control the mono earpiece output. (Note 29) TABLE 29. EP_OUTPUT (0x16h) Bits 0 1 2 3 4 Field CPI_SELECT RIGHT_SELECT LEFT_SELECT EP_MUTE Description If set, the cell phone input channel of the mixer is added to the earpiece output signal. If set, the right channel of the mixer is added to the earpiece output signal. If set, the left channel of the mixer is added to the earpiece output signal. If set, the earpiece output is muted. SIDETONE_SELECT If set, the sidetone channel of the mixer is added to the earpiece output signal. Note 29: The gain of the earpiece output amplifier is 6 dB. www.national.com 42 LM49370 12.28 DETECT CONFIGURATION REGISTER This register is used to control the headset detection system. TABLE 30. DETECT (0x17h) Bits 0 1 2 Field DET_INT BTN_INT TEMP_INT Description If set, an IRQ is raised when a change is detected in the headset status. Clearing this bit will clear an IRQ that has been triggered by the headset detect. If set, an IRQ is raised when the headset button is pressed. Clearing this bit will clear an IRQ that has been triggered by a button event. If set, an IRQ is raised during a temperature event. The LM49370 will still automatically cycle the class AB power amplifiers off if the internal temperature is too high. This bit should not be set whenever the class D amplifier is turned on. Clearing this bit will clear an IRQ that has been triggered by a temperature event. This sets the time used for debouncing the analog signals from the detection inputs used to sense the insertion/removal of a headset. HS_DBNC_TIME 00002 00012 00102 00112 01002 01012 01102 01112 10002 10012 10102 10112 11002 11012 11102 11112 Time (ms) 0 8 16 32 48 64 96 128 192 256 384 512 768 1024 1536 2048 6:3 HS_ DBNC_TIME 43 www.national.com LM49370 12.29 HEADSET DETECT OVERVIEW The LM49370 has built in monitors to automatically detect headset insertion or removal. The detection scheme can differentiate between mono, stereo, mono-cellular and stereo-cellular headsets. Upon detection of headset insertion or removal, the LM49370 updates read-only bit 0 - headset absence/presence, bit 1- mono/stereo headset and bit 2 - headset without mic / with mic, of the STATUS register (0x18h). Headset insertion/removal and headset type can also be detected in standby mode; this consumes no analog supply current when the headset is absent. The LM49370 can be programmed to raise an interrupt (set the IRQ pin high) when headset insert/removal is sensed by setting bit 0 of DETECT (0x17h). When headset detection is enabled in active mode and a headset is not detected, the HPL_OUT and HPR_OUT amplifiers will be disabled (switched off for capless mode and muted for AC-coupled mode) and the EXT_BIAS pin will be disconnected from the MIC_BIAS amplifier, irrespective of control register settings. The LM49370 also has the capability to detect button press, when a button is present on the headset microphone. Both parallel button-type (in parallel with the headset microphone, default value) and series button-type (in series with the headset microphone) can be detected; the button type used needs to be defined in bit 3 of MIC_2 (0x0Ch). Button press can also be detected in standby mode; this consumes 10 µA of analog supply current for a series type push button and 100 µA for a parallel type push button. Upon button press, the LM49370 updates bit 3 of STATUS (0x18h). In active OCL mode, with internal microphone selected (INT_EXT = 0; (reg 0x0Bh)), if a parallel pushbutton headset is inserted into the system, INT_EXT must be set high before BTN (bit 3 of STATUS (0x18h)) can be read. The LM49370 can also be programmed to raise an interrupt on the IRQ pin when button press is sensed by setting bit 1 of DETECT (0x17h). The LM49370 provides debounce programmability for headset and button detect. Debounce programmability can be used to reject glitches generated, and hence avoid false detection, while inserting/removing a headset or pressing a button. Headset insert/removal debounce time is defined by HS_DBNC_TIME; bits 6:3 of DETECT (0x17h). Parallel button press debounce time is defined by BTN_DBNC_TIME; bits 5:4 of MIC_2 (0x0Ch). Note that since the first effect of a series button press (microphone disconnected) is indistinguishable from headset removal, the debounce time for series button press in defined by HS_DBNC_TIME. Headset and push button detection can be enabled by setting CHIP_MODE 0; bit 0 of BASIC (0x00h). For reliable headset / push button detection all following bits should be defined before enabling the headset detection system: 1) the OCL-bit (AC-Coupled / Capless headphone interface (bit 6 of HP_OUTPUT (0x15h)) 2) the headset insert/removal debounce settings (bit 6:3 of DETECT (0x17h)) 3) the BTN_TYPE-bit (Parallel / Series push button type (bit 3 of MIC_2 (0x0Ch)) 4) the parallel push button debounce settings (bit 5:4 of MIC_2 (0x0Ch)) Figure 8 shows terminal connections and jack configuration for various headsets. Care should be taken to avoid any DC path from the MIC_DET pin to ground when a headset is not inserted. www.national.com 44 LM49370 20191713 FIGURE 8. Headset Configurations Supported by the LM49370 The wiring of the headset jack to the LM49370 will depend on the intended mode of the headphone amplifier: 45 www.national.com LM49370 20191714 FIGURE 9. Connection of Headset Jack to LM49370 Depends on the Mode of the Headphone Amplifier. www.national.com 46 LM49370 12.30 STATUS REGISTER This register is used to report the status of the device. TABLE 31. STATUS (0x18h) Bits 0 1 2 3 4 Field HEADSET STEREO_ HEADSET MIC BTN TEMP Description This field is high when headset presence is detected (only valid if the detection system is enabled). (Note 30) This field is high when a headset with stereo speakers is detected (only valid if the detection system is enabled). (Note 30) This field is high when a headset with a microphone is detected (only valid if the detection system is enabled). (Note 30) This field is high when the button on the headset is pressed (only valid if the detection system is enabled). IRQ is cleared when the button has been released and this register has been written to. (Note 31) If this field is high then a temperature event has occurred (write to this register to clear IRQ). This field will stay high even when the IRQ is cleared so long as the event occurs. This bit is only valid whenever the loudspeaker amplifier is turned off. (Note 31) When GPIO_SEL is set to a readable configuration a digital input on GPIO1 can be read back here. When GPIO_SEL is set to a readable configuration, a digital input on the relevant GPIO can be read back here. 5 6 GPIN1 GPIN2 Note 30: The detection IRQ is cleared when this register has been written to. Note 31: This field is cleared whenever the STATUS (0x18h) register has been written to. 47 www.national.com LM49370 12.31 3D CONFIGURATION REGISTER This register is used to control the configuration of the 3D circuit. TABLE 32. 3D (0x19h) Bits 0 Field 3D_ENB Description Setting this bit enables the 3D effect. When cleared to zero, the 3D effect is disabled and the 3D module then passes the I2S left and right channel inputs to the DAC unchanged. The stereo AUX inputs are unaffected by the 3D module. This bit selects between type 1 and type 2 3D sound effect. Clearing this bit to zero selects type 1 effect and setting it to one selects type 2. Type1: Rout = Ri-G*Lout3d, Lout = Li-G*Rout3d Type2: Rout = -Ri-G*Lout3d, Lout = Li+G*Rout3d where, Ri = Right I2S channel input Li = Left I2S channel input G = 3D gain level (Mix ratio) Rout3d = Ri filtered through a high-pass filter with a corner frequency controlled by FREQ Lout3d = Li filtered through a high-pass filter with a corner frequency controlled by FREQ This programs the level of 3D effect that is applied. LEVEL 002 012 102 112 5:4 FREQ 25% 37.5% 50% 75% FREQ 002 012 102 112 6 ATTENUATE 0Hz 300Hz 600Hz 900Hz 1 3D_TYPE 3:2 LEVEL This programs the HPF rolloff (-3dB) frequency of the 3D effect. Clearing this bit to zero maintains the level of the left and right input channels at the output. Setting this bit to one attenuates the output level by 50%. This may be appropriate for high level audio inputs when type 2 3D effect is used. Type 2 effect involves adding the same polarity of left and right inputs to give the final outputs. Type 2 effect has the potential for creating a clipping condition, however this bit offers an alternative to clipping. If set, the DAC compensation filter may be programmed by the user through registers (0x20h) to( 0x25h). Otherwise, the defaults are used. 7 CUST_COMP www.national.com 48 LM49370 12.32 I2S PORT MODE CONFIGURATION REGISTER This register is used to control the audio data interfaces. TABLE 33. I2S Mode (0x1Ah) Bits 0 1 2 Field I2S_OUT_ENB I2S_IN_ENB I2S_MODE If set, the gated. I2S Description output bus is enabled. If cleared, the I2S output will be tristate and all RX clocks will be If set, the I2S input is enabled. If this bit cleared, the I2S input is ignored and all TX clocks gated. This programs the format of the I2S interface. Definition 0 1 Normal Left Justified Operation 0 1 Normal Reversed 3 I2S_STEREO_REVERSE If set, the left and right channels are reversed. 4 6:5 I2S_WS_MS I2S_WS_GEN_MODE If set, I2S_WS generation is enabled and is Master. If cleared, I2S_WS acts as slave. This programs the I2S word length. Bits/Word 002 012 102 112 16 25 32 — 7 I2S_WORD_ORDER This bit alters the RX phasing of left and right channels. If this bit is cleared: right then left. If this bit is set: left then right. 201917r4 I2S Audio Port CLOCK/SYNC Options 49 www.national.com LM49370 12.33 I2S PORT CLOCK CONFIGURATION REGISTER This register is used to control the audio data interfaces. TABLE 34. I2S Clock (0x1Bh) Bit s 0 1 Field I2S_CLOCK_MS I2S_CLOCK_SOURCE Description If set, then I2S clock generation is enabled and is Master. If this bit is cleared, then the I2S clock is driven by the device slave. This selects the source of the clock to be used by the I2S clock generator. I2S_CLOCK_SOURCE 0 1 Clock is source from DAC (from R divider) ADC (from Q divider) 5:2 I2S_CLOCK_GEN_MODE This programs a clock divider that divides the clock defined by I2S_CLOCK_SOURCE. This divided clock is used to generate I2S_CLK in Master mode. (Note 32) Value 00002 00012 00102 00112 01002 01012 01102 01112 10002 10012 10102 10112 11002 11012 11102 11112 7:6 PCM_SYNC_WIDTH Divide By 1 2 4 6 8 10 16 20 2.5 3 3.90625 5 7.8125 — — — — 2/5 1/3 32/125 25/125 16/125 — — — Generated SYNC Looks like: 002 012 102 112 1 bit (Used for Short PCM Modes) 4 bits (Used for Long PCM Modes) 8 bits (Used for Long PCM Modes) 15 bits (Used for Long PCM Modes) Should not be set if the bits/word is less than 16. Ratio This programs the width of the PCM sync signal. Note 32: For DAC_MODE = '00', '10', '11', DAC_CLOCK is the clock at the output of the R divider. For DAC_MODE = '01', DAC_CLOCK is a divided by two version of the clock at the output of the R divider. www.national.com 50 LM49370 12.34 DIGITAL AUDIO DATA FORMATS I2S master mode can only be used when the DAC is enabled unless the FORCE_RQ bit is set. PCM Master mode can only be used when the ADC is enabled, unless the FORCE_RQ bit is set. If the PCM receiver interface is operated in slave mode the clock and sync should be enabled at the same time because the PCM receiver uses the first PCM frame to calculate the PCM interface format. This format can not be changed unless a soft reset is issued. Operating the LM49370 in master mode eliminates the risk of sample rate mismatch between the data converters and the audio interfaces. In slave mode, the PCM and I2S receivers only record the 1st 16 and 18 bits of the serial words respectively. The I2S and PCM formats are as followed: 20191715 FIGURE 10. I2S Serial Data Format (Default Mode) 201917q8 FIGURE 11. I2S Serial Data Format (Left Justified) 20191716 FIGURE 12. PCM Serial Data Format (16 bit Slave Example) 51 www.national.com LM49370 12.35 PCM PORT MODE CONFIGURATION REGISTER This register is used to control the audio data interfaces. TABLE 35. PCM MODE (0x1Ch) Bits 0 1 3 4 5 6 7 Field PCM_OUT_ENB PCM_IN_ENB Description If set, the PCM output bus is enabled. If this bit is cleared, thr PCM output will be tristate and all RX clocks will be gated. If set, the PCM input is enabled. If this bit is cleared, the PCM input is ignored and TX clocks are generated. If set, PCM_SYNC generation is enabled and is driven by the device (Master). If set, when the PCM port has run out of bits to transmit, it will tristate the SDO output. If set, the data sent to the PCM port is companded and the PCM data received by the PCM receiver is treated as companded data. If PCM_ COMPAND is set, then the data across the PCM interface to the DAC and from the ADC is companded as follows: PCM_ALAW_μLAW 0 1 Commanding Type μ-LAW A-Law PCM_CLOCK_SOURCE DAC or ADC Clock 0 = DAC, 1 = ADC (Note 32) PCM_SYNC_MS PCM_SDO_LSB_HZ PCM_COMPAND PCM_ALAW_μLAW 201917r1 FIGURE 13. PCM Audio Port CLOCK/SYNC Options www.national.com 52 LM49370 12.36 PCM PORT CLOCK CONFIGURATION REGISTER This register is used to control the configuration of audio data interfaces. TABLE 36. PCM Clock (0x1Dh) Bits 3:0 Field PCM_CLOCK_ GEN_MODE Description This programs a clock divider that divides the clock defined by PCM_CLOCK_SOURCE reg (0x1Ch). The divided clock is used to generate PCM_CLK in Master mode. (Note 32) Value 00002 00012 00102 00112 01002 01012 01102 01112 10002 10012 10102 10112 11002 11012 11102 11112 6:4 PCM_SYNC_MODE Divide By 1 2 4 6 8 10 16 20 2.5 3 3.90625 5 7.8125 — — — — 2/5 1/3 32/125 25/125 16/125 — — — Ratio This programs a clock divider that divides PCM_CLK. The divided clock is used to generate PCM_SYNC. Valve 0002 0012 0102 0112 1002 1012 1102 1112 Divide By 8 16 25 32 64 128 — — 53 www.national.com LM49370 12.37 SRC CONFIGURATION REGISTER This register is used to control the configuration of the Digital Routing interfaces. (Note 33) TABLE 37. Bridges (0x1Eh) Bits 0 Field PCM_TX_SEL PCM_TX_SEL 0 1 2:1 I2S_TX_SEL This controls the data sent to the I2S transmitter. I2S_TX_SEL 002 012 102 112 4:3 DAC_INPUT_SEL This controls the data sent to the DAC. DAC_INPUT_SEL 002 012 102 112 5 MONO_SUM_SEL This controls the data sent to the Stereo to Mono Converter MONO_SUM_SEL 0 1 7:6 MONO_SUM_MODE This controls the operation of the Stereo to Mono Converter. MONO_SUM_ MODE 002 012 102 112 Note 33: Please refer to the Application Note AN-1591 for the detailed discussion on how to use the I2S to PCM Bridge. Description This controls the data sent to the PCM transmitter. Source ADC MONO SUM Circuit Source ADC PCM Receiver DAC Interpolator (oversampled) Disabled Source I2S Receiver (In stereo) PCM Receiver (Dual Mono) ADC Disabled Source DAC Interpolated Output I2S Receiver Output Operation (Left + Right)/2 Left Right (Left + Right)/2 www.national.com 54 LM49370 201917r2 FIGURE 14. I2S to PCM Bridge 55 www.national.com LM49370 12.38 GPIO CONFIGURATION REGISTER This register is used to control the GPIOs and to control the digital signal routing when using the ADC and DAC to perform sample rate conversion. TABLE 38. GPIO Control (0x1Fh) Bits 2:0 Field GPIO_1_SEL This configures the GPIO_1 pin. GPIO_1_SEL 0002 0012 0102 0112 1002 1012 1102 1112 5:3 GPIO_2_SEL This configures the GPIO_2 pin. GPIO_2_SEL 0002 0012 0102 0112 1002 1012 1102 1112 6 7 Does What? Disable SPI_SDO Output 0 Output 1 Read Class D Enable Dig_Mic L Clock Dig_Mic R Clock Direction HiZ Output Output Output Input Output Output Output Does What? Disable SPI_SDO Output 0 Output 1 Read Class D Enable AUX Enable Dig_Mic_Data Direction HiZ Output Output Output Input Output Output Input Description ADC_SRC_MODE If set, the ADC analog is disabled and the digital is enabled, using the resampler input. DAC_SRC_MODE This does not have to be set to use DAC in SRC mode, but should be set if the user wishes to disable the DAC analog to save power. 12.39 DAC PATH COMPENSATION FIR CONFIGURATION REGISTERS To allow for compensation of roll off in the DAC and analog filter sections an FIR compensation filter is applied to the DAC input data at the original sample rate. Since the DAC can operate at different over sampling ratios the FIR compensation filter is programmable. By default the filter applies approx 2dB of compensation at 20kHz. 5 taps is sufficient to allow passband equalization and ripple cancellation to around +/0.01dB. The filter can also be used for precise digital gain and simple tone controls although a DSP or CPU should be used for more powerful tone control if required. As the FIR filter must always be phase linear, the coefficients are symmetrical. Coefficients C0, C1, and C2 are programmable, C3 is equal to C1 and C4 is equal to C0. The maximum power of this filter must not exceed that of the examples given below: www.national.com 56 LM49370 201917r3 FIGURE 15. FIR Consumption Filter Taps Sample Rate 48kHz 48kHz DAC_MODE 00 01 C0 334 61 C1 –2291 –371 C2 26984 25699 C3 –2291 –371 C4 343 61 For DAC_MODE = '00 and '01', the defaults should be sufficient; but for DAC_MODE = '10' and '11', care should be taken to ensure the widest bandwidth is available without requiring such a large attenuation at DC that inband noise becomes audible. TABLE 39. Compensation Filter C0 LSBs (0x20h) Bits 7:0 Field C0_LSB Bits 7:0 of C0[15:0] TABLE 40. Compensation Filter C0 MSBs (0x21h) Bits 7:0 Field C0_MSB Bits 15:8 of C0[15:0] TABLE 41. Compensation Filter C1 LSBs (0x22h) Bits 7:0 Field C1_LSB Bits 7:0 of C1[15:0] TABLE 42. Compensation Filter C1 MSBs (0x23h) Bits 7:0 Field C1_MSB Bits 15:8 of C1[15:0] TABLE 43. Compensation Filter C2 LSBs (0x24h) Bits 7:0 Field C2_LSB Bits 7:0 of C2[15:0] TABLE 44. Compensation Filter C2 MSBs (0x25h) Bits 7:0 Field C2_MSB Bits 15:8 of C2[15:0] Description Description Description Description Description Description 57 www.national.com LM49370 13.0 Typical Performance Characteristics (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. Stereo DAC Frequency Response fS = 8kHz Stereo DAC Frequency Response Zoom fS = 8kHz 20191701 20191702 Stereo DAC Frequency Response fS = 16kHz Stereo DAC Frequency Response Zoom fS = 16kHz 20191703 20191704 Stereo DAC Frequency Response fS = 24kHz Stereo DAC Frequency Response Zoom fS = 24kHz 20191705 20191708 www.national.com 58 LM49370 Stereo DAC Frequency Response fS = 32kHz Stereo DAC Frequency Response Zoom fS = 32kHz 20191711 20191717 Stereo DAC Frequency Response fS = 48kHz Stereo DAC Frequency Response Zoom fS = 48kHz 20191718 20191719 THD+N vs Stereo DAC Input Voltage (0dB DAC, AUXOUT) Stereo DAC Crosstalk (0dB DAC, HP SE) 20191721 20191720 59 www.national.com LM49370 MONO ADC Frequency Response fS = 8kHz, 6dB MIC MONO ADC Frequency Response Zoom fS = 8kHz, 6dB MIC 20191722 20191725 MONO ADC Frequency Response fS = 8kHz, 36dB MIC MONO ADC Frequency Response Zoom fS = 8kHz, 36dB MIC 20191726 20191727 MONO ADC Frequency Response fS = 16kHz, 6dB MIC MONO ADC Frequency Response Zoom fS = 16kHz, 6dB MIC 20191728 20191729 www.national.com 60 LM49370 MONO ADC Frequency Response fS = 16kHz, 36dB MIC MONO ADC Frequency Response Zoom fS = 16kHz, 36dB MIC 20191747 20191748 MONO ADC Frequency Response fS = 24kHz, 6dB MIC MONO ADC Frequency Response Zoom fS = 24kHz, 6dB MIC 20191749 20191750 MONO ADC Frequency Response fS = 24kHz, 36dB MIC MONO ADC Frequency Response Zoom fS = 24kHz, 36dB MIC 20191751 20191752 61 www.national.com LM49370 MONO ADC Frequency Response fS = 32kHz, 6dB MIC MONO ADC Frequency Response Zoom fS = 32kHz, 6dB MIC 20191753 20191754 MONO ADC Frequency Response fS = 32kHz, 36dB MIC MONO ADC Frequency Response Zoom fS = 32kHz, 36dB MIC 20191755 20191756 MONO ADC HPF Frequency Response fS = 8kHz, 36dB MIC (from left to right: HPF_MODE '00', '10', '01') MONO ADC HPF Frequency Response fS = 16kHz, 36dB MIC (from left to right: HPF_MODE '00', '10', '01') 20191757 20191758 www.national.com 62 LM49370 MONO ADC HPF Frequency Response fS = 24kHz, 36dB MIC (from left to right: HPF_MODE '00', '10', '01') MONO ADC HPF Frequency Response fS = 32kHz, 36dB MIC (from left to right: HPF_MODE '00', '10', '01') 20191759 20191760 MONO ADC THD+N vs MIC Input Voltage (fS = 8kHz, 6dB MIC) MONO ADC THD+N vs MIC Input Voltage (fS = 8kHz, 36dB MIC) 20191761 20191762 MONO ADC PSRR vs Frequency AVDD = 3.3V, 6dB MIC MONO ADC PSRR vs Frequency AVDD = 5V, 6dB MIC 20191763 20191764 63 www.national.com LM49370 MONO ADC PSRR vs Frequency AVDD = 3.3V, 36dB MIC MONO ADC PSRR vs Frequency AVDD = 5V, 36dB MIC 20191765 20191766 AUXOUT PSRR vs Frequency AVDD = 3.3V, 0dB AUX (AUX inputs terminated) AUXOUT PSRR vs Frequency AVDD = 5V, 0dB AUX (AUX inputs terminated) 20191767 20191768 AUXOUT PSRR vs Frequency AVDD = 3.3V, 0dB CPI (CPI inputs terminated) AUXOUT PSRR vs Frequency AVDD = 5V, 0dB CPI (CPI inputs terminated) 20191769 20191770 www.national.com 64 LM49370 AUXOUT PSRR vs Frequency AVDD = 3.3V, 0dB DAC (DAC inputs selected) AUXOUT PSRR vs Frequency AVDD = 5V, 0dB DAC (DAC inputs selected) 20191771 20191772 CPOUT PSRR vs Frequency AVDD = 3.3V, 0dB AUX (AUX inputs terminated) CPOUT PSRR vs Frequency AVDD = 5V, 0dB AUX (AUX inputs terminated) 20191773 20191774 CPOUT PSRR vs Frequency AVDD = 3.3V, 0dB DAC (DAC inputs selected) CPOUT PSRR vs Frequency AVDD = 5V, 0dB DAC (DAC inputs selected) 20191775 20191776 65 www.national.com LM49370 Earpiece PSRR vs Frequency AVDD = 3.3V, 0dB AUX (AUX inputs terminated) Earpiece PSRR vs Frequency AVDD = 5V, 0dB AUX (AUX inputs terminated) 20191777 20191778 Earpiece PSRR vs Frequency AVDD = 3.3V, 0dB CPI (CPI input terminated) Earpiece PSRR vs Frequency AVDD = 5V, 0dB CPI (CPI input terminated) 20191779 20191780 Earpiece PSRR vs Frequency AVDD = 3.3V, 0dB DAC (DAC input selected) Earpiece PSRR vs Frequency AVDD = 5V, 0dB DAC (DAC input selected) 20191781 20191782 www.national.com 66 LM49370 Headphone PSRR vs Frequency AVDD = 3.3V, 0dB AUX, OCL 1.2V (AUX inputs terminated) Headphone PSRR vs Frequency AVDD = 5V, 0dB AUX, OCL 1.2V (AUX inputs terminated) 20191783 20191784 Headphone PSRR vs Frequency AVDD = 3.3V, 0dB CPI, OCL 1.2V (CPI input terminated) Headphone PSRR vs Frequency AVDD = 5V, 0dB CPI, OCL 1.2V (CPI input terminated) 20191785 20191786 Headphone PSRR vs Frequency AVDD = 3.3V, 0dB ADC, OCL 1.2V (DAC input selected) Headphone PSRR vs Frequency AVDD = 5V, 0dB ADC, OCL 1.2V (DAC input selected) 20191787 20191788 67 www.national.com LM49370 Headphone PSRR vs Frequency AVDD = 3.3V, 0dB AUX, OCL 1.5V (AUX inputs terminated) Headphone PSRR vs Frequency AVDD = 5V, 0dB AUX, OCL 1.5V (AUX inputs terminated) 20191789 20191790 Headphone PSRR vs Frequency AVDD = 3.3V, 0dB CPI, OCL 1.5V (CPI input terminated) Headphone PSRR vs Frequency AVDD = 5V, 0dB CPI, OCL 1.5V (CPI input terminated) 20191791 20191792 Headphone PSRR vs Frequency AVDD = 3.3V, 0dB DAC, OCL 1.5V (DAC input selected) Headphone PSRR vs Frequency AVDD = 5V, 0dB DAC, OCL 1.5V (DAC input selected) 20191793 20191794 www.national.com 68 LM49370 Headphone PSRR vs Frequency AVDD = 3.3V, 0dB AUX, SE (AUX inputs terminated) Headphone PSRR vs Frequency AVDD = 5V, 0dB AUX, SE (AUX inputs terminated) 20191795 20191796 Headphone PSRR vs Frequency AVDD = 3.3V, 0dB CPI, SE (CPI input terminated) Headphone PSRR vs Frequency AVDD = 5V, 0dB CPI, SE (CPI input terminated) 20191797 20191798 Headphone PSRR vs Frequency AVDD = 3.3V, 0dB DAC, SE (DAC input selected) Headphone PSRR vs Frequency AVDD = 5V, 0dB DAC, SE (DAC input selected) 20191799 201917a0 69 www.national.com LM49370 Loudspeaker PSRR vs Frequency AVDD = 3.3V, 0dB AUX (AUX inputs terminated) Loudspeaker PSRR vs Frequency AVDD = 5V, 0dB AUX (AUX inputs terminated) 20191730 20191731 Loudspeaker PSRR vs Frequency AVDD = 3.3V, 0dB CPI (CPI input terminated) Loudspeaker PSRR vs Frequency AVDD = 5V, 0dB CPI (CPI input terminated) 20191732 20191733 Loudspeaker PSRR vs Frequency AVDD = 3.3V, 0dB DAC (DAC input selected) Loudspeaker PSRR vs Frequency AVDD = 5V, 0dB DAC (DAC input selected) 20191734 20191735 www.national.com 70 LM49370 INT/EXT MICBIAS PSRR vs Frequency AVDD = 3.3V, MICBIAS = 2.0V INT/EXT MICBIAS PSRR vs Frequency AVDD = 5V, MICBIAS = 2.0V 201917a1 201917a2 INT/EXT MICBIAS PSRR vs Frequency AVDD = 3.3V, MICBIAS = 2.5V INT/EXT MICBIAS PSRR vs Frequency AVDD = 5V, MICBIAS = 2.5V 201917a3 201917a4 INT/EXT MICBIAS PSRR vs Frequency AVDD = 3.3V, MICBIAS = 2.8V INT/EXT MICBIAS PSRR vs Frequency AVDD = 5V, MICBIAS = 2.8V 201917a5 201917a6 71 www.national.com LM49370 INT/EXT MICBIAS PSRR vs Frequency AVDD = 5V, MICBIAS = 3.3V AUXOUT THD+N vs Frequency AVDD = 3.3V, 0dB, VOUT = 1VRMS, 5kΩ 201917a8 201917a7 AUXOUT THD+N vs Frequency AVDD = 5V, 0dB, VOUT = 1VRMS, 5kΩ CPOUT THD+N vs Frequency AVDD = 3.3V, 0dB, VOUT = 1VRMS, 5kΩ 201917a9 201917b0 CPOUT THD+N vs Frequency AVDD = 5V, 0dB, VOUT = 1VRMS, 5kΩ Earpiece THD+N vs Frequency AVDD = 3.3V, 0dB, POUT = 500mW, 32Ω 201917b1 201917b2 www.national.com 72 LM49370 Earpiece THD+N vs Frequency AVDD = 5V, 0dB, POUT = 50mW, 32Ω Headphone THD+N vs Frequency AVDD = 3.3V, OCL 1.5V, 0dB POUT = 7.5mW, 32Ω 201917b3 201917b4 Headphone THD+N vs Frequency AVDD = 5V, OCL 1.5V, 0dB POUT = 10mW, 32Ω Headphone THD+N vs Frequency AVDD = 3.3V, OCL 1.2V, 0dB POUT = 7.5mW, 32Ω 201917b5 201917b6 Headphone THD+N vs Frequency AVDD = 5V, OCL 1.2V, 0dB POUT = 10mW, 32Ω Headphone THD+N vs Frequency AVDD = 3.3V, SE, 0dB POUT = 7.5mW, 32Ω 201917b7 201917b8 73 www.national.com LM49370 Headphone THD+N vs Frequency AVDD = 5V, SE, 0dB POUT = 10mW, 32Ω Loudspeaker THD+N vs Frequency AVDD = 3.3V, POUT = 400mW 15μH+8Ω+15μH 201917b9 20191736 Loudspeaker THD+N vs Frequency AVDD = 5V, POUT = 400mW 15μH+8Ω+15μH Earpiece THD+N vs Output Power AVDD = 3.3V, 0dB AUX fOUT = 1kHz, 16Ω 20191737 201917c0 Earpiece THD+N vs Output Power AVDD = 5V, 0dB AUX fOUT = 1kHz, 16Ω Earpiece THD+N vs Output Power AVDD = 3.3V, 0dB AUX fOUT = 1kHz, 32Ω 201917c1 201917c2 www.national.com 74 LM49370 Earpiece THD+N vs Output Power AVDD = 5V, 0dB AUX fOUT = 1kHz, 32Ω Earpiece THD+N vs Output Power AVDD = 3.3V, 0dB CPI fOUT = 1kHz, 16Ω 201917c3 201917c4 Earpiece THD+N vs Output Power AVDD = 5V, 0dB CPI fOUT = 1kHz, 16Ω Earpiece THD+N vs Output Power AVDD = 3.3V, 0dB CPI fOUT = 1kHz, 32Ω 201917c5 201917c6 Earpiece THD+N vs Output Power AVDD = 5V, 0dB CPI fOUT = 1kHz, 32Ω Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.2V, 0dB DAC fOUT = 1kHz, 16Ω 201917c7 201917c8 75 www.national.com LM49370 Headphone THD+N vs Output Power AVDD = 5V, OCL 1.2V, 0dB DAC fOUT = 1kHz, 16Ω Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.2V, 0dB DAC fOUT = 1kHz, 32Ω 201917c9 201917d0 Headphone THD+N vs Output Power AVDD = 5V, OCL 1.2V, 0dB DAC fOUT = 1kHz, 32Ω Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.2V, 12dB DAC fOUT = 1kHz, 16Ω 201917d1 201917d2 Headphone THD+N vs Output Power AVDD = 5V, OCL 1.2V, 12dB DAC fOUT = 1kHz, 16Ω Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.2V, 12dB DAC fOUT = 1kHz, 32Ω 201917d3 201917d4 www.national.com 76 LM49370 Headphone THD+N vs Output Power AVDD = 5V, OCL 1.2V, 12dB DAC fOUT = 1kHz, 32Ω Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.5V, 0dB DAC fOUT = 1kHz, 16Ω 201917d5 201917d6 Headphone THD+N vs Output Power AVDD = 5V, OCL 1.5V, 0dB DAC fOUT = 1kHz, 16Ω Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.5V, 0dB DAC fOUT = 1kHz, 32Ω 201917d7 201917d8 Headphone THD+N vs Output Power AVDD = 5V, OCL 1.5V, 0dB DAC fOUT = 1kHz, 32Ω Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.5V, 12dB DAC fOUT = 1kHz, 16Ω 201917d9 201917e0 77 www.national.com LM49370 Headphone THD+N vs Output Power AVDD = 5V, OCL 1.5V, 12dB DAC fOUT = 1kHz, 16Ω Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.5V, 12dB DAC fOUT = 1kHz, 32Ω 201917e1 201917e2 Headphone THD+N vs Output Power AVDD = 5V, OCL 1.5V, 12dB DAC fOUT = 1kHz, 32Ω Headphone THD+N vs Output Power AVDD = 3.3V, SE, 0dB DAC fOUT = 1kHz, 16Ω 201917e3 201917e4 Headphone THD+N vs Output Power AVDD = 5V, SE, 0dB DAC fOUT = 1kHz, 16Ω Headphone THD+N vs Output Power AVDD = 3.3V, SE, 0dB DAC fOUT = 1kHz, 32Ω 201917e5 201917e6 www.national.com 78 LM49370 Headphone THD+N vs Output Power AVDD = 5V, SE, 0dB DAC fOUT = 1kHz, 32Ω Headphone THD+N vs Output Power AVDD = 3.3V, SE, 12dB DAC fOUT = 1kHz, 16Ω 201917e7 201917e8 Headphone THD+N vs Output Power AVDD = 5V, SE, 12dB DAC fOUT = 1kHz, 16Ω Headphone THD+N vs Output Power AVDD = 3.3V, SE, 12dB DAC fOUT = 1kHz, 32Ω 201917e9 201917f0 Headphone THD+N vs Output Power AVDD = 5V, SE, 12dB DAC fOUT = 1kHz, 32Ω Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.2V, 0dB AUX fOUT = 1kHz, 16Ω 201917f1 201917f2 79 www.national.com LM49370 Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.2V, 12dB AUX fOUT = 1kHz, 16Ω Headphone THD+N vs Output Power AVDD = 5V, OCL 1.2V, 0dB AUX fOUT = 1kHz, 16Ω 201917f3 201917f4 Headphone THD+N vs Output Power AVDD = 5V, OCL 1.2V, 12dB AUX fOUT = 1kHz, 16Ω Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.2V, 0dB AUX fOUT = 1kHz, 32Ω 201917f5 201917f6 Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.2V, 12dB AUX fOUT = 1kHz, 32Ω Headphone THD+N vs Output Power AVDD = 5V, OCL 1.2V, 0dB AUX fOUT = 1kHz, 32Ω 201917f7 201917f8 www.national.com 80 LM49370 Headphone THD+N vs Output Power AVDD = 5V, OCL 1.2V, 12dB AUX fOUT = 1kHz, 32Ω Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.2V, 0dB CPI fOUT = 1kHz, 16Ω 201917f9 201917g0 Headphone THD+N vs Output Power AVDD = 5V, OCL 1.2V, 0dB CPI fOUT = 1kHz, 16Ω Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.2V, 0dB CPI fOUT = 1kHz, 32Ω 201917g1 201917g2 Headphone THD+N vs Output Power AVDD = 5V, OCL 1.2V, 0dB CPI fOUT = 1kHz, 32Ω Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.5V, 0dB AUX fOUT = 1kHz, 16Ω 201917g3 201917g4 81 www.national.com LM49370 Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.5V, 12dB AUX fOUT = 1kHz, 16Ω Headphone THD+N vs Output Power AVDD = 5V, OCL 1.5V, 0dB AUX fOUT = 1kHz, 16Ω 201917g5 201917g6 Headphone THD+N vs Output Power AVDD = 5V, OCL 1.5V, 12dB AUX fOUT = 1kHz, 16Ω Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.5V, 0dB AUX fOUT = 1kHz, 32Ω 201917g7 201917g8 Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.5V, 12dB AUX fOUT = 1kHz, 32Ω Headphone THD+N vs Output Power AVDD = 5V, OCL 1.5V, 0dB AUX fOUT = 1kHz, 32Ω 201917g9 201917h0 www.national.com 82 LM49370 Headphone THD+N vs Output Power AVDD = 5V, OCL 1.5V, 12dB AUX fOUT = 1kHz, 32Ω Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.5V, 0dB CPI fOUT = 1kHz, 16Ω 201917h1 201917h2 Headphone THD+N vs Output Power AVDD = 5V, OCL 1.5V, 0dB CPI fOUT = 1kHz, 16Ω Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.5V, 0dB CPI fOUT = 1kHz, 32Ω 201917h3 201917h4 Headphone THD+N vs Output Power AVDD = 5V, OCL 1.5V, 0dB CPI fOUT = 1kHz, 32Ω Headphone THD+N vs Output Power AVDD = 3.3V, SE, 0dB AUX fOUT = 1kHz, 16Ω 201917h5 201917h6 83 www.national.com LM49370 Headphone THD+N vs Output Power AVDD = 5V, SE, 0dB AUX fOUT = 1kHz, 16Ω Headphone THD+N vs Output Power AVDD = 3.3V, SE, 0dB AUX fOUT = 1kHz, 32Ω 201917h7 201917h8 Headphone THD+N vs Output Power AVDD = 5V, SE, 0dB AUX fOUT = 1kHz, 32Ω Headphone THD+N vs Output Power AVDD = 3.3V, SE, 0dB CPI fOUT = 1kHz, 16Ω 201917h9 201917i0 Headphone THD+N vs Output Power AVDD = 5V, SE, 0dB CPI fOUT = 1kHz, 16Ω Headphone THD+N vs Output Power AVDD = 3.3V, SE, 0dB CPI fOUT = 1kHz, 32Ω 201917i1 201917i2 www.national.com 84 LM49370 Headphone THD+N vs Output Power AVDD = 5V, SE, 0dB CPI fOUT = 1kHz, 32Ω Loudspeaker THD+N vs Output Power AVDD = 3.3V, 0dB AUX fOUT = 1kHz, 15μH+8Ω+15μH 201917i3 20191738 Loudspeaker THD+N vs Output Power AVDD = 4.2V, 0dB AUX fOUT = 1kHz, 15μH+8Ω+15μH Loudspeaker THD+N vs Output Power AVDD = 5V, 0dB AUX fOUT = 1kHz, 15μH+8Ω+15μH 20191739 20191740 Loudspeaker THD+N vs Output Power AVDD = 3.3V, 0dB CPI fOUT = 1kHz, 15μH+8Ω+15μH Loudspeaker THD+N vs Output Power AVDD = 4.2V, 0dB CPI fOUT = 1kHz, 15μH+8Ω+15μH 20191741 20191742 85 www.national.com LM49370 Loudspeaker THD+N vs Output Power AVDD = 5V, 0dB CPI fOUT = 1kHz, 15μH+8Ω+15μH Loudspeaker THD+N vs Output Power AVDD = 3.3V, 0dB DAC fOUT = 1kHz, 15μH+8Ω+15μH 20191743 20191744 Loudspeaker THD+N vs Output Power AVDD = 4.2V, 0dB DAC fOUT = 1kHz, 15μH+8Ω+15μH Loudspeaker THD+N vs Output Power AVDD = 5V, 0dB DAC fOUT = 1kHz, 15μH+8Ω+15μH 20191745 20191746 AUXOUT THD+N vs Output Voltage AVDD = 3.3V, 0dB AUX fOUT = 1kHz, 5kΩ AUXOUT THD+N vs Output Voltage AVDD = 5V, 0dB AUX fOUT = 1kHz, 5kΩ 201917i4 201917i5 www.national.com 86 LM49370 AUXOUT THD+N vs Output Voltage AVDD = 3.3V, 0dB CPI fOUT = 1kHz, 5kΩ AUXOUT THD+N vs Output Voltage AVDD = 5V, 0dB CPI fOUT = 1kHz, 5kΩ 201917i6 201917i7 AUXOUT THD+N vs Output Voltage AVDD = 3.3V, 0dB DAC fOUT = 1kHz, 5kΩ AUXOUT THD+N vs Output Voltage AVDD = 5V, 0dB DAC fOUT = 1kHz, 5kΩ 201917i8 201917i9 AUXOUT THD+N vs Output Voltage AVDD = 3.3V, 12dB DAC fOUT = 1kHz, 5kΩ AUXOUT THD+N vs Output Voltage AVDD = 5V, 12dB DAC fOUT = 1kHz, 5kΩ 201917j0 201917j1 87 www.national.com LM49370 CPOUT THD+N vs Output Voltage AVDD = 3.3V, 0dB AUX fOUT = 1kHz, 5kΩ CPOUT THD+N vs Output Voltage AVDD = 5V, 0dB AUX fOUT = 1kHz, 5kΩ 201917j2 201917j3 CPOUT THD+N vs Output Voltage AVDD = 3.3V, 0dB DAC fOUT = 1kHz, 5kΩ CPOUT THD+N vs Output Voltage AVDD = 5V, 0dB DAC fOUT = 1kHz, 5kΩ 201917j5 201917j4 CPOUT THD+N vs Output Voltage AVDD = 3.3V, 6dB MIC fOUT = 1kHz, 5kΩ CPOUT THD+N vs Output Voltage AVDD = 5V, 6dB MIC fOUT = 1kHz, 5kΩ 201917j6 201917j7 www.national.com 88 LM49370 CPOUT THD+N vs Output Voltage AVDD = 3.3V, 12dB DAC fOUT = 1kHz, 5kΩ CPOUT THD+N vs Output Voltage AVDD = 5V, 12dB DAC fOUT = 1kHz, 5kΩ 201917j8 201917j9 CPOUT THD+N vs Output Voltage AVDD = 3.3V, 36dB MIC fOUT = 1kHz, 5kΩ CPOUT THD+N vs Output Voltage AVDD = 5V, 36dB MIC fOUT = 1kHz, 5kΩ 201917k0 201917k1 Headphone Crosstalk vs Frequency OCL 1.2V, 0dB AUX, 32Ω Headphone Crosstalk vs Frequency OCL 1.5V, 0dB AUX, 32Ω 201917k2 201917k3 89 www.national.com LM49370 Headphone Crosstalk vs Frequency SE, 0dB AUX, 32Ω 201917k4 www.national.com 90 LM49370 14.0 LM49370 Demonstration Board Schematic Diagram 201917z3 91 www.national.com LM49370 15.0 Demoboard PCB Layout 201917z9 Top Silkscreen www.national.com 92 LM49370 201917z8 Top Layer 93 www.national.com LM49370 201917z6 Mid Layer 1 www.national.com 94 LM49370 201917z7 Mid Layer 2 95 www.national.com LM49370 201917z4 Bottom Layer www.national.com 96 LM49370 201917z5 Bottom Silkscreen 97 www.national.com LM49370 16.0 Revision History Rev 1.0 Date 02/14/07 Description Initial released. www.national.com 98 LM49370 17.0 Physical Dimensions inches (millimeters) unless otherwise noted 49 Bump micro SMDxt Package Order Number LM49370RL Dimensions: X1 = 3.924±0.03mm, X2 = 3.924±0.03mm, X3 = 0.650±0.75mm NS Package Number RLA49UUA 99 www.national.com LM49370 Audio Sub-System with an Ultra Low EMI, Spread Spectrum, Class D Loudspeaker Amplifier, a Dual-Mode Stereo Headphone Amplifier, and a Dedicated PCM Interface for Bluetooth Transceivers Notes THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. NATIONAL MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE ACCURACY OR COMPLETENESS OF THE CONTENTS OF THIS PUBLICATION AND RESERVES THE RIGHT TO MAKE CHANGES TO SPECIFICATIONS AND PRODUCT DESCRIPTIONS AT ANY TIME WITHOUT NOTICE. NO LICENSE, WHETHER EXPRESS, IMPLIED, ARISING BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. TESTING AND OTHER QUALITY CONTROLS ARE USED TO THE EXTENT NATIONAL DEEMS NECESSARY TO SUPPORT NATIONAL’S PRODUCT WARRANTY. EXCEPT WHERE MANDATED BY GOVERNMENT REQUIREMENTS, TESTING OF ALL PARAMETERS OF EACH PRODUCT IS NOT NECESSARILY PERFORMED. NATIONAL ASSUMES NO LIABILITY FOR APPLICATIONS ASSISTANCE OR BUYER PRODUCT DESIGN. BUYERS ARE RESPONSIBLE FOR THEIR PRODUCTS AND APPLICATIONS USING NATIONAL COMPONENTS. PRIOR TO USING OR DISTRIBUTING ANY PRODUCTS THAT INCLUDE NATIONAL COMPONENTS, BUYERS SHOULD PROVIDE ADEQUATE DESIGN, TESTING AND OPERATING SAFEGUARDS. EXCEPT AS PROVIDED IN NATIONAL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NATIONAL ASSUMES NO LIABILITY WHATSOEVER, AND NATIONAL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO THE SALE AND/OR USE OF NATIONAL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE CHIEF EXECUTIVE OFFICER AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness. National Semiconductor and the National Semiconductor logo are registered trademarks of National Semiconductor Corporation. All other brand or product names may be trademarks or registered trademarks of their respective holders. Copyright© 2007 National Semiconductor Corporation For the most current product information visit us at www.national.com National Semiconductor Americas Customer Support Center Email: new.feedback@nsc.com Tel: 1-800-272-9959 National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530-85-86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +49 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Support Center Email: ap.support@nsc.com National Semiconductor Japan Customer Support Center Fax: 81-3-5639-7507 Email: jpn.feedback@nsc.com Tel: 81-3-5639-7560 www.national.com