LM4946

LM4946 Output Capacitor-Less Audio Subsystem with Programmable National 3D June 2007 LM4946 Output Capacitor-Less Audio Subsystem with Programmable National 3D General Description The LM4946 is an audio power amplifier capable of delivering 540mW of continuous average power into a mono 8Ω bridged-tied load (BTL) with 1% THD+N, 35mW per channel of continuous average power into stereo 32Ω single-ended (SE) loads with 1% THD+N, or an output capacitor-less (OCL) configuration with identical specifications as the SE configuration, from a 3.3V power supply. The LM4946 has three input channels: one pair for a twochannel stereo signal and the third for a differential singlechannel mono input. The LM4946 features a 32-step digital volume control and eight distinct output modes. The digital volume control, 3D enhancement, and output modes (mono/ SE/OCL) are programmed through a two-wire I2C or a threewire SPI compatible interface that allows flexibility in routing and mixing audio channels. The LM4946 is designed for cellular phone, PDA, and other portable handheld applications. It delivers high quality output power from a surface-mount package and requires only seven external components in the OCL mode (two additional components in SE mode). Key Specifications ■ THD+N at 1kHz, 540mW  into 8Ω BTL (3.3V) ■ THD+N at 1kHz, 35mW  into 32Ω SE (3.3V) ■ Single Supply Operation (VDD) ■  I2C/SPI Single Supply Operation 2.2 to 5.5V 1.7 to 5.5V 1.0% (typ) 1.0% (typ) 2.7 to 5.5V   LLP   micro SMD Features ■ I2C/SPI Control Interface ■ I2C/SPI programmable National 3D Audio ■ I2C/SPI controlled 32 step digital volume control (-54dB to ■ ■ ■ ■ ■ ■ ■ +18dB) Three independent volume channels (Left, Right, Mono) Eight distinct output modes LLP and microSMD surface mount packaging “Click and Pop” suppression circuitry Thermal shutdown protection Low shutdown current (0.02uA, typ) RF immunity topology Applications ■ Mobile Phones ■ PDAs Boomer® is a registered trademark of National Semiconductor Corporation. © 2007 National Semiconductor Corporation 201628 www.national.com LM4946 Typical Application 201628g1 FIGURE 1. Typical Audio Amplifier Application Circuit-Output Capacitor-less 201628n4 FIGURE 2. Typical Audio Amplifier Application Circuit-Single Ended www.national.com 2 LM4946 Connection Diagrams 24 Lead LLP Package 201628e8 20162803 Top View Top View U - Wafer Fab Code Z - Assembly Plant Code XY - Date Code TT - Die Traceability xxx - L4946SQ 25 Bump micro SMD Package 201628n3 201628n2 Top View Top View U - Wafer Fab Code Z - Assembly Plant Code XY - Date Code TT - Die Traceability G- Boomer I9 - LM4946TM 3 www.national.com LM4946 Pin Descriptions Pin Number (LLP) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Bump (Mirco SMD) B2 A1 A2 A3 A4 A5 B4 B5 B3 C5 C4 D5 D4 E5 E4 D3 E2 E1 D2 D1 C3 C1 C2 B1 E3 Name LHP3D2 VOC VDD GND ROUT LOUT I2CSPI_V RIN LIN SDA SCL GND ID_ENB I2CSPI_SEL MONO+ VDD MONOLHP3D1 RHP3D1 GND BYPASS MONO_INMONO_IN+ RHP3D2 VDD DD Description Left Headphone 3D Input 1 Center Amplifier Output Voltage Supply Ground Right Headphone Output Left Headphone Output I2C or SPI Interface Voltage Supply Right Input Channel Left Input Channel Data Clock Ground Address Identification/Enable Bar I2C or SPI Select Loudspeaker Output Positive Voltage Supply Loudspeaker Output Negative Left Headphone 3D Input 2 Right Headphone 3D Input 1 Ground Half-Supply Bypass Loudspeaker Negative Input Loudspeaker Positive Input Right Headphone 3D Input 2 Voltage Supply www.national.com 4 LM4946 Absolute Maximum Ratings (Note 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage Storage Temperature Input Voltage ESD Susceptibility (Note 3) ESD Machine model (Note 6) Junction Temperature Solder Information (Note 1) Vapor Phase (60 sec.) 6.0V −65°C to +150°C −0.3 to VDD +0.3 2.0kV 200V 150°C 215°C Infrared (15 sec.) Thermal Resistance (Note 8)  θJA (typ) - SQA24A  θJA (typ) - TMD25A 220°C 46°C/W 49°C/W Operating Ratings Temperature Range Supply Voltage (VDD) Supply Voltage (I2C/SPI) (Note 10) −40°C to 85°C 2.7V ≤ VDD ≤ 5.5V 2.2V ≤ I2CSPI_VDD ≤ 5.5V 1.7V ≤ I2CSPI_VDD ≤ 5.5V I2CSPI_VDD ≤ VDD   LLP   micro SMD Electrical Characteristics 3.3V Symbol Parameter (Notes 2, 7) The following specifications apply for VDD = 3.3V, TA = 25°C, all volume controls set to 0dB, unless otherwise specified. Conditions LM4946 Typical (Note 4) Output Modes 2, 4, 6 VIN = 0V; No load, SE Headphone Output Modes 1, 3, 5, 7 VIN = 0V; No load, SE Headphone IDD Supply Current Output Modes 2, 4, 6 VIN = 0V; No load, OCL Headphone Output Modes 1, 3, 5, VIN = 0V; No load, OCL Headphone Output Modes 7 VIN = 0V; No load, OCL Headphone ISD Shutdown Current Output Mode 0 VIN = 0V, Mode 7 Mono VIN = 0V, Mode 7 Headphones (Note 11) MONO OUT; RL = 8Ω THD+N = 1%; f = 1kHz, BTL, Mode 1 ROUT and LOUT; RL = 32Ω THD+N = 1%; f = 1kHz, SE, Mode 4 MONOOUT f = 1kHz POUT = 250mW; RL = 8Ω, BTL, Mode 1 ROUT and LOUT f = 1kHz POUT = 12mW; RL = 32Ω, SE, Mode 4 3.25 Limits (Note 5) Units (Limits) mA 5.65 mA 4 6.5 mA (max) 5 mA 6.5 0.02 12 3 540 35 10.5 1 50 mA (max) µA (max) VOS Output Offset Voltage mV (max) 15 500 30 mW (min) mW (min) PO Output Power 0.05 % THD+N Total Harmonic Distortion + Noise 0.015 % 5 www.national.com LM4946 Symbol Parameter Conditions LM4946 Typical (Note 4) Limits (Note 5) Units (Limits) A-weighted, inputs terminated to GND, output referred Speaker; Mode 1 Speaker; Mode 3, 7 Speaker; Mode 5 NOUT Output Noise Headphone; SE, Mode 2 Headphone; SE, Mode 4, 7 Headphone; SE, Mode 6 Headphone; OCL, Mode 2 Headphone; OCL, Mode 4, 7 Headphone; OCL, Mode 6 VRIPPLE = 200mVPP; f = 217Hz, RL = 8Ω CB = 2.2µF, BTL All audio inputs terminated to GND; output referred BTL, Output Mode 1 BTL, Output Mode 3, 7 BTL, Output Mode 5 PSRR VRIPPLE = 200mVPP; f = 217Hz, RL = 32Ω CB = 2.2µF, All audio inputs terminated to GND output referred Power Supply Rejection Ratio ROUT and LOUT SE, Output Mode 2 SE, Output Mode 4,7 SE, Output Mode 6 OCL, Output Mode 2 OCL, Output Mode 4, 7 OCL, Output Mode 6 Volume Control Step Size Error Maximum attenuation Digital Volume Control Range Maximum gain HP(SE) Mute Attenuation MONO_IN Input Impedance RIN and LIN Input Impedance Output Mode 1, 3, 5 Maximum gain setting Maximum attenuation setting f = 217Hz, VCM = 1Vpp, CMRR Common-Mode Rejection Ratio Mode 1, BTL, RL = 8Ω f = 217Hz, VCM = 1Vpp, Mode 2, RL = 32Ω Headphone; PO = 12mW f = 1kHz, OCL, Mode 4 Headphone; PO = 12mW f = 1kHz, SE, Mode 4 CB = 2.2μF, OCL CB = 2.2μF, SE 18 96 12.5 110 61 dB 66 –54 –72 100 135 dB dB ms ms 10 15 90 130 78 82 78 84 78 77 ±0.2 -54 –56 –52 17.4 18.6 dB dB dB dB dB dB dB dB (max) dB (min) dB (min) dB (max) dB kΩ (min) kΩ (max) kΩ (min) kΩ (max) 76 65 63 dB dB dB 17 27 33 8 8 12 8 9 12 μV μV μV μV μV μV μV μV μV Power Supply Rejection Ratio MONOOUT XTALK Crosstalk TWU Wake-Up Time from Shutdown www.national.com 6 LM4946 Electrical Characteristics 5.0V Symbol Parameter (Notes 2, 7) The following specifications apply for VDD = 5.0V, TA = 25°C, all volume controls set to 0dB, unless otherwise specified. Conditions LM4946 Typical (Note 4) Output Modes 2, 4, 6 VIN = 0V; No load SE Headphone Output Modes 1, 3, 5, 7 VIN = 0V; No Load, SE Headphone IDD Supply Current Output Modes 2, 4, 6 VIN = 0V; No load, OCL Headphone Output Modes 1, 3, 5 VIN = 0V; No Load, OCL Headphone Output Modes 7 VIN = 0V; No Load, OCL Headphone ISD Shutdown Current Output Mode 0 VIN = 0V, Mode 7 Mono VIN = 0V, Mode 7 Headphones MONOOUT; RL = 8Ω THD+N = 1%; f = 1kHz, BTL, Mode 1 ROUT and LOUT; RL = 32Ω THD+N = 1%; f = 1kHz, SE, Mode 4 MONOOUT, f = 1kHz THD+N Total Harmonic Distortion + Noise POUT = 500mW; RL = 8Ω, BTL, Mode 1 ROUT and LOUT, f = 1kHz POUT = 30mW; RL = 32Ω, SE, Mode 4 A-weighted, inputs terminated to GND, output referred Speaker; Mode 1 Speaker; Mode 3, 7 Speaker; Mode 5 NOUT Output Noise Headphone; SE, Mode 2 Headphone; SE, Mode 4, 7 Headphone; SE, Mode 6 Headphone; OCL, Mode 2 Headphone; OCL, Mode 4, 7 Headphone; OCL, Mode 6 VRIPPLE = 200mVPP; f = 217Hz, RL = 8Ω CB = 2.2µF, BTL All audio inputs terminated to GND; output referred BTL, Output Mode 1 BTL, Output Mode 3, 7 BTL, Output Mode 5 69 60 58 dB dB dB 17 27 33 8 8 12 8 9 12 μV μV μV μV μV μV μV μV μV 3.8 Limits (Note 5) Units (Limits) mA 6.6 mA 4.6 mA 6 mA 7.4 0.05 12 3 mA µA VOS Output Offset Voltage mV 1.3 85 0.05 0.012 W mW % % PO Output Power PSRR Power Supply rejection Ratio MONOOUT 7 www.national.com LM4946 Symbol Parameter Conditions LM4946 Typical (Note 4) Limits (Note 5) Units (Limits) VRIPPLE = 200mVPP; f = 217Hz, RL = 32Ω CB = 2.2µF, BTL All audio inputs terminated to GND; output referred PSRR Power Supply Rejection Ratio ROUT and LOUT SE, Output Mode 2 SE, Output Mode 4,7 SE, Output Mode 6 OCL, Output Mode 2 OCL, Output Mode 4, 7 OCL, Output Mode 6 Maximum attenuation Digital Volume Control Range Maximum gain HP(SE) Mute Attenuation MONO_IN Input Impedance RIN and LIN Input Impedance Output Mode 1, 3, 5 Maximum attenuation Maximum gain f = 217Hz, VCM = 1Vpp, 0dB gain CMRR Common-Mode Rejection Ratio Mode 1, BTL, RL = 8Ω f = 217Hz, VCM = 1Vpp, 0dB gain Mode 2, RL = 32Ω XTALK TWU Crosstalk Wake-Up Time from Shutdown Headphone; PO = 30mW, OCL, Mode 4 Headphone; PO = 30mW, SE, Mode 4 CB = 2.2μF, OCL CB = 2.2μF, SE 18 96 12.5 110 61 dB 66 –55 –72 135 180 dB dB ms ms 10 15 90 130 75 75 72 75 79 72 -54 -56 -52 17.4 18.6 dB dB dB dB dB dB dB (max) dB (min) dB (min) dB (max) dB kΩ (min) kΩ (max) kΩ (min) kΩ (max) www.national.com 8 LM4946 I2C/SPI LLP/micro SMD Symbol Parameter (Notes 2, 7) Conditions LM4946 Typical Limits (Notes 5, (Note 4) 7) Units (Limits) µs (min) ns (min) ns (min) ns (min) ns (min) ns (min) kHz (max) ns (min) ns (min) ns (min) ns (min) ns (min) ns (min) ns (min) V (min) V (max) The following specifications apply for VDD = 5.0V and 3.3V, TA = 25°C, 2.2V ≤ I2CSPI_VDD ≤ 5.5V, unless otherwise specified. t1 t2 t3 t4 t5 t6 fSPI tEL tDS tES tDH tEH tCL tCH VIH VIL I2C Clock Period I2C Data Setup Time I2C Data Stable Time Start Condition Time Stop Condition Time I2C Data Hold Time Maximum SPI Frequency SPI ENB High Time SPI Data Setup Time SPI ENB Setup Time SPI Data Hold Time SPI Enable Hold Time SPI Clock Low Time SPI Clock High Time I2C/SPI Input Voltage High I2C/SPI Input Voltage Low 2.5 100 0 100 100 100 1000 100 100 100 100 100 500 500 0.7xI2CSPI VDD 0.3xI2CSPI VDD (Notes 2, 7) Conditions Typical (Note 4) LM4946 Limits (Notes 5, 7) 2.5 250 0 250 250 250 250 250 250 250 250 250 500 500 0.7xI2CSPI VDD 0.25 xI2CSPI VDD I2C/SPI micro SMD only Symbol Parameter The following specifications apply for VDD = 5.0V and 3.3V, TA = 25°C, 1.7V ≤ I2CSPI_VDD ≤ 2.2V, unless otherwise specified. Units (Limits) µs (min) ns (min) ns (min) ns (min) ns (min) ns (min) kHz (max) ns (min) ns (min) ns (min) ns (min) ns (min) ns (min) ns (min) V (min) V (max) t1 t2 t3 t4 t5 t6 fSPI tEL tDS tES tDH tEH tCL tCH VIH VIL I2C Clock Period I2C Data Setup Time I2C Data Stable Time Start Condition Time Stop Condition Time I2C Data Hold Time Maximum SPI Frequency SPI ENB High Time SPI Data Setup Time SPI ENB Setup Time SPI Data Hold Time SPI Enable Hold Time SPI Clock Low Time SPI Clock High Time I2C/SPI Input Voltage High I2C/SPI Input Voltage Low 9 www.national.com LM4946 Note 1: See AN-450 "Surface Mounting and their effects on Product Reliability" for other methods of soldering surface mount devices. Note 2: Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 3: Human body model, 100pF discharged through a 1.5kΩ resistor. Note 4: Typical specifications are specified at +25°C and represent the most likely parametric norm. Note 5: Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level). Note 6: Machine Model ESD test is covered by specification EIAJ IC-121-1981. A 200pF cap is charged to the specified voltage, then discharged directly into the IC with no external series resistor (resistance of discharge path must be under 50Ω). Note 7: All voltages are measured with respect to the ground pin, unless otherwise specified. Note 8: The given θJA for an LM4946SQ mounted on a demonstration board with a 9in2 area of 1oz printed circuit board copper ground plane. Note 9: Datasheet min/max specifications are guaranteed by design, test, or statistical analysis. Note 10: Refer to table on page 9. Note 11: For LM4946 LLP package, revised specification goes into effect starting with date code 79. Existing specification is per datasheet rev 1.0 www.national.com 10 LM4946 Typical Performance Characteristics THD+N vs Frequency VDD = 3.3V, RL = 8Ω, PO = 250mW Mode 1, BTL, BW = 80kHz THD+N vs Frequency VDD = 3.3V, RL = 32Ω, PO = 12mW Mode 4, 7, OCL, BW = 80kHz 20162826 201628e3 THD+N vs Frequency VDD = 3.3V, RL = 32Ω, PO = 12mW Mode 6, OCL, BW = 80kHz THD+N vs Frequency VDD = 3.3V, RL = 32Ω, PO = 12mW Mode 4, 7, SE, BW = 80kHz 201628e4 20162832 THD+N vs Frequency VDD = 3.3V, RL = 32Ω, PO = 12mW Mode 6, SE, BW = 80kHz THD+N vs Frequency VDD = 3.3V, RL = 8Ω, PO = 250mW Mode 5, BTL, BW = 80kHz 20162834 20162827 11 www.national.com LM4946 THD+N vs Frequency VDD = 5V, RL = 8Ω, PO = 500mW Mode 1, BTL, BW = 80kHz THD+N vs Frequency VDD = 5V, RL = 32Ω, PO = 30mW Mode 4, 7, OCL, BW = 80kHz 20162835 20162873 THD+N vs Frequency VDD = 5V, RL = 32Ω, PO = 30mW Mode 4, 7, SE, BW = 80kHz THD+N vs Frequency VDD = 5V, RL = 32Ω, PO = 30mW Mode 6, OCL, BW = 80kHz 20162874 20162875 THD+N vs Frequency VDD = 5V, RL = 32Ω, PO = 30mW Mode 6, SE, BW = 80kHz THD+N vs Frequency VDD = 5V, RL = 8Ω, PO = 500mW Mode 5, BTL 20162876 20162836 www.national.com 12 LM4946 THD+N vs Frequency VDD = 3.3V, RL = 32Ω, PO = 12mW Mode 2, OCL THD+N vs Frequency VDD = 3.3V, RL = 32Ω, PO = 12mW Mode 2, SE, BW = 80kHz 201628m3 201628m4 THD+N vs Frequency VDD = 3.3V, RL = 8Ω, PO = 250mW Mode 3, BTL THD+N vs Output Power VDD = 3.3V, RL = 8Ω, f = 1kHz Mode 1, BTL 201628m5 201628b0 THD+N vs Output Power VDD = 3.3V, RL = 8Ω, f = 1kHz Mode 5, BTL THD+N vs Output Power VDD = 3.3V, RL = 32Ω, f = 1kHz Mode 4, 7, OCL 201628b4 201628e6 13 www.national.com LM4946 THD+N vs Output Power VDD = 3.3V, RL = 32Ω, f = 1kHz Mode 4, 7, SE THD+N vs Output Power VDD = 3.3V, RL = 32Ω, f = 1kHz Mode 6, SE 201628b1 201628e7 THD+N vs Output Power VDD = 5V, RL = 8Ω, f = 1kHz Mode 1, BTL THD+N vs Output Power VDD = 5V, RL = 8Ω, f = 1kHz Mode 5, BTL 201628b2 201628b6 THD+N vs Output Power VDD = 5V, RL = 32Ω, f = 1kHz Mode 4, 7, OCL THD+N vs Output Power VDD = 5V, RL = 32Ω, f = 1kHz Mode 4, 7, SE 201628c0 201628b3 www.national.com 14 LM4946 THD+N vs Output Power VDD = 5V, RL = 32Ω, f = 1kHz Mode 6, SE THD+N vs Output Power VDD = 3.3V, RL = 32Ω, f = 1kHz Mode 6, Mono Input, OCL 201628c1 201628m1 THD+N vs Output Power VDD = 3.3V, RL = 32Ω, f = 1kHz Mode 6, Stereo Input, OCL THD+N vs Output Power VDD = 3.3V, RL = 32Ω, f = 1kHz Mode 2, OCL 201628m6 201628m2 THD+N vs Output Power VDD = 3.3V, RL = 32Ω, f = 1kHz Mode 2, SE THD+N vs Output Power VDD = 3.3V, RL = 8Ω, f = 1kHz Mode 3, BTL 201628m7 201628m8 15 www.national.com LM4946 PSRR vs Frequency VDD = 3.3V, 0dB Mode 4, 7, OCL PSRR vs Frequency VDD = 3.3V, 0dB Mode 4, 7, SE 20162819 20162820 PSRR vs Frequency VDD = 3.3V, 0dB Mode 6, OCL PSRR vs Frequency VDD = 3.3V, 0dB Mode 6, SE 20162821 20162822 PSRR vs Frequency VDD = 3.3V, 6dB Mode 1, BTL PSRR vs Frequency VDD = 3.3V, RL = 8Ω Mode 3, 7, BTL 20162823 20162877 www.national.com 16 LM4946 PSRR vs Frequency VDD = 3.3V, RL = 32Ω Mode 2, OCL PSRR vs Frequency VDD = 3.3V, RL = 8Ω Mode 2, SE 201628l6 201628l7 PSRR vs Frequency VDD = 3.3V, 6dB Mode 5, BTL PSRR vs Supply Voltage RL = 8Ω, 217Hz Mode 1, BTL 20162825 201628l8 PSRR vs Supply Voltage RL = 32Ω, 217Hz Mode 4, OCL PSRR vs Supply Voltage RL = 32Ω, 217Hz Mode 4, SE 201628l9 201628m0 17 www.national.com LM4946 Power Dissipation vs Output Power VDD = 3.3V, RL = 32Ω f = 1kHz, Mode 2, 4, 6, SE Power Dissipation vs Output Power VDD = 5V, RL = 8Ω f = 1kHz, Mode 1, 3, 5, BTL 201628g0 201628c5 Power Dissipation vs Output Power VDD = 5V, RL = 32Ω f = 1kHz, Mode 2, 4, 6, OCL Power Dissipation vs Output Power VDD = 3.3V, RL = 8Ω, f = 1kHz, Modes 1, 3, 5, BTL 201628c6 201628k5 Power Dissipation vs Output Power VDD = 3.3V, RL = 32Ω, f = 1kHz, Modes 2, 4, 6, OCL Power Dissipation vs Output Power VDD = 3.3V, RL = 8Ω, f = 1kHz, Mode 7, OCL 201628k6 201628k7 www.national.com 18 LM4946 Power Dissipation vs Output Power VDD = 3.3V, RL = 32Ω, f = 1kHz, Mode 7, SE Crosstalk vs Frequency VDD = 3.3V, RL = 32Ω, PO = 12mW Right-Left, Mode 4, OCL 201628k9 201628e9 Crosstalk vs Frequency VDD = 5V, RL = 32Ω, PO = 30mW Left-Right, Mode 4, OCL Crosstalk vs Frequency VDD = 3.3V, RL = 32Ω, PO = 12mW Mode 4, SE 201628f1 201628f0 Crosstalk vs Frequency VDD = 5V, RL = 32Ω, PO = 30mW Mode 4, SE Supply Current vs Supply Voltage No Load, Mode 7 201628k2 201628f2 19 www.national.com LM4946 Supply Current vs Supply Voltage VDD = 3.3V, No Load, Modes 1, 3, 5 Supply Current vs Supply Voltage No Load, Modes 2, 4, 6 201628k3 201628k4 Output Power vs Supply Voltage RL = 8Ω, f = 1kHz, Mono, Mode 1 Output Power vs Supply Voltage RL = 32Ω, f = 1kHz, OCL, Mode 4 201628n0 201628n1 www.national.com 20 LM4946 Application Information I2C PIN DESCRIPTION SDA: This is the serial data input pin. SCL: This is the clock input pin. ID_ENB: This is the address select input pin. I2CSPI_SEL: This is tied LOW for I2C mode. I2C COMPATIBLE INTERFACE The LM4946 uses a serial bus which conforms to the I2C protocol to control the chip's functions with two wires: clock (SCL) and data (SDA). The clock line is uni-directional. The data line is bi-directional (open-collector). The maximum clock frequency specified by the I2C standard is 400kHz. In this discussion, the master is the controlling microcontroller and the slave is the LM4946. The I2C address for the LM4946 is determined using the ID_ENB pin. The LM4946's two possible I2C chip addresses are of the form 111110X10 (binary), where X1 = 0, if ID_ENB is logic LOW; and X1 = 1, if ID_ENB is logic HIGH. If the I2C interface is used to address a number of chips in a system, the LM4946's chip address can be changed to avoid any possible address conflicts. The bus format for the I2C interface is shown in Figure 3. The bus format diagram is broken up into six major sections: The "start" signal is generated by lowering the data signal while the clock signal is HIGH. The start signal will alert all devices attached to the I2C bus to check the incoming address against their own address. The 8-bit chip address is sent next, most significant bit first. The data is latched in on the rising edge of the clock. Each address bit must be stable while the clock level is HIGH. For I2C interface operation, the I2CSPI_SEL pin needs to be tied LOW (and tied high for SPI operation). After the last bit of the address bit is sent, the master releases the data line HIGH (through a pull-up resistor). Then the master sends an acknowledge clock pulse. If the LM4946 has received the address correctly, then it holds the data line LOW during the clock pulse. If the data line is not held LOW during the acknowledge clock pulse, then the master should abort the rest of the data transfer to the LM4946. The 8 bits of data are sent next, most significant bit first. Each data bit should be valid while the clock level is stable HIGH. After the data byte is sent, the master must check for another acknowledge to see if the LM4946 received the data. If the master has more data bytes to send to the LM4946, then the master can repeat the previous two steps until all data bytes have been sent. The "stop" signal ends the transfer. To signal "stop", the data signal goes HIGH while the clock signal is HIGH. The data line should be held HIGH when not in use. I2C INTERFACE POWER SUPPLY PIN (I2CSPI_VDD) The LM4946's I2C interface is powered up through the I2CSPI_VDD pin. The LM4946's I2C interface operates at a voltage level set by the I2CVDD pin which can be set independent to that of the main power supply pin VDD. This is ideal whenever logic levels for the I2C interface are dictated by a microcontroller or microprocessor that is operating at a lower supply voltage than the main battery of a portable system. 201628f5 FIGURE 3. I2C Bus Format 21 www.national.com LM4946 201628f4 FIGURE 4. I2C Timing Diagram SPI DESCRIPTION (For 2.2V ≤ I2CSPI_VDD ≤ 5.5V, see page 9 for more information). 0. I2CSPI_SEL: This pin is tied HIGH for SPI mode. 1. The data bits are transmitted with the MSB first. 2. The maximum clock rate is 1MHz for the CLK pin. 3. CLK must remain HIGH for at least 500ns (tCH ) after the rising edge of CLK, and CLK must remain LOW for at least 500ns (tCL) after the falling edge of CLK. 4. The serial data bits are sampled at the rising edge of CLK. Any transition on DATA must occur at least 100ns (tDS) before the rising edge of CLK. Also, any transition on DATA must occur at least 100ns (tDH) after the rising edge of CLK and stabilize before the next rising edge of CLK. 5.ID_ENB should be LOW only during serial data transmission. 6. ID_ENB must be LOW at least 100ns (tES ) before the first rising edge of CLK, and ID_ENB has to remain LOW at least 100ns (tEH) after the eighth rising edge of CLK. 7. If ID_ENB remains HIGH for more than 100ns before all 8 bits are transmitted then the data latch will be aborted. 8. If ID_ENB is LOW for more than 8 CLK pulses then only the first 8 data bits will be latched and activated when ID_ENB transitions to logic-high. 9. ID_ENB must remain HIGH for at least 100ns (tEL ) to latch in the data. 10. Coincidental rising or falling edges of CLK and ID_ENB are not allowed. If CLK is to be held HIGH after the data transmission, the falling edge of CLK must occur at least 100ns (tCS) before ID_ENB transitions to LOW for the next set of data. 20162824 FIGURE 5. SPI Timing Diagram www.national.com 22 LM4946 TABLE 1. Chip Address A7 Chip Address ID_ENB = 0 ID_ENB = 1 1 1 1 A6 1 1 1 A5 1 1 1 A4 1 1 1 A3 1 1 1 A2 0 0 0 A1 EC 0 1 A0 0 0 0 EC — Externally Controlled TABLE 2. Control Registers D7 Mode Control Programmable 3D Mono Volume Control Left Volume Control Right Volume Control 0 0 1 1 1 D6 0 1 0 1 1 D5 0 0 0 0 1 D4 0 0 MVC4 LVC4 RVC4 D3 OCL N3D3 MVC3 LVC3 RVC3 D2 MC2 N3D2 MVC2 LVC2 RVC2 D1 MC1 N3D1 MVC1 LVC1 RVC1 D0 MC0 N3D0 MVC0 LVC0 RVC0 1. Bits MVC0 — MVC4 control 32 step volume control for MONO input 2. Bits LVC0 — LVC4 control 32 step volume control for LEFT input 3. Bits RVC0 — RVC4 control 32 step volume control for RIGHT input 4. Bits MC0 — MC2 control 8 distinct modes 5. Bits N3D3, N3D2, N3D1, N3D0 control programmable 3D function 6. N3D0 turns the 3D function ON (N3D0 = 1) or OFF (N3D0 = 0), and N3D1 = 0 provides a “wider” aural effect or N3D1 = 1 a “narrower” aural effect 7. Bit OCL selects between SE with output capacitor (OCL = 0) or SE without output capacitors (OCL = 1). Default is OCL = 0 TABLE 3. Programmable National 3D Audio N3D3 Low Medium High Maximum 0 0 1 1 TABLE 4. Output Mode Selection Output Mode Number 0 1 2 3 4 5 6 7 MC2 0 0 0 0 1 1 1 1 MC1 0 0 1 1 0 0 1 1 MC0 0 1 0 1 0 1 0 1 Handsfree Speaker Output SD GP X P SD 2 X (GL X L + GR X R) SD 2 X (GL X L + GR X R) + GP X P SD 2 X (GR X R + GL X L) Right HP Output SD MUTE GP X P/2 MUTE GR X R MUTE GR X R + GP X P/2 GR X R Left HP Output SD MUTE GP X P/2 MUTE GL X L MUTE GL X L + GP X P/2 GL X L N3D2 0 1 0 1 On initial POWER ON, the default mode is 000 P = Phone-in (Mono) R = RIN L = LIN SD = Shutdown MUTE = Mute Mode GP = Phone In (Mono) volume control gain GR = Right stereo volume control gain GL = Left stereo volume control gain 23 www.national.com LM4946 TABLE 5. Volume Control Table Volume Step 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 xVC4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 xVC3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 xVC2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 xVC1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 xVC0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Gain,dB –54.00 –46.50 –40.50 –34.50 –30.00 –27.00 –24.00 –21.00 –18.00 –15.00 –13.50 –12.00 –10.50 –9.00 –7.50 –6.00 –4.50 –3.00 –1.50 0.00 1.50 3.00 4.50 6.00 7.50 9.00 10.50 12.00 13.50 15.00 16.50 18.00 1. x = M, L, or R 2. Gain / Attenuation is from input to output www.national.com 24 LM4946 NATIONAL 3D ENHANCEMENT The LM4946 features a stereo headphone, 3D audio enhancement effect that widens the perceived soundstage from a stereo audio signal. The 3D audio enhancement creates a perceived spatial effect optimized for stereo headphone listening. The LM4946 can be programmed for a “narrow” or “wide” soundstage perception. The narrow soundstage has a more focused approaching sound direction, while the wide soundstage has a spatial, theater-like effect. Within each of these two modes, four discrete levels of 3D effect that can be programmed: low, medium, high, and maximum (Table 2, 3), each level with an ever increasing aural effect, respectively. The difference between each level is 3dB. The external capacitors, shown in Figure 6, are required to enable the 3D effect. The value of the capacitors set the cutoff frequency of the 3D effect, as shown by Equations 1 and 2. Note that the internal 20kΩ resistor is nominal. Optional resistors R3DL and R3DR can also be added (Figure 7) to affect the -3dB frequency and 3D magnitude. 20162894 FIGURE 7. External RC Network with Optional R3DL and R3DR Resistors f3DL(-3dB) = 1 / 2π * (20kΩ + R3DL) * C3DL f3DR(-3dB) = 1 / 2π * 20kΩ + R3DR) * C3DR (3) (4) 20162895 FIGURE 6. External 3D Effect Capacitors ΔAV (change in AC gain) = 1 / 1 + M, where M represents some ratio of the nominal internal resistor, 20kΩ (see example below). f3dB (3D) = 1 / 2π (1 + M)(20kΩ * C3D) (5) (6) f3DL(-3dB) = 1 / 2π * 20kΩ * C3DL f3DR(-3dB) = 1 / 2π * 20kΩ * C3DR (1) CEquivalent (new) = C3D / 1 + M (2) TABLE 6. Pole Locations R3D (kΩ) (optional) C3D (nF) M ΔAV (dB) f-3dB (3D) (Hz) Value of C3D to keep same pole location (nF) 64.8 54.4 45.3 34.0 new Pole Location (Hz) 0 1 5 10 20 68 68 68 68 68 0 0.05 0.25 0.50 1.00 0 –0.4 –1.9 –3.5 –6.0 117 111 94 78 59 117 117 117 117 25 www.national.com LM4946 PCB LAYOUT AND SUPPLY REGULATION CONSIDERATIONS FOR DRIVING 8Ω LOAD Power dissipated by a load is a function of the voltage swing across the load and the load's impedance. As load impedance decreases, load dissipation becomes increasingly dependent on the interconnect (PCB trace and wire) resistance between the amplifier output pins and the load's connections. Residual trace resistance causes a voltage drop, which results in power dissipated in the trace and not in the load as desired. For example, 0.1Ω trace resistance reduces the output power dissipated by an 8Ω load from 158.3mW to 156.4mW. The problem of decreased load dissipation is exacerbated as load impedance decreases. Therefore, to maintain the highest load dissipation and widest output voltage swing, PCB traces that connect the output pins to a load must be as wide as possible. Poor power supply regulation adversely affects maximum output power. A poorly regulated supply's output voltage decreases with increasing load current. Reduced supply voltage causes decreased headroom, output signal clipping, and reduced output power. Even with tightly regulated supplies, trace resistance creates the same effects as poor supply regulation. Therefore, making the power supply traces as wide as possible helps maintain full output voltage swing. BRIDGE CONFIGURATION EXPLANATION The LM4946 drives a load, such as a speaker, connected between outputs, MONO+ and MONO-. This results in both amplifiers producing signals identical in magnitude, but 180° out of phase. Taking advantage of this phase difference, a load is placed between MONO- and MONO+ and driven differentially (commonly referred to as ”bridge mode”). This results in a differential or BTL gain of: AVD = 2(Rf / Ri) = 2 (7) supply and an 8Ω load, the maximum MONO power dissipation is 634mW. PDMAX-SPKROUT = 4(VDD)2 / (2π2 RL): Bridge Mode (8) The LM4946 also has a pair of single-ended amplifiers driving stereo headphones, ROUT and LOUT. The maximum internal power dissipation for ROUT and LOUT is given by equation (9) and (10). From Equations (9) and (10), assuming a 5V power supply and a 32Ω load, the maximum power dissipation for LOUT and ROUT is 40mW, or 80mW total. PDMAX-LOUT = (VDD)2 / (2π2 RL): Single-ended Mode PDMAX-ROUT = (VDD)2 / (2π2 RL): Single-ended Mode (9) (10) The maximum internal power dissipation of the LM4946 occurs when all three amplifiers pairs are simultaneously on; and is given by Equation (11). PDMAX-TOTAL = PDMAX-SPKROUT + PDMAX-LOUT + PDMAX-ROUT (11) The maximum power dissipation point given by Equation (11) must not exceed the power dissipation given by Equation (12): PDMAX = (TJMAX - TA) / θJA (12) Bridge mode amplifiers are different from single-ended amplifiers that drive loads connected between a single amplifier's output and ground. For a given supply voltage, bridge mode has a distinct advantage over the single-ended configuration: its differential output doubles the voltage swing across the load. Theoretically, this produces four times the output power when compared to a single-ended amplifier under the same conditions. This increase in attainable output power assumes that the amplifier is not current limited and that the output signal is not clipped. Another advantage of the differential bridge output is no net DC voltage across the load. This is accomplished by biasing MONO- and MONO+ outputs at half-supply. This eliminates the coupling capacitor that single supply, single-ended amplifiers require. Eliminating an output coupling capacitor in a typical single-ended configuration forces a single-supply amplifier's half-supply bias voltage across the load. This increases internal IC power dissipation and may permanently damage loads such as speakers. POWER DISSIPATION Power dissipation is a major concern when designing a successful single-ended or bridged amplifier. A direct consequence of the increased power delivered to the load by a bridge amplifier is higher internal power dissipation. The LM4946 has a pair of bridged-tied amplifiers driving a handsfree speaker, MONO. The maximum internal power dissipation operating in the bridge mode is twice that of a single-ended amplifier. From Equation (8), assuming a 5V power www.national.com 26 The LM4946's TJMAX = 150°C. In the SQ package, the LM4946's θJA is 46°C/W. At any given ambient temperature TA, use Equation (12) to find the maximum internal power dissipation supported by the IC packaging. Rearranging Equation (12) and substituting PDMAX-TOTAL for PDMAX' results in Equation (13). This equation gives the maximum ambient temperature that still allows maximum stereo power dissipation without violating the LM4946's maximum junction temperature. TA = TJMAX - PDMAX-TOTAL θJA (13) For a typical application with a 5V power supply and an 8Ω load, the maximum ambient temperature that allows maximum mono power dissipation without exceeding the maximum junction temperature is approximately 121°C for the SQ package. TJMAX = PDMAX-TOTAL θJA + TA (14) Equation (14) gives the maximum junction temperature TJMAX. If the result violates the LM4946's 150°C, reduce the maximum junction temperature by reducing the power supply voltage or increasing the load resistance. Further allowance should be made for increased ambient temperatures. The above examples assume that a device is a surface mount part operating around the maximum power dissipation point. Since internal power dissipation is a function of output power, higher ambient temperatures are allowed as output power or duty cycle decreases. If the result of Equation (11) is greater than that of Equation (12), then decrease the supply voltage, increase the load impedance, or reduce the ambient temperature. If these measures are insufficient, a heat sink can be added to reduce θJA. The heat sink can be created using additional copper area around the package, with connections to LM4946 the ground pin(s), supply pin and amplifier output pins. External, solder attached SMT heatsinks such as the Thermalloy 7106D can also improve power dissipation. When adding a heat sink, the θJA is the sum of θJC, θCS, and θSA. (θJC is the junction-to-case thermal impedance, θCS is the case-to-sink thermal impedance, and θSA is the sink-to-ambient thermal impedance). Refer to the Typical Performance Characteristics curves for power dissipation information at lower output power levels. POWER SUPPLY BYPASSING As with any power amplifier, proper supply bypassing is critical for low noise performance and high power supply rejection. Applications that employ a 5V regulator typically use a 1µF in parallel with a 0.1µF filter capacitors to stabilize the regulator's output, reduce noise on the supply line, and improve the supply's transient response. However, their presence does not eliminate the need for a local 1.0µF tantalum bypass capacitor and a parallel 0.1µF ceramic capacitor connected between the LM4946's supply pin and ground. Keep the length of leads and traces that connect capacitors between the LM4946's power supply pin and ground as short as possible. SELECTING EXTERNAL COMPONENTS Input Capacitor Value Selection Amplifying the lowest audio frequencies requires high value input coupling capacitor (Ci in Figures 1 & 2). A high value capacitor can be expensive and may compromise space efficiency in portable designs. In many cases, however, the speakers used in portable systems, whether internal or external, have little ability to reproduce signals below 150Hz. Applications using speakers with this limited frequency response reap little improvement by using large input capacitor. The internal input resistor (Ri), minimum 10kΩ, and the input capacitor (Ci) produce a high pass filter cutoff frequency that is found using Equation (15). fc = 1 / (2πRiCi) (15) As an example when using a speaker with a low frequency limit of 150Hz, Ci, using Equation (15) is 0.106µF. The 0.22µF Ci shown in Figure 1 allows the LM4946 to drive high efficiency, full range speaker whose response extends below 40Hz. Bypass Capacitor Value Selection Besides minimizing the input capacitor size, careful consideration should be paid to value of CB, the capacitor connected to the BYPASS pin. Since CB determines how fast the LM4946 settles to quiescent operation, its value is critical when minimizing turn-on pops. The slower the LM4946's outputs ramp to their quiescent DC voltage (nominally VDD/2), the smaller the turn-on pop. Choosing CB equal to 2.2µF along with a small value of Ci (in the range of 0.1µF to 0.33µF), produces a click-less and pop-less shutdown function. As discussed above, choosing Ci no larger than necessary for the desired bandwidth helps minimize clicks and pops. CB's value should be in the range of 7 to 10 times the value of Ci. This ensures that output transients are eliminated when power is first applied or the LM4946 resumes operation after shutdown. 27 www.national.com LM4946 Demo Board Schematic Diagram www.national.com 28 201628l2 LM4946 29 201628n5 www.national.com LM4946 Revision History Rev 1.0 1.1 1.2 1.3 1.4 Date 01/23/06 03/05/07 03/13/07 04/24/07 04/26/07 Description Initial release. Added the TMD25XXX package. Edited the 25–pin micro SMD connection diagram. Added the I2C/SPI (1.7V 2.2V ) table. Added the numerical values for the X1, X2, and X3 in the Physical Dimension section. Text edits. Added the TM package. Added the TM board schematic and input some text edits. More text edits. Added Note 11 and more text edits. 1.5 1.6 1.7 1.8 05/02/07 05/15/07 05/16/07 06/06/07 www.national.com 30 LM4946 Physical Dimensions inches (millimeters) unless otherwise noted 24 Lead LLP Package Order Number LM4946SQ NS Package Number SQA24A Dimensions are in millimeters X1 = 4 ± 0.1 X2 = 4 ± 0.1 X3 = 0.8 ± 0.1 31 www.national.com LM4946 25 Bump micro SMD Package Order Number LM4946TM NS Package Number TMD25ABA X1 = 2015μm, X2 = 2047μm, X3 = 600μm www.national.com 32 LM4946 Notes 33 www.national.com LM4946 Output Capacitor-Less Audio Subsystem with Programmable National 3D Notes THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. NATIONAL MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE ACCURACY OR COMPLETENESS OF THE CONTENTS OF THIS PUBLICATION AND RESERVES THE RIGHT TO MAKE CHANGES TO SPECIFICATIONS AND PRODUCT DESCRIPTIONS AT ANY TIME WITHOUT NOTICE. NO LICENSE, WHETHER EXPRESS, IMPLIED, ARISING BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. TESTING AND OTHER QUALITY CONTROLS ARE USED TO THE EXTENT NATIONAL DEEMS NECESSARY TO SUPPORT NATIONAL’S PRODUCT WARRANTY. EXCEPT WHERE MANDATED BY GOVERNMENT REQUIREMENTS, TESTING OF ALL PARAMETERS OF EACH PRODUCT IS NOT NECESSARILY PERFORMED. NATIONAL ASSUMES NO LIABILITY FOR APPLICATIONS ASSISTANCE OR BUYER PRODUCT DESIGN. BUYERS ARE RESPONSIBLE FOR THEIR PRODUCTS AND APPLICATIONS USING NATIONAL COMPONENTS. PRIOR TO USING OR DISTRIBUTING ANY PRODUCTS THAT INCLUDE NATIONAL COMPONENTS, BUYERS SHOULD PROVIDE ADEQUATE DESIGN, TESTING AND OPERATING SAFEGUARDS. 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As used herein: Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness. National Semiconductor and the National Semiconductor logo are registered trademarks of National Semiconductor Corporation. All other brand or product names may be trademarks or registered trademarks of their respective holders. Copyright© 2007 National Semiconductor Corporation For the most current product information visit us at www.national.com National Semiconductor Americas Customer Support Center Email: new.feedback@nsc.com Tel: 1-800-272-9959 National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530-85-86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +49 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Support Center Email: ap.support@nsc.com National Semiconductor Japan Customer Support Center Fax: 81-3-5639-7507 Email: jpn.feedback@nsc.com Tel: 81-3-5639-7560 www.national.com