LM5067MM-1

LM5067 Negative Hot Swap / Inrush Current Controller with Power Limiting September 9, 2009 LM5067 Negative Hot Swap / Inrush Current Controller with Power Limiting General Description The LM5067 negative hot swap controller provides intelligent control of the power supply connections during insertion and removal of circuit cards from a live system backplane or other “hot” power sources. The LM5067 provides in-rush current control to limit system voltage droop and transients. The current limit and power dissipation in the external series pass NChannel MOSFET are programmable, ensuring operation within the Safe Operating Area (SOA). In addition, the LM5067 provides circuit protection by monitoring for overcurrent and over-voltage conditions. The POWER GOOD output indicates when the output voltage is close to the input voltage. The input under-voltage and over-voltage lockout levels and hysteresis are programmable, as well as the fault detection time. The LM5067-1 latches off after a fault detection, while the LM5067-2 automatically attempts restarts at a fixed duty cycle. The LM5067 is available in a 10 pin MSOP package and a 14 pin SOIC package. ■ ■ ■ ■ ■ Adjustable current limit Circuit breaker function for severe over-current events Adjustable under-voltage lockout (UVLO) and hysteresis Adjustable over-voltage lockout (OVLO) and hysteresis Initial insertion timer allows ringing and transients to subside after system connection ■ Programmable fault timer avoids nuisance trips ■ Active high open drain POWER GOOD output ■ Available in latched fault and automatic restart versions Applications ■ ■ ■ ■ ■ ■ ■ Server Backplane Systems In-Rush Current Limiting Solid State Circuit Breaker Transient Voltage Protector Solid State Relay Under-voltage Lock-out Power Good Detector/Indicator Features ■ Wide operating range: -9V to -80V ■ In-rush current limit for safe board insertion into live power sources ■ Programmable maximum power dissipation in the external pass device Package ■ MSOP-10 ■ SO-14 (Latched Fault Version) Typical Application 30030901 Negative Power Bus In-Rush and Fault Protection © 2009 National Semiconductor Corporation 300309 www.national.com LM5067 Connection Diagrams (Note 7) 30030902 Top View 10-Lead MSOP 30030964 Top View 14-Lead SOIC Ordering Information Order Number LM5067MM-1 LM5067MMX-1 LM5067MM-2 LM5067MMX-2 LM5067MW-1 LM5067MWX-1 Fault Response Latch Off Latch Off Auto Restart Auto Restart Latch Off Latch Off SO-14 M14B MSOP-10 MUB10A Package Type NSC Package Drawing Supplied As 1000 Units on Tape and Reel 3500 Units on Tape and Reel 1000 Units on Tape and Reel 3500 Units on Tape and Reel 50 Units per Rail 1000 Units on Tape and Reel Pin Descriptions Pin # MSOP-10 1 SO-14 1 Name VCC Description Positive supply input Under-voltage lockout Applications Information Connect to system ground through a resistor. Connect a bypass capacitor to VEE. The voltage from VCC to VEE is nominally 13V set by an internal zener diode. An external resistor divider from the system input voltage sets the undervoltage turn-on threshold. The enable threshold at the pin is 2.5V above VEE. An internal 22 µA current source provides hysteresis. This pin can be used for remote enable and disable. An external resistor divider from the system input voltage sets the overvoltage turn-off threshold. The disable threshold at the pin is 2.5V above VEE. An internal 22 µA current source provides hysteresis. An external resistor at this pin, in conjunction with the current sense resistor (RS), sets the maximum power dissipation in the external series pass MOSFET. 2 3 UVLO/EN 3 4 OVLO Over-voltage lockout Power limit set 4 5 PWR 5 6 7 6 8 9 VEE TIMER SENSE Negative supply Connect to the system negative supply voltage (typically -48V). input Timing capacitor An external capacitor at this pin sets the insertion time delay and the fault timeout period. The capacitor also sets the restart timing of the LM5067-2. Current sense input The voltage across the current sense resistor (RS) is measured from VEE to this pin. If the voltage across RS reaches 50 mV the load current is limited and the fault timer activates. 8 10 GATE Gate drive output Connect to the external N-channel MOSFET’s gate. www.national.com 2 LM5067 Pin # MSOP-10 9 10 SO-14 12 14 Name OUT PGD Description Applications Information Output feedback Connect to the external MOSFET’s drain. Internally used to determine the MOSFET VDS voltage for power limiting, and to control the PGD output pin. Power Good indicator An open drain output capable of sustaining 80V when off. When the external MOSFET VDS decreases below 1.23V the PGD pin switches high. When the external MOSFET VDS increases above ≊2.5V the PGD pin switches low. 3 www.national.com LM5067 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Current into VCC (100 µs pulse) OUT, PGD to VEE UVLO, OVLO to VEE SENSE to VEE ESD Rating (Note 2) Human Body Model 100 mA -0.3V to 100V -0.3V to 17V -0.3V to +0.3V 2kV Storage Temperature Junction Temperature -65°C to +150°C +150°C Operating Ratings Current into VCC (Note 5) OUT Voltage above VEE PGD Off Voltage above VEE Junction Temperature 2 mA (min) 0V to 80V 0V to 80V −40°C to +125°C Electrical Characteristics Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are guaranteed through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply: ICC = 2 mA, OUT Pin = 48V above VEE, all voltages are with respect to VEE. See (Note 3). Symbol Parameter Operating voltage, VCC – VEE Internal operating current, enabled Internal operating current, disabled Threshold voltage to start insertion timer Threshold voltage to enable all functions POREN hysteresis OUT bias current, enabled OUT bias current, disabled SENSE bias current, enabled SENSE bias current, disabled UVLO threshold UVLO hysteresis current UVLO delay UVLO bias current OVLO threshold OVLO hysteresis current OVLO delay OVLO bias current Source current Sink current OVLO = VEE+2.8V Delay to GATE high Delay to GATE low OVLOBIAS IGATE OVLO = VEE + 2.4V Normal Operation UVLO < 2.5V SENSE - VEE =150 mV or VCC - VEE < PORIT, VGATE = 5V VGATE Gate output voltage in normal operation GATE-VEE voltage -72 1.9 45 -52 2.2 110 VZ UVLO = VEE + 2V Delay to GATE high Delay to GATE low UVLOBIAS OVLOTH OVLOHYS OVLODEL UVLO = VEE + 5V 2.43 -34 2.5 -22 26 12 1 -32 2.68 200 V Conditions ICC = 2 mA, UVLO = 5V VCC-VEE = 11V, UVLO = 5V VCC-VEE = 11V, UVLO = 2V VCC-VEE increasing VCC-VEE increasing VCC-VEE decreasing OUT = VEE, Normal operation Disabled, OUT = VEE + 48V OUT = VEE, Normal operation Disabled, OUT = VEE + 48V 2.45 10 Min 12.35 Typ 13 0.8 480 7.7 8.4 125 0.1 50 -6 -50 2.5 22 26 12 1 2.57 -10 2.55 34 V µA µs µs µA V µA µs µs µA µA mA µA Max 13.65 1 660 8.2 8.7 Units V mA µA V V mV µA Input VZ ICC-EN ICC-DIS PORIT POREN POREN-HYS OUT Pin IOUT-EN IOUT-DIS SENSE Pin ISNS-EN ISNS-DIS UVLO, OVLO Pins UVLOTH UVLOHYS UVLODEL Gate Control (GATE Pin) www.national.com 4 LM5067 Symbol Current Limit VCL tCL Circuit Breaker VCB tCB Parameter Threshold voltage Response time Conditions SENSE - VEE voltage SENSE - VEE stepped from 0 mV to 80 mV SENSE - VEE voltage SENSE - VEE stepped from 0 mV to 150 mV, time to GATE low, no load OUT - SENSE = 24V, RPWR = 75 kΩ VPWR = 2.5V Min 44 Typ 50 25 Max 56 Units mV µs Threshold voltage Response time 70 100 0.65 130 1.0 mV µs Power Limit (PWR Pin) PWRLIM IPWR Timer (TIMER Pin) VTMRH VTMRL Upper threshold Lower threshold Restart cycles (LM5067-2) End of 8th cycle (LM5067-2) Re-enable threshold (LM5067-1) ITIMER Insertion time current Sink current, end of insertion time Fault detection current Sink current, end of fault time DCFAULT tFAULT PGDTH Fault Restart Duty Cycle Fault to GATE low delay Threshold measured at OUT - SENSE LM5067-2 TIMER pin reaches 4.0V Decreasing TIMER pin = 2V TIMER pin = 2V TIMER pin = 2V -9.5 1.2 -140 0.9 3.76 1.18 4 1.25 0.3 0.3 -6 1.55 -85 2.5 0.5 15 1.162 1.23 1.285 -2.5 1.9 -44 4.25 4.16 1.32 V V V V µA mA µA µA % µs V Power limit sense voltage (SENSE - VEE) PWR pin current 16.5 22 -23 27.5 mV µA Power Good (PGD Pin) Increasing, relative to decreasing 1.143 1.25 1.325 threshold PGDVOL PGDIOH θJA θJC θJA θJC Output low voltage Off leakage current Junction to Ambient Junction to Case Junction to Ambient Junction to Case ISINK = 2 mA VPGD = 80V MSOP package MSOP package SO-14 Package SO-14 Package 94 44 90 27 60 150 5 mV µA °C/W °C/W °C/W °C/W Thermal Resistance (Note 6) Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and conditions see the Electrical Characteristics. Note 2: The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. Note 3: Current out of a pin is indicated as a negative value. Note 4: For detailed information on soldering plastic MSOP package refer to the Packaging Databook available from National Semiconductor Corporation. Note 5: Maximum continuous current into VCC is limited by power dissipation and die temperature. See the Thermal Considerations section. Note 6: Tested on a 4 layer JEDEC board with 2 vias under the package. See JEDEC standards JESD51-7 and JESD51-3. See the Thermal Considerations section. Note 7: N/C Pins are internally not connected to anything. 5 www.national.com LM5067 Typical Performance Characteristics apply: TJ = 25°C. ICC vs. Operating Voltage - Disabled Unless otherwise specified the following conditions ICC vs. Operating Voltage - Enabled 30030904 30030905 Operating Voltage vs. ICC SENSE Pin Current vs. System Voltage 30030906 30030907 OUT Pin Current vs. System Voltage GATE Source Current vs. Operating Voltage 30030908 30030909 www.national.com 6 LM5067 GATE Pull-Down Current, Circuit Breaker vs. GATE Voltage PGD Low Voltage vs. Sink Current 30030910 30030911 MOSFET Power Dissipation Limit vs. RPWR and RS UVLO & OVLO Hysteresis Current vs. Temperature 30030912 30030913 UVLO, OVLO Threshold Voltage vs. Temperature VZ Operating Voltage vs. Temperature 30030915 30030916 7 www.national.com LM5067 Current Limit Threshold vs. Temperature Circuit Breaker Threshold vs. Temperature 30030917 30030918 Power Limit Threshold vs. Temperature Gate Source Current vs. Temperature 30030919 30030920 GATE Pull-Down Current, Circuit Breaker vs. Temperature PGD Pin Low Voltage vs. Temperature 30030921 30030922 www.national.com 8 LM5067 POREN Threshold vs. Temperature TIMER Pin Thresholds vs. Temperature 30030925 30030923 TIMER Pin Fault Detection Current vs. Temperature 30030926 9 www.national.com LM5067 Block Diagram 30030927 30030928 FIGURE 1. Basic Application Circuit www.national.com 10 LM5067 Functional Description The LM5067 is designed to control the in-rush current to the load upon insertion of a circuit card into a live backplane or other “hot” power source, thereby limiting the voltage sag on the backplane’s supply voltage, and the dV/dt of the voltage applied to the load. Effects on other circuits in the system are minimized, preventing possible unintended resets. During the system power up, the maximum power dissipation in the series pass device is limited to a safe value within the device’s Safe Operating Area (SOA). After the system power up is complete, the LM5067 monitors the load for excessive currents due to a fault or short circuit at the load. Limiting the load current and/or the power in the external MOSFET for an ex- tended period of time results in the shutdown of the series pass MOSFET. After a fault event, the LM5067-1 latches off until the circuit is re-enabled by external control, while the LM5067-2 automatically restarts with defined timing. The circuit breaker function quickly switches off the series pass device upon detection of a severe over-current condition caused by, e.g. a short circuit at the load. The Power Good (PGD) output pin indicates when the output voltage is close to the normal operating value. Programmable under-voltage lock-out (UVLO) and over-voltage lock-out (OVLO) circuits shut down the LM5067 when the system input voltage is outside the desired operating range. The typical configuration of a circuit card with LM5067 hot swap protection is shown in Figure 2. 30030929 FIGURE 2. LM5067 Application The LM5067 can be used in a variety of applications, other than plug-in boards, to monitor for excessive load current, provide transient protection, and ensuring the voltage to the load is within preferred limits. The circuit breaker function protects the system from a sudden short circuit at the load. Use of the UVLO/EN pin allows the LM5067 to be used as a solid state relay. The PGD output provides a status indication of the voltage at the load relative to the input system voltage. the operating voltage reaches the POREN threshold (8.4V). As VSYS continues to increase, the LM5067 operating voltage is limited at ≊13V by an internal zener diode. The remainder of the system voltage is dropped across the input resistor RIN. The GATE pin switches on Q1 when VSYS exceeds the UVLO threshold (UVLO pin >2.5V above VEE). If VSYS exceeds the UVLO threshold at the end of the insertion time, Q1 is switched on at that time. The GATE pin sources 52 µA to charge Q1’s gate capacitance. The maximum gate-to-source voltage of Q1 is limited by the LM5067’s operating voltage (VZ) to approximately 13V. During power up, as the voltage at the OUT pin increases in magnitude with respect to Ground, the LM5067 monitors Q1’s drain current and power dissipation. In-rush current limiting and/or power limiting circuits actively control the current delivered to the load. During the in-rush limiting interval (t2 in Figure 3) an internal current source charges CT at the TIMER pin. When the load current reduces from the limiting value to a value determined by the load the in-rush limiting interval is complete and CT is discharged. The PGD pin switches high when the voltage at the OUT pin reaches to within 1.25V of the voltage at the SENSE pin. If the TIMER pin voltage reaches 4.0V before in-rush current limiting or power limiting ceases (during t2), a fault is declared and Q1 is turned off. See the Fault Timer & Restart section for a complete description of the fault mode. Power Up Sequence The system voltage range of the LM5067 is -9V to -80V, with a transient capability to -100V. Referring to the Block Diagram and Figures 1 and 3, as the system voltage (VSYS) initially increases from zero, the external N-channel MOSFET (Q1) is held off by an internal 110 mA pull-down current at the GATE pin. The strong pull-down current at the GATE pin prevents an inadvertent turn-on as the MOSFET’s gate-to-drain (Miller) capacitance is charged. When the operating voltage of the LM5067 (VCC – VEE) reaches the PORIT threshold (7.7V) the insertion timer starts. During the insertion time, the capacitor at the TIMER pin (CT) is charged by a 6 µA current source, and Q1 is held off by a 2.2 mA pull-down current at the GATE pin regardless of the system voltage. The insertion time delay allows ringing and transients at VSYS to settle before Q1 can be enabled. The insertion time ends when the TIMER pin voltage reaches 4.0V above VEE, and CT is then quickly discharged by an internal 1.5 mA pull-down current. After the insertion time, the LM5067 control circuitry is enabled when 11 www.national.com LM5067 30030930 FIGURE 3. Power Up Sequence (Current Limit only) Operating Voltage The LM5067 operating voltage is the voltage from VCC to VEE. The maximum operating voltage is set by an internal 13V zener diode. With the IC connected as shown in Figure 1, the LM5067 controller operates in the voltage range between VEE and VEE+13V. The remainder of the system voltage is dropped across the input resistor RIN, which must be selected to pass at least 2 mA into the LM5067 at the minimum system voltage. Gate Control The external N-channel MOSFET is turned on when the GATE pin sources 52 µA to enhance the gate. During normal operation (t3 in Figure 3) Q1’s gate is held charged to approximately 13V above VEE, typically within 20 mV of the voltage at VCC. If the maximum VGS rating of Q1 is less than 13V, a lower voltage external zener diode must be added between the GATE and SENSE pins. The external zener diode must have a forward current rating of at least 110 mA. www.national.com 12 When the system voltage is initially applied (before the operating voltage reaches the PORIT threshold), the GATE pin is held low by a 110 mA pull-down current. The pull-down current helps prevent an inadvertent turn-on of the MOSFET through its drain-gate capacitance as the applied system voltage increases. During the insertion time (t1 in Figure 3) the GATE pin is held low by a 2.2 mA pull-down current. This maintains Q1 in the off-state until the end of t1, regardless of the voltage at VCC and UVLO. Following the insertion time, during t2 in Figure 3, the gate voltage of Q1 is modulated to keep the current or Q1’s power dissipation level from exceeding the programmed levels. Current limiting and power limiting are considered fault conditions, during which the voltage on the TIMER pin capacitor increases. If the current and power limiting cease before the TIMER pin reaches 4V the TIMER pin capacitor is discharged, and the circuit enters normal operation. See the Fault Timer & Restart paragraph for details on the fault timer. LM5067 If the system input voltage falls below the UVLO threshold, or rises above the OVLO threshold, the GATE pin is pulled low by the 2.2 mA pull-down current to switch off Q1. maximum power dissipation of MOSFET Q1 within the device SOA rating. The LM5067 determines the power dissipation in Q1 by monitoring its drain-source voltage (OUT to SENSE), and the drain current through the sense resistor (SENSE to VEE). The product of the current and voltage is compared to the power limit threshold programmed by the resistor at the PWR pin. If the power dissipation reaches the limiting threshold, the GATE voltage is modulated to reduce the current in Q1, and the fault timer is active as described in the Fault Timer & Restart section. Fault Timer & Restart When the current limit or power limit threshold is reached during turn-on or as a result of a fault condition, the gate-tosource voltage of Q1 is modulated to regulate the load current and power dissipation in Q1. When either limiting function is active, an 85 µA fault timer current source charges the external capacitor (CT) at the TIMER pin as shown in Figure 6 (Fault Timeout Period). If the fault condition subsides before the TIMER pin reaches 4.0V, the LM5067 returns to the normal operating mode and CT is discharged by the 2.5 µA current sink. If the TIMER pin reaches 4.0V during the Fault Timeout Period, Q1 is switched off by a 2.2 mA pull-down current at the GATE pin. The subsequent restart procedure depends on which version of the LM5067 is in use. The LM5067-1 latches the GATE pin low at the end of the Fault Timeout Period, and CT is discharged by the 2.5 µA fault current sink. The GATE pin is held low until a power up sequence is externally initiated by cycling the input voltage (VSYS), or momentarily pulling the UVLO/EN pin within 2.5V of VEE with an open-collector or open-drain device as shown in Figure 5. The voltage across CT must be