LM5069MMX-1

LM5069 Positive High Voltage Hot Swap / Inrush Current Controller with Power Limiting March 5, 2008 LM5069 Positive High Voltage Hot Swap / Inrush Current Controller with Power Limiting General Description The LM5069 positive hot swap controller provides intelligent control of the power supply connections during insertion and removal of circuit cards from a live system backplane or other "hot" power sources. The LM5069 provides in-rush current control to limit system voltage droop and transients. The current limit and power dissipation in the external series pass NChannel MOSFET are programmable, ensuring operation within the Safe Operating Area (SOA). The POWER GOOD output indicates when the output voltage is within 1.25V of the input voltage. The input under-voltage and over-voltage lockout levels and hysteresis are programmable, as well as the initial insertion delay time and fault detection time. The LM5069-1 latches off after a fault detection, while the LM5069-2 automatically restarts at a fixed duty cycle. The LM5069 is available in a 10 pin MSOP package. ■ Adjustable current limit ■ Circuit breaker function for severe over-current events ■ Internal high side charge pump and gate driver for external N-channel MOSFET ■ Adjustable under-voltage lockout (UVLO) and hysteresis ■ Adjustable over-voltage lockout (OVLO) and hysteresis ■ Initial insertion timer allows ringing and transients to subside after system connection ■ Programmable fault timer avoids nuisance trips ■ Active high open drain POWER GOOD output ■ Available in latched fault and automatic restart versions Applications ■ ■ ■ ■ Server Backplane Systems Base Station Power Distribution Systems Solid State Circuit Breaker 24V/48V Industrial Systems Features ■ Wide operating range: +9V to +80V ■ In-rush current limit for safe board insertion into live power sources ■ Programmable maximum power dissipation in the external pass device Package ■ MSOP-10 Typical Application 20197201 Positive Power Supply Control © 2008 National Semiconductor Corporation 201972 www.national.com LM5069 Connection Diagram 20197202 Top View 10-Lead MSOP Ordering Information Order Number LM5069MM-1 LM5069MMX-1 LM5069MM-2 LM5069MMX-2 Fault Response Latch Off Latch Off Auto Restart Auto Restart MSOP-10 MUB10A Package Type NSC Package Drawing Supplied As 1000 Units on Tape and Reel 3500 Units on Tape and Reel 1000 Units on Tape and Reel 3500 Units on Tape and Reel Pin Descriptions Pin # 1 Name SENSE Description Current sense input Applications Information The voltage across the current sense resistor (RS) is measured from VIN to this pin. If the voltage across RS reaches 55mV the load current is limited and the fault timer activates. A small ceramic bypass capacitor close to this pin is recommended to suppress transients which occur when the load current is switched off. An external resistor divider from the system input voltage sets the under-voltage turn-on threshold. An internal 21 µA current source provides hysteresis. The enable threshold at the pin is 2.5V. This pin can also be used for remote shutdown control. An external resistor divider from the system input voltage sets the over-voltage turn-off threshold. An internal 21 µA current source provides hysteresis. The disable threshold at the pin is 2.5V. An external capacitor connected to this pin sets the insertion time delay and the Fault Timeout Period. The capacitor also sets the restart timing of the LM5069-2. An external resistor connected to this pin, in conjunction with the current sense resistor (RS), sets the maximum power dissipation allowed in the external series pass MOSFET. An open drain output. When the external MOSFET VDS decreases below 1.25V, the PGD indicator is active (high). When the external MOSFET VDS increases above 2.5V the PGD indicator switches low. Connect to the output rail (external MOSFET source). Internally used to determine the MOSFET VDS voltage for power limiting, and to control the PGD indicator. Connect to the external MOSFET’s gate. This pin's voltage is typically 12V above the OUT pin when enabled. 2 3 VIN UVLO Positive supply input Under-voltage lockout 4 OVLO Over-voltage lockout 5 6 7 GND TIMER PWR Circuit ground Timing capacitor Power limit set 8 PGD Power Good indicator 9 10 OUT GATE Output feedback Gate drive output www.national.com 2 LM5069 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. VIN to GND (Note 5) SENSE, OUT, PGD to GND GATE to GND (Note 5) UVLO to GND OVLO to GND VIN to SENSE -0.3V to 100V -0.3V to 100V -0.3V to 100V -0.3V to 100V -0.3V to 7V -0.3V to +0.3V ESD Rating (Note 2) Human Body Model Storage Temperature Junction Temperature 2kV -65°C to +150°C +150°C Operating Ratings VIN Supply Voltage PGD Off Voltage Junction Temp. Range +9.0V to 80V 0V to 80V −40°C to +125°C Electrical Characteristics Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are guaranteed through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply: VIN = 48V. Symbol Parameter Input Current, enabled Input Current, disabled Conditions UVLO > 2.5V and OVLO < 2.5V UVLO 2.5V Min. Typ. 1.3 480 7.6 8.4 90 11 50 2.45 UVLO = 1V Delay to GATE high Delay to GATE low UVLOBIAS OVLOTH OVLOHYS OVLODEL OVLOBIAS PWRLIM-1 PWRLIM-2 IPWR IGATE PWR pin current Source current Sink current UVLO bias current OVLO threshold OVLO hysteresis current OVLO delay OVLO bias current Power limit sense voltage (VIN-SENSE) OVLO = 2.6V Delay to GATE high Delay to GATE low OVLO = 2.4V SENSE-OUT = 48V, RPWR = 150 kΩ SENSE-OUT = 24V, RPWR = 75 kΩ VPWR = 2.5V Normal Operation, GATE-OUT = 5V UVLO < 2.5V VIN - SENSE = 150 mV or VIN < PORIT, VGATE = 5V VGATE Gate output voltage in normal operation GATE-OUT voltage 10 1.75 45 11.4 19 25 25 20 16 2 110 12 22 2.6 175 12.6 UVLO = 48V 2.40 12 2.5 21 55 11 1 31 µA mV mV µA µA mA mA V 12 2.5 21 55 11 1 2.60 30 µA V µA µs 2.55 30 V µA µs Max. 1.6 650 8.0 9.0 Units mA µA V V mV µA Input (VIN pin) IIN-EN IIN-DIS PORIT POREN POREN-HYS OUT pin IOUT-EN IOUT-DIS UVLO, OVLO pins UVLOTH UVLOHYS UVLODEL UVLO threshold UVLO hysteresis current UVLO delay OUT bias current, enabled OUT bias current, disabled (Note 3) OUT = VIN, Normal operation Disabled, OUT = 0V, SENSE = VIN Power On Reset threshold at VIN to trigger VIN Increasing insertion timer Power On Reset threshold at VIN to enable all functions POREN hysteresis VIN increasing VIN decreasing Power Limit (PWR pin) Gate Control (GATE pin) 3 www.national.com LM5069 Symbol Current Limit VCL tCL ISENSE Circuit Breaker VCB tCB Timer (TIMER pin) VTMRH VTMRL Parameter Threshold voltage Response time SENSE input current Conditions VIN-SENSE voltage VIN-SENSE stepped from 0 mV to 80 mV Enabled, SENSE = OUT Disabled, OUT = 0V Min. 48.5 Typ. 55 45 23 60 Max. 61.5 Units mV µs µA Threshold voltage Response time VIN - SENSE VIN - SENSE stepped from 0 mV to 150 mV, time to GATE low, no load 80 105 0.44 130 1.2 mV µs Upper threshold Lower threshold Restart cycles (LM5069-2) End of 8th cycle (LM5069-2) Re-enable Threshold (LM5069-1) 3.76 1.187 4 1.25 0.3 0.3 4.16 1.313 V V V V ITIMER Insertion time current Sink current, end of insertion time Fault detection current Fault sink current TIMER pin = 2V 3 1.0 51 1.25 LM5069-2 only TIMER pin reaches 4.0V Decreasing Increasing, relative to decreasing threshold 0.67 0.95 5.5 1.5 85 2.5 0.5 12 1.25 1.25 60 8 2.0 120 3.75 µA mA µA µA % µs DCFAULT tFAULT PGDTH Fault Restart Duty Cycle Fault to GATE low delay Threshold measured at SENSE-OUT Power Good (PGD pin) 1.85 1.55 150 5 mV µA V PGDVOL PGDIOH Output low voltage Off leakage current ISINK = 2 mA VPGD = 80V Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and conditions see the Electrical Characteristics. Note 2: The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. Note 3: OUT bias current (disabled) due to leakage current through an internal 1.0 MΩ resistance from SENSE to VOUT. Note 4: For detailed information on soldering plastic MSOP packages refer to the Packaging Databook available from National Semiconductor Corporation. Note 5: The GATE pin voltage is typically 12V above VIN when the LM5069 is enabled. Therefore the Absolute Maximum Ratings for VIN (100V) applies only when the LM5069 is disabled, or for a momentary surge to that voltage since the Absolute Maximum Rating for the GATE pin is also 100V. www.national.com 4 LM5069 Typical Performance Characteristics 25°C, VIN = 48V VIN Pin Input Current vs. VIN Unless otherwise specified the following conditions apply: TJ = SENSE Pin Input Current 20197203 20197204 OUT Pin Current GATE Pin Voltage vs. VIN 20197206 20197205 GATE Pin Source Current vs. VIN PGD Pin Low Voltage vs. Sink Current 20197207 20197208 5 www.national.com LM5069 MOSFET Power Dissipation Limit vs. RPWR and RS GATE Pull-Down Current, Circuit Breaker vs GATE Voltage 20197209 20197266 UVLO Hysteresis Current vs. Temperature OVLO Hysteresis Current vs. Temperature 20197255 20197256 UVLO, OVLO Threshold vs. Temperature Input Current, Enabled vs. Temperature 20197257 20197258 www.national.com 6 LM5069 Current Limit Threshold vs. Temperature Circuit Breaker Threshold vs. Temperature 20197259 20197260 Power Limit Threshold vs. Temperature GATE Output Voltage vs. Temperature 20197261 20197262 GATE Source Current vs. Temperature GATE Pull-Down Current, Circuit Breaker vs. Temperature 20197263 20197264 7 www.national.com LM5069 PGD Low Voltage vs. Temperature 20197265 Block Diagram 20197210 www.national.com 8 LM5069 20197211 FIGURE 1. Basic Application Circuit Functional Description The LM5069 is designed to control the in-rush current to the load upon insertion of a circuit card into a live backplane or other "hot" power source, thereby limiting the voltage sag on the backplane’s supply voltage, and the dV/dt of the voltage applied to the load. Effects on other circuits in the system are minimized, preventing possible unintended resets. A controlled shutdown when the circuit card is removed can also be implemented using the LM5069. In addition to a programmable current limit, the LM5069 monitors and limits the maximum power dissipation in the series pass device to maintain operation within the device Safe Operating Area (SOA). Either current limiting or power limiting for an extended period of time results in the shutdown of the series pass device. In this event, the LM5069-1 latches off until the circuit is re-enabled by external control, while the LM5069-2 automatically restarts with defined timing. The circuit breaker function quickly switches off the series pass device upon detection of a severe over-current condition. The Power Good (PGD) output pin indicates when the output voltage is within 1.25V of the system input voltage (VSYS). Programmable under-voltage lock-out (UVLO) and over-voltage lock-out (OVLO) circuits shut down the LM5069 when the system input voltage is outside the desired operating range. The typical configuration of a circuit card with LM5069 hot swap protection is shown in Figure 2. 20197212 FIGURE 2. LM5069 Application Power Up Sequence The VIN operating range of the LM5069 is +9V to +80V, with a transient capability to +100V. Referring to the Block Diagram and Figure 1 and Figure 3, as the voltage at VIN initially increases, the external N-channel MOSFET (Q1) is held off by an internal 230 mA pull-down current at the GATE pin. The strong pull-down current at the GATE pin prevents an inadvertent turn-on as the MOSFET’s gate-to-drain (Miller) capacitance is charged. Additionally, the TIMER pin is initially held at ground. When the VIN voltage reaches the PORIT threshold (7.6V) the insertion time begins. During the insertion time, the capacitor at the TIMER pin (CT) is charged by a 5.5 µA current source, and Q1 is held off by a 2 mA pull-down current at the GATE pin regardless of the VIN voltage. The insertion time delay allows ringing and transients at VIN to 9 settle before Q1 can be enabled. The insertion time ends when the TIMER pin voltage reaches 4.0V. CT is then quickly discharged by an internal 1.5 mA pull-down current. After the insertion time, the LM5069 control circuitry is enabled when VIN reaches the POREN threshold (8.4V). The GATE pin then switches on Q1 when VSYS exceeds the UVLO threshold (UVLO pin >2.5V). If VSYS is above the UVLO threshold at the end of the insertion time, Q1 switches on at that time. The GATE pin charge pump sources 16 µA to charge Q1’s gate capacitance. The maximum gate-to-source voltage of Q1 is limited by an internal 12V zener diode. As the voltage at the OUT pin increases, the LM5069 monitors the drain current and power dissipation of MOSFET Q1. Inrush current limiting and/or power limiting circuits actively control the current delivered to the load. During the in-rush www.national.com LM5069 limiting interval (t2 in Figure 3) an internal 85 µA fault timer current source charges CT. If Q1’s power dissipation and the input current reduce below their respective limiting thresholds before the TIMER pin reaches 4.0V the 85 µA current source is switched off, and CT is discharged by the internal 2.5 µA current sink (t3 in Figure 3). The in-rush limiting interval is complete when the voltage at the OUT pin increases to within 1.25V of the input voltage (VSYS), and the PGD pin switches high. If the TIMER pin voltage reaches 4.0V before in-rush current limiting or power limiting ceases (during t2), a fault is declared and Q1 is turned off. See the Fault Timer & Restart section for a complete description of the fault mode. 20197213 FIGURE 3. Power Up Sequence (Current Limit only) Gate Control A charge pump provides internal bias voltage above the output voltage (OUT pin) to enhance the N-Channel MOSFET’s gate. The gate-to-source voltage is limited by an internal 12V zener diode. During normal operating conditions (t3 in Figure 3) the gate of Q1 is held charged by an internal 16 µA current source to approximately 12V above OUT. If the maximum VGS rating of Q1 is less than 12V, a lower voltage external zener diode must be added between the GATE and OUT pins. The external zener diode must have a forward current rating of at least 250 mA. When the system voltage is initially applied, the GATE pin is held low by a 230 mA pull-down current. This helps prevent an inadvertent turn-on of the MOSFET through its drain-gate capacitance as the applied system voltage increases. During the insertion time (t1 in Figure 3) the GATE pin is held low by a 2 mA pull-down current. This maintains Q1 in the off- state until the end of t1, regardless of the voltage at VIN or UVLO. Following the insertion time, during t2 in Figure 3, the gate voltage of Q1 is modulated to keep the current or power dissipation level from exceeding the programmed levels. While in the current or power limiting mode the TIMER pin capacitor is charging. If the current and power limiting cease before the TIMER pin reaches 4V the TIMER pin capacitor then discharges, and the circuit enters normal operation. If the in-rush limiting condition persists such that the TIMER pin reached 4V during t2, the GATE pin is then pulled low by the 2 mA pull-down current. The GATE pin is then held low until either a power up sequence is initiated (LM5069-1), or until the end of the restart sequence (LM5069-2). See the Fault Timer & Restart section. If the system input voltage falls below the UVLO threshold, or rises above the OVLO threshold, the GATE pin is pulled low by the 2 mA pull-down current to switch off Q1. www.national.com 10 LM5069 20197214 FIGURE 4. Gate Control Current Limit The current limit threshold is reached when the voltage across the sense resistor RS (VIN to SENSE) reaches 55 mV. In the current limiting condition, the GATE voltage is controlled to limit the current in MOSFET Q1. While the current limit circuit is active, the fault timer is active as described in the Fault Timer & Restart section. If the load current falls below the current limit threshold before the end of the Fault Timeout Period, the LM5069 resumes normal operation. For proper operation, the RS resistor value should be no larger than 100 mΩ. Q1 by monitoring its drain-source voltage (SENSE to OUT), and the drain current through the sense resistor (VIN to SENSE). The product of the current and voltage is compared to the power limit threshold programmed by the resistor at the PWR pin. If the power dissipation reaches the limiting threshold, the GATE voltage is modulated to reduce the current in Q1. While the power limiting circuit is active, the fault timer is active as described in the Fault Timer & Restart section. Fault Timer & Restart When the current limit or power limit threshold is reached during turn-on or as a result of a fault condition, the gate-tosource voltage of Q1 is modulated to regulate the load current and power dissipation. When either limiting function is activated, an 85 µA fault timer current source charges the external capacitor (CT) at the TIMER pin as shown in Figure 6 (Fault Timeout Period). If the fault condition subsides during the Fault Timeout Period before the TIMER pin reaches 4.0V, the LM5069 returns to the normal operating mode and CT is discharged by the 2.5 µA current sink. If the TIMER pin reaches 4.0V during the Fault Timeout Period, Q1 is switched off by a 2 mA pull-down current at the GATE pin. The subsequent restart procedure then depends on which version of the LM5069 is in use. The LM5069-1 latches the GATE pin low at the end of the Fault Timeout Period. CT is then discharged to ground by the 2.5 µA fault current sink. The GATE pin is held low by the 2 mA pull-down current until a power up sequence is externally initiated by cycling the input voltage (VSYS), or momentarily pulling the UVLO pin below 2.5V with an open-collector or open-drain device as shown in Figure 5. The voltage at the TIMER pin must be