LM5088MHX-2

LM5088 Wide Input Range Non-Synchronous Buck Controller June 8, 2009 LM5088 Wide Input Range Non-Synchronous Buck Controller General Description The LM5088 high voltage non-synchronous buck controller features all the necessary functions to implement an efficient high voltage buck converter using a minimum number of external components. The LM5088 can be configured to operate over an ultra-wide input voltage range of 4.5V to 75V. This easy to use controller includes a level shifted gate driver capable of controlling an external N-channel buck switch. The control method is based upon peak current mode control utilizing an emulated current ramp. The use of an emulated control ramp reduces noise sensitivity of the pulse-width modulation circuit, allowing reliable control of very small duty cycles necessary in high input voltage/low output voltage applications. The LM5088 switching frequency is programmable from 50 kHz to 1 MHz. The LM5088 is available in two versions: The LM5088-1 provides a +/-5% frequency dithering function to reduce the conducted and radiated EMI, while the LM5088-2 provides a versatile restart timer for overload protection. Additional features include a low dropout bias regulator, tri-level enable input to control shutdown and standby modes, soft-start and oscillator synchronization capability. The device is available in a thermally enhanced TSSOP-16EP pin package. Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Emulated current mode control Drives external high-side N-channel MOSFET Ultra-wide input voltage range from 4.5V to 75V Low IQ Shutdown and Standby modes High duty cycle ratio feature for reduced dropout voltage Spread spectrum EMI reduction (LM5088-1) Hiccup timer for overload protection (LM5088-2) Adjustable output voltage from 1.205V with 1.5% feedback reference accuracy Wide bandwidth error amplifier Single resistor oscillator frequency setting Oscillator synchronization capability Programmable soft-start High voltage, low dropout bias regulator Thermal shutdown protection Package ■ TSSOP-16EP Simplified Application Schematic 30083901 © 2009 National Semiconductor Corporation 300839 www.national.com LM5088 Connection Diagrams 30083902 30083903 Top View (Dither version) LM5088-1 Top View (Restart version) LM5088-2 Ordering Information Order Number LM5088MH-1 LM5088MHX-1 LM5088MH-2 LM5088MHX-2 Description TSSOP-16EP, Dithering TSSOP-16EP, Dithering TSSOP-16EP, Restart TSSOP-16EP, Restart NSC Package Drawing MXA16A MXA16A MXA16A MXA16A Supplied As 73 Units in a Rail 2500 Units on Tape and Reel 73 Units in a Rail 2500 Units on Tape and Reel Pin Descriptions Pin(S) 1 2 Name VIN EN Description Input supply voltage Enable input Application Information IC supply voltage. The operating range is 4.5V to 75V If the EN pin voltage is below 0.4V the regulator will be in a low power state. If the EN pin voltage is between 0.4V and 1.2V the controller will be in standby mode. If the EN pin voltage is above 1.2V the controller will be operational. An external voltage divider can be used to set a line under voltage shutdown threshold. If the EN pin is left open, a 5µA pull-up current forces the pin to the high state and enables the controller. When SS is below the internal 1.2V reference, the SS voltage will control the error amplifier. An internal 11 µA current source charges an external capacitor to set the start-up rate of the controller. The SS pin is held low in the standby, VCC UV and thermal shutdown states. The SS pin can be used for voltage tracking by connecting this pin to a master voltage supply less than 1.2V. The applied voltage will act as the reference for the error amplifier. An external capacitor connected between this pin and the GND pin sets the ramp slope used for emulated current mode control. Recommended capacitor range 100 pF to 2000 pF. See the Applications section for selection of capacitor value. 3 SS Soft-start 4 RAMP Ramp control signal www.national.com 2 LM5088 Pin(S) 5 Name RT/SYNC Description Application Information Internal oscillator frequency The internal oscillator is programmed with a single resistor between this pin set input and and the GND pin. The recommended frequency range is 50 kHz to 1 MHz. An synchronization input external synchronization signal, which is higher in frequency than the programmed frequency, can be applied to this pin through a small coupling capacitor. The RT resistor to ground is required even when using external synchronization. Ground Ground return. Output of the internal error The loop compensation network should be connected between this pin and the amplifier FB pin. Feedback signal from the regulated output Output voltage connection Frequency Dithering ( LM5088-1 Only) This pin is connected to the inverting input of the internal error amplifier. The regulation threshold is 1.205V. Connect directly to the regulated output voltage. A capacitor connected between DITH pin and GND is charged and discharged by 27 µA current sources. As the voltage on the DITH pin ramps up and down, the oscillator frequency is modulated between -5% to +5% of the nominal frequency set by the RT resistor. Grounding the DITH pin will disable the frequency dithering mode. The RES pin is normally connected to an external capacitor that sets the timing for hiccup mode current limiting. In normal operation, a 25µA current source discharges the RES pin capacitor to ground. If cycle-by-cycle current limit threshold is exceeded during any PWM cycle, the current sink is disabled and RES capacitor is charged by an internal 50 µA current. If the RES voltage reaches 1.2V, the HG pin gate drive signal will be disabled and the RES pin capacitor will be discharged by a 1 µA current sink. Normal operation will resume when the RES pin falls below 0.2V. Low side reference for the current sense resistor. Current measurement connection for the re-circulating diode. An external sense resistor and an internal sample/hold circuit sense the diode current at the conclusion of the buck switch off-time. This current measurement provides the DC offset level for the emulated current ramp. Connect to the source terminal of the external MOSFET switch. Connect to the gate terminal of the external MOSFET switch. 6 7 8 9 10 GND COMP FB OUT DITH 10 RES Hiccup Mode Restart ( LM5088-2 Only) 11 12 CSG CS Current Sense Ground Current sense 13 14 15 SW HG BOOT Switching node High Gate Input for bootstrap capacitor An external capacitor is required between the BOOT and the SW pins to provide bias to the MOSFET gate driver. The capacitor is charged from VCC via an internal diode during the off-time of the buck switch. Output of the bias regulator VCC tracks VIN up to the regulation level (7.8V Typ). A 0.1 µF to 10 µF ceramic decoupling capacitor is required. An external voltage between 8.3V and 13V can be applied to this pin to reduce internal power dissipation. 16 VCC 3 www.national.com LM5088 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. VIN, VOUT to GND BOOT to GND SW to GND VCC to GND HG to SW EN to GND BOOT to SW 76V 90V -2V to 76V -0.3V to 16V -0.3V to BOOT +0.3V 14V -0.3V to 16V CS, CSG to GND All other inputs to GND ESD Rating Human Body Model Storage Temperature Range Junction Temperature -0.3V to 0.3V -0.3V to 7V 2 kV −65°C to + 150°C + 150°C (Note 1) 4.5V to 75V 8.3V to 13V −40°C to + 125°C Operating Ratings VIN Voltage VCC Voltage (externally supplied) Operation Junction Temperature Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are guaranteed through test, design, or statistical correlation. Typical values represent at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply: VVIN = 48V, VVCC= 8V, VEN = 5V RRT = 31.6 kΩ, No load on HG. See Note 4. Symbol VIN SUPPLY IBIAS ISTANDBY ISHUTDOWN VVCC(Reg) VVCC(Reg) VVCC(UV) VIN Operating Current VIN Standby Current VIN Shutdown Current VCC Regulation VCC Regulation VCC Sourcing Current Limit VCC Under-Voltage Hysteresis ENABLE THRESHOLDS EN Shutdown Threshold EN Shutdown Hysteresis EN Standby Threshold EN Standby Hysteresis EN Pull-up Current Source SOFT- START SS Pull-up Current Source FB to SS Offset ERROR AMPLIFIER VREF FB Reference Voltage FB Input Bias Current COMP Sink/Source Current AOL FBW THG(OFF) TON(MIN) DC Gain Unity gain bandwidth Forced HG Off-time Minimum HG On-time COMP to PWM comparator offset VVIN = 60V 185 Measured at FB Pin FB = COMP VFB = 1.2V 3 60 3 280 55 930 365 1.187 1.205 18 1.223 100 V nA mA dB MHz ns ns mV VSS = 0V VFB = 1.3V 8 11 150 13 µA mV VEN Rising VEN Falling VEN Rising VEN Falling VEN = 0V 1.1 320 400 100 1.2 120 5 1.3 480 mV mV V mV µA VFB = 1.3V VEN = 1V VEN = 0V VVCC = open VVIN = 4.5V,VVCC=open VVCC = 0 7.4 4.3 30 3.7 35 4 200 4.2 3.8 2.9 15 7.8 5.5 3.6 26 8.2 4.5 mA mA µA V V mA V mV Parameter Conditions Min Typ Max Units Electrical Characteristics VCC REGULATOR VCC Under-Voltage Lockout Threshold Positive going VVCC PWM COMPARATORS www.national.com 4 LM5088 Symbol Parameter Conditions LM5088-2 (Non-Dithering) Min Typ Max Units OSCILLATOR (RT Pin) Fnom1 Fnom2 Fmin Fmax SYNC SYNC positive threshold SYNC Pulse Width CURRENT LIMIT VCS(TH) Cycle by cycle sense voltage threshold VRAMP = 0V Cycle by Cycle Current Limit Delay Buck Switch VDS protection CURRENT LIMIT RESTART (RES Pin) Vresup Vresdown Icharge Idischarge Irampdown IRAMP1 IRAMP2 RES Threshold Upper (rising) RES Threshold Lower (falling) Charge source current Discharge sink current Discharge sink current -(post fault) RAMP Current 1 RAMP Current 2 VOUT Bias Current RAMP Output Low Voltage HIGH SIDE (HG) GATE DRIVER VOLH VOHH HG Low-state Output Voltage HG High-state Output Voltage HG Rise Time HG Fall Time IOHH IOLH Pre RDS(ON) THERMAL TSD θJC θJA Thermal Shutdown Temperature Thermal Shutdown Hysterisis Thermal Resistance Thermal Resistance Junction Temperature Rising Junction Temperature Falling Junction to Case Junction to Ambient 165 25 6 40 °C °C °C /W °C /W Peak HG Source Current Peak HG Sink Current BOOT UVLO Pre-Charge Switch ON- resistance Pre-Charge switch ON time IHG = 100 mA IHG = -100 mA, VOHH = VBOOT - VHG Cload = 1000 pF Cload = 1000 pF VHG = 0V VHG = VVCC BOOT to SW IVCC = 1 mA 115 240 12 6 1.5 2 3 72 300 215 mV mV ns ns A A V Ω ns VVIN = 60V, VOUT = 10V VVIN = 10V, VOUT = 10V VOUT = 48V VVIN = 60V, VOUT = 10V VCS >= 0.125 VCS < 0.125 VCS = 0.125 1.1 0.1 40 20 0.8 235 18 1.2 0.2 50 27 1.2 295 25 250 200 1.3 0.3 65 34 1.6 345 30 V V µA µA µA µA µA µA mV VRAMP = 2.5V VIN to SW 112 120 280 1.5 136 mV ns V 15 2.3 150 V ns Dithering Range Nominal Oscillator Frequency RRT = 31.6 kΩ RRT = 11.3 kΩ LM5088-1 (Dithering) Minimum Dither Frequency Maximum Dither Frequency Fnom-5% Fnom+5% kHz kHz 180 430 200 500 220 565 kHz kHz RAMP GENERATOR Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is intended to be functional. For guaranteed specifications and test conditions, see the Electrical Characteristics. Note 2: The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. Note 3: RAMP and COMP are output pins. As such they are not specified to have an external voltage applied. Note 4: Typical specifications represent the most likely parametric norm at 25°C operation. Note 5: For detailed information on soldering plastic MSOP packages refer to the Packaging Data Book available from National Semiconductor Corporation. 5 www.national.com LM5088 Typical Performance Characteristics Typical Application Circuit Efficiency VCC vs VIN 30083940 30083941 VVCC vs IVCC Shutdown Current 30083942 30083943 Frequency vs RRT Frequency vs VVCC 30083944 30083945 www.national.com 6 LM5088 VFB vs Temperature Forced-Off Time vs Temperature 30083946 30083947 Soft-Start vs Temperature Current-Limit vs Temperature 30083948 30083949 Frequency vs Temperature Error Amplifier Gain/Phase 30083950 30083951 7 www.national.com LM5088 Block Diagram 30083904 FIGURE 1. Block Diagram www.national.com 8 LM5088 Detailed Operation The LM5088 Wide Input Range Buck Controller features all the functions necessary to implement an efficient high voltage step-down converter using a minimum number of external components. The control method is based on peak current mode control utilizing an emulated current ramp. Peak current mode control provides inherent line voltage feed-forward, cycle-by-cycle current limiting and ease of loop compensation. The use of an emulated control ramp reduces noise sensitivity of the pulse-width modulation circuit, allowing reliable processing of very small duty cycles necessary in high input voltage applications. The operating frequency is user programmable from 50 kHz to 1 MHz. The LM5088-1 provides a ±5% frequency dithering function to reduce the conducted and radiated EMI, while the LM5088-2 provides a versatile restart timer for overload protection. Additional features include the low dropout bias regulator, tri-level enable input to control shutdown and standby modes, soft-start, and voltage tracking and oscillator synchronization capability. The device is available in a thermally enhanced TSSOP-16EP pin package. The functional block diagram and typical application schematic of the LM5088 are shown in figure 1. The LM5088 is well suited for a wide range of applications where efficient stepdown of high, unregulated input voltage is required. The LM5088’s typical applications include Telecom, Industrial and Automotive. imum voltage rating of 76V. During line or load transients, voltage ringing on the VIN pin that exceeds the absolute maximum ratings may damage the IC. Both careful PC board layout and the use of high quality bypass capacitors located close to the VIN and GND pins are essential. Line Under-Voltage Detector The LM5088 contains a dual level under-voltage lockout (UVLO) circuit. When the EN pin is below 0.4V, the controller is in a low current shutdown mode. When the EN pin is greater than 0.4V but less than 1.2V, the controller is in a standby mode. In standby mode the VCC regulator is active but the output switch is disabled and the SS pin is held low. When the EN pin exceeds 1.2V and VCC exceeds the VCC UV threshold, the SS pin and the output switch is enabled and normal operation begins. An internal 5 µA pull-up current source at the EN pin configures the controller to be fully operational if the EN pin is left open. An external VIN UVLO set-point voltage divider from VIN to GND can be used to set the minimum startup input voltage of the controller. The divider must be designed such that the voltage at the EN pin exceeds 1.2V (typ) when VIN is in the desired operating range. The internal 5 µA pull-up current source must be included in calculations of the external setpoint divider. 100 mV of hysteresis is included for both the shutdown and standby thresholds. The EN pin is internally connected to a 1 kΩ resistor and an 8V zener clamp. If the voltage at the EN pin exceeds 8V, the bias current for the EN pin will increase at the rate of 1mA/V. The voltage at the EN pin should never exceed 14V. High Voltage Low-Dropout Regulator The LM5088 contains a high voltage, low-dropout regulator that provides the VCC bias supply for the controller and the bootstrap MOSFET gate driver. The input pin (VIN) can be connected directly to an input voltage as high as 75V. The output of the VCC regulator (7.8V) is internally current limited to 30 mA. Upon power up, the regulator sources current into the capacitor connected to the VCC pin. When the voltage at the VCC pin exceeds the upper VCC UV threshold of 4.0V and the EN pin is greater than 1.2 Volts, the output (HG) is enabled and a soft-start sequence begins. The output is terminated if VCC falls below its lower UV threshold (3.8V) or the EN pin falls below 1.1V. When VIN is less than VCC regulation point of 7.8V, then the internal pass device acts as a switch. Thereby, VCC tracks VIN with a voltage drop determined by the RDS(ON) of the internal switch and operating current of the controller. The required VCC capacitor value is dependant on system startup characteristics with a minimum value no less than 0.1 µF. An auxiliary supply voltage can be applied to the VCC pin to reduce the IC power dissipation. If the auxiliary voltage is greater than 8.2V, the internal regulator will be disabled. The VCC regulator series pass transistor includes a diode between VCC and VIN that should not be forward biased in normal operation. In high voltage applications, additional care should be taken to ensure that the VIN pin does not exceed the absolute max- Oscillator and Sync Capability The LM5088 oscillator frequency is set by a single external resistor connected between the RT pin and the GND pin. The RT resistor should be located very close to the device. To set a desired oscillator frequency (fSW), the necessary value of RT resistor can be calculated from the following equation: The RT pin can also be used to synchronize the internal oscillator to an external clock. The internal oscillator is synchronized to an external clock by AC coupling a positive edge into the RT/SYNC pin. The RT/SYNC pin voltage must exceed 3V to trip the internal clock synchronization pulse detector. The free-running frequency should be set nominally 15% below the external clock frequency and the pulse width applied to the RT/SYNC pin must be less than 150ns. Synchronization to an external clock more than twice the free-running frequency can produce abnormal behavior of the pulse-width modulator. 9 www.national.com LM5088 30083905 FIGURE 2. Basic Enable Configuration Error Amplifier and PWM Comparator The internal high gain error amplifier generates an error signal proportional to the difference between the regulated output voltage and an internal precision voltage reference (1.205V). The output of the error amplifier is connected to the COMP pin allowing the user to connect loop compensation components. Generally a type II network, as illustrated in Figure 1, is sufficient. This network creates a pole at DC, a mid-band zero for phase boost and a high frequency pole for noise reduction. The PWM comparator compares the emulated current signal from the RAMP generator to the error amplifier output voltage at the COMP pin. A typical control loop gain/ phase plot is shown in performance curves section of this document. Ramp Generator The ramp signal used for the pulse width modulator in current mode control is typically derived directly from the buck switch current. This signal corresponds to the positive slope portion of the buck inductor current. Using this signal for the PWM ramp simplifies the control loop transfer function to a single pole response and provides inherent input voltage feed-forward compensation. The disadvantage of using the buck switch current signal for PWM control is the large leading edge spike due to circuit parasitics which must be filtered or blanked. Also, the current measurement may introduce significant propagation delays. The filtering time, blanking time and propagation delay limit the minimum achievable pulse width. In applications where the input voltage may be relatively large in comparison to the output voltage, controlling small pulse widths and duty cycles is necessary for regulation. The LM5088 utilizes a unique ramp generator which does not actually measure the buck switch current but rather reconstructs or emulates the signal. Emulating the inductor current provides a ramp signal that is free of leading edge spikes and measurement or filtering delays. The current reconstruction is comprised of two elements; a sample & hold DC level and an emulated current ramp. www.national.com 10 LM5088 30083907 FIGURE 3. Composition of Current Sense Signal The sample & hold DC level illustrated in Figure 3 is derived from a measurement of the re-circulating (or free-wheeling) diode current. The diode current flows through the current sense resistor connected between the CS and CSG pins. The voltage across the sense resistor is sampled and held just prior to the onset of the next conduction interval of the buck switch. The diode current sensing and sample & hold provide the DC level for the reconstructed current signal. The positive slope inductor current ramp is emulated by an external capacitor connected from the RAMP pin to GND and an internal voltage controlled current source. The ramp current source that emulates the inductor current is a function of the VIN and VOUT voltages per the following equation: IRAMP = 5 µA/V x (VIN x VOUT) + 25 µA Proper selection of the RAMP capacitor depends upon the selected value of the output inductor and the current sense resistor (RS). For proper current emulation, the DC sample & hold value and the ramp amplitude must have the same dependence on the load current. That is: oscillation is normally characterized by alternating wide and narrow pulses at the SW pin. Adding a fixed slope voltage ramp (slope compensation) to the current sense signal prevents this oscillation. The 25 µA offset current supplied by the emulated current source provides a fixed slope to the ramp signal. In some high output voltage, high duty cycles applications; additional slope compensation may be required. In these applications, a pull-up resistor may be added between the RAMP and VCC pins to increase the ramp slope compensation. A formula to configure pull-up resistor is shown in Applications Information section. Dropout Voltage Reduction The LM5088 features unique circuitry to reduce the dropout voltage. Dropout voltage is defined as the difference between the minimum input voltage to maintain regulation and the output voltage (VINmin - Vout). Dropout voltage thus determines the lowest input voltage at which the converter maintains regulation. In a buck converter, dropout voltage primarily depends upon the maximum duty cycle. The maximum duty cycle is dependant on the oscillator frequency and minimum off-time. An approximation for the dropout voltage is: Where, gm is the ramp current generator transconductance (5 µA/V) and A is the gain of the current sense amplifier (10V/ V). The RAMP capacitor should connected directly to the RAMP and GND pins of the IC. For duty cycles greater than 50%, peak current mode control circuits are subject to sub-harmonic oscillation. Sub-harmonic 11 www.national.com LM5088 Where, TOSC = 1/fSW and TOFF (max) is the forced off-time (280 ns typical, 365 ns maximum); fSW and TOSC are the oscillator frequency and oscillator period, respectively. From the above equation, it can be seen that for a given output voltage, reducing the dropout voltage requires either reducing the forced off-time or oscillator frequency (1/TOSC). The forced off-time is limited by the time required to replenish the bootstrap capacitor and time required to sample the recirculating diode current. The 365 ns forced off-time of the LM5088 controller is a good trade-off between these two requirements. Thus the LM5088 reduces dropout voltage by dynamically decreasing the operating frequency during dropout. The Dynamic Frequency Control (DFC) is achieved using a dropout monitor, which detects a dropout condition and reduces the operating frequency. The operating frequency will continue to decrease with decreasing input voltage until the frequency falls to the minimum value set by the DFC circuitry. fSW(minDFC) ≊ 1/3 x fSW(nominal) If the VIN voltage continues to fall below this point, output regulation can no longer be maintained. The oscillator frequency will revert back to the nominal operating frequency set by the RT resistor when the input voltage increases above the dropout range. DFC circuitry does not affect the PWM during normal operating conditions. 30083910 FIGURE 4. Dropout Voltage Reduction using Dynamic Frequency Control Frequency Dithering (LM5088-1 Only) Electro-Magnetic Interference (EMI) emissions are fundamentally associated with switch-mode power supplies due to sharp voltage transitions, diode reverse recovery currents and the ringing of parasitic L-C circuits. These emissions will conduct back to the power source or radiate into the environment and potentially interfering with nearby electronic systems. System designers typically use a combination of shielding, filtering and layout techniques to reduce the EMI emissions sufficiently to satisfy EMI emission standards established by regulatory bodies. In a typical fixed frequency switching converter, narrowband emissions typically peak at the switching frequency with the successive harmonics having less energy. Dithering the oscillator frequency spreads the EMI energy over a range of frequencies, thus reducing the peak levels. Dithering can also reduce the system cost by reducing the size and quantity of EMI filtering components. The LM5088-1 provides an optional frequency dithering function which is enabled by connecting a capacitor from the dither www.national.com 12 pin (DITH) to GND. Connecting the DITH pin directly to GND disables frequency dithering causing the oscillator to operate at the frequency established by the RT resistor. As shown in Figure 5, the Cdither capacitor is used to generate a triangular wave centered at 1.2V. This triangular waveform is used to manipulate the oscillator circuit such that the oscillator frequency modulates from -5% to +5% of the nominal operating frequency set by the RT resistor. The Cdither capacitor value sets the rate of the low frequency modulation i.e., a lower value Cdither capacitor will modulate the oscillator frequency from -5% to +5% at a faster rate than a higher value capacitor. For the dither circuit to work effectively the modulation rate must be much less than the oscillator frequency (fSW) , Cdither should be selected such that; LM5088 30083912 FIGURE 5. Frequency Dithering Scheme Cycle-by-Cycle Current Limit The LM5088 contains a current limit feature that protects the circuit from extended over current conditions. The emulated current signal is directly proportional to the buck switch current and is applied to the current limit comparator. If the emulated current exceeds 1.2V, the PWM cycle is terminated. The peak inductor current required to trigger the current limit comparator is given by: 30083913 FIGURE 6. Conducted Emissions Measured at the Input of a LM5088 Based Buck Converter Figure 6 shows the conducted emissions on the LM5088 evaluation board input power line. It can be seen from the above picture that, the peak emissions with non-dithering operation are centered narrowly at the operating frequency of the converter. With dithering operation, the conducted emissions are spread around the operating frequency and the maximum amplitude is reduced by approximately 10dB. (Figure 6 was captured using a Chroma DC power supply model number 62006P and an Agilent network analyzer model number 4395A). Where, A = 10V/V is the current sense amplifier gain, CRAMP is the Ramp capacitor, RS is the sense resistor, is the voltage ramp added for slope compensation and 1.2V is the reference of the current limit comparator. Since the current that charges the RAMP capacitor is proportional to VIN-VOUT, if the output is suddenly shorted, the VOUT term is zero and the RAMP charging current increases. The increased RAMP charging current will immediately reduce the PWM duty cycle.The LM5088 also includes a buck switch protection scheme. A dedicated comparator monitors 13 www.national.com LM5088 the drain to source voltage of the buck FET when it is turned ON, if the VDS exceeds 1.5V, the comparator turns off the buck FET immediately. This feature will help protect the buck FET in catastrophic conditions such as a sudden saturation of the inductor. • Overload Protection Timer (LM5088-2 Only) To further protect the external circuitry during a prolonged over current condition, the LM5088-2 provides a current limit timer to disable the switching regulator and provide a delay before restarting (hiccup mode). The number of current limit events required to trigger the restart mode is programmed by an external capacitor at the RES pin. During each PWM cycle, as shown in Figure 8, the LM5088 either sinks current from or sources current into the RES capacitor. If the emulated current ramp exceeds the 1.2V current limit threshold, the present PWM cycle is terminated and the LM5088 sources 50 µA into the RES pin capacitor during the next PWM clock cycle. If a current limit event is not detected in a given PWM cycle, the LM5088 disables the 50 µA source current and sinks 27 µA from the RES pin capacitor during the next cycle. In an overload condition, the LM5088 protects the converter with cycle-by-cycle current limiting until the voltage at RES pin reaches 1.2V. When RES reaches 1.2V, a hiccup mode sequence is initiated as follows: • The SS capacitor is fully discharged. • The RES capacitor is discharged with 1.2 µA • Once the RES capacitor reaches 0.2V, a normal soft-start sequence begins. This provides a time delay before restart. If the overload condition persists after restart, the cycle repeats. • If the overload condition no longer exists after restart, the RES pin is held at ground by the 27 µA discharge current source and normal operation resumes. The overload protection timer is very versatile and can be configured for the following modes of protection: 1. 1. Cycle-by-Cycle only: The hiccup mode can be completely disabled by connecting the RES pin to GND. In this configuration, the cycle-by-cycle protection will limit the output current indefinitely and no hiccup sequence will occur. 2. 2. Delayed Hiccup: Connecting a capacitor to the RES pin provides a programmed number of cycle-by-cycle current limit events before initiating a hiccup mode restart, as previously described. The advantage of this configuration is that a short term overload will not cause a hiccup mode restart but during extended overload conditions, the average dissipation of the power converter will be very low. 3. 3. Externally Controlled Hiccup: The RES pin can also be used as an input. By externally driving the pin to a level greater than the 1.2V hiccup threshold, the controller will be forced into the delayed restart sequence. For example, the external trigger for a delayed restart sequence could come from an over-temperature protection or an output over-voltage sensor. 30083916 FIGURE 7. Current Limit Restart Circuit www.national.com 14 LM5088 30083917 FIGURE 8. Current Limit Restart Timing Diagram Soft-Start The soft-start (SS) feature forces the output to rise linearly until it reaches the steady-state operating voltage set by the feedback resistors. The LM5088 will regulate the FB pin to the SS pin voltage or the internal 1.205V reference, which ever is lower. At the beginning of the soft-start sequence VSS = 0V and, an internal 11 µA current source gradually increases the voltage of the external soft-start capacitor (CSS). An internal amplifier clamps the SS pin voltage at 120 mV above the FB voltage. This feature provides soft-start controlled recovery with reduced output overshoot in the event that the output voltage momentarily dips out of regulation. Applications Information EXTERNAL COMPONENTS The procedure for calculating the external components is illustrated with the following design example. The Bill of Materials for this design is listed in Table 1.The circuit shown in Figure 14 and 15 is configured for the following specifications: • Output Voltage = 5V • Input Voltage = 5.5V to 55V • Maximum Load Current = 7A • Switching Frequency = 250 kHz TIMING RESISTOR The RT resistor sets the oscillator switching frequency. Higher frequencies result in smaller size components such as the inductor and filter capacitors. However, operating at higher frequencies also results in higher MOSFET and diode switching losses. Operation at 250 kHz was selected for this example as a reasonable compromise between size and efficiency. The value of RT resistor can be calculated as follows: HG Output The LM5088 provides a high current, high-side driver and associated level shift circuit to drive an external N-Channel MOSFET. The gate driver works in conjunction with an internal diode and external bootstrap capacitor. A ceramic bootstrap capacitor is recommended, and should be connected directly between the BOOT and SW pins. During the off-time of the buck switch, the bootstrap capacitor charges from VCC through an internal diode. When operating with a high PWM duty cycle, the HG output will be forced-off each cycle for 365 ns (max) to ensure that BOOT capacitor is recharged. A “precharge” circuit, comprised of a MOSFET between SW and GND, is turned ON during the forced off-time to help replenish the BOOT capacitor. The pre-charge circuit provides charge to the BOOT capacitor under light load or pre-biased load conditions when the SW voltage does not remain low during the entire off-time. The nearest standard value of 24.9Ω was chosen for RT. OUTPUT INDUCTOR The inductor value is determined based on the operating frequency, load current, ripple current and the input and output voltages. Knowing the switching frequency (fSW), maximum ripple current (IPP), maximum input voltage (VIN(max)) and the nominal output voltage (VOUT), the inductor value can be calculated as follows: Thermal Protection Internal thermal shutdown circuitry is provided to protect the integrated circuit in the event the maximum operating temperature is exceeded. When activated, typically at 165°C, the controller is forced into a low power reset state, disabling the output driver and the bias supply of the controller. The feature prevents catastrophic failures from accidental device overheating. 15 www.national.com LM5088 30083918 FIGURE 9. Inductor Current The maximum ripple current occurs at the maximum input voltage. Typically, IPP is selected between 20% and 40% of the full load current. Higher ripple current will result in a smaller inductor. However, it places more burden on the output capacitor to smooth out the ripple current to achieve low output ripple voltage. For this example 40% ripple was chosen for a smaller sized inductor. the current limit is set at 10% above the maximum load current, resulting in a RS value of 10 mΩ. The CS and CSG pins should be Kelvin connected to the current sense resistor. RAMP CAPACITOR With the inductor and sense resistor value selected, the value of the ramp capacitor (CRAMP) necessary for the emulation ramp circuit is given by: The nearest standard value of 6.8 µH will be used. To prevent saturation, the inductor must be rated for the peak current. During normal operation, the peak current occurs at maximum load current (plus maximum ripple). With properly scaled component values, the peak current is limited to VCS (TH)/RS During overload conditions. At the maximum input voltage with a shorted output, the chosen inductor must be evaluated at elevated temperature. It should be noted that the saturation current rating of inductors drops significantly at elevated temperatures. CURRENT SENSE RESISTOR The current limit value (ILIM) is set by the current sense resistor (RS). RS can be calculated by Where, L is the value of the output inductor, gm is the ramp generator transconductance (5 µA/V) and A is the current sense amplifier gain (10V/V). For the current design example, the ramp capacitor is calculated as: The next lowest standard value 270 pF was selected for CRAMP. An NPO capacitor with 5% or better tolerance is recommended. It should be noted that selecting a capacitor value lower than the calculated value will increase the slope compensation. Furthermore, selecting a ramp capacitor substantially lower or higher than the calculated value will also result in incorrect PWM operation. For VOUT > 5V, internal slope compensation provided by the LM5088 may not be adequate for certain operating conditions especially at low input voltages. A pull-up resistor may be added from VCC to RAMP the pin to increase the slope compensation. Optimal slope compensation current may be calculated from IOS = VOUT x 5 µA/V and RRAMP is given by Some ‘margin’ beyond the maximum load current is recommended for the current limit threshold. In this design example, www.national.com 16 LM5088 off. The input capacitors should be selected for RMS current rating and minimum ripple voltage. A good approximation for the ripple current is IRMS > IOUT/2. Quality ceramic capacitors with a low ESR should be selected for the input filter. To allow for capacitor tolerances and voltage rating, five 2.2 µF, 100V ceramic capacitors were selected. With ceramic capacitors, the input ripple voltage will be triangular and will peak at 50% duty cycle. Taking into account the capacitance change with DC bias a worst case input peakto-peak ripple voltage can be approximated as: 30083926 FIGURE 10. Additional Slope Compensation for VOUT > 5V OUTPUT CAPACITORS The output capacitors smooth the inductor current ripple and provide a source of charge for load transient conditions. The output capacitor selection is primarily dictated by the following specifications: 1. Steady-state output peak-peak ripple (ΔVPK-PK) 2. Output voltage deviation during transient condition (ΔVTransient) For the 5V output design example, ΔVPK-PK = 50 mV (1% of VOUT) and ΔTTransient = 100 mV (2% of VOUT) was chosen. The magnitude of output ripple primarily depends on ESR of the capacitors while load transient voltage deviation depends both on the output capacitance and ESR. When a full load is suddenly removed from the output, the output capacitor must be large enough to prevent the inductor energy to raise the output voltage above the specified maximum voltage. In other words, the output capacitor must be large enough to absorb the inductor’s maximum stored energy. Equating, the stored energy equations of both the inductor and the output capacitor it can be shown that: When the converter is connected to an input power source, a resonant circuit is formed by the line impedance and the input capacitors. This can result in an overshoot at the VIN pin and could result in VIN exceeding its absolute maximum rating. Because of those conditions, it is recommended that either an aluminum type capacitor with an ESR or increasing CIN>10 x LIN While using aluminum type capacitor care should be taken to not exceed its maximum ripple current rating. Tantalum capacitors must be avoided at the input as they are prone to shorting. VCC CAPACITOR The capacitor at the VCC pin provides noise filtering and stability for the VCC regulator. The recommended value should be no smaller than 0.1 µF, and should be a good quality, low ESR, ceramic capacitor. A value of 1 µF was selected for this design. BOOTSTRAP CAPACITOR The bootstrap capacitor between HB and SW pins supplies the gate current to charge the high-side MOSFET gate at each cycle’s turn-on as well as supplying the recovery charge for the bootstrap diode (D1).The peak current can be several amperes. The recommended value of the bootstrap capacitor is at least 0.022 µF and should be a good quality, low ESR, ceramic capacitor located close to the pins of the IC. The absolute minimum value for the bootstrap capacitor is calculated as: Evaluating, the above equation with a ΔVout of 100 mV results in an output capacitance of 475 µF. As stated earlier, the maximum peak to peak ripple primarily depends on the ESR of the output capacitor and the inductor ripple current. To satisfy the ΔVPK-PK of 50 mV with 40% inductor current ripple, the ESR should be less than 15 mΩ. In this design example a 470 µF aluminum capacitor with an ESR of 10 mΩ is paralleled with two 47 µF ceramic capacitors to further reduce the ESR. INPUT CAPACITORS The input power supply typically has large source impedance at the switching frequency. Good quality input capacitors are necessary to limit the ripple voltage at the VIN pin while supplying most of the switch current during the on-time. When the buck switch turns ON, the current into the external FET steps to the valley of the inductor current waveform at turn-on, ramps up to the peak value, and then drops to zero at turn17 Where, Qg is the high-side MOSFET gate charge and ΔVHB is the tolerable voltage droop on CHB, which is typically less than 5% of the VCC. A value of 0.1 µF was selected for this design. SOFT-START CAPACITOR The capacitor at the SS capacitor determines the soft-start time, the output voltage to reach the final regulated value. The value of CSS for a given time is determined from: For this design example, a value of 0.022 µF was chosen for a soft start time of approximately 2 ms. www.national.com LM5088 OUTPUT VOLTAGE DIVIDER RFB1 and RFB2 set the output voltage level, the ratio of these resistors can be calculated from: both current and voltage are present in the MOSFET. The switching loss can be approximated as: PSW = 0.5 x VIN x IO x (tR + tF) x fSW Where, tR and tF are the rise and fall times of the MOSFET. The rise and fall times are usually mentioned in the MOSFET datasheet or can be empirically observed on the scope. Another loss, which is associated with the buck MOSFET is the “gate-charging loss”. This loss differs from the above two losses in the sense that it is dissipated in the LM5088 and not in the MOSFET itself. Gate charging loss, PGC, results from the current driving charging the gate capacitance of the power MOSFETs and is approximated as: PGC = VCC x Qg x fSW For this example with the maximum input voltage of 55V, the Vds breakdown rating of the selected MOSFET must be greater than 55V plus any ringing across drain to source due to parasitics. In order to minimize switching time and gate drive losses, the selected MOSFET must also have low gate charge (Qg). A good choice of MOSFET for this design example is the SI7148DP which has a total gate charge of 30nC and rise and fall times of 10 ns and 12 ns respectively. DIODE SELECTION A Schottky type re-circulating diode is required for all LM5088 applications. The near ideal reverse recovery current transients and low forward voltage drop are particularly important diode characteristics for high input voltage and low output voltage applications common to LM5088. The diode switching loss is minimized in a Schottky diode because of near ideal reverse recovery. The conduction loss can be approximated by: Pdc_diode = (1 - D) x IO x VF Where, VF is the forward drop of the diode. The worst case is to assume a short circuit load condition. In this case, the diode will carry the output current almost continuously. The reverse breakdown rating should be selected for the maximum input voltage level plus some additional safety margin to withstand ringing at the SW node. For this application a 60V On Semiconductor Schottky diode (MBRB2060) with a specified forward drop of 0.6V at 7A at a junction temperature of 50°C was selected. For output loads of 5A and greater and high input voltage applications, a diode in a D2PAK package is recommended to support the worst case power dissipation SNUBBER COMPONENTS SELECTION Excessive ringing and spikes can cause erratic operation and couple spikes and noise to the output. Voltage spikes beyond the rating of the LM5088 or the re-circulating diode can damage these devices. A snubber network across the power diode reduces ringing and spikes at the switching node. Selecting the values for the snubber is best accomplished through empirical methods. First, make sure that the lead lengths for the snubber connections are very short. For the current levels typical for the LM5088, a resistor value between 3 and 10Ω should be adequate. As a rule of thumb, a snubber capacitor which is 4~5 times the Schottky diode’s junction capacitance will reduce spikes adequately. Increasing the value of the snubber capacitor will result in more damping but also results in higher losses. The resistor’s power dissipation is independent of the resistance value as the resistor dissipates the energy stored by the snubber capacitor. The resistor’s power dissipation can be approximated as: PR_SNUB = CSNUB x VINmax2 x fSW 1.62 kΩ was chosen for RFB1 in this design which results in a RFB2 value of 5.11 kΩ. A reasonable guide is to select the value of RFB1 value such that the current through the resistor (1.2V/ RFB1) is in between 1 mA and 100 µA. UVLO DIVIDER A voltage divider can be connected to the EN pin to the set the minimum startup voltage (VIN(min)) of the regulator. If this feature is required, set the value of RUV2 between 10 kΩ and 100 kΩ and then calculate RUV1 from: In this design, for a VIN(min) of 5V, RUV2 was selected to be 54.9 kΩ resulting in a RUV1value of 16.2 kΩ. it is recommended to install a capacitor parallel to RUV1 for filtering. If the EN pin is left open, the LM5088 will begin operation once the upper VCC UV threshold of 4.0V (typ) is reached. RESTART CAPACITOR (LM5008-2 only) The basic operation of the hiccup mode current limit is described in the functional description. In the LM5088-2 application example the RES pin is configured for delayed hiccup mode. Please refer to the functional description to configure this pin in alternate configurations and also refer figure 8 for the timing diagram. The delay time to initiate a hiccup cycle (t1) is programmed by the selection of RES pin capacitor. In the case of continuous cycle-by-cycle current limit detection at the CS pin, the time required for CRES to reach the 1.2V is given by The cool down time (t2) is set by the time taken to discharge the RES cap with 1.2 µA current source. This feature will reduce the input power drawn by the converter during a prolonged over current condition. In this application 500 µs of delay time was selected. The minimum value of CRES capacitor should be no less than 0.022 µF. MOSFET SELECTION Selection of the Buck MOSFET is governed by the same tradeoffs as the switching frequency. Losses in power MOSFETs can be broken down into conduction losses and switching losses. The conduction loss is given by: PDC = D x (IO2 x RDS(ON) x 1.3) Where, D is the duty cycle and IO is the maximum load current. The factor 1.3 accounts for the increase in MOSFET onresistance due to heating. Alternatively, for a more precise calculation, the factor of 1.3 can be ignored and the on-resistance of the MOSFET can be estimated using the RDS(ON) vs. Temperature curves in the MOSFET datasheet. The switching loss occurs during the brief transition period as the MOSFET turns on and off. During the transition period www.national.com 18 LM5088 ERROR AMPLIFIER COMPENSATION RCOMP, CCOMP and CHF configure the error amplifier gain characteristics to accomplish a stable voltage loop gain. One advantage of current mode control is the ability of to close the loop with only two feedback components RCOMP and CCOMP. The voltage loop gain is the product of the modulator gain and the error amplifier gain. For this example, the modulator can be treated as an ideal voltage-to-current (transconductance) converter, The DC modulator gain of the LM5088 can be modeled as: DC Gain (MOD) = RLOAD/ (A x RS) The dominant low frequency pole of the modulator is determined by the load resistance (RLOAD) and the output capacitance (COUT). The corner frequency of this pole is: For, RLOAD = 5V/7A = 0.714Ω and COUT = 500 µF (effective), then FP(MOD) = 550 Hz. DC Gain(MOD) = 0.714/ (10 x 10 mΩ) = 7.14 = 17dB For the 5V design example the modulator gain vs. frequency characteristic was measured as shown in Figure 11. 30083935 FIGURE 12. Error Amplifier Gain and Phase The overall voltage loop gain can be predicted as the sum (in dB) of the modulator gain and the error amp gain. If a network analyzer is available, the modulator gain can be measured and the error amplifier gain can be configured for the desired loop transfer function. If a network analyzer is not available, the error amplifier compensation components can be designed with the suggested guidelines. Step load transient tests can be performed to verify performance. The step load goal is minimum overshoot with a damped response. CHF can be added to the compensation network to decrease noise susceptibility of the error amplifier. The value of CHF must be sufficiently small since the addition of this capacitor adds a pole in the error amplifier transfer function. A good approximation of the location of the pole added by CHF is FP2 = FZero x CCOMP/ C HF .Using CHF is recommended to minimize coupling of any switching noise into the modulator. The value of CHF was selected as 100 pF for this design example. 30083934 FIGURE 11. Modular Gain Phase Components RCOMP and CCOMP configure the error amplifier as a type II compensation configuration. The DC gain of the amplifier is 80dB which has a pole at low frequency and a zero at FZero = 1/(2π x RCOMP x CCOMP). The error amplifier zero is set such that it cancels the modulator pole leaving a single pole response at the crossover frequency of the voltage loop. A single pole response at the crossover frequency yields a very stable loop with 90° of phase margin. For the design example, a target loop bandwidth (crossover frequency) of 15 kHz was selected. The compensation network zero (FZero) should be at least an order of magnitude lower than the target crossover frequency. This constrains the product of RCOMP and CCOMP for a desired compensation network zero 1/ (2π x RCOMP x CCOMP) to be less than 1.5 kHz. Increasing RCOMP, while proportionally decreasing CCOMP, decreases the error amp gain. For the design example CCOMP was selected to be 0.015 µF and RCOMP was selected to be 18 kΩ. These values configure the compensation network zero at 0.6 kHz. The error amp gain at frequencies greater than FZero is RCOMP /RFB2, which is approximately 3.56 (11dB). 30083936 FIGURE 13. Overall Loop Gain and Phase 19 www.national.com LM5088 PCB BOARD LAYOUT AND THERMAL CONSIDERATIONS In a buck regulator there are two loops where currents are switched very fast. The first loop starts from the input capacitors, through the buck MOSFET, to the inductor then out to the load. The second loop starts from the output capacitor ground, to the regulator PGND pins, to the current sense resistor, through the Schottky diode, to the inductor and then out to the load. Minimizing the area of these two loops reduces the stray inductance and minimizes noise which can cause erratic operation. A ground plane is recommended as a means to connect the input filter capacitors of the output filter capacitors and the PGND pin of the regulator. Connect all of the low power ground connections (CSS, RT, CRAMP) directly to the regulator GND pin. Connect the GND pin and PGND pins together through to topside copper area covering the entire underside of the device. Place several vias in this underside copper area to the ground plane. The input capacitor ground connection should be as close as possible to the current sense ground connection. In a buck converter, most of the losses can be attributed to MOSFET conduction and switching loss, re-circulating diode conduction loss, inductor DCR loss and LM5088 VIN and VCC loss. The other dissipative components in a buck con- verter produce losses but these other losses collectively account for about 2% of the total loss. Formulae to calculate all the major losses are described in their respective sections of this datasheet. The easiest method to determine the power dissipated within the LM5088 is to measure the total conversion losses (Pin-Pout), then subtract the power losses in the Schottky diode, MOSFET, output inductor and snubber resistor. When operating at 7A of output current and at 55V, the power dissipation of the LM5088 is approximately 850 mW. The junction to ambient thermal resistance of the LM5088 mounted in the evaluation board is approximately 40°C with no airflow. At 25°C ambient temperature and no airflow, the predicted junction temperature will be 25+40*0.9 = 61°C. The LM5088 has an exposed thermal pad to aid in power dissipation. Adding several vias under the device will greatly reduce the controller junction temperature. The junction to ambient thermal resistance will vary with application. The most significant variables are the area of copper in the PC board; the number of vias under the IC exposed pad and the amount of forced air cooling. The integrity of solder connection from the IC exposed pad to the PC board is critical. Excessive voids will greatly diminish the thermal dissipation capacity. www.national.com 20 LM5088 21 30083937 FIGURE 14. LM5088-1 Application Schematic www.national.com LM5088 www.national.com 30083938 22 FIGURE 15. LM5088-2 Application Schematic LM5088 Bill of Materials for LM5088-1 and LM5088-2 Evaluation Boards Part C1,C2,C3,C4, C5 C6,C19 C7 C8,C11 C9 C13 C10 C12 C15 C17,C18 C20 C16 C21 C14 (LM5088-1) C14 (LM5088-2) D1 D2 L1 Q1 R1 R2 R3 R4 R5 R6 R7 R8 R9 Value 2.2µF 0.1µF 1µF 100pF 270pF 0.1µF 0.022µF 0.015µF 470µF 47µF 1000pF NU NU 0.1µF 0.022µF Schottky Diode NU 6.8µH MOSFET 54.9k Ohm 16.2k Ohm 24.9k Ohm 18.2k Ohm 10m Ohm 5.1 Ohm 10 Ohm 5.11k Ohm 1.62k Ohm Package C1210 C0805 C0603 C0603 C0603 C0603 C0603 C0603 0.327x0.327x0. 303 C1210 C0805 0.327x0.327x0. 303 C0603 C0603 C0603 D2PAK SOD123 HC9 series SO-8 R0805 R0603 R0603 R0603 R0815 R2512 R0805 R0603 R0603 Manufacturer Murata TDK Corporation Murata AVX Corporation Murata Murata Murata Murata Nippon-Chemicon Murata Murata NU NU Murata Murata On Semi NU Coiltronics Vishay IR Rohm Rohm Rohm Rohm Susumu Co Ltd Panasonic - ECG Rohm Rohm Rohm Manufacturer Part Number Description GRM32ER72A225KA35L C2012X7R2A104K GRM188R71C105KA12D 06031A101FAT2A GRM1885C2A271JA01D GRM188R72A104KA35D GRM188R71C223KA01D GRM188R71H153KA01D APXF6R3ARA471MH80G GRM32ER61A476KE20L GRM2195C2A102JA01D NU NU GRM188R72A104KA35D GRM188R71C223KA01D MBRB2060CT NU HC9-6R8-R SI7148DP-T1-E3 MCR10EZHF5492 MCR03EZPFX1622 MCR03EZPFX2492 MCR03EZPFX1822 RL3720WT-R010-F ERJ-1TRQF5R1U MCR10EZHF10R0 MCR03EZPFX5111 MCR03EZPFX1621 CAP CER 2.2µF 100V X7R 1210 CAP CER .10µF 100V X7R 10% 0805 CAP CER 1µF 16V X7R 0603 CAP CERM 100pF 1% 100V NP0 0603 CAP CER 270pF 100V 5% C0G 0603 CAP CER .1µF 100V X7R 0603 CAP CER 22000pF 16V 10% X7R 0603 CAP CER 15000pF 50V 10% X7R 0603 CAP 470UF 6.3V ELECT POLY SMD CAP CER 47µF 10V X5R 1210 CAP CER 1000pF 100V 5% C0G 0805 NU NU CAP CER .1µF 100V X7R 0603 CAP CER 22000pF 16V 10% X7R 0603 Schottky Rectifiers 20 Amp 60 Volt NU INDUCTOR HIGH CURRENT 6.8µH MOSFET N-CH 75V 28A PWR PAK SO8 RES 54.9 kΩ 1/8W 1% 0805 SMD RES 16.2 kΩ 1/10W 1% 0603 SMD RES 24.9 kΩ 1/10W 1% 0603 SMD RES 18.2 kΩ 1/10W 1% 0603 SMD RES .01Ω 1W 1% 0815 SMD RES 5.1Ω 1W 1% 2512 SMD RES 10.0Ω 1/8W 1% 0805 SMD RES 5.11 kΩ 1/10W 1% 0603 SMD RES 1.62 kΩ 1/10W 1% 0603 SMD 23 www.national.com LM5088 Part R10 J1,J2,J3,J4 TP1,TP2 U1 Value NU Terminal_Turret Slotted test point PWM IC Package R0603 Manufacturer NU Keystone Keystone Manufacturer Part Number Description NU 1509 1040 LM5088-1/LM5088-2 NU Terminal, Turret Terminal test point slotted ECM Buck Controller TSSOP16_EP National www.national.com 24 LM5088 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead TSSOP-EP Package NS Package Number MXA16A 25 www.national.com LM5088 Wide Input Range Non-Synchronous Buck Controller Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Amplifiers Audio Clock and Timing Data Converters Interface LVDS Power Management Switching Regulators LDOs LED Lighting Voltage Reference PowerWise® Solutions Temperature Sensors Wireless (PLL/VCO) www.national.com/amplifiers www.national.com/audio www.national.com/timing www.national.com/adc www.national.com/interface www.national.com/lvds www.national.com/power www.national.com/switchers www.national.com/ldo www.national.com/led www.national.com/vref www.national.com/powerwise WEBENCH® Tools App Notes Reference Designs Samples Eval Boards Packaging Green Compliance Distributors Quality and Reliability Feedback/Support Design Made Easy Solutions Mil/Aero PowerWise® Design University Design Support www.national.com/webench www.national.com/appnotes www.national.com/refdesigns www.national.com/samples www.national.com/evalboards www.national.com/packaging www.national.com/quality/green www.national.com/contacts www.national.com/quality www.national.com/feedback www.national.com/easy www.national.com/solutions www.national.com/milaero www.national.com/solarmagic www.national.com/training Serial Digital Interface (SDI) www.national.com/sdi www.national.com/wireless www.national.com/tempsensors SolarMagic™ THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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