LM5101SDX

LM5100/LM5101 High Voltage High Side and Low Side Gate Driver January 2004 LM5100/LM5101 High Voltage High Side and Low Side Gate Driver General Description The LM5100/LM5101 High Voltage Gate Drivers are designed to drive both the high side and the low side N-Channel MOSFETs in a synchronous buck or a half bridge configuration. The floating high-side driver is capable of operating with supply voltages up to 100V. The outputs are independently controlled with CMOS input thresholds (LM5100) or TTL input thresholds (LM5101). An integrated high voltage diode is provided to charge the high side gate drive bootstrap capacitor. A robust level shifter operates at high speed while consuming low power and providing clean level transitions from the control logic to the high side gate driver. Under-voltage lockout is provided on both the low side and the high side power rails. This device is available in the standard SOIC-8 pin and the LLP-10 pin packages. n n n n n n n Bootstrap supply voltage range up to 118V DC Fast propagation times (25 ns typical) Drives 1000 pF load with 15 ns rise and fall times Excellent propagation delay matching (3 ns typical) Supply rail under-voltage lockouts Low power consumption Pin compatible with HIP2100/HIP2101 Typical Applications n n n n n Current Fed push-pull converters Half and Full Bridge power converters Synchronous buck converters Two switch forward power converters Forward with Active Clamp converters Features n Drives both a high side and low side N-Channel MOSFET n Independent high and low driver logic inputs (TTL for LM5101 or CMOS for LM5100) Package n SOIC-8 n LLP-10 (4 mm x 4 mm) Simplified Block Diagram 20088803 FIGURE 1. © 2004 National Semiconductor Corporation DS200888 www.national.com LM5100/LM5101 Connection Diagrams 20088801 20088802 FIGURE 2. Ordering Information Ordering Number LM5100/01M LM5100/01MX LM5100/01SD LM5100/01SDX Package Type SOIC-8 SOIC-8 LLP-10 LLP-10 NSC Package Drawing M08A M08A SDC10A SDC10A Supplied As Shipped in anti static rails 2500 shipped as Tape & Reel 1000 shipped as Tape & Reel 4500 shipped as Tape & Reel Pin Description Pin # SO-8 1 2 LLP-10 1 2 Name VDD HB Description Positive gate drive supply High side gate driver bootstrap rail High side gate driver output High side MOSFET source connection High side driver control input Application Information Locally decouple to VSS using low ESR/ESL capacitor located as close to IC as possible. Connect the positive terminal of the bootstrap capacitor to HB and the negative terminal to HS. The Bootstrap capacitor should be place as close to IC as possible. Connect to gate of high side MOSFET with a short low inductance path. Connect to bootstrap capacitor negative terminal and the source of the high side MOSFET. The LM5100 inputs have CMOS type thresholds. The LM5101 inputs have TTL type thresholds. Unused inputs should be tied to ground and not left open. The LM5100 inputs have CMOS type thresholds. The LM5101 inputs have TTL type thresholds. Unused inputs should be tied to ground and not left open. All signals are referenced to this ground. Connect to the gate of the low side MOSFET with a short low inductance path. 3 4 5 3 4 7 HO HS HI 6 8 LI Low side driver control input 7 8 9 10 VSS LO Ground return Low side gate driver output Note: For LLP-10 package, it is recommended that the exposed pad on the bottom of the LM5100 / LM5101 be soldered to ground plane on the PC board, and the ground plane should extend out from beneath the IC to help dissipate the heat. Pins 5 and 6 have no connection. www.national.com 2 LM5100/LM5101 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. VDD to VSS VHB to VHS LI or HI Inputs LO Output HO Output VHS to VSS VHB to VSS Junction Temperature −0.3V to +18V −0.3V to +18V −0.3V to VDD +0.3V −0.3V to VDD +0.3V VHS −0.3V to VHB +0.3V −1V to +100V 118V +150˚C Storage Temperature Range ESD Rating HBM (Note 2) −55˚C to +150˚C 2 kV Recommended Operating Conditions VDD HS HB HS Slew Rate Junction Temperature +9V to +14V −1V to 100V VHS +8V to VHS +14V < 50 V/ns −40˚C to +125˚C Electrical Characteristics Specifications in standard typeface are for TJ = +25˚C, and those in boldface type apply over the full operating junction temperature range. Unless otherwise specified, VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO . Symbol SUPPLY CURRENTS IDD IDDO IHB IHBO IHBS IHBSO VIL VIL VIH VIH VIHYS RI VDDR VDDH VHBR VHBH VDL VDH RD VOLL VOHL IOHL IOLL VOLH VDD Quiescent Current VDD Operating Current Total HB Quiescent Current Total HB Operating Current HB to VSS Current, Quiescent HB to VSS Current, Operating Low Level Input Voltage Threshold (LM5100) Low Level Input Voltage Threshold (LM5101) High Level Input Voltage Threshold (LM5100) High Level Input Voltage Threshold (LM5101) Input Voltage Hysteresis (LM5100) Input Pulldown Resistance VDD Rising Threshold VDD Threshold Hysteresis HB Rising Threshold HB Threshold Hysteresis Low-Current Forward Voltage High-Current Forward Voltage Dynamic Resistance Low-Level Output Voltage High-Level Output Voltage Peak Pullup Current Peak Pulldown Current Low-Level Output Voltage IVDD-HB = 100 µA IVDD-HB = 100 mA IVDD-HB = 100 mA ILO = 100 mA ILO = −100 mA, VOHL = VDD–VLO VLO = 0V VLO = 12V IHO = 100 mA 3 Parameter Conditions LI = HI = 0V (LM5100) LI = HI = 0V (LM5101) f = 500 kHz LI = HI = 0V f = 500 kHz VHS = VHB = 100V f = 500 kHz Min Typ 0.1 0.25 1.5 0.06 1.3 0.05 0.08 Max 0.2 0.4 3 0.2 3 10 Units mA mA mA mA µA mA INPUT PINS 3 0.8 5.0 1.8 5.5 1.8 0.5 100 6.0 5.7 200 6.9 0.5 6.6 0.4 0.6 0.85 0.8 0.23 0.35 1.6 1.8 0.23 0.4 0.9 1.1 1.5 0.4 0.55 7.1 500 7.4 8 2.2 V V V V V kΩ V V V V V V Ω V V A A V www.national.com UNDER VOLTAGE PROTECTION BOOT STRAP DIODE LO GATE DRIVER HO GATE DRIVER LM5100/LM5101 Electrical Characteristics Symbol HO GATE DRIVER VOHH IOHH IOLH θJA High-Level Output Voltage Peak Pullup Current Peak Pulldown Current Junction to Ambient Parameter (Continued) Specifications in standard typeface are for TJ = +25˚C, and those in boldface type apply over the full operating junction temperature range. Unless otherwise specified, VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO . Conditions IHO = −100 mA VOHH = VHB–VHO VHO = 0V VHO = 12V SOIC-8 LLP-10 (Note 3) Min Typ Max Units 0.35 1.6 1.8 170 40 0.55 V A A THERMAL RESISTANCE ˚C/W Switching Characteristics Specifications in standard typeface are for TJ = +25˚C, and those in boldface type apply over the full operating junction temperature range. Unless otherwise specified, VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO. Symbol LM5100 tLPHL tHPHL tLPLH tHPLH tMON tMOFF tRC, tFC tR, tF tPW tBS LM5101 tLPHL tHPHL tLPLH tHPLH tMON tMOFF tRC, tFC tR, tF Lower Turn-Off Propagation Delay (LI Falling to LO Falling) Upper Turn-Off Propagation Delay (HI Falling to HO Falling) Lower Turn-On Propagation Delay (LI Rising to LO Rising) Upper Turn-On Propagation Delay (HI Rising to HO Rising) Delay Matching: Lower Turn-On and Upper Turn-Off Delay Matching: Lower Turn-Off and Upper Turn-On Either Output Rise/Fall Time Either Output Rise/Fall Time (3V to 9V) CL = 1000 pF CL = 0.1 µF 25 25 25 25 2 2 15 0.6 56 56 56 56 10 10 ns ns ns ns ns ns ns µs Lower Turn-Off Propagation Delay (LI Falling to LO Falling) Upper Turn-Off Propagation Delay (HI Falling to HO Falling) Lower Turn-On Propagation Delay (LI Rising to LO Rising) Upper Turn-On Propagation Delay (HI Rising to HO Rising) Delay Matching: Lower Turn-On and Upper Turn-Off Delay Matching: Lower Turn-Off and Upper Turn-On Either Output Rise/Fall Time Either Output Rise/Fall Time (3V to 9V) Minimum Input Pulse Width that Changes the Output Bootstrap Diode Turn-Off Time IF = 20 mA, IR = 200 mA CL = 1000 pF CL = 0.1 µF 24 24 24 24 2 2 15 0.6 50 50 45 45 45 45 10 10 ns ns ns ns ns ns ns µs ns ns Parameter Conditions Min Typ Max Units www.national.com 4 LM5100/LM5101 Switching Characteristics Symbol LM5101 tPW tBS Minimum Input Pulse Width that Changes the Output Bootstrap Diode Turn-Off Time Parameter (Continued) Specifications in standard typeface are for TJ = +25˚C, and those in boldface type apply over the full operating junction temperature range. Unless otherwise specified, VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO. Conditions Min Typ Max Units 50 IF = 20 mA, IR = 200 mA 50 ns ns Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical Characteristics tables. Note 2: The human body model is a 100 pF capacitor discharged through a 1.5kΩ resistor into each pin. 2 kV for all pins except Pin 2, Pin 3 and Pin 4 which are rated at 500V. Note 3: 4 layer board with Cu finished thickness 1.5/1/1/1.5 oz. Maximum die size used. 5x body length of Cu trace on PCB top. 50 x 50mm ground and power planes embedded in PCB. See Application Note AN-1187. Note 4: Min and Max limits are 100% production tested at 25˚C. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate National’s Average Outgoing Quality Level (AOQL). Note 5: The θJA is not a given constant for the package and depends on the printed circuit board design and the operating environment. 5 www.national.com LM5100/LM5101 Typical performance Characteristics LM5100 IDD vs Frequency LM5101 IDD vs Frequency 20088809 20088810 LM5100/LM5101 Operating Current vs Temperature IHB vs Frequency 20088811 20088814 Quiescent Current vs Supply Voltage LM5100/LM5101 Quiescent Current vs Temperature 20088818 20088819 www.national.com 6 LM5100/LM5101 Typical performance Characteristics Undervoltage Rising Thresholds vs Temperature (Continued) LM5100 Undervoltage Threshold Hysteresis vs Temperature 20088822 20088817 Bootstrap Diode Forward Voltage HO and LO Peak Output Current vs Output Voltage 20088816 20088815 LO and HO Gate Drive — High Level Output Voltage vs Temperature LO and HO Gate Drive — Low Level Output Voltage vs Temperature 20088820 20088821 7 www.national.com LM5100/LM5101 Typical performance Characteristics LM5100 Propagation Delay vs Temperature (Continued) LM5101 Propagation Delay vs Temperature 20088812 20088813 www.national.com 8 LM5100/LM5101 Timing Diagram 20088804 FIGURE 3. Layout Considerations The optimum performance of high and low side gate drivers cannot be achieved without taking due considerations during circuit board layout. Following points are emphasized. 1. A low ESR / ESL capacitor must be connected close to the IC, and between VDD and VSS pins and between HB and HS pins to support high peak currents being drawn from VDD during turn-on of the external MOSFET. 2. To prevent large voltage transients at the drain of the top MOSFET, a low ESR electrolytic capacitor must be connected between MOSFET drain and ground (VSS). 3. In order to avoid large negative transients on the switch node (HS) pin, the parasitic inductances in the source of top MOSFET and in the drain of the bottom MOSFET (synchronous rectifier) must be minimized. 4. Grounging Considerations: a) The first priority in designing grounding connections is to confine the high peak currents from charging and discharging the MOSFET gate in a minimal physical area. This will decrease the loop inductance and minimize noise issues on the gate terminal of the MOSFET. The MOSFETs should be placed as close as possible to the gate driver. b) The second high current path includes the bootstrap capacitor, the bootstrap diode, the local ground referenced bypass capacitor and low side MOSFET body diode. The bootstrap capacitor is recharged on the cycle-by-cycle basis through the bootstrap diode from the ground referenced VDD bypass capacitor. The recharging occurs in a short time interval and involves high peak current. Minimizing this loop length and area on the circuit board is important to ensure reliable operation. losses are related to the switching frequency (f), output load capacitance on LO and HO (CL), and supply voltage (VDD) and can be roughly calculated as: PDGATES = 2 • f • CL • VDD2 There are some additional losses in the gate drivers due to the internal CMOS stages used to buffer the LO and HO outputs. The following plot shows the measured gate driver power dissipation versus frequency and load capacitance. At higher frequencies and load capacitance values, the power dissipation is dominated by the power losses driving the output loads and agrees well with the above equation. This plot can be used to approximate the power losses due to the gate drivers. Gate Driver Power Dissipation (LO + HO) VCC = 12V, Neglecting Diode Losses 20088805 Power Dissipation Considerations The total IC power dissipation is the sum of the gate driver losses and the bootstrap diode losses. The gate driver 9 www.national.com LM5100/LM5101 Power Dissipation Considerations (Continued) The bootstrap diode power loss is the sum of the forward bias power loss that occurs while charging the bootstrap capacitor and the reverse bias power loss that occurs during reverse recovery. Since each of these events happens once per cycle, the diode power loss is proportional to frequency. Larger capacitive loads require more current to recharge the bootstrap capacitor resulting in more losses. Higher input voltages (VIN) to the half bridge result in higher reverse recovery losses. The following plot was generated based on calculations and lab measurements of the diode recovery time and current under several operating conditions. This can be useful for approximating the diode power dissipation. Diode Power Dissipation VIN = 80V Diode Power Dissipation VIN = 40V 20088807 The total IC power dissipation can be estimated from the previous plots by summing the gate drive losses with the bootstrap diode losses for the intended application. Because the diode losses can be significant, an external diode placed in parallel (refer to Figure 4) with the internal bootstrap diode can be helpful in removing power from the IC. For this to be effective, the external diode must be placed close to the IC to minimize series inductance and have a significantly lower forward voltage drop than the internal diode. 20088806 20088808 FIGURE 4. LM5101 Driving MOSFETs Connected in Half-Bridge Configuration www.national.com 10 LM5100/LM5101 Physical Dimensions inches (millimeters) unless otherwise noted Controlling dimension is inch. Values in [ ] are millimeters. Notes: Unless otherwise specified. 1. 2. 3. Standard lead finish to be 200 microinches/5.08 micrometers minimum lead/tin (solder) on copper. Dimension does not include mold flash. Reference JEDEC registration MS-012, Variation AA, dated May 1990. SOIC-8 Outline Drawing NS Package Number M08A 11 www.national.com LM5100/LM5101 High Voltage High Side and Low Side Gate Driver Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Notes: Unless otherwise specified. 1. For solder thickness and composition, see “Solder Information” in the packaging section of the National Semiconductor web page (www.national.com). 2. Maximum allowable metal burr on lead tips at the package edges is 76 microns. 3. No JEDEC registration as of May 2003. LLP-10 Outline Drawing NS Package Number SDC10A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 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