LM5104M

LM5104 High Voltage Half-Bridge Gate Driver with Adaptive Delay January 2004 LM5104 High Voltage Half-Bridge Gate Driver with Adaptive Delay General Description The LM5104 High Voltage Gate Driver is designed to drive both the high side and the low side N-Channel MOSFETs in a synchronous buck configuration. The floating high-side driver is capable of working with supply voltages up to 100V. The high side and low side gate drivers are controlled from a single input. Each change in state is controlled in an adaptive manner to prevent shoot-through issues. In addition to the adaptive transition timing, an additional delay time can be added, proportional to an external setting resistor. An integrated high voltage diode is provided to charge high side gate drive bootstrap capacitor. A robust level shifter operates at high speed while consuming low power and providing clean level transitions from the control logic to the high side gate driver. Under-voltage lockout is provided on both the low side and the high side power rails. This device is available in the standard SOIC-8 pin and the LLP-10 pin packages. n Adaptive rising and falling edges with programmable additional delay n Single input control n Bootstrap supply voltage range up to 118V DC n Fast turn-off propagation delay (25 ns typical) n Drives 1000 pF loads with 15 ns rise and fall times n Supply rail under-voltage lockout Typical Applications n n n n Current Fed Push-Pull Power Converters High Voltage Buck Regulators Active Clamp Forward Power Converters Half and Full Bridge Converters Package n SOIC-8 n LLP-10 (4 mm x 4 mm) Features n Drives both a high side and low side N-channel MOSFET Simplified Block Diagram 20089003 FIGURE 1. © 2004 National Semiconductor Corporation DS200890 www.national.com LM5104 Connection Diagram 20089001 8-Lead SOIC See NS Package Number M08A 20089002 10-Lead LLP See NS Package Number SDC10A FIGURE 2. Ordering Information Ordering Number LM5104M LM5104MX LM5104SD LM5104SDX Package Type SOIC-8 SOIC-8 LLP-10 LLP-10 NSC Package Drawing M08A M08A SDC10A SDC10A Supplied As Shipped with Anti-Static Rails 2500 shipped as Tape & Reel 1000 shipped as Tape & Reel 4500 shipped as Tape & Reel Pin Descriptions Pin SOIC-8 1 2 LLP-10 1 2 Name VDD HB Description Application Information Positive gate drive supply Locally decouple to VSS using low ESR/ESL capacitor, located as close to IC as possible. High side gate driver bootstrap rail High side gate driver output High side MOSFET source connection Deadtime programming pin Control input Ground return Low side gate driver output Connect the positive terminal of bootstrap capacitor to the HB pin and connect negative terminal to HS. The Bootstrap capacitor should be placed as close to IC as possible. Connect to gate of high side MOSFET with short low inductance path. Connect to bootstrap capacitor negative terminal and source of high side MOSFET. Resistor from RT to ground programs the deadtime between high and low side transitions.The resistor should be located close to the IC to minimize noise coupling from adjacent traces. Logic 1 equals High Side ON and Low Side OFF. Logic 0 equals High Side OFF and Low Side ON. All signals are referenced to this ground. Connect to the gate of the low side MOSFET with a short low inductance path. 3 4 5 3 4 7 HO HS RT 6 7 8 8 9 10 IN VSS LO Note: For LLP-10 package, it is recommended that the exposed pad on the bottom of the LM5100 / LM5101 be soldered to ground plane on the PC board, and the ground plane should extend out from beneath the IC to help dissipate the heat. Pins 5 and 6 have no connection. www.national.com 2 LM5104 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. VDD to VSS VHB to VHS IN to VSS LO Output HO Output VHS to VSS VHB to VSS RT to VSS Junction Temperature –0.3V to +18V –0.3V to +18V –0.3V to VDD + 0.3V –0.3V to VDD + 0.3V VHS – 0.3V to VHB + 0.3V −1V to +100V 118V –0.3V to 5V +150˚C Storage Temperature Range ESD Rating HBM (Note 2) –55˚C to +150˚C 2 kV Recommended Operating Conditions VDD HS HB HS Slew Rate Junction Temperature +9V to +14V –1V to 100V VHS + 8V to VHS + 14V < 50V/ns –40˚C to +125˚C Electrical Characteristics Specifications in standard typeface are for TJ = +25˚C, and those in boldface type apply over the full operating junction temperature range. Unless otherwise specified, VDD = VHB = 12V, VSS = VHS = 0V, RT = 100kΩ. No Load on LO or HO. Symbol SUPPLY CURRENTS IDD IDDO IHB IHBO IHBS IHBSO INPUT PINS VIL VIH RI VRT IRT TD1 TD2 VDDR VDDH VHBR VHBH VDL VDH RD VOLL VOHL IOHL IOLL VOLH Low Level Input Voltage Threshold High Level Input Voltage Threshold Input Pulldown Resistance Nominal Voltage at RT RT Pin Current Limit Delay Timer, RT = 10 kΩ Delay Timer, RT = 100 kΩ VDD Rising Threshold VDD Threshold Hysteresis HB Rising Threshold HB Threshold Hysteresis Low-Current Forward Voltage High-Current Forward Voltage Dynamic Resistance Low-Level Output Voltage High-Level Output Voltage Peak Pullup Current Peak Pulldown Current Low-Level Output Voltage IVDD-HB = 100 µA IVDD-HB = 100 mA IVDD-HB = 100 mA ILO = 100 mA ILO = –100 mA VOHL = VDD – VLO VLO = 0V VLO = 12V IHO = 100 mA 5.7 RT = 0V 100 2.7 0.75 58 140 6.0 0.8 1.8 1.8 200 3 1.5 90 200 6.9 0.5 6.6 0.4 0.60 0.85 0.8 0.25 0.35 1.6 1.8 0.25 0.4 0.9 1.1 1.5 0.4 0.55 7.1 2.2 500 3.3 2.25 130 270 7.4 V V kΩ V mA ns ns V V V V V V Ω V V A A V VDD Quiescent Current VDD Operating Current Total HB Quiescent Current Total HB Operating Current HB to VSS Current, Quiescent HB to VSS Current, Operating LI = HI = 0V f = 500 kHz LI = HI = 0V f = 500 kHz VHS = VHB = 100V f = 500 kHz 0.4 1.9 0.06 1.3 0.05 0.08 0.6 3 0.2 3 10 mA mA mA mA µA mA Parameter Conditions Min Typ Max Units TIME DELAY CONTROLS UNDER VOLTAGE PROTECTION BOOT STRAP DIODE LO GATE DRIVER HO GATE DRIVER 3 www.national.com LM5104 Electrical Characteristics Specifications in standard typeface are for TJ = +25˚C, and those in boldface type apply over the full operating junction temperature range. Unless otherwise specified, VDD = VHB = 12V, VSS = VHS = 0V, RT = 100kΩ. No Load on LO or HO. (Continued) Symbol VOHH IOHH IOLH θJA Parameter High-Level Output Voltage Peak Pullup Current Peak Pulldown Current Junction to Ambient Conditions IHO = –100 mA, VOHH = VHB – VHO VHO = 0V VHO = 12V SOIC-8 LLP-10 (Note 3) Min Typ 0.35 1.6 1.8 170 40 Max 0.55 Units V A A ˚C/W THERMAL RESISTANCE Switching Characteristics Specifications in standard typeface are for TJ = +25˚C, and those in boldface type apply over the full operating junction temperature range. Unless otherwise specified, VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO . Symbol tLPHL tHPHL tRC, tFC t R , tF tBS Parameter Lower Turn-Off Propagation Delay (IN Rising to LO Falling) Upper Turn-Off Propagation Delay (IN Falling to HO Falling) Either Output Rise/Fall Time Either Output Rise/Fall Time (3V to 9V) Bootstrap Diode Turn-Off Time CL = 1000 pF CL = 0.1 µF IF = 20 mA, IR = 200 mA Conditions Min Typ 25 25 15 0.6 50 Max 56 56 Units ns ns ns µs ns Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical Characteristics tables. Note 2: The human body model is a 100 pF capacitor discharged through a 1.5kΩ resistor into each pin. 2 kV for all pins except Pin 2, Pin 3 and Pin 4 which are rated at 500V. Note 3: 4 layer board with Cu finished thickness 1.5/1/1/1.5 oz. Maximum die size used. 5x body length of Cu trace on PCB top. 50 x 50mm ground and power planes embedded in PCB. See Application Note AN-1187. Note 4: Min and Max limits are 100% production tested at 25˚C. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate National’s Average Outgoing Quality Level (AOQL). Note 5: The θJA is not a given constant for the package and depends on the printed circuit board design and the operating environment. www.national.com 4 LM5104 Typical Performance Characteristics IDD vs Frequency Operating Current vs Temperature 20089010 20089011 Quiescent Current vs Supply Voltage Quiescent Current vs Temperature 20089012 20089013 IHB vs Frequency HO & LO Peak Output Current vs Output Voltage 20089017 20089018 5 www.national.com LM5104 Typical Performance Characteristics Diode Forward Voltage (Continued) Undervoltage Threshold Hysteresis vs Temperature 20089016 20089019 Undervoltage Rising Threshold vs Temperature LO & HO Gate Drive — High Level Output Voltage vs Temperature 20089020 20089021 LO & HO Gate Drive — Low Level Output Voltage vs Temperature Turn Off Propagation Delay vs Temperature 20089022 20089023 www.national.com 6 LM5104 Typical Performance Characteristics Timing vs Temperature RT = 10K (Continued) Timing vs Temperature RT = 100K 20089015 20089024 Turn On Delay vs RT Resistor Value 20089014 7 www.national.com LM5104 LM5104 Waveforms 20089005 FIGURE 3. Application Timing Waveforms Operational Description ADAPTIVE SHOOT-THROUGH PROTECTION LM5104 is a high voltage, high speed dual output driver designed to drive top and bottom MOSFET’s connected in synchronous buck or half-bridge configuration, from one externally provided PWM signal. LM5104 features adaptive delay to prevent shoot-through current through top and bottom MOSFETs during switching transitions. Referring to the timing diagram Figure 3, the rising edge of the PWM input (IN) turns off the bottom MOSFET (LO) after a short propagation delay (tP). An adaptive circuit in the LM5104 monitors the bottom gate voltage (LO) and triggers a programmable delay generator when the LO pin falls below an internally set threshold (≈ Vdd/2). The gate drive of the upper MOSFET (HO) is disabled until the deadtime expires. The upper gate www.national.com 8 is enabled after the TIMER delay (tP+TRT) , and the upper MOSFET turns-on. The additional delay of the timer prevents lower and upper MOSFETs from conducting simultaneously, thereby preventing shoot-through. A falling transition on the PWM signal (IN) initiates the turnoff of the upper MOSFET and turn-on of the lower MOSFET. A short propagation delay (tP) is encountered before the upper gate voltage begins to fall. Again, the adaptive shootthrough circuitry and the programmable deadtime TIMER delays the lower gate turn-on time. The upper MOSFET gate voltage is monitored and the deadtime delay generator is triggered when the upper MOSFET gate voltage with respect to ground drops below an internally set threshold (≈ Vdd/2). The lower gate drive is momentarily disabled by the timer and turns on the lower MOSFET after the deadtime delay expires (tP+TRT). LM5104 Operational Description (Continued) The RT pin is biased at 3V and current limited to 1mA. It is designed to accommodate a resistor between 5K and 100K, resulting in an effective dead-time proportional to RT and ranging from 90ns to 200ns. RT values below 5K will saturate the timer and are not recommended. Startup and UVLO Both top and bottom drivers include under-voltage lockout (UVLO) protection circuitry which monitors the supply voltage (VDD) and bootstrap capacitor voltage (VHB – VHS) independently. The UVLO circuit inhibits each driver until sufficient supply voltage is available to turn-on the external MOSFETs, and the built-in hysteresis prevents chattering during supply voltage transitions. When the supply voltage is applied to VDD pin of LM5104, the top and bottom gates are held low until VDD exceeds UVLO threshold, typically about 6.9V. Any UVLO condition on the bootstrap capacitor will disable only the high side output (HO). LAYOUT CONSIDERATIONS The optimum performance of high and low side gate drivers cannot be achieved without taking due considerations during circuit board layout. Following points are emphasized. 1. A low ESR/ESL capacitor must be connected close to the IC, and between VDD and VSS pins and between HB and HS pins to support high peak currents being drawn from VDD during turn-on of the external MOSFET. 2. To prevent large voltage transients at the drain of the top MOSFET, a low ESR electrolytic capacitor must be connected between MOSFET drain and ground (VSS). 3. In order to avoid large negative transients on the switch node (HS) pin, the parasitic inductances in the source of top MOSFET and in the drain of the bottom MOSFET (synchronous rectifier) must be minimized. 4. Grounding considerations: a) The first priority in designing grounding connections is to confine the high peak currents from charging and discharging the MOSFET gate in a minimal physical area. This will decrease the loop inductance and minimize noise issues on the gate terminal of the MOSFET. The MOSFETs should be placed as close as possible to the gate driver. b) The second high current path includes the bootstrap capacitor, the bootstrap diode, the local ground referenced bypass capacitor and low side MOSFET body diode. The bootstrap capacitor is recharged on the cycle-by-cycle basis through the bootstrap diode from the ground referenced VDD bypass capacitor. The recharging occurs in a short time interval and involves high peak current. Minimizing this loop length and area on the circuit board is important to ensure reliable operation. 5. The resistor on the RT pin must be placed very close to the IC and seperated from high current paths to avoid noise coupling to the time delay generator which could disrupt timer operation. PDGATES = 2 • f • CL • VDD2 There are some additional losses in the gate drivers due to the internal CMOS stages used to buffer the LO and HO outputs. The following plot shows the measured gate driver power dissipation versus frequency and load capacitance. At higher frequencies and load capacitance values, the power dissipation is dominated by the power losses driving the output loads and agrees well with the above equation. This plot can be used to approximate the power losses due to the gate drivers. Gate Driver Power Dissipation (LO + HO) VCC = 12V, Neglecting Diode Losses 20089006 The bootstrap diode power loss is the sum of the forward bias power loss that occurs while charging the bootstrap capacitor and the reverse bias power loss that occurs during reverse recovery. Since each of these events happens once per cycle, the diode power loss is proportional to frequency. Larger capacitive loads require more current to recharge the bootstrap capacitor resulting in more losses. Higher input voltages (VIN) to the half bridge result in higher reverse recovery losses. The following plot was generated based on calculations and lab measurements of the diode recovery time and current under several operating conditions. This can be useful for approximating the diode power dissipation. Diode Power Dissipation VIN = 80V POWER DISSIPATION CONSIDERATIONS The total IC power dissipation is the sum of the gate driver losses and the bootstrap diode losses. The gate driver losses are related to the switching frequency (f), output load capacitance on LO and HO (CL), and supply voltage (VDD) and can be roughly calculated as: 20089007 9 www.national.com LM5104 Startup and UVLO (Continued) Diode Power Dissipation VIN = 40V The total IC power dissipation can be estimated from the above plots by summing the gate drive losses with the bootstrap diode losses for the intended application. Because the diode losses can be significant, an external diode placed in parallel with the internal bootstrap diode (refer to Figure 4) can be helpful in removing power from the IC. For this to be effective, the external diode must be placed close to the IC to minimize series inductance and have a significantly lower forward voltage drop than the internal diode. 20089008 20089009 FIGURE 4. LM5104 Driving MOSFETs Connected in Synchronous Buck Configuration www.national.com 10 LM5104 Physical Dimensions inches (millimeters) unless otherwise noted Notes: Unless otherwise specified 1. 2. 3. Standard lead finish to be 200 microinches/5.00 micrometers minimum tin/lead (solder) on copper. Pin 1 identification to have half of full circle option. No JEDEC registration as of Feb. 2000. LLP-10 Outline Drawing NS Package Number SDC10A 11 www.national.com LM5104 High Voltage Half-Bridge Gate Driver with Adaptive Delay Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Notes: Unless otherwise specified 1. 2. 3. For solder thickness and composition, see “Solder Information” in the packaging section of the National Semiconductor web page (www.national.com). Maximum allowable metal burr on lead tips at the package edges is 76 microns. No JEDEC registration as of May 2003. SOIC-8 Outline Drawing NS Package Number M08A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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