LM5109AMA

LM5109A High Voltage 1A Peak Half Bridge Gate Driver April 2006 LM5109A High Voltage 1A Peak Half Bridge Gate Driver General Description The LM5109A is a cost effective, high voltage gate driver designed to drive both the high-side and the low-side N-Channel MOSFETs in a synchronous buck or a half bridge configuration. The floating high-side driver is capable of working with rail voltages up to 90V. The outputs are independently controlled with TTL compatible input thresholds. The robust level shift technology operates at high speed while consuming low power and providing clean level transitions from the control input logic to the high-side gate driver. Under-voltage lockout is provided on both the lowside and the high-side power rails. The device is available in the SOIC-8 and the thermally enhanced LLP-8 packages. n n n n n n n Bootstrap supply voltage to 108V DC Fast propagation times (30 ns typical) Drives 1000 pF load with 15ns rise and fall times Excellent propagation delay matching (2 ns typical) Supply rail under-voltage lockout Low power consumption Pin compatible with ISL6700 Typical Applications n n n n Current Fed push-pull converters Half and Full Bridge power converters Solid state motor drives Two switch forward power converters Features n Drives both a high-side and low-side N-Channel MOSFET n 1A peak output current (1.0A sink / 1.0A source) n Independent TTL compatible inputs Package n SOIC-8 n LLP-8 (4 mm x 4 mm) Simplified Block Diagram 20170201 FIGURE 1. © 2006 National Semiconductor Corporation DS201702 www.national.com LM5109A Connection Diagrams 20170202 20170203 FIGURE 2. Ordering Information Ordering Number LM5109AMA LM5109AMAX LM5109ASD LM5109ASDX Package Type SOIC-8 SOIC-8 LLP-8 LLP-8 NSC Package Drawing M08A M08A SDC08A SDC08A Supplied As 95 Units in anti static rails 2500 Units on Tape & Reel 1000 Units on Tape & Reel 4500 Units on Tape & Reel Pin Descriptions Pin # SO-8 1 2 3 4 5 6 7 8 LLP-8 1 2 3 4 5 6 7 8 Name VDD HI LI VSS LO HS HO HB Description Positive gate drive supply High side control input Low side control input Ground reference Low side gate driver output High side source connection High side gate driver output High side gate driver positive supply rail Application Information Locally decouple to VSS using low ESR/ESL capacitor located as close to IC as possible. The HI input is compatible with TTL input thresholds. Unused HI input should be tied to ground and not left open The LI input is compatible with TTL input thresholds. Unused LI input should be tied to ground and not left open. All signals are referenced to this ground. Connect to the gate of the low-side N-MOS device. Connect to the negative terminal of the bootstrap capacitor and to the source of the high-side N-MOS device. Connect to the gate of the high-side N-MOS device. Connect the positive terminal of the bootstrap capacitor to HB and the negative terminal of the bootstrap capacitor to HS. The bootstrap capacitor should be placed as close to IC as possible. Note: For LLP-8 package it is recommended that the exposed pad on the bottom of the package be soldered to ground plane on the PCB and the ground plane should extend out from underneath the package to improve heat dissipation. www.national.com 2 LM5109A Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. VDD to VSS HB to HS LI or HI to VSS LO to VSS HO to VSS HS to VSS (Note 6) HB to VSS Junction Temperature -0.3V to 18V −0.3V to 18V −0.3V to VDD +0.3V −0.3V to VDD +0.3V VHS −0.3V to VHB +0.3V −5V to 90V 108V -40˚C to +150˚C Storage Temperature Range ESD Rating HBM (Note 2) −55˚C to +150˚C 1.5 kV Recommended Operating Conditions VDD HS (Note 6) HB HS Slew Rate Junction Temperature 8V to 14V −1V to 90V VHS +8V to VHS +14V < 50 V/ns −40˚C to +125˚C Electrical Characteristics Specifications in standard typeface are for TJ = +25˚C, and those in boldface type apply over the full operating junction temperature range. Unless otherwise specified, VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO (Note 4). Symbol SUPPLY CURRENTS IDD IDDO IHB IHBO IHBS IHBSO VIL VIH RI VDDR VDDH VHBR VHBH VOLL VOHL IOHL IOLL VOLH VOHH IOHH IOLH θJA VDD Quiescent Current VDD Operating Current Total HB Quiescent Current Total HB Operating Current HB to VSS Current, Quiescent HB to VSS Current, Operating Low Level Input Voltage Threshold High Level Input Voltage Threshold Input Pulldown Resistance VDD Rising Threshold VDD Threshold Hysteresis HB Rising Threshold HB Threshold Hysteresis Low-Level Output Voltage High-Level Output Voltage Peak Pullup Current Peak Pulldown Current Low-Level Output Voltage High-Level Output Voltage Peak Pullup Current Peak Pulldown Current Junction to Ambient ILO = 100 mA VOHL = VLO – VSS ILO = −100 mA, VOHL = VDD– VLO VLO = 0V VLO = 12V IHO = 100 mA VOLH = VHO– VHS IHO = −100 mA VOHH = VHB– VHO VHO = 0V VHO = 12V SOIC-8 (Note 3), (Note 5) LLP-8 (Note 3), (Note 5) VHBR = VHB - VHS 5.7 VDDR = VDD - VSS 100 6.0 LI = HI = 0V f = 500 kHz LI = HI = 0V f = 500 kHz VHS = VHB = 90V f = 500 kHz 0.8 0.3 1.8 0.06 1.4 0.1 0.5 1.8 1.8 200 6.7 0.5 6.6 0.4 7.1 2.2 500 7.4 0.6 2.9 0.2 2.8 10 mA mA mA mA µA mA V V kΩ V V V V Parameter Conditions Min Typ Max Units INPUT PINS LI and HI UNDER VOLTAGE PROTECTION LO GATE DRIVER 0.38 0.72 1.0 1.0 0.65 1.20 V V A A HO GATE DRIVER 0.38 0.72 1.0 1.0 160 40 0.65 1.20 V V A A THERMAL RESISTANCE ˚C/W 3 www.national.com LM5109A Switching Characteristics Specifications in standard typeface are for TJ = +25˚C, and those in boldface type apply over the full operating junction temperature range. Unless otherwise specified, VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO. Symbol LM5109A tLPHL tHPHL tLPLH tHPLH tMON tMOFF tRC, tFC tPW Lower Turn-Off Propagation Delay (LI Falling to LO Falling) Upper Turn-Off Propagation Delay (HI Falling to HO Falling) Lower Turn-On Propagation Delay (LI Rising to LO Rising) Upper Turn-On Propagation Delay (HI Rising to HO Rising) Delay Matching: Lower Turn-On and Upper Turn-Off Delay Matching: Lower Turn-Off and Upper Turn-On Either Output Rise/Fall Time Minimum Input Pulse Width that Changes the Output CL = 1000 pF 30 30 32 32 2 2 15 50 56 56 56 56 15 15 ns ns ns ns ns ns ns ns Parameter Conditions Min Typ Max Units Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical Characteristics tables. Note 2: The human body model is a 100 pF capacitor discharged through a 1.5kΩ resistor into each pin. Note 3: 4 layer board with Cu finished thickness 1.5/1/1/1.5 oz. Maximum die size used. 5x body length of Cu trace on PCB top. 50 x 50mm ground and power planes embedded in PCB. See Application Note AN-1187. Note 4: Min and Max limits are 100% production tested at 25˚C. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate National’s Average Outgoing Quality Level (AOQL). Note 5: The θJA is not a constant for the package and depends on the printed circuit board design and the operating conditions. Note 6: In the application the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS voltage will generally not exceed -1V. However in some applications, board resistance and inductance may result in the HS node exceeding this stated voltage transiently. If negative transients occur on HS, the HS voltage must never be more negative than VDD - 15V. For example, if VDD = 10V, the negative transients at HS must not exceed -5V. www.national.com 4 LM5109A Typical Performance Characteristics VDD Operating Current vs Frequency HB Operating Current vs Frequency 20170204 20170205 Operating Current vs Temperature Quiescent Current vs Temperature 20170206 20170207 Quiescent Current vs Voltage Propagation Delay vs Temperature 20170208 20170209 5 www.national.com LM5109A Typical Performance Characteristics LO and HO High Level Output Voltage vs Temperature (Continued) LO and HO Low Level Output Voltage vs Temperature 20170210 20170211 Undervoltage Rising Thresholds vs Temperature Undervoltage Hysteresis vs Temperature 20170214 20170215 Input Thresholds vs Temperature Input Thresholds vs Supply Voltage 20170216 20170217 www.national.com 6 LM5109A Timing Diagram 20170218 FIGURE 3. Layout Considerations Optimum performance of high and low-side gate drivers cannot be achieved without taking due considerations during circuit board layout. The following points are emphasized: 1. Low ESR / ESL capacitors must be connected close to the IC between VDD and VSS pins and between HB and HS pins to support high peak currents being drawn from VDD and HB during the turn-on of the external MOSFETs. 2. To prevent large voltage transients at the drain of the top MOSFET, a low ESR electrolytic capacitor and a good quality ceramic capacitor must be connected between the MOSFET drain and ground (VSS). 3. In order to avoid large negative transients on the switch node (HS) pin, the parasitic inductances between the source of the top MOSFET and the drain of the bottom MOSFET (synchronous rectifier) must be minimized. 4. Grounding considerations: a) The first priority in designing grounding connections is to confine the high peak currents that charge and discharge the MOSFET gates to a minimal physical area. This will decrease the loop inductance and minimize noise issues on the gate terminals of the MOSFETs. The gate driver should be placed as close as possible to the MOSFETs. b) The second consideration is the high current path that includes the bootstrap capacitor, the bootstrap diode, the local ground referenced bypass capacitor, and the low-side MOSFET body diode. The bootstrap capacitor is recharged on a cycle-by-cycle basis through the bootstrap diode from the ground referenced VDD bypass capacitor. The recharging occurs in a short time interval and involves high peak current. Minimizing this loop length and area on the circuit board is important to ensure reliable operation. HS Transient Voltages Below Ground The HS node will always be clamped by the body diode of the lower external FET. In some situations, board resistances and inductances can cause the HS node to transiently swing several volts below ground. The HS node can swing below ground provided: 1. HS must always be at a lower potential than HO. Pulling HO more than -0.3V below HS can activate parasitic transistors resulting in excessive current flow from the HB supply, possibly resulting in damage to the IC. The same relationship is true with LO and VSS. If necessary, a Schottky diode can be placed externally between HO and HS or LO and GND to protect the IC from this type of transient. The diode must be placed as close to the IC pins as possible in order to be effective. 2. HB to HS operating voltage should be 15V or less. Hence, if the HS pin transient voltage is -5V, VDD should be ideally limited to 10V to keep HB to HS below 15V. 3. Low ESR bypass capacitors from HB to HS and from VDD to VSS are essential for proper operation. The capacitor should be located at the leads of the IC to minimize series inductance. The peak currents from LO and HO can be quite large. Any series inductances with the bypass capacitor will cause voltage ringing at the leads of the IC which must be avoided for reliable operation. 7 www.national.com LM5109A Physical Dimensions inches (millimeters) unless otherwise noted Controlling dimension is inch. Values in [ ] are millimeters. Notes: Unless otherwise specified. 1. 2. 3. Standard lead finish to be 200 microinches/5.08 micrometers minimum lead/tin (solder) on copper. Dimension does not include mold flash. Reference JEDEC registration MS-012, Variation AA, dated May 1990. SOIC-8 Outline Drawing NS Package Number M08A www.national.com 8 LM5109A High Voltage 1A Peak Half Bridge Gate Driver Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Notes: Unless otherwise specified. 1. 2. 3. For solder thickness and composition, see “Solder Information” in the packaging section of the National Semiconductor web page (www.national.com). Maximum allowable metal burr on lead tips at the package edges is 76 microns. No JEDEC registration as of May 2003. LLP-8 Outline Drawing NS Package Number SDC08A National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. BANNED SUBSTANCE COMPLIANCE National Semiconductor manufactures products and uses packing materials that meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2. Leadfree products are RoHS compliant. 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