LM5112-SDX

LM5112 Tiny 7A MOSFET Gate Driver October 2004 LM5112 Tiny 7A MOSFET Gate Driver General Description The LM5112 MOSFET gate driver provides high peak gate drive current in the tiny LLP-6 package (SOT23 equivalent footprint) with improved package power dissipation required for high frequency operation. The compound output driver stage includes MOS and bipolar transistors operating in parallel that together sink more than 7A peak from capacitive loads. Combining the unique characteristics of MOS and bipolar devices reduces drive current variation with voltage and temperature. Under-voltage lockout protection is provided to prevent damage to the MOSFET due to insufficient gate turn-on voltage. The LM5112 provides both inverting and non-inverting inputs to satisfy requirements for inverting and non-inverting gate drive with a single device type. Features n Compound CMOS and bipolar outputs reduce output current variation n 7A sink/3A source current n Fast propagation times (25 ns typical) n Fast rise and fall times (14 ns/12 ns rise/fall with 2 nF load) n Inverting and non-inverting inputs provide either configuration with a single device n Supply rail under-voltage lockout protection n Dedicated input ground (IN_REF) for split supply or single supply operation n Power Enhanced 6-pin LLP package (3.0mm x 3.0mm) n Output swings from VCC to VEE which can be negative relative to input ground Block Diagram 20066801 Block Diagram of LM5112 © 2004 National Semiconductor Corporation DS200668 www.national.com LM5112 Pin Configurations 20066802 LLP-6 Ordering Information Order Number LM5112-SD LM5112-SDX Package Type LLP-6 LLP-6 NSC Package Drawing SDE06A SDE06A Supplied As 1000 shipped in Tape & Reel 4500 shipped in Tape & Reel Pin Description Pin 1 2 IN VEE Name Description Non-inverting input pin Power ground for driver outputs Application Information TTL compatible thresholds. Pull up to VCC when not used Connect to either power ground or a negative gate drive supply for positive or negative voltage swing Locally decouple to VEE. The decoupling capacitor should be located close to the chip Capable of sourcing 3A and sinking 7A. Voltage swing of this output is from VEE to VCC Connect to power ground (VEE) for standard positive only output voltage swing. Connect to system logic ground when VEE is connected to a negative gate drive supply TTL compatible thresholds. Connect to IN_REF when not used Internally bonded to the die substrate. Connect to VEE ground pin for low thermal impedance 3 4 5 VCC OUT IN_REF Positive Supply voltage input Gate drive output Ground reference for control inputs 6 --- INB Exposed Pad Inverting input pin Exposed Pad, underside of LLP package www.national.com 2 LM5112 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. VCC to VEE VCC to IN_REF IN/INB to IN_REF −0.3V to 15V −0.3V to 15V −0.3V to 15V IN_REF to VEE Storage Temperature Range Maximum Junction Temperature Operating Junction Temperature ESD Rating −0.3V to 5V −55˚C to +150˚C +150˚C −40˚C+125˚C 2kV Electrical Characteristics put, unless otherwise specified. SYMBOL SUPPLY VCC UVLO VCCH ICC VIH VIL HYS IIL IIH ROH ROL ISOURCE ISINK VCC operating range PARAMETER TJ = −40˚C to +125˚C, VCC = 12V, INB = IN_REF = VEE = 0V, No Load on outCONDITIONS VCC – IN_REF and VCC - VEE VCC – IN_REF MIN 3.5 2.4 3.0 230 1.0 1.75 0.8 IN = INB = 0V IN = INB = VCC IOUT = -10mA IOUT = 10mA OUT = VCC/2, 200ns pulsed current OUT = VCC/2, 200ns pulsed current CLOAD = 2 nF, see Figure 3 -1 -1 1.35 400 0.1 0.1 30 1.4 3 7 1 1 50 2.5 2.0 2.3 TYP MAX 14 3.5 UNITS V V mV mA V V mV µA µA Ω Ω A A VCC Under-voltage lockout (rising) VCC Under-voltage hysteresis VCC supply current Logic High Logic low Input Hysteresis Input Current Low Input Current High Output Resistance High Output Resistance Low Peak Source Current Peak Sink Current CONTROL INPUTS OUTPUT DRIVER SWITCHING CHARACTERISTICS td1 Propagation Delay Time Low to High, IN/ INB rising ( IN to OUT) Propagation Delay Time High to Low, IN / INB falling (IN to OUT) Rise time Fall time AEC –Q100, METHOD 004 25 40 ns td2 CLOAD = 2 nF, see Figure 3 25 40 ns tr tf CLOAD = 2 nF , see Figure 3 CLOAD = 2 nF , see Figure 3 TJ = 150˚C 14 12 500 ns ns mA LATCHUP PROTECTION Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is intended to be functional. For guaranteed specifications and test conditions, see the Electrical Characteristics. 3 www.national.com LM5112 Timing Waveforms 20066804 20066805 (a) FIGURE 1. (a) Inverting, (b) Non-Inverting (b) www.national.com 4 LM5112 Typical Performance Characteristics Supply Current vs Frequency Supply Current vs Capacitive Load 20066808 20066807 Rise and Fall Time vs Supply Voltage Rise and Fall Time vs Temperature 20066809 20066810 Rise and Fall Time vs Capacitive Load Delay Time vs Supply Voltage 20066811 20066812 5 www.national.com LM5112 Typical Performance Characteristics Delay Time vs Temperature (Continued) RDSON vs Supply Voltage 20066813 20066814 UVLO Thresholds and Hysteresis vs Temperature Peak Current vs Supply Voltage 20066816 20066815 www.national.com 6 LM5112 20066803 FIGURE 2. Simplified Application Block Diagram Detailed Operating Description The LM5112 is a high speed , high peak current (7A) single channel MOSFET driver. The high peak output current of the LM5112 will switch power MOSFET’s on and off with short rise and fall times, thereby reducing switching losses considerably. The LM5112 includes both inverting and noninverting inputs that give the user flexibility to drive the MOSFET with either active low or active high logic signals. The driver output stage consists of a compound structure with MOS and bipolar transistor operating in parallel to optimize current capability over a wide output voltage and operating temperature range. The bipolar device provides high peak current at the critical Miller plateau region of the MOSFET VGS , while the MOS device provides rail-to-rail output swing. The totem pole output drives the MOSFET gate between the gate drive supply voltage VCC and the power ground potential at the VEE pin. The control inputs of the driver are high impedance CMOS buffers with TTL compatible threshold voltages. The negative supply of the input buffer is connected to the input ground pin IN_REF. An internal level shifting circuit connects the logic input buffers to the totem pole output drivers. The level shift circuit and separate input/output ground pins provide the option of single supply or split supply configurations. 7 When driving the MOSFET gates from a single positive supply, the IN_REF and VEE pins are both connected to the power ground. The isolated input and output stage grounds provide the capability to drive the MOSFET to a negative VGS voltage for a more robust and reliable off state. In split supply configuration, the IN_REF pin is connected to the ground of the controller which drives the LM5112 inputs. The VEE pin is connected to a negative bias supply that can range from the IN_REF potential to as low as 14 V below the Vcc gate drive supply. For reliable operation, the maximum voltage difference between VCC and IN_REF or between VCC and VEE is 14V. The minimum recommended operating voltage between Vcc and IN_REF is 3.5V. An Under Voltage Lock Out (UVLO) circuit is included in the LM5112 which senses the voltage difference between VCC and the input ground pin, IN_REF. When the VCC to IN_REF voltage difference falls below 2.8V the driver is disabled and the output pin is held in the low state. The UVLO hysteresis prevents chattering during brown-out conditions; the driver will resume normal operation when the VCC to IN_REF differential voltage exceeds 3.0V. www.national.com LM5112 Layout Considerations Attention must be given to board layout when using LM5112. Some important considerations include: 1. A Low ESR/ESL capacitor must be connected close to the IC and between the VCC and VEE pins to support high peak currents being drawn from VCC during turn-on of the MOSFET. Proper grounding is crucial. The driver needs a very low impedance path for current return to ground avoiding inductive loops. Two paths for returning current to ground are a) between LM5112 IN_REF pin and the ground of the circuit that controls the driver inputs and b) between LM5112 VEE pin and the source of the power MOSFET being driven. Both paths should be as short as possible to reduce inductance and be as wide as possible to reduce resistance. These ground paths should be distinctly separate to avoid coupling between the high current output paths and the logic signals that drive the LM5112. With rise and fall times in the range of 10 to 30nsec, care is required to minimize the lengths of current carrying conductors to reduce their inductance and EMI from the high di/dt transients generated when driving large capacitive loads. If either channel is not being used, the respective input pin (IN or INB) should be connected to either VEE or VCC to avoid spurious output signals. 2. 20066806 FIGURE 3. The schematic above shows a conceptual diagram of the LM5112 output and MOSFET load. Q1 and Q2 are the switches within the gate driver. Rg is the gate resistance of the external MOSFET, and Cin is the equivalent gate capacitance of the MOSFET. The equivalent gate capacitance is a difficult parameter to measure as it is the combination of Cgs (gate to source capacitance) and Cgd (gate to drain capacitance). The Cgd is not a constant and varies with the drain voltage. The better way of quantifying gate capacitance is the gate charge Qg in coloumbs. Qg combines the charge required by Cgs and Cgd for a given gate drive voltage Vgate. The gate resistance Rg is usually very small and losses in it can be neglected. The total power dissipated in the MOSFET driver due to gate charge is approximated by: PDRIVER = VGATE x QG x FSW Where FSW = switching frequency of the MOSFET. For example, consider the MOSFET MTD6N15 whose gate charge specified as 30 nC for VGATE = 12V. Therefore, the power dissipation in the driver due to charging and discharging of MOSFET gate capacitances at switching frequency of 300 kHz and VGATE of 12V is equal to PDRIVER = 12V x 30 nC x 300 kHz = 0.108W. In addition to the above gate charge power dissipation, transient power is dissipated in the driver during output transitions. When either output of the LM5112 changes state, current will flow from VCC to VEE for a very brief interval of time through the output totem-pole N and P channel MOSFETs. The final component of power dissipation in the driver is the power associated with the quiescent bias current consumed by the driver input stage and Under-voltage lockout sections. Characterization of the LM5112 provides accurate estimates of the transient and quiescent power dissipation components. At 300 kHz switching frequency and 30 nC load used in the example, the transient power will be 8 mW. The 1 mA nominal quiescent current and 12V VGATE supply produce a 12 mW typical quiescent power. Therefore the total power dissipation PD = 0.118 + 0.008 + 0.012 = 0.138W. We know that the junction temperature is given by TJ = PD x θJA + TA Or the rise in temperature is given by TRISE = TJ − TA = PD x θJA 3. Thermal Performance INTRODUCTION The primary goal of the thermal management is to maintain the integrated circuit (IC) junction temperature (Tj) below a specified limit to ensure reliable long term operation. The maximum TJ of IC components should be estimated in worst case operating conditions. The junction temperature can be calculated based on the power dissipated on the IC and the junction to ambient thermal resistance θJA for the IC package in the application board and environment. The θJA is not a given constant for the package and depends on the PCB design and the operating environment. DRIVE POWER REQUIREMENT CALCULATIONS IN LM5112 LM5112 is a single low side MOSFET driver capable of sourcing / sinking 3A / 7A peak currents for short intervals to drive a MOSFET without exceeding package power dissipation limits. High peak currents are required to switch the MOSFET gate very quickly for operation at high frequencies. www.national.com 8 LM5112 Thermal Performance (Continued) For LLP-6 package, the integrated circuit die is attached to leadframe die pad which is soldered directly to the printed circuit board. This substantially decreases the junction to ambient thermal resistance (θJA). By providing suitable means of heat dispersion from the IC to the ambient through exposed copper pad, which can readily dissipate heat to the surroundings, θJA as low as 40˚C / Watt is achievable with the package. The resulting Trise for the driver example above is thereby reduced to just 5.5 degrees. Therefore TRISE is equal to TRISE = 0.138 x 40 = 5.5˚C 9 www.national.com LM5112 Tiny 7A MOSFET Gate Driver Physical Dimensions unless otherwise noted inches (millimeters) 6-Lead LLP Package NS Package Number SDE06A National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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