LM5642MHX

LM5642/LM5642X High Voltage, Dual Synchronous Buck Converter with Oscillator Synchronization June 2007 LM5642/LM5642X High Voltage, Dual Synchronous Buck Converter with Oscillator Synchronization General Description The LM5642 series consists of two current mode synchronous buck regulator controllers operating 180° out of phase with each other at a normal switching frequency of 200kHz for the LM5642 and at 375kHz for the LM5642X. Out of phase operation reduces the input RMS ripple current, thereby significantly reducing the required input capacitance. The switching frequency can be synchronized to an external clock between 150kHz and 250kHz for the LM5642 and between 200 kHz and 500 kHz for the LM5642X. The two switching regulator outputs can also be paralleled to operate as a dual-phase, single output regulator. The output of each channel can be independently adjusted from 1.3V to 90% of Vin. An internal 5V rail is also available externally for driving bootstrap circuitry. Current-mode feedback control assures excellent line and load regulation and wide loop bandwidth for excellent response to fast load transients. Current is sensed across either the Vds of the top FET or across an external current-sense resistor connected in series with the drain of the top FET. The LM5642 features analog soft-start circuitry that is independent of the output load and output capacitance making the soft-start behavior more predictable and controllable than traditional soft-start circuits. Over-voltage protection is available for both outputs. A UVDelay pin is also available to allow delayed shut off time for the IC during an output under-voltage event. Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Two synchronous buck regulators 180° out of phase operation 200kHz fixed nominal frequency: LM5642 375kHz fixed nominal frequency: LM5642X Synchronizable switching frequency from 150kHz to 250kHz for the LM5642 and 200kHz to 500kHz for the LM5642X 4.5V to 36V input range 50µA Shutdown current Adjustable output from 1.3V to 90% of Vin 0.04% (typical) line and load regulation accuracy Current mode control with or without a sense resistor Independent enable/soft-start pins allow simple sequential startup configuration. Configurable for single output parallel operation. (See Figure 2) Adjustable cycle-by-cycle current limit Input under-voltage lockout Output over-voltage latch protection Output under-voltage protection with delay Thermal shutdown Self discharge of output capacitors when the regulator is OFF TSSOP and eTSSOP (Exposed PAD) packages Applications ■ ■ ■ ■ ■ ■ Embedded Computer Systems Navigation Systems Telecom Systems Set-Top Boxes WebPAD Point Of Load Power Architectures Typical Application Circuit 20060101 © 2007 National Semiconductor Corporation 200601 www.national.com LM5642/LM5642X Connection Diagrams 20060102 20060194 Top View Top View Ordering Information Order Number LM5642MH LM5642MHX LM5642MTC LM5642MTCX 28-Lead TSSOP MTC28 Package Type 28-Lead eTSSOP NSC Package Drawing MXA28A Supplied As 48 units per Rail 2500 Units on Tape and Reel 48 units per Rail 2500 Units on Tape and Reel UV_DELAY (Pin 6): A capacitor from this pin to ground sets the delay time for UVP. The capacitor is charged from a 5µA current source. When UV_DELAY charges to 2.3V (typical), the system immediately latches off. Connecting this pin to ground will disable the output under-voltage protection. VLIN5 (Pin 7): The output of an internal 5V LDO regulator derived from VIN. It supplies the internal bias for the chip and powers the bootstrap circuitry for gate drive. Bypass this pin to signal ground with a minimum of 4.7µF ceramic capacitor. SGND (Pin 8): The ground connection for the signal-level circuitry. It should be connected to the ground rail of the system. ON/SS1 (Pin 9): Channel 1 enable pin. This pin is internally pulled up to one diode drop above VLIN5. Pulling this pin below 1.2V (open-collector type) turns off Channel 1. If both ON/ SS1 and ON/SS2 pins are pulled below 1.2V, the whole chip goes into shut down mode. Adding a capacitor to this pin provides a soft-start feature that minimizes inrush current and output voltage overshoot. ON/SS2 (Pin 10): Channel 2 enable pin. See the description for Pin 9, ON/SS1. May be connected to ON/SS1 for simultaneous startup or for parallel operation. FB2 (Pin 11): Feedback input for channel 2. Connect to VOUT through a voltage divider to set the Channel 2 output voltage. COMP2 (Pin 12): Compensation pin for Channel 2. This is the output of the internal transconductance error amplifier. The loop compensation network should be connected between this pin and the signal ground SGND (Pin 8). ILIM2 (Pin 13): Current limit threshold setting for Channel 2. See ILIM1 (Pin 2). KS2 (Pin 14): The positive (+) Kelvin sense for the internal current sense amplifier of Channel 2. See KS1 (Pin 1). Pin Descriptions KS1 (Pin 1): The positive (+) Kelvin sense for the internal current sense amplifier of Channel 1. Use a separate trace to connect this pin to the current-sense point. It should be connected to VIN as close as possible to the current-sense resistor. When no current-sense resistor is used, connect as close as possible to the drain node of the upper MOSFET. ILIM1 (Pin 2): Current limit threshold setting for Channel 1. It sinks a constant current of 9.9µA, which is converted to a voltage across a resistor connected from this pin to VIN. The voltage across the resistor is compared with either the VDS of the top MOSFET or the voltage across the external current sense resistor to determine if an over-current condition has occurred in Channel 1. COMP1 (Pin 3): Compensation pin for Channel 1. This is the output of the internal transconductance error amplifier. The loop compensation network should be connected between this pin and the signal ground, SGND (Pin 8). FB1 (Pin 4): Feedback input for channel 1. Connect to VOUT through a voltage divider to set the Channel 1 output voltage. SYNC (Pin 5): The switching frequency of the LM5642 can be synchronized to an external clock.  SYNC = LOW: Free running at 200kHz for LM5642, and at 375kHz for LM5642X. Channels are 180° out of phase.  SYNC = HIGH: Waiting for external clock   SYNC = Falling Edge: Channel 1 HDRV pin goes high. Channel 2 HDRV pin goes high after 2.5µs delay. The maximum SYNC pulse width must be greater than 100ns. For SYNC = Low operation, connect this pin to signal ground through a 220kΩ resistor. www.national.com 2 LM5642/LM5642X RSNS2 (Pin 15): The negative (-) Kelvin sense for the internal current sense amplifier of Channel 2. Connect this pin to the low side of the current sense resistor that is placed between VIN and the drain of the top MOSFET. When the Rds of the top MOSFET is used for current sensing, connect this pin to the source of the top MOSFET. Always use a separate trace to form a Kelvin connection to this pin. SW2 (Pin 16): Switch-node connection for Channel 2, which is connected to the source of the top MOSFET of Channel 2. It serves as the negative supply rail for the top-side gate driver, HDRV2. HDRV2 (Pin 17): Top-side gate-drive output for Channel 2. HDRV is a floating drive output that rides on the corresponding switching-node voltage. CBOOT2 (Pin 18): Bootstrap capacitor connection. It serves as the positive supply rail for the Channel 2 top-side gate drive. Connect this pin to VDD2 (Pin 19) through a diode, and connect the low side of the bootstrap capacitor to SW2 (Pin16). VDD2 (Pin 19): The supply rail for the Channel 2 low-side gate drive. Connected to VLIN5 (Pin 7) through a 4.7Ω resistor and bypassed to power ground with a ceramic capacitor of at least 1µF. Tie this pin to VDD1 (Pin 24). LDRV2 (Pin 20): Low-side gate-drive output for Channel 2. PGND (Pin 21): The power ground connection for both channels. Connect to the ground rail of the system. VIN (Pin 22): The power input pin for the chip. Connect to the positive (+) input rail of the system. This pin must be connected to the same voltage rail as the top FET drain (or the current sense resistor when used). LDRV1 (Pin 23): Low-side gate-drive output for Channel 1. VDD1 (Pin 24): The supply rail for Channel 1 low-side gate drive. Tie this pin to VDD2 (Pin 19). CBOOT1 (Pin 25): : Bootstrap capacitor connection. This pin serves as the positive supply rail for the Channel 1 top-side gate drive. See CBOOT2 (Pin 18). HDRV1 (Pin 26): Top-side gate-drive output for Channel 1. See HDRV2 (Pin 17). SW1 (Pin 27): Switch-node connection for Channel 1. See SW2 (Pin16). RSNS1 (Pin 28): The negative (-) Kelvin sense for the internal current sense amplifier of Channel 1. See RSNS2 (Pin 15). PGND (DAP): The power ground connection for both channels. Connect to the ground rail of the system. Use of multiple vias to internal ground plane or GND layer helps to dissipate heat generated by output power. 3 www.national.com LM5642/LM5642X Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Voltages from the indicated pins to SGND/PGND: VIN, ILIM1, ILIM2, KS1, KS2 −0.3V to 38V SW1, SW2, RSNS1, RSNS2 −0.3 to (VIN + 0.3)V FB1, FB2, VDD1, VDD2 −0.3V to 6V SYNC, COMP1, COMP2, UV Delay −0.3V to (VLIN5 +0.3)V ON/SS1, ON/SS2 (Note 2) −0.3V to (VLIN5 +0.6)V CBOOT1, CBOOT2 43V CBOOT1 to SW1, CBOOT2 to SW2 −0.3V to 7V LDRV1, LDRV2 −0.3V to (VDD+0.3) V HDRV1 to SW1, HDRV2 to SW2 −0.3V HDRV1 to CBOOT1, HDRV2 to CBOOT2 +0.3V Power Dissipation (TA = 25°C), (Note 3) TSSOP eTSSOP Ambient Storage Temp. Range Soldering Dwell Time, Temp. (Note 4) Wave Infrared Vapor Phase ESD Rating (Note 5) 1.1W 3.4W −65°C to +150°C 4 sec, 260°C 10sec, 240°C 75sec, 219°C 2kV (Note 1) 4.5V to 5.5V 5.5V to 36V −40°C to +125°C Operating Ratings VIN (VLIN5 tied to VIN) VIN (VIN and VLIN5 separate) Junction Temperature Electrical Characteristics Unless otherwise specified, VIN = 28V, GND = PGND = 0V, VLIN5 = VDD1 = VDD2. Limits appearing in boldface type apply over the specified operating junction temperature range, (-40°C to +125°C, if not otherwise specified). Specifications appearing in plain type are measured using low duty cycle pulse testing with TA = 25°C (Note 6), (Note 7). Min/Max limits are guaranteed by design, test, or statistical analysis. Symbol System ΔVOUT/VOUT VFB1_FB2 IVIN Load Regulation Line Regulation Feedback Voltage Input Supply Current VIN = 28V, Vcompx = 0.5V to 1.5V 5.5V ≤ VIN ≤ 36V, Vcompx =1.25V 5.5V ≤ VIN ≤ 36V -20°C to 85°C VON_SSx > 2V 5.5V ≤ VIN ≤ 36V 1.2154 1.2179 0.04 0.04 1.2364 1.2364 1.1 50 4.70 5 ±2 8.4 VON_ss1 = VON_ss2 = 1.5V (on) VON_ss1 = VON_ss2 = 1.5V 0.5 2 0.7 (Note 9) UV-DELAY = 2V UV-DELAY = 0.4V 9.9 2.4 5.5 1.12 3.4 2 0.2 5 0.48 2.3 75 80.7 3.7 86 9 1.2 1.2574 1.2549 2.0 110 5.30 ±7.0 11.4 5.0 10 1.4 % % V mA µA V mV µA µA µA V V µA mA V % % Parameter Conditions Min Typ Max Units Shutdown (Note 8) VON_SS1 = VON_SS2= 0V VLIN5 VCLos ICL VLIN5 Output Voltage IVLIN5 = 0 to 25mA, 5.5V ≤ VIN ≤ 36V Current Limit Comparator VIN = 6V Offset (VILIMX −VRSNSX) Current Limit Sink Current Iss_SC1, Iss_SC2 Soft-Start Source Current Iss_SK1, Iss_SK2 Soft-Start Sink Current VON_SS1, VON_SS2 VSSTO Isc_uvdelay Isk_uvdelay VUVDelay VUVP Soft-Start On Threshold Soft-Start Timeout Threshold UV_DELAY Source Current UV_DELAY Sink Current UV_DELAY Threshold Voltage FB1, FB2, Under Voltage As a percentage of nominal output voltage Protection Latch Threshold (falling edge) Hysteresis www.national.com 4 LM5642/LM5642X Symbol VOVP Swx_R Gate Drive ICBOOT ISC_DRV Isk_HDRV Isk_LDRV RHDRV Parameter Conditions Min 107 420 Typ 114 487 10 0.5 0.8 1.1 3.1 1.5 Max 122 560 Units % Ω nA A A A Ω Ω Ω Ω VOUT Overvoltage As a percentage measured at VFB1, VFB2 Shutdown Latch Threshold SW1, SW2 ON-Resistance VSW1 = VSW2 = 0.4V CBOOTx Leakage Current VCBOOT1 = VCBOOT2 = 7V HDRVx and LDRVx Source VCBOOT1 = VCBOOT2 = 5V, VSWx=0V, Current HDRVx=LDRVx=2.5V HDRVx Sink Current LDRVx Sink Current HDRV1 & 2 Source OnResistance HDRV1 & 2 Sink OnResistance VCBOOTx = VDDx = 5V, VSWx = 0V, HDRVX = 2.5V VCBOOTx = VDDx = 5V, VSWx = 0V, LDRVX = 2.5V VCBOOT1 = VCBOOT2 = 5V, VSW1 = VSW2 = 0V RLDRV LDRV1 & 2 Source OnResistance LDRV1 & 2 Sink OnResistance VCBOOT1 = VCBOOT2 = 5V, VSW1 = VSW2 = 0V VDD1 = VDD1 = 5V 3.1 1.1 Oscillator and Sync Controls Fosc Don_max Ton_min SSOT_delta VHS VLS IFB1, IFB2 Icomp1_SC, Icomp2_SC Icomp1_SK, Icomp2_SK gm1, gm2 GISNS1, GISNS2 UVLO Oscillator Frequency Maximum On-Duty Cycle Minimum On-Time HDRV1 and HDRV2 Delta ON/SS1 = ON/SS2 = 2V On Time SYNC Pin Min High Input SYNC Pin Max Low Input Feedback Input Bias Current COMP Output Source Current VFB1_FIX = 1.5V, VFB2_FIX = 1.5V VFB1_FIX = VFB2_FIX = 1V, VCOMP1 = VCOMP2 = 1V -20°C to 85°C COMP Output Sink Current VFB1_FIX = VFB2_FIX = 1.5V and VCOMP1 = VCOMP2 = 0.5V -20°C to 85°C Transconductance Current Sense Amplifier (1&2) Gain VLIN5 Under-voltage Lockout Threshold Rising VCOMPx = 1.25V 4.2 2 5.5 ≤ VIN ≤ 36V, LM5642 5.5 ≤ VIN ≤ 36V, LM5642X VFB1 = VFB2 = 1V, Measured at pins HDRV1 and HDRV2 166 311 96 200 375 98.9 166 20 1.52 1.44 0.8 250 226 424 kHz % ns ns V V Error Amplifier 80 6 18 6 18 720 5.2 7.5 µmho 118 µA 127 ±200 nA µA Voltage References and Linear Voltage Regulators ON/SS1, ON/SS2 transition from low to high 3.6 4.0 4.4 V 5 www.national.com LM5642/LM5642X Note 1: Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating Range indicates conditions for which the device is intended to be functional, but does not guarantee specfic performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: ON/SS1 and ON/SS2 are internally pulled up to one diode drop above VLIN5. Do not apply an external pull-up voltage to these pins. It may cause damage to the IC. Note 3: The maximum allowable power dissipation is calculated by using PDMAX = (TJMAX - TA)/θJA, where TJMAX is the maximum junction temperature, TA is the ambient temperature and θJA is the junction-to-ambient thermal resistance of the specified package. The power dissipation ratings results from using 125°C, 25° C, and 90.6°C/W for TJMAX, TA, and θJA respectively. A θJA of 90.6°C/W represents the worst-case condition of no heat sinking of the 28-pin TSSOP. The eTSSOP package has a θJA of 29°C/W. The eTSSOP package thermal ratings results from the IC being mounted on a 4 layer JEDEC standard board using the same temperature conditions as the TSSOP package above. A thermal shutdown will occur if the temperature exceeds the maximum junction temperature of the device. Note 4: For detailed information on soldering plastic small-outline packages, refer to the Packaging Databook available from National Semiconductor Corporation. Note 5: For testing purposes, ESD was applied using the human-body model, a 100pF capacitor discharged through a 1.5kΩ resistor. Note 6: A typical is the center of characterization data measured with low duty cycle pulse tsting at TA = 25°C. Typicals are not guaranteed. Note 7: All limits are guaranteed. All electrical characteristics having room-temperature limits are tested during production with TA = TJ = 25°C. All hot and cold limits are guaranteed by correlating the electrical characteristics to process and temperature variations and applying statistical process control. Note 8: Both switching controllers are off. The linear regulator VLIN5 remains on. Note 9: When SS1 and SS2 pins are charged above this voltage and either of the output voltages at Vout1 or Vout2 is still below the regulation limit, the under voltage protection feature is initialized. www.national.com 6 LM5642/LM5642X 20060103 FIGURE 1. Typical 2 Channel Application Circuit 7 www.national.com LM5642/LM5642X 20060104 FIGURE 2. Typical Single Channel Application Circuit www.national.com 8 Block Diagram LM5642/LM5642X 9 20060105 www.national.com LM5642/LM5642X Typical Performance Characteristics Softstart Waveforms (No-Load Both Channels) UVP Startup Waveform (VIN = 24V) 20060168 20060123 Over-Current and UVP Shutdown (VIN = 24V, Io2 = 0A) Shutdown Waveforms (VIN = 24V, No-Load) 20060120 20060122 Ch.1 Load Transient Response (VIN = 24V, Vo1 = 1.8V) Ch.2 Load Transient Response (VIN = 24V, Vo2 = 3.3V) 20060165 20060129 www.national.com 10 LM5642/LM5642X Ch. 2 Load Transient Response (VIN = 36V, Vo2 = 3.3V) Ch.1 Load Transient Response (VIN = 36V, Vo1 = 1.8V) 20060128 20060191 Input Supply Current vs Temperature (Shutdown Mode VIN = 28V) Input Supply Current vs VIN Shutdown Mode (25°C) 20060124 20060125 VLIN5 vs Temperature VLIN5 vs VIN (25°C) 20060126 20060127 11 www.national.com LM5642/LM5642X FB Reference Voltage vs Temperature Operating Frequency vs Temperature (VIN = 28V) 20060166 20060167 Error Amplifier Tranconductance Gain vs Temperature Efficiency vs Load Current Using Resistor Sense Ch.1 = 1.8V, Ch.2 = Off 20060169 20060170 Efficiency vs Load Current Ch.2 = 3.3V, Ch.1 = Off Efficiency vs Load Current Using Vds Sense Ch.2 = 1.8V, Ch.2 = Off 20060171 20060172 www.national.com 12 LM5642/LM5642X Efficiency vs Load Current Using Vds Sense Ch.2 = 3.3V, Ch.1 = Off 20060173 13 www.national.com LM5642/LM5642X Operating Descriptions SOFT START The ON/SS1 pin has dual functionality as both channel enable and soft start control. Referring to the soft start block diagram is shown in Figure 3, the LM5642 will remain in shutdown mode while both soft start pins are grounded. In a normal application (with a soft start capacitor connected between the ON/SS1 pin and SGND) soft start functions as follows: As the input voltage rises (note, Iss starts to flow when VIN ≥ 2.2V), the internal 5V LDO starts up, and an internal 2.4µA current charges the soft start capacitor. During soft start, the error amplifier output voltage at the COMPx pin is clamped at 0.55V and the duty cycle is controlled only by the soft start voltage. As the SSx pin voltage ramps up, the duty cycle increases proportional to the soft start ramp, causing the output voltage to ramp up. The rate at which the duty cycle increases depends on the capacitance of the soft start capacitor. The higher the capacitance, the slower the output voltage ramps up. When the corresponding output voltage exceeds 98% (typical) of the set target voltage, the regulator switches from soft start to normal operating mode. At this time, the 0.55V clamp at the output of the error amplifier releases and peak current feedback control takes over. Once in peak current feedback control mode, the output voltage of the error amplifier will travel within a 0.5V and 2V window to achieve PWM control. See Figure 4. The amount of capacitance needed for a desired soft-start time can be approximated in the following equation: 20060106 FIGURE 3. Soft-Start and ON/OFF 20060107 (1) In this equation Iss = 2.4µA for one channel and 4.8µA if the channels are paralleled. tss is the desired soft-start time. Finally, FIGURE 4. Voltage Clamp at COMPx Pin (2) During soft start, over-voltage protection and current limit remain in effect. The under voltage protection feature is activated when the ON/SS pin exceeds the timeout threshold (3.4V typical). If the ON/SSx capacitor is too small, the duty cycle may increase too rapidly, causing the device to latch off due to output voltage overshoot above the OVP threshold. This becomes more likely in applications with low output voltage, high input voltage and light load. A capacitance of 10nF is recommended at each soft start pin to provide a smooth monotonic output ramp. 20060108 FIGURE 5. OVP and UVP OVER VOLTAGE PROTECTION (OVP) If the output voltage on either channel rises above 113% of nominal, over voltage protection activates. Both channels will latch off. When the OVP latch is set, the high side FET driver, HDRVx, is immediately turned off and the low side FET driver, LDRVx, is turned on to discharge the output capacitor through the inductor. To reset the OVP latch, either the input voltage must be cycled, or both channels must be switched off (both ON/SS pins pulled low). www.national.com 14 LM5642/LM5642X UNDER VOLTAGE PROTECTION (UVP) AND UV DELAY If the output voltage on either channel falls below 80% of nominal, under voltage protection activates. As shown in Figure 5, an under-voltage event will shut off the UV_DELAY MOSFET, which will allow the UV_DELAY capacitor to charge with 5µA (typical). If the UV_DELAY pin voltage reaches the 2.3V threshold both channels will latch off. UV_DELAY will then be disabled and the UV_DELAY pin will return to 0V. During UVP, both the high side and low side FET drivers will be turned off. If no capacitor is connected to the UV_DELAY pin, the UVP latch will be activated immediately. To reset the UVP latch, either the input voltage must be cycled, or both ON/SS pins must be pulled low. The UVP function can be disabled by connecting the UV_DELAY pin to ground. THERMAL SHUTDOWN The LM5642 IC will enter thermal shutdown if the die temperature exceeds 160°C. The top and bottom FETs of both channels will be turned off immediately. In addition, both soft start capacitors will begin to discharge through separate 5.5µA current sinks. The voltage on both capacitors will settle to approximately 1.1V, where it will remain until the thermal shutdown condition has cleared. The IC will return to normal operating mode when the die temperature has fallen to below 146°C. At this point the two soft start capacitors will begin to charge with their normal 2.4µA current sources. This allows a controlled return to normal operation, similar to the soft start during turn-on. If the thermal shutdown condition clears before the voltage on the soft start capacitors has fallen to 1.1V, the capacitors will first be discharged to 1.1V, and then immediately begin charging back up. OUTPUT CAPACITOR DISCHARGE Each channel has an embedded 480Ω MOSFET with the drain connected to the SWx pin. This MOSFET will discharge the output capacitor of its channel if its channel is off, or the IC enters a fault state caused by one of the following conditions: 1. UVP 2. UVLO If an output over voltage event occurs, the HDRVx will be turned off and LDRVx will be turned on immediately to discharge the output capacitors of both channels through the inductors. BOOTSTRAP DIODE SELECTION The bootstrap diode and capacitor form a supply that floats above the switch node voltage. VLIN5 powers this supply, creating approximately 5V (minus the diode drop) which is used to power the high side FET drivers and driver logic. When selecting a bootstrap diode, Schottky diodes are preferred due to their low forward voltage drop, but care must be taken for circuits that operate at high ambient temperature. The reverse leakage of some Schottky diodes can increase by more than 1000x at high temperature, and this leakage path can deplete the charge on the bootstrap capacitor, starving the driver and logic. Standard PN junction diodes and fast rectifier diodes can also be used, and these types maintain tighter control over reverse leakage current across temperature. SWITCHING NOISE REDUCTION Power MOSFETs are very fast switching devices. In synchronous rectifier converters, the rapid increase of drain current in the top FET coupled with parasitic inductance will generate unwanted Ldi/dt noise spikes at the source node of the FET (SWx node) and also at the VIN node. The magnitude 15 of this noise will increase as the output current increases. This parasitic spike noise may produce excessive electromagnetic interference (EMI), and can also cause problems in device performance. Therefore, it must be suppressed using one of the following methods. When using resistor based current sensing, it is strongly recommended to add R-C filters to the current sense amplifier inputs as shown in Figure 7. This will reduce the susceptibility to switching noise, especially during heavy load transients and short on time conditions. The filter components should be connected as close as possible to the IC. As shown in Figure 6, adding a resistor in series with the HDRVx pin will slow down the gate drive, thus slowing the rise and fall time of the top FET, yielding a longer drain current transition time. Usually a 3.3Ω to 4.7Ω resistor is sufficient to suppress the noise. Top FET switching losses will increase with higher resistance values. Small resistors (1-5 ohms) can also be placed in series with the CBOOTx pin to effectively reduce switch node ringing. A CBOOT resistor will slow the rise time of the FET, whereas a resistor at HDRV will increase both rise and fall times. 20060109 FIGURE 6. HDRV Series Resistor CURRENT SENSING AND LIMITING As shown in Figure 7, the KSx and RSNSx pins are the inputs of the current sense amplifier. Current sensing is accomplished either by sensing the Vds of the top FET or by sensing the voltage across a current sense resistor connected from VIN to the drain of the top FET. The advantages of sensing current across the top FET are reduced parts count, cost and power loss. The RDS-ON of the top FET is not as stable over temperature and voltage as a sense resistor, hence great care must be used in layout for VDS sensing circuits. At input voltages above 30V, the maximum recommended output current is 5A per channel. Keeping the differential current-sense voltage below 200mV ensures linear operation of the current sense amplifier. Therefore, the RDS-ON of the top FET or the current sense resistor must be small enough so that the current sense voltage does not exceed 200mV when the top FET is on. There is a leading edge blanking circuit that forces the top FET on for at least 166ns. Beyond this minimum on time, the output of the PWM comparator is used to turn off the top FET. Additionally, a minimum voltage of at least 50mV across Rsns is recommended to ensure a high SNR at the current sense amplifier. Assuming a maximum of 200mV across Rsns, the current sense resistor can be calculated as follows: (3) www.national.com LM5642/LM5642X where Imax is the maximum expected load current, including overload multiplier (ie:120%), and Irip is the inductor ripple current (See Equation 17). The above equation gives the maximum allowable value for Rsns. Conduction losses will increase with larger Rsns, thus lowering efficiency. The peak current limit is set by an external resistor connected between the ILIMx pin and the KSx pin. An internal 10µA current sink on the ILIMx pin produces a voltage across the resistor to set the current limit threshold which is then compared to the current sense voltage. A 10nF capacitor across this resistor is required to filter unwanted noise that could improperly trip the current limit comparator. INPUT UNDER VOLTAGE LOCKOUT (UVLO) The input under-voltage lock out threshold, which is sensed via the VLIN5 internal LDO output, is 4.0V (typical). Below this threshold, both HDRVx and LDRVx will be turned off and the internal 480Ω MOSFETs will be turned on to discharge the output capacitors through the SWx pins. When the input voltage is below the UVLO threshold, the ON/SS pins will sink 5mA to discharge the soft start capacitors and turn off both channels. As the input voltage increases again above 4.0V, UVLO will be de-activated, and the device will restart through a normal soft start phase. If the voltage at VLIN5 remains below 4.5V, but above the 4.0V UVLO threshold, the device cannot be guaranteed to operate within specification. If the input voltage is between 4.0V and 5.2V, the VLIN5 pin will not regulate, but will follow approximately 200mV below the input voltage. DUAL-PHASE PARALLEL OPERATION In applications with high output current demand, the two switching channels can be configured to operate as a two phase converter to provide a single output voltage with current sharing between the two switching channels. This approach greatly reduces the stress and heat on the output stage components while lowering input ripple current. The inductor ripple currents also cancel to a varying degree which results in lowered output ripple voltage. Figure 2 shows an example of a typical two-phase circuit. Because precision current sense is the primary design criteria to ensure accurate current sharing between the two channels, both channels must use external sense resistors for current sensing. To minimize the error between the error amplifiers of the two channels, tie the feedback pins FB1 and FB2 together and connect to a single voltage divider for output voltage sensing. Also, tie the COMP1 and COMP2 together and connect to the compensation network. ON/SS1 and ON/SS2 must be tied together to enable and disable both channels simultaneously. EXTERNAL FREQUENCY SYNC The LM5642 series has the ability to synchronize to external sources in order to set the switching frequency. This allows the LM5642 to use frequencies from 150 kHz to 250 kHz and the LM5642X to use frequencies from 200 kHz to 500 kHz. Lowering the switching frequency allows a smaller minimum duty cycle, DMIN, and hence a greater range between input and output voltage. Increasing switching frequency allows the use of smaller output inductors and output capacitors (See Component Selection). In general, synchronizing all the switching frequencies in multi-converter systems makes filtering of the switching noise easier. The sync input can be from a system clock, from another switching converter in the system, or from any other periodic signal with a logic low-level less than 1.4V and a logic high level greater than 2V. Both CMOS and TTL level inputs are acceptable. The LM5642 series uses a fixed delay between Channel 1 and Channel 2. The nominal switching frequency of 200kHz for the LM5642 corresponds to a switching period of 5µs. Channel 2 always turns its high-side switch on 2.5µs after Channel 1 Figure 8 (a). When the converter is synchronized to a frequency other than 200kHz, the switching period is reduced or increased, while the fixed delay between Channel 1 and Channel 2 remains constant. The phase difference between channels is therefore no longer 180°. At the extremes of the sync range, the phase difference drops to 135° Figure 8 (b) and Figure 8 (c). The result of this lower phase difference is a reduction in the maximum duty cycle of one channel that 20060110 FIGURE 7. Current Sense and Current Limit Current limit is activated when the inductor current is high enough to cause the voltage at the RSNSx pin to be lower than that of the ILIMx pin. This toggles the Ilim comparator, thus turning off the top FET immediately. The comparator is disabled when the top FET is turned off and during the leading edge blanking time. The equation for current limit resistor, Rlim, is as follows: (4) Where Ilim is the load current at which the current limit comparator will be tripped. When sensing current across the top FET, replace Rsns with the RDS-ON of the FET. This calculated Rlim value guarantees that the minimum current limit will not be less than Imax. It is recommended that a 1% tolerance resistor be used. When sensing across the top FET (VDS sensing), RDS-ON will show more variation than a current-sense resistor, largely due to temperature variation. RDS-ON will increase proportional to temperature according to a specific temperature coefficient. Refer to the FET manufacturer's datasheet to determine the range of RDS-ON values over operating temperature or see the Component Selection section (Equation 27) for a calculation of maximum RDS-ON. This will prevent RDS-ON variations from prematurely tripping the current limit comparator as the operating temperature increases. To ensure accurate current sensing using VDS sensing, special attention in board layout is required. The KSx and RSNSx pins require separate traces to form a Kelvin connection at the corresponding current sense nodes. In addition, the filter components R14, R16, C14, C15 should be removed. www.national.com 16 LM5642/LM5642X will not overlap the duty cycle of the other. As shown in Input Capacitor Selection section, when the duty cycle D1 for Channel 1 overlaps the duty cycle D2 for Channel 2, the input rms current increases, requiring more input capacitors or input capacitors with higher ripple current ratings. The new, reduced maximum duty cycle can be calculated by multiplying the sync frequency (in Hz) by 2.5x10-6 (the fixed delay in seconds). The same logic applies to the LM5642X. However the LM5642X has a nominal switching frequency of 375kHz which corresponds to a period of 2.67µs. Therefore channel 2 of the LM5642X always begins it's period after 1.33µs. DMAX = FSYNC*2.5x10-6 (5) Therefore, a maximum value is recommended for R2 in order to keep the output within .3% of Vnom. This maximum R2 value should be calculated first with the following equation: (7) Where 200nA is the maximum current drawn by FBx pin. At a sync frequency of 150kHz, for example, the maximum duty cycle for Channel 1 that will not overlap Channel 2 would be 37.5%. At 250kHz, it is the duty cycle for Channel 2 that is reduced to a DMAX of 37.5%. 20060111 FIGURE 9. Output Voltage Setting Example: Vnom=5V, Vfb=1.2364V, Ifbmax=200nA. (8) Choose 60K (9) The Cycle Skip and Dropout modes of the LM5642 series regulate the minimum and maximum output voltage/duty cycle that the converter can deliver. Both modes check the voltage at the COMP pin. Minimum output voltage is determined by the Cycle Skip Comparator. This circuitry skips the high side FET ON pulse when the COMP pin voltage is below 0.5V at the beginning of a cycle. The converter will continue to skip every other pulse until the duty cycle (and COMP pin voltage) rise above 0.5V, effectively halving the switching frequency. Maximum output voltage is determined by the Dropout circuitry, which skips the low side FET ON pulse whenever the COMP pin voltage exceeds the ramp voltage derived from the current sense. Up to three low side pulses may be skipped in a row before a minimum on-time pulse must be applied to the low side FET. Figure 10 shows the range of ouput voltage (for Io = 3A) with respect to input voltage that will keep the converter from entering either Skip Cycle or Dropout mode. For input voltages below 5.5V, VLIN5 must be connected to Vin through a small resistor (approximately 4.7 ohm). This will ensure that VLIN5 does not fall below the UVLO threshold. 20060195 FIGURE 8. Period Fixed Delay Example Component Selection OUTPUT VOLTAGE SETTING The output voltage for each channel is set by the ratio of a voltage divider as shown in Figure 9. The resistor values can be determined by the following equation: (6) Where Vfb=1.238V. Although increasing the value of R1 and R2 will increase efficiency, this will also decrease accuracy. 17 www.national.com LM5642/LM5642X Maximum ESR criterion can be used when the associated capacitance is high enough, otherwise more capacitors than the number determined by this criterion should be used in parallel. MINIMUM CAPACITANCE CALCULATION In a switch mode power supply, the minimum output capacitance is typically dictated by the load transient requirement. If there is not enough capacitance, the output voltage excursion will exceed the maximum allowed value even if the maximum ESR requirement is met. The worst-case load transient is an unloading transient that happens when the input voltage is the highest and when the current switching cycle has just finished. The corresponding minimum capacitance is calculated as follows: 20060113 (13) Notice it is already assumed the total ESR, Re, is no greater than Re_max, otherwise the term under the square root will be a negative value. Also, it is assumed that L has already been selected, therefore the minimum L value should be calculated before Cmin and after Re (see Inductor Selection below). Example: Re = 20mΩ, Vnom = 5V, ΔVc_s = 160mV, ΔIc_s = 3A, L = 8µH FIGURE 10. Output Voltage Range Output Capacitor Selection In applications that exhibit large, fast load current swings, the slew rate of such a load current transient will likely be beyond the response speed of the regulator. Therefore, to meet voltage transient requirements during worst-case load transients, special consideration should be given to output capacitor selection. The total combined ESR of the output capacitors must be lower than a certain value, while the total capacitance must be greater than a certain value. Also, in applications where the specification of output voltage regulation is tight and ripple voltage must be low, starting from the required output voltage ripple will often result in fewer design iterations. ALLOWED TRANSIENT VOLTAGE EXCURSION The allowed output voltage excursion during a load transient (ΔVc_s) is: (10) Where ±δ% is the output voltage regulation window and ±ε% is the output voltage initial accuracy. Example: Vnom = 5V, δ% = 7%, ε% = 3.4%, Vrip = 40mV peak to peak. (14) Generally speaking, Cmin decreases with decreasing Re, ΔIc_s, and L, but with increasing Vnom and ΔVc_s. Inductor Selection The size of the output inductor can be determined from the desired output ripple voltage, Vrip, and the impedance of the output capacitors at the switching frequency. The equation to determine the minimum inductance value is as follows: (15) In the above equation, Re is used in place of the impedance of the output capacitors. This is because in most cases, the impedance of the output capacitors at the switching frequency is very close to Re. In the case of ceramic capacitors, replace Re with the true impedance at the switching frequency. Example: Vin = 36V, Vo = 3.3V, VRIP = 60mV, Re = 20mΩ, F = 200kHz. (11) MAXIMUM ESR CALCULATION Unless the rise and fall times of a load transient are slower than the response speed of the control loop, if the total combined ESR (Re) is too high, the load transient requirement will not be met, no matter how large the capacitance. The maximum allowed total combined ESR is: (16) The actual selection process usually involves several iterations of all of the above steps, from ripple voltage selection, to capacitor selection, to inductance calculations. Both the highest and the lowest input and output voltages and load transient requirements should be considered. If an inductance value larger than Lmin is selected, make sure that the Cmin requirement is not violated. Priority should be given to parameters that are not flexible or more costly. For example, if there are very few types of capacitors to choose from, it may be a good idea to adjust the inductance value so that a requirement of 3.2 capacitors can be reduced to 3 capacitors. 18 (12) Since the ripple voltage is included in the calculation of ΔVc_s, the inductor ripple current should not be included in the worst-case load current excursion. Simply use the worstcase load current excursion for ΔIc_s. Example: ΔVc_s = 160mV, ΔIc_s = 3A. Then Re_max = 53.3mΩ. www.national.com LM5642/LM5642X Since inductor ripple current is often the criterion for selecting an output inductor, it is a good idea to double-check this value. The equation is: will be highest under these circumstances. The input RMS current in this case is given by: (17) Also important is the ripple content, which is defined by Irip / Inom. Generally speaking, a ripple content of less than 50% is ok. Larger ripple content will cause too much power loss in the inductor. Example: Vin = 36V, Vo = 3.3V, F = 200kHz, L = 5µH, 3A max IOUT (23) Where, again, I1 and I2 are the maximum load currents of channel 1 and 2, and D1 and D2 are the duty cycles. This equation should be used when both duty cycles are expected to be higher than 50%. If the LM5642 is being used with an external clock frequency other than 200kHz, or 375 kHz for the LM5642X, the preceding equations for input rms current can still be used. The selection of the first equation or the second changes because overlap can now occur at duty cycles that are less than 50%. From the External Frequency Sync section, the maximum duty cycle that ensures no overlap between duty cycles (and hence input current pulses) is: DMAX = FSYNC* 2.5 x 10-6 (24) There are now three distinct possibilities which must be considered when selecting the equation for input rms current. The following applies for the LM5642, and also the LM5642X by replacing 200 kHz with 375 kHz: 1. Both duty cycles D1 and D2 are less than DMAX. In this case, the first, simple equation can always be used. 2. One duty cycle is greater than DMAX and the other duty cycle is less than DMAX. In this case, the system designer can take advantage of the fact that the sync feature reduces DMAX for one channel, but lengthens it for the other channel. For FSYNC < 200kHz, D1 is reduced to DMAX while D2 actually increases to (1-DMAX). For FSYNC > 200kHz, D2 is reduced to DMAX while D1 increases to (1-DMAX). By using the channel reduced to DMAX for the lower duty cycle, and the channel that has been increased for the higher duty cycle, the first, simple rms input current equation can be used. 3. Both duty cycles are greater than DMAX. This case is identical to a system at 200kHz where either duty cycle is 50% or greater. Some overlap of duty cycles is guaranteed, and hence the second, more complicated rms input current equation must be used. Input capacitors must meet the minimum requirements of voltage and ripple current capacity. The size of the capacitor should then be selected based on hold up time requirements. Bench testing for individual applications is still the best way to determine a reliable input capacitor value. Input capacitors should always be placed as close as possible to the current sense resistor or the drain of the top FET. When high ESR capacitors such as tantalum are used, a 1µF ceramic capacitor should be added as closely as possible to the high-side FET drain and low-side FET source. (18) 3A is 100% ripple which is too high. In this case, the inductor should be reselected on the basis of ripple current. Example: 40% ripple, 40% • 3A = 1.2A (19) (20) When choosing the inductor, the saturation current should be higher than the maximum peak inductor current and the RMS current rating should be higher than the maximum load current. Input Capacitor Selection The fact that the two switching channels of the LM5642 are 180° out of phase will reduce the RMS value of the ripple current seen by the input capacitors. This will help extend input capacitor life span and result in a more efficient system. Input capacitors must be selected that can handle both the maximum ripple RMS current at highest ambient temperature as well as the maximum input voltage. In applications in which output voltages are less than half of the input voltage, the corresponding duty cycles will be less than 50%. This means there will be no overlap between the two channels' input current pulses. The equation for calculating the maximum total input ripple RMS current for duty cycles under 50% is: (21) where I1 is maximum load current of Channel 1, I2 is the maximum load current of Channel 2, D1 is the duty cycle of Channel 1, and D2 is the duty cycle of Channel 2. Example: Imax_1 = 3.6A, Imax_2 = 3.6A, D1 = 0.42, and D2 = 0.275 MOSFET Selection BOTTOM FET SELECTION During normal operation, the bottom FET is switching on and off at almost zero voltage. Therefore, only conduction losses are present in the bottom FET. The most important parameter when selecting the bottom FET is the on-resistance (RDSON). The lower the on-resistance, the lower the power loss. The bottom FET power loss peaks at maximum input voltage and load current. The equation for the maximum allowed onresistance at room temperature for a given FET package, is: (22) Choose input capacitors that can handle 1.66A ripple RMS current at highest ambient temperature. In applications where output voltages are greater than half the input voltage, the corresponding duty cycles will be greater than 50%, and there will be overlapping input current pulses. Input ripple current 19 www.national.com LM5642/LM5642X Loop Compensation The general purpose of loop compensation is to meet static and dynamic performance requirements while maintaining stability. Loop gain is what is usually checked to determine small-signal performance. Loop gain is equal to the product of control-output transfer function and the feedback transfer function (the compensation network transfer function). Generally speaking it is desirable to have a loop gain slope that is roughly -20dB /decade from a very low frequency to well beyond the crossover frequency. The crossover frequency should not exceed one-fifth of the switching frequency. The higher the bandwidth, the faster the load transient response speed will be. However, if the duty cycle saturates during a load transient, further increasing the small signal bandwidth will not help. Since the control-output transfer function usually has very limited low frequency gain, it is a good idea to place a pole in the compensation at zero frequency, so that the low frequency gain will be relatively large. A large DC gain means high DC regulation accuracy (i.e. DC voltage changes little with load or line variations). The rest of the compensation scheme depends highly on the shape of the control-output plot. (25) where Tj_max is the maximum allowed junction temperature in the FET, Ta_max is the maximum ambient temperature, Rθja is the junction-to-ambient thermal resistance of the FET, and TC is the temperature coefficient of the on-resistance which is typically in the range of 4000ppm/°C. If the calculated RDS-ON (MAX) is smaller than the lowest value available, multiple FETs can be used in parallel. This effectively reduces the Imax term in the above equation, thus reducing RDS-ON. When using two FETs in parallel, multiply the calculated RDS-ON (MAX) by 4 to obtain the RDS-ON (MAX) for each FET. In the case of three FETs, multiply by 9. (26) If the selected FET has an Rds value higher than 35.3Ω, then two FETs with an RDS-ON less than 141mΩ (4 x 35.3mΩ) can be used in parallel. In this case, the temperature rise on each FET will not go to Tj_max because each FET is now dissipating only half of the total power. TOP FET SELECTION The top FET has two types of losses: switching loss and conduction loss. The switching losses mainly consist of crossover loss and losses related to the low-side FET body diode reverse recovery. Since it is rather difficult to estimate the switching loss, a general starting point is to allot 60% of the top FET thermal capacity to switching losses. The best way to precisely determine switching losses is through bench testing. The equation for calculating the on resistance of the top FET is thus: 20060114 FIGURE 11. Control-Output Transfer Function As shown in Figure 11, the control-output transfer function consists of one pole (fp), one zero (fz), and a double pole at fn (half the switching frequency). The following can be done to create a -20dB /decade roll-off of the loop gain: Place the first pole at 0Hz, the first zero at fp, the second pole at fz, and the second zero at fn. The resulting feedback transfer function is shown in Figure 12. (27) Example: Tj_max = 100°C, Ta_max = 60°C, Rqja = 60°C/W, Vin_min = 5.5V, Vnom = 5V, and Iload_max = 3.6A. 20060112 (28) When using FETs in parallel, the same guidelines apply to the top FET as apply to the bottom FET. www.national.com 20 FIGURE 12. Feedback Transfer Function LM5642/LM5642X The control-output corner frequencies, and thus the desired compensation corner frequencies, can be determined approximately by the following equations: A second zero can also be added with a resistor in series with Cc2. If used, this zero should be placed at fn, where the control to output gain rolls off at -40dB/dec. Generally, fn will be well below the 0dB level and thus will have little effect on stability. Rc2 can be calculated with the following equation: (29) (39) (30) Since fp is determined by the output network, it will shift with loading (Ro). It is best to use a minimum Iout value of approximately 100mA when determining the maximum Ro value. Example: Re=20mΩ, Co=100uF, Romax=5V/100mA=50Ω: (31) 20060174 FIGURE 13. Compensation Network (32) First determine the minimum frequency (fpmin) of the pole across the expected load range, then place the first compensation zero at or below that value. Once fpmin is determined, Rc1 should be calculated using: PCB Layout Considerations To produce an optimal power solution with the LM5642 series, good layout and design of the PCB are as important as the component selection. The following are several guidelines to aid in creating a good layout. KELVIN TRACES FOR SENSE LINES When using the current sense resistor to sense the load current connect the KS pin using a separate trace to VIN, as close as possible to the current-sense resistor. The RSNS pin should be connected using a separate trace to the low-side of the current sense resistor. The traces should be run parallel to each other to give common mode rejection. Although it can be difficult in a compact design, these traces should stay away from the output inductor and switch node if possible, to avoid coupling stray flux fields. When a current-sense resistor is not used the KS pin should be connected as close as possible to the drain node of the upper MOSFET and the RSNS pin should be connected as close as possible to the source of the upper MOSFET using Kelvin traces. To further help minimize noise pickup on the sense lines is to use RC filtering on the KS and RSNS pins. SEPARATE PGND AND SGND Good layout techniques include a dedicated ground plane, usually on an internal layer. Signal level components like the compensation and feedback resistors should be connected to a section of this internal SGND plane. The SGND section of the plane should be connected to the power ground at only one point. The best place to connect the SGND and PGND is right at the PGND pin.. MINIMIZE THE SWITCH NODE The plane that connects the power FETs and output inductor together radiates more EMI as it gets larger. Use just enough copper to give low impedance to the switching currents, preferably in the form of a wide, but short, trace run. LOW IMPEDANCE POWER PATH The power path includes the input capacitors, power FETs, output inductor, and output capacitors. Keep these components on the same side of the PCB and connect them with thick traces or copper planes (shapes) on the same layer. Vias add resistance and inductance to the power path, and 21 www.national.com (33) Where B is the desired gain in V/V at fp (fz1), gm is the transconductance of the error amplifier, and R1 and R2 are the feedback resistors. A gain value around 10dB (3.3v/v) is generally a good starting point. Example: B=3.3v/v, gm=650m, R1=20KΩ, R2=60.4KΩ: (34) Bandwidth will vary proportional to the value of Rc1. Next, Cc1 can be determined with the following equation: (35) Example: fpmin=695Hz, Rc1=20KΩ: (36) The compensation network (Figure 13) will also introduce a low frequency pole which will be close to 0Hz. A second pole should also be placed at fz. This pole can be created with a single capacitor Cc2 and a shorted Rc2 (see Figure 13). The minimum value for this capacitor can be calculated by: (37) Cc2 may not be necessary, however it does create a more stable control loop. This is especially important with high load currents and in current sharing mode. Example: fz=80kHz, Rc1= 20KΩ: (38) LM5642/LM5642X have relatively high impedance connections to the internal planes. If high switching currents must be routed through vias and/or internal planes, use multiple vias in parallel to reduce their resistance and inductance. The power components should be kept close together. The longer the paths that connect them, the more they act as antennas, radiating unwanted EMI. Please see AN-1229 for further PCB layout considerations. www.national.com 22 LM5642/LM5642X Bill Of Materials for Figure 1 24V to 1.8, 3.3V LM5642 ID U1 Part Number LM5642 Type Dual Synchronous Controller N-MOSFET N-MOSFET Schottky Diode Inductor Inductor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Resistor Resistor Resistor Resistor Resistor Size TSSOP-28 Parameters Qty 1 Vendor NSC Q1, Q4 Q2, Q5 D3 L1 L2 C1 C3, C4, C14, C15 C27 C6, C16 C9, C23 C2, C11, C12, C13 C7, C25, C34 C19 C20 C26 R1 R2, R6, R14, R16 R13 R7, R15 R8, R9, R12, R17, R18, R21, R31, R32 R10 R23 R24 R11, R20 R19 R27 R28 Si4850EY Si4840DY BAS40-06 RLF12560T-4R2N100 RLF12545T-100M5R1 C3216X7R1H105K VJ1206Y101KXXAT C2012X5R1C105K C5750X5R1H106M 6TPD330M VJ1206Y103KXXAT VJ1206Y104KXXAT VJ1206Y822KXXAT VJ1206Y153KXXAT C3216X7R1C475K CRCW1206123J CRCW1206100J CRCW1206682J WSL-2512 .010 1% CRCW1206000Z SO-8 SO-8 SOT-23 12.5x12.5x 6mm 12.5x12.5x 4.5mm 1206 1206 0805 2220 7.3x4.3x 3.8mm 1206 1206 1206 1206 1206 1206 1206 1206 2512 1206 60V 40V 40V 4.2µH, 7mΩ 10A 10µH, 12mΩ 5.1A 1µF, 50V 100pF, 25V 1µF, 16V 10µF 50V, 2.8A 330µF, 6.3V, 10mΩ 10nF, 25V 100nF, 25V 8.2nF 10% 15nF 10% 4.7µF 25V 12kΩ 5% 100Ω 5% 6.8kΩ 12% 10mΩ 1W 0Ω 2 2 1 1 1 1 3 1 2 2 4 3 1 1 1 1 1 1 2 8 Vishay Vishay Vishay TDK TDK TDK Vishay TDK TDK Sanyo Vishay Vishay Vishay Vishay TDK Vishay Vishay Vishay Vishay Vishay CRCW12062261F CRCW12068451F CRCW12061372F CRCW12064991F CRCW12068251F CRCW12064R7J CRCW1206224J Resistor Resistor Resistor Resistor Resistor Resistor Resistor 1206 1206 1206 1206 1206 1206 1206 2.26kΩ 1% 8.45kΩ 1% 13.7kΩ 1% 4.99kΩ 1% 8.25kΩ 1% 4.7Ω 5% 220kΩ 5% 1 1 1 2 1 1 1 Vishay Vishay Vishay Vishay Vishay Vishay Vishay 23 www.national.com LM5642/LM5642X Bill of Materials for Figure 2 30V to 1.8V, 20A LM5642 ID U1 Part Number LM5642 Type Dual Synchronou s Controller N-MOSFET N-MOSFET Schottky Diode Inductor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Resistor Resistor Resistor Resistor Size TSSOP-28 Parameters Qty 1 Vendor NSC Q1, Q4 Q2, Q3, Q5, Q6 D3 L1,L2 C1 C10, C24, C27 C6, C16, C28, C30 C9, C23 C2, C13 C11 C7,C25, C34 C19 C26 R1, R13 R2, R6, R14, R16 R7, R15 R8, R9, R12, R17, R18, R21, R31, R32 R10 R11 R23 R27 R28 Si4850EY Si4470DY BAS40-06 RLF12560T-2R7N110 C3216X7R1H105K C2012X5R1C105K C5750X5R1H106M 16MV1000WX VJ1206Y103KXXAT VJ1206Y223KXXAT VJ1206Y104KXXAT VJ1206Y273KXXAT C3216X7R1C475K CRCW1206123J CRCW1206100J WSL-2512 .010 1% CRCW1206000Z SO-8 SO-8 SOT-23 12.5x12.5x 6mm 1206 0805 2220 10mm D20mm H 1206 1206 1206 1206 1206 1206 1206 2512 1206 60V 60V 40V 2.7µH,4.5mΩ 11.5A 1µF, 50V 1µF, 16V 10µF 50V, 2.8A 1000µF, 16V, 22mΩ 10nF, 25V 22nF, 25V 100nF, 25V 27nF 10% 4.7µF 25V 16.9kΩ 1% 100Ω 5% 10mΩ 1W 0Ω 2 4 1 2 1 3 4 2 2 1 3 1 1 1 1 2 8 Vishay Vishay Vishay TDK TDK TDK TDK Sanyo Vishay Vishay Vishay Vishay TDK Vishay Vishay Vishay Vishay CRCW12062261F CRCW12064991F CRCW12061152F CRCW12064R7J CRCW1206224J Resistor Resistor Resistor Resistor Resistor 1206 1206 1206 1206 1206 2.26kΩ 1% 4.99kΩ 1% 11.5kΩ 1% 4.7Ω 5% 220kΩ 5% 1 1 1 1 1 Vishay Vishay Vishay Vishay Vishay www.national.com 24 LM5642/LM5642X Bill Of Materials Based on Figure 1 Vin= 9-16V, VO1,2=1.5V,1.8V, 5A LM5642X ID U1 Part Number LM5642X Type Dual Synchronous Controller N-MOSFET N-MOSFET Schottky Diode Inductor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Resistor Resistor Resistor Resistor Size TSSOP-28 Parameters Qty 1 Vendor NSC Q1, Q4 Q2, Q5 D3 L1, L2 C1 C3, C4, C14, C15 C27 C6, C28 C9, C23 C2, C11, C12, C13 C7, C25, C34 C18, C20 C26 R1, R13 R2, R6, R14, R16 R7, R15 R8, R9, R12, R17, R18, R21, R31, R32 R10, R19 R11 R20 R22, R24 R27 R28 Si4850EY Si4840DY BA54A RLF12545T-4R2N100 C3216X7R1H105K VJ1206Y101KXXAT C2012X5R1C105K C5750X7R1H106M C4532X7R0J107M VJ1206Y103KXXAT VJ1206Y104KXXAT VJ1206Y473KXXAT C3216X7R1C475K CRCW12061912F CRCW1206100J WSL-1206 .020 1% CRCW1206000Z SO-8 SO-8 SOT-23 12.5x12.5x 4.5mm 1206 1206 0805 2220 1812 1206 1206 1206 1206 1206 1206 1206 1206 60V 40V 30V 4.2µH, 7mΩ 6.5A 1µF, 50V 100pF, 25V 1µF, 16V 10µF 50V, 2.8A 100µF, 6.3V, 1mΩ 10nF, 25V 100nF, 25V 47nF 10% 4.7µF 25V 19.1kΩ 1% 100Ω 5% 20mΩ 1W 0Ω 2 2 1 2 1 4 1 2 2 4 3 2 1 2 1 2 8 Vishay Vishay Vishay TDK TDK Vishay TDK TDK TDK Vishay Vishay Vishay TDK Vishay Vishay Vishay Vishay CRCW12061001F CRCW12062611F CRCW12062321F CRCW12063011F CRCW12064R7J CRCW1206224J Resistor Resistor Resistor Resistor Resistor Resistor 1206 1206 1206 1206 1206 1206 1kΩ 1% 2.61kΩ 1% 2.32kΩ 1% 3.01kΩ 1% 4.7Ω 5% 220kΩ 5% 2 1 1 2 1 1 Vishay Vishay Vishay Vishay Vishay Vishay 25 www.national.com LM5642/LM5642X Bill Of Materials Based on Figure 1 Vin= 9-16V, VO1,2=3.3V,5V, 5A LM5642X ID U1 Part Number LM5642X Type Dual Synchronous Controller N-MOSFET N-MOSFET Schottky Diode Inductor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Resistor Resistor Resistor Resistor Size TSSOP-28 Parameters Qty 1 Vendor NSC Q1, Q4 Q2, Q5 D3 L1, L2 C1 C3, C4, C14, C15 C27 C6, C28 C9, C23 C2, C11, C12, C13 C7, C25, C34 C18, C20 C26 R1, R13 R2, R6, R14, R16 R7, R15 R8, R9, R12, R17, R18, R21, R31, R32 R10, R19 R11 R20 R22, R24 R27 R28 Si4850EY Si4840DY BA54A RLF12545T-5R6N6R1 C3216X7R1H105K VJ1206Y101KXXAT C2012X5R1C105K C5750X7R1H106M C4532X7R0J107M VJ1206Y103KXXAT VJ1206Y104KXXAT VJ1206Y393KXXAT C3216X7R1C475K CRCW12061912F CRCW1206100J WSL-1206 .020 1% CRCW1206000Z SO-8 SO-8 SOT-23 12.5x12.5x 4.5mm 1206 1206 0805 2220 1812 1206 1206 1206 1206 1206 1206 1206 1206 60V 40V 30V 5.6µH, 9mΩ 6.1A 1µF, 50V 100pF, 25V 1µF, 16V 10µF 50V, 2.8A 100µF, 6.3V, 1mΩ 10nF, 25V 100nF, 25V 39nF 10% 4.7µF 25V 19.1kΩ 1% 100Ω 5% 20mΩ 1W 0Ω 2 2 1 2 1 4 1 2 2 4 3 2 1 2 1 2 8 Vishay Vishay Vishay TDK TDK Vishay TDK TDK TDK Vishay Vishay Vishay TDK Vishay Vishay Vishay Vishay CRCW12061002F CRCW12066191F CRCW12063321F CRCW12063831F CRCW12064R7J CRCW1206224J Resistor Resistor Resistor Resistor Resistor Resistor 1206 1206 1206 1206 1206 1206 10kΩ 1% 6.19kΩ 1% 3.32kΩ 1% 3.83kΩ 1% 4.7Ω 5% 220kΩ 5% 2 1 1 2 1 1 Vishay Vishay Vishay Vishay Vishay Vishay www.national.com 26 LM5642/LM5642X Physical Dimensions inches (millimeters) unless otherwise noted 28-Lead TSSOP Package Order Number LM5642MTC, LM5642XMT NS Package Number MTC28 28-Lead eTSSOP Package Order Number LM5642MH, LM5642XMH NS Package Number MXA28A 27 www.national.com LM5642/LM5642X High Voltage, Dual Synchronous Buck Converter with Oscillator Synchronization Notes THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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