LM7171QML Very High Speed, High Output Current, Voltage Feedback Amplifier
October 20, 2010
LM7171QML Very High Speed, High Output Current, Voltage Feedback Amplifier
General Description
The LM7171 is a high speed voltage feedback amplifier that has the slewing characteristic of a current feedback amplifier; yet it can be used in all traditional voltage feedback amplifier configurations. The LM7171 is stable for gains as low as +2 or −1. It provides a very high slew rate at 4100V/μs and a wide unity-gain bandwidth of 200 MHz while consuming only 6.5 mA of supply current. It is ideal for video and high speed signal processing applications such as HDSL and pulse amplifiers. With 100 mA output current, the LM7171 can be used for video distribution, as a transformer driver or as a laser diode driver. Operation on ±15V power supplies allows for large signal swings and provides greater dynamic range and signal-tonoise ratio. The LM7171 offers low SFDR and THD, ideal for ADC/DAC systems. In addition, the LM7171 is specified for ±5V operation for portable applications. The LM7171 is built on National's advanced VIP® III (Vertically integrated PNP) complementary bipolar process.
Features
(Typical Unless Otherwise Noted) ■ Easy-To-Use Voltage Feedback Topology ■ Very High Slew Rate: 2400V/μs ■ Wide Unity-Gain Bandwidth: 200 MHz ■ −3 dB Frequency @ AV = +2: 220 MHz ■ Low Supply Current: 6.5 mA ■ High Open Loop Gain: 85 dB ■ High Output Current: 100 mA ■ Specified for ±15V and ±5V Operation ■ Available with radiation guarantee — Total Ionizing Dose — ELDRS Free
300 krad(Si) 300 krad(Si)
Applications
■ ■ ■ ■ ■ ■ ■ ■
HDSL and ADSL Drivers Multimedia Broadcast Systems Professional Video Cameras Video Amplifiers Copiers/Scanners/Fax HDTV Amplifiers Pulse Amplifiers and Peak Detectors CATV/Fiber Optics Signal Processing
Ordering Information
NS Part Number LM7171AMJ-QML LM7171AMJFQMLV HIGH DOSE RATE (Note 5) LM7171AMWFQMLV HIGH DOSE RATE (Note 5) LM7171AMWFLQMLV ELDRS FREE (Note 14) LM7171AMWG-QML LM7171AMWGFQMLV HIGH DOSE RATE (Note 5) LM7171AMWGFLQV ELDRS FREE (Note 14) SMD Part Number 5962-9553601QPA 5962F9553601VPA 300 krad(Si) 5962F9553601VHA 300 krad(Si) 5962F9553602VHA 300 krad(Si) 5962-9553601QXA 5962F9553601QXA 300 krad(Si) 5962F9553602VXA 300 krad(Si) NS Package Number J08A J08A W10A W10A WG10A WG10A WG10A Package Description 8LD Ceramic Dip 8LD Ceramic Dip 10LD Ceramic Flatpack 10LD Ceramic Flatpack 10LD Ceramic SOIC 10LD Ceramic SOIC 10LD Ceramic SOIC
VIP® is a registered trademark of National Semiconductor Corporation.
© 2010 National Semiconductor Corporation
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LM7171QML
Connection Diagrams
8-Pin Ceramic DIP 10-Pin Ceramic SOIC & Ceramic Flatpack
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Top View
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Top View
Simplified Schematic Diagram
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Note: M1 and M2 are current mirrors.
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Typical Performance
Large Signal Pulse Response AV = +2, VS = ±15V
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Absolute Maximum Ratings (Note 1)
Supply Voltage (V+–V−) Differential Input Voltage (Note 10) Maximum Power Dissipation (Note 2) Output Short Circuit to Ground (Note 6) Storage Temperature Range Thermal Resistance (Note 13) θJA 8LD Ceramic Dip (Still Air) 8LD Ceramic Dip (500LF/Min Air flow) 10LD Ceramic Flatpack (Still Air) 10LD Ceramic Flatpack (500LF/Min Air flow) 10LD Ceramic SOIC (Still Air) 10LD Ceramic SOIC (500LF/Min Air flow) θJC 8LD Ceramic Dip 10LD Ceramic Flatpack 10LD Ceramic SOIC (Note 3) Package Weight (Typical) 8LD Ceramic Dip 10LD Ceramic Flatpack 10LD Ceramic SOIC Maximum Junction Temperature (Note 2) ESD Tolerance (Note 4) 106°C/W 53°C/W 182°C/W 105°C/W 182°C/W 105°C/W 3°C/W 5°C/W 5°C/W 965mg 235mg 230mg 150°C 3000V (Note 1) 5.5V ≤ VS ≤ 36V 36V ±10V 730mW Continuous −65°C ≤ TA ≤ +150°C
Recommended Operating Conditions
Supply Voltage Operating Temperature Range
−55°C ≤ TA ≤ +125°C
Quality Conformance Inspection
Mil-Std-883, Method 5005 - Group A Subgroup 1 2 3 4 5 6 7 8A 8B 9 10 11 12 13 14 Description Static tests at Static tests at Static tests at Dynamic tests at Dynamic tests at Dynamic tests at Functional tests at Functional tests at Functional tests at Switching tests at Switching tests at Switching tests at Settling time at Settling time at Settling time at Temp °C 25 125 -55 25 125 -55 25 125 -55 25 125 -55 25 125 -55
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LM7171 (±15) Electrical Characteristics DC Parameters
DC: Symbol VIO +IIB -IIB IIO CMRR PSRR AV (Note 5) The following conditions apply, unless otherwise specified. TJ = 25°C, V+ = +15V, V− = −15V, VCM = 0V, and RL > 1MΩ Parameter Input Offset Voltage Input Bias Current Input Bias Current Input Offset Current Common Mode Rejection Ratio Power Supply Rejection Ratio Large Signal Voltage Gain VCM = ±10V VS = ±15V to ±5V RL = 1KΩ, VO = ±5V RL = 100Ω, VO = ±5V VO Output Swing RL = 1KΩ RL = 100Ω Output Current (Open Loop) Sourcing RL = 100Ω Sinking RL = 100Ω IS Supply Current (Note 8) (Note 8) (Note 8) (Note 8) (Note 7) (Note 7) (Note 7) (Note 7) −4.0 −6.0 85 70 85 80 80 75 75 70 13 12.7 10.5 9.5 105 95 -95 -90 8.5 9.5 -13 -12.7 -9.5 -9.0 Conditions Notes Min −1.0 −7.0 Max 1.0 7.0 10 12 10 12 4.0 6.0 Units mV mV µA µA µA µA µA µA dB dB dB dB dB dB dB dB V V V V mA mA mA mA mA mA Subgroups 1 2, 3 1 2, 3 1 2, 3 1 2, 3 1 2, 3 1 2, 3 1 2, 3 1 2, 3 1 2, 3 1 2, 3 1 2, 3 1 2, 3 1 2, 3
AC Parameters
AC: Symbol SR GBW Slew Rate
(Note 5) The following conditions apply, unless otherwise specified. TJ = 25°C, V+ = +15V, V− = −15V, VCM = 0V, and RL > 1MΩ Parameter Conditions AV = 2, VI = ±2.5V 3nS Rise & Fall time Notes (Note 11), (Note 9) (Note 12) Min 2000 170 Max Units V/µS MHz Subgroups 4 4
Unity-Gain Bandwidth
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DC Drift Parameters (Note 5) The following conditions apply, unless otherwise specified.
DC: TJ = 25°C, V+ = +15V, V− = −15V, VCM = 0V, and RL > 1MΩ Delta calculations performed on QMLV devices at group B , subgroup 5. Symbol VIO +IBias -IBias Parameter Input Offset Voltage Input Bias Current Input Bias Current Conditions Notes Min -250 -500 -500 Max 250 500 500 Units µV nA nA Subgroups 1 1 1
LM7171 (±5) Electrical Characteristics DC Parameters
DC: Symbol VIO +IIB -IIB IIO CMRR AV (Note 5) The following conditions apply, unless otherwise specified. TJ = 25°C, V+ = +5V, V− = −5V, VCM = 0V, and RL > 1MΩ Parameter Input Offset Voltage Input Bias Current Input Bias Current Input Offset Current Common Mode Rejection Ratio Large Signal Voltage Gain VCM = ±2.5V RL = 1KΩ, VO = ±1V RL = 100Ω, VO = ±1V VO Output Swing RL = 1KΩ RL = 100Ω Output Current (Open Loop) Sourcing RL = 100Ω Sinking RL = 100Ω IS Supply Current (Note 8) (Note 8) (Note 8) (Note 8) (Note 7) (Note 7) (Note 7) (Note 7) −4.0 −6.0 80 70 75 70 72 67 3.2 3.0 2.9 2.8 29 28 -29 -27.5 8.0 9.0 -3.2 -3.0 -2.9 -2.75 Conditions Notes Min −1.5 −7.0 Max 1.5 7.0 10 12 10 12 4.0 6.0 Units mV mV µA µA µA µA µA µA dB dB dB dB dB dB V V V V mA mA mA mA mA mA Subgroups 1 2, 3 1 2, 3 1 2, 3 1 2, 3 1 2, 3 1 2, 3 1 2, 3 1 2, 3 1 2, 3 1 2, 3 1 2, 3 1 2, 3
DC Drift Parameters (Note 5) The following conditions apply, unless otherwise specified.
DC: TJ = 25°C, V+ = +5V, V− = −5V, VCM = 0V, and RL > 1MΩ Delta calculations performed on QMLV devices at group B , subgroup 5. Symbol VIO +IBias -IBias Parameter Input Offset Voltage Input Bias Current Input Bias Current Conditions Notes Min -250 -500 -500 Max 250 500 500 Units µV nA nA Subgroups 1 1 1
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Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature), θJA (package junction to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperature is PDmax = (TJmax - TA)/ θJA or the number given in the Absolute Maximum Ratings, whichever is lower. Note 3: The package material for these devices allows much improved heat transfer over our standard ceramic packages. In order to take full advantage of this improved heat transfer, heat sinking must be provided between the package base (directly beneath the die), and either metal traces on, or thermal vias through, the printed circuit board. Without this additional heat sinking, device power dissipation must be calculated using θJA, rather than θJC, thermal resistance. It must not be assumed that the device leads will provide substantial heat transfer out the package, since the thermal resistance of the leadframe material is very poor, relative to the material of the package base. The stated θJC thermal resistance is for the package material only, and does not account for the additional thermal resistance between the package base and the printed circuit board. The user must determine the value of the additional thermal resistance and must combine this with the stated value for the package, to calculate the total allowed power dissipation for the device. Note 4: Human body model, 1.5 kΩ in series with 100 pF. Note 5: Pre and post irradiation limits are identical to those listed under AC and DC electrical characteristics except as listed in the Post Radiation Limits Table. These parts may be dose rate sensitive in a space environment and demonstrate enhanced low dose rate effect. Radiation end point limits for the noted parameters are guaranteed only for the conditions as specified in MIL-STD-883, per Test Method 1019, Condition A. Note 6: Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150°C. Note 7: Large signal voltage gain is the total output swing divided by the input signal required to produce that swing. For VS = ±15V, VOUT = ±5V. For VS = ±5V, VOUT = ±1V. Note 8: The open loop output current is guaranteed, by the measurement of the open loop output voltage swing, using 100Ω output load. Note 9: Slew Rate measured between ±4V. Note 10: Differential input voltage is applied at VS = ±15V. Note 11: See AN00001 for SR test circuit. Note 12: See AN00002 for GBW test circuit. Note 13: All numbers apply for packages soldered directly into a PC board. Note 14: Pre and post irradiation limits are identical to those listed under AC and DC electrical characteristics except as listed in the Post Radiation Limits Table. Low dose rate testing has been peformed on a wafer-by-wafer basis, per Test Method 1019, Condition D of MIL-STD-883, with no enhanced low dose rate sensitivity (ELDRS).
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Typical Performance Characteristics
Supply Current vs Supply Voltage
unless otherwise noted, TA= 25°C Supply Current vs Temperature
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Input Offset Voltage vs Temperature
Input Bias Current vs Temperature
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Short Circuit Current vs Temperature (Sourcing)
Short Circuit Current vs Temperature (Sinking)
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Output Voltage vs Output Current
Output Voltage vs Output Current
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CMRR vs Frequency
PSRR vs Frequency
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PSRR vs Frequency
Open Loop Frequency Response
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Open Loop Frequency Response
Gain-Bandwidth Product vs Supply Voltage
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Gain-Bandwidth Product vs Load Capacitance
Large Signal Voltage Gain vs Load
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Large Signal Voltage Gain vs Load
Input Voltage Noise vs Frequency
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Input Voltage Noise vs Frequency
Input Current Noise vs Frequency
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Input Current Noise vs Frequency
Slew Rate vs Supply Voltage
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Slew Rate vs Input Voltage
Slew Rate vs Load Capacitance
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Open Loop Output Impedance vs Frequency
Open Loop Output Impedance vs Frequency
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Large Signal Pulse Response AV = −1, VS = ±15V
Large Signal Pulse Response AV = −1, VS = ±5V
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Large Signal Pulse Response AV = +2, VS = ±15V
Large Signal Pulse Response AV = +2, VS = ±5V
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Small Signal Pulse Response AV = −1, VS = ±15V
Small Signal Pulse Response AV = −1, VS = ±5V
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Small Signal Pulse Response AV = +2, VS = ±15V
Small Signal Pulse Response AV = +2, VS = ±5V
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Closed Loop Frequency Response vs Supply Voltage (AV = +2)
Closed Loop Frequency Response vs Capacitive Load (AV = +2)
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Closed Loop Frequency Response vs Capacitive Load (AV = +2)
Closed Loop Frequency Response vs Input Signal Level (AV = +2)
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Closed Loop Frequency Response vs Input Signal Level (AV = +2)
Closed Loop Frequency Response vs Input Signal Level (AV = +2)
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Closed Loop Frequency Response vs Input Signal Level (AV = +2)
Closed Loop Frequency Response vs Input Signal Level (AV = +4)
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Closed Loop Frequency Response vs Input Signal Level (AV = +4)
Closed Loop Frequency Response vs Input Signal Level (AV = +4)
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Closed Loop Frequency Response vs Input Signal Level (AV = +4)
Total Harmonic Distortion vs Frequency (Note 15)
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Total Harmonic Distortion vs Frequency (Note 15)
Undistorted Output Swing vs Frequency
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Undistorted Output Swing vs Frequency
Undistorted Output Swing vs Frequency
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Harmonic Distortion vs Frequency
Harmonic Distortion vs Frequency
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Maximum Power Dissipation vs Ambient Temperature
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Note 15: The THD measurement at low frequency is limited by the test instrument.
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Application Notes LM7171 Performance Discussion
The LM7171 is a very high speed, voltage feedback amplifier. It consumes only 6.5 mA supply current while providing a unity-gain bandwidth of 200 MHz and a slew rate of 4100V/μs. It also has other great features such as low differential gain and phase and high output current. The LM7171 is a true voltage feedback amplifier. Unlike current feedback amplifiers (CFAs) with a low inverting input impedance and a high non-inverting input impedance, both inputs of voltage feedback amplifiers (VFAs) have high impedance nodes. The low impedance inverting input in CFAs and a feedback capacitor create an additional pole that will lead to instability. As a result, CFAs cannot be used in traditional op amp circuits such as photodiode amplifiers, I-toV converters and integrators where a feedback capacitor is required.
Layout Consideration
PRINTED CIRCUIT BOARDS AND HIGH SPEED OP AMPS There are many things to consider when designing PC boards for high speed op amps. Without proper caution, it is very easy to have excessive ringing, oscillation and other degraded AC performance in high speed circuits. As a rule, the signal traces should be short and wide to provide low inductance and low impedance paths. Any unused board space needs to be grounded to reduce stray signal pickup. Critical components should also be grounded at a common point to eliminate voltage drop. Sockets add capacitance to the board and can affect high frequency performance. It is better to solder the amplifier directly into the PC board without using any socket. USING PROBES Active (FET) probes are ideal for taking high frequency measurements because they have wide bandwidth, high input impedance and low input capacitance. However, the probe ground leads provide a long ground loop that will produce errors in measurement. Instead, the probes can be grounded directly by removing the ground leads and probe jackets and using scope probe jacks. COMPONENT SELECTION AND FEEDBACK RESISTOR It is important in high speed applications to keep all component leads short. For discrete components, choose carbon composition-type resistors and mica-type capacitors. Surface mount components are preferred over discrete components for minimum inductive effect. Large values of feedback resistors can couple with parasitic capacitance and cause undesirable effects such as ringing or oscillation in high speed amplifiers. For the LM7171, a feedback resistor of 510Ω gives optimal performance.
LM7171 Circuit Operation
The class AB input stage in the LM7171 is fully symmetrical and has a similar slewing characteristic to the current feedback amplifiers. In the LM7171 Simplified Schematic, Q1 through Q4 form the equivalent of the current feedback input buffer, RE the equivalent of the feedback resistor, and stage A buffers the inverting input. The triple-buffered output stage isolates the gain stage from the load to provide low output impedance.
LM7171 Slew Rate Characteristic
The slew rate of the LM7171 is determined by the current available to charge and discharge an internal high impedance node capacitor. This current is the differential input voltage divided by the total degeneration resistor RE. Therefore, the slew rate is proportional to the input voltage level, and the higher slew rates are achievable in the lower gain configurations. A curve of slew rate versus input voltage level is provided in the “Typical Performance Characteristics”. When a very fast large signal pulse is applied to the input of an amplifier, some overshoot or undershoot occurs. By placing an external resistor such as 1 kΩ in series with the input of the LM7171, the bandwidth is reduced to help lower the overshoot.
Compensation for Input Capacitance
The combination of an amplifier's input capacitance with the gain setting resistors, adds a pole that can cause peaking or oscillation. To solve this problem, a feedback capacitor with a value CF > (RG × CIN)/RF can be used to cancel that pole. For the LM7171, a feedback capacitor of 2 pF is recommended. Figure 1 illustrates the compensation circuit.
Slew Rate Limitation
If the amplifier's input signal has too large of an amplitude at too high of a frequency, the amplifier is said to be slew rate limited; this can cause ringing in time domain and peaking in frequency domain at the output of the amplifier. In the “Typical Performance Characteristics” section, there are several curves of AV = +2 and AV = +4 versus input signal levels. For the AV = +4 curves, no peaking is present and the LM7171 responds identically to the different input signal levels of 30 mV, 100 mV and 300 mV. For the AV = +2 curves, slight peaking occurs. This peaking at high frequency (>100 MHz) is caused by a large input signal at high enough frequency that exceeds the amplifier's slew rate. The peaking in frequency response does not limit the pulse response in time domain, and the LM7171 is stable with noise gain of ≥+2.
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FIGURE 1. Compensating for Input Capacitance
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Power Supply Bypassing
Bypassing the power supply is necessary to maintain low power supply impedance across frequency. Both positive and negative power supplies should be bypassed individually by placing 0.01 μF ceramic capacitors directly to power supply pins and 2.2 μF tantalum capacitors close to the power supply pins.
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FIGURE 4. Improperly Terminated Signal To minimize reflection, coaxial cable with matching characteristic impedance to the signal source should be used. The other end of the cable should be terminated with the same value terminator or resistor. For the commonly used cables, RG59 has 75Ω characteristic impedance, and RG58 has 50Ω characteristic impedance.
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Driving Capacitive Loads
Amplifiers driving capacitive loads can oscillate or have ringing at the output. To eliminate oscillation or reduce ringing, an isolation resistor can be placed as shown below in Figure 5. The combination of the isolation resistor and the load capacitor forms a pole to increase stability by adding more phase margin to the overall system. The desired performance depends on the value of the isolation resistor; the bigger the isolation resistor, the more damped the pulse response becomes. For LM7171, a 50Ω isolation resistor is recommended for initial evaluation. Figure 6 shows the LM7171 driving a 150 pF load with the 50Ω isolation resistor.
FIGURE 2. Power Supply Bypassing
Termination
In high frequency applications, reflections occur if signals are not properly terminated. Figure 3 shows a properly terminated signal while Figure 4 shows an improperly terminated signal.
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FIGURE 3. Properly Terminated Signal
FIGURE 5. Isolation Resistor Used to Drive Capacitive Load
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= (6.5 mA) × (30V) + (10 mA) × (15V − 10V) = 195 mW + 50 mW = 245 mW
Application Circuit
Fast Instrumentation Amplifier
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FIGURE 6. The LM7171 Driving a 150 pF Load with a 50Ω Isolation Resistor
Power Dissipation
The maximum power allowed to dissipate in a device is defined as: PD = (TJ(max) − TA)/θJA Where PD is the power dissipation in a device TJ(max) is the maximum junction temperature TA is the ambient temperature is the thermal resistance of a particular package θJA For example, for the LM7171 in a Ceramic SOIC package, the maximum power dissipation at 25°C ambient temperature is 680 mW. Thermal resistance, θJA, depends on parameters such as die size, package size and package material. The smaller the die size and package, the higher θJA becomes. The 8-pin DIP package has a lower thermal resistance (106°C/W) than that of the Ceramic SOIC (182°C/W). Therefore, for higher dissipation capability, use an 8-pin DIP package. The total power dissipated in a device can be calculated as: PD = PQ + PL PQ is the quiescent power dissipated in a device with no load connected at the output. PL is the power dissipated in the device with a load connected at the output; it is not the power dissipated by the load. Furthermore, PQ: = supply current × total supply voltage with no load PL: = output current × (voltage difference between supply voltage and output voltage of the same side of supply voltage) For example, the total power dissipated by the LM7171 with VS = ±15V and output voltage of 10V into 1 kΩ is PD = PQ + PL Multivibrator
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Pulse Width Modulator
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Video Line Driver
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Revision History
Released 02/04/09 Revision A Section New Release, Corporate format Changes 1 MDS data sheet converted into one Corp. data sheet format. Added ELDRS NSID's to Ordering Information Table. MNLM7171AM-X-RH Rev 0C0 will be archived.
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Physical Dimensions inches (millimeters) unless otherwise noted
10-Lead Ceramic Flatpack NS Package Number W10A
10-Lead Ceramic SOIC NS Package Number WG10A
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8-Lead Dual-In-Line Package NS Package Number J08A
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LM7171QML Very High Speed, High Output Current, Voltage Feedback Amplifier
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