LM9040M

LM9040 Dual Lambda Sensor Interface Amplifier August 1995 LM9040 Dual Lambda Sensor Interface Amplifier General Description The LM9040 is a dual sensor interface circuit consisting of two independent sampled input differential amplifiers designed for use with conventional Lambda Oxygen Sensors The Lambda Sensor is used for monitoring the oxygen concentration in the exhaust of gasoline engines using catalytic after treatment and will deliver a voltage signal which is dependent on the air-fuel mixture The gain of the amplifiers are internally set and can directly convert the Lambda sensor output voltage to a level suitable for A D conversion in a system using a 5V reference The input common mode voltage range of each amplifier is g 2V with respect to the IC ground pin This will allow the IC to connect to sensors which are remotely grounded at the engine exhaust manifold or exhaust pipe Each amplifier is capable of independent default operation should either or both of the leads to a sensor become open circuited Noise filtering is provided by an internal switched capacitor low pass filter as part of each amplifier and by external components The LM9040 is fully specified over the automotive temperature range of b40 C to a 125 C and is provided in a 14-pin Small Outline surface mount package Features Y Y Y Y Y Y Y Y Y Y Single 5V supply operation Common mode input voltage range of g 2V Differential input voltage range of 50 mV to 950 mV Sampled differential input Switched capacitor low pass filter Internal oscillator and VBB generator Open input default operation Cold sensor default operation Low power consumption (42 mW max) Gain set by design and guaranteed over the operating temperature range Applications Y Y Closed loop emissions control Catalytic converter monitoring Connection Diagram TL H 12372 – 1 Top View Ordering Information LM9040M See NS Package Number M14B C1995 National Semiconductor Corporation TL H 12372 RRD-B30M115 Printed in U S A Absolute Maximum Ratings If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage b 0 3V to a 6 0V g 14V Input Voltage Continuous (Note 1) g 60V Input Voltage Transient t s 1 ms (Note 1) g 2000V ESD Susceptibility (Note 2) Maximum Junction Temperature 150 C b 65 C to a 150 C Storage Temperature Range Lead Soldering Information Vapor Phase (60 Seconds) 215 C Infrared (15 Seconds) 220 C Operating Ratings Supply Voltage Differential Input Voltage Common Mode Voltage Power Dissipation 4 75V to 5 25V 0V to a 1V g 2V 42 mW DC Electrical Characteristics The following specifications apply for VCC e 5 0V VDIFF e 500 mV VCM e 0V ROSC e 178 kX b40 C s TA s a 125 C DC Test Circuit Figure 1 unless otherwise specified Symbol ICC ZDIFF ZIO VOL VOC VOUT(ERROR) VOH ROUT CMRR(DC) TRISE TFALL FC Parameter Supply Current Differential Input Impedance Inverting Input to Ground Impedance Output Low Voltage VOUT Center (VOUT)– (VDIFF  4 53) Output High Voltage Output Resistance DC Common Mode Error Output Rise Time Output Fall Time Low Pass Filter b3 dB b 2V s VCM s a 2V Conditions 4 75V s VCC s 5 25V 4 75V s VCC s 5 25V Non-Inverting Inputs Open VDIFF e 0V ILOAD e 2 0 mA One or Both Input(s) Open 4 75V s VCC s 5 25V 50 mV s VDIFF s 950 mV VCM e 0V VDIFF e 5V ILOAD e b2 mA Min Max 80 Units mA Meg X Meg X 1 05 10 00 1 60 100 VCC  0 380 VCC  0 425 g 65 mV V mV V VCC b 0 1V 1500 3500 g4 5 X mV V ms ms Hz COUT e 0 01 mF COUT e 0 01 mF COUT e 0 01 mF 400 12 12 700 Note 1 The input voltage must be applied through external 4 kX input resistors See Figure 2 AC Test Circuit Amplifier operation will be disrupted but will not be destructive Note 2 ESD rating is with Human Body Model 100 pF discharged through a 1500X resistor TL H 12372 – 3 TL H 12372–2 FIGURE 1 DC Test Circuit FIGURE 2 AC Test Circuit 2 Typical Performance Characteristics Supply Current vs Temperature FCLOCK (Normalized) vs ROSC FCLOCK (Normalized) vs VCC TL H 12372–4 TL H 12372 – 5 TL H 12372 – 6 Output R vs Temperature ZDIFF vs Temperature FC vs Temperature TL H 12372–7 TL H 12372 – 8 TL H 12372 – 9 Voltage Gain vs Frequency PSRR vs Frequency CMRR vs Frequency TL H 12372–10 TL H 12372 – 11 TL H 12372 – 12 3 Circuit Description The LM9040 is fabricated in CMOS technology and is designed to operate from a single well regulated 5V supply The IC consists of two independent differential amplifiers which are designed using two-phased switched capacitor networks (SCN) The differential inputs have a common mode operating range of 2V above and below ground The SCN includes the input sampling the lowpass filter cold sensor bias voltage and the gain circuitry Each amplifier has an independent voltage comparator to detect an open inverting input pin Additional support circuitry includes the oscillator clock generator and VBB bias generator The oscillator resistor should be located as close to the OSC RES pin as possible Any variation of the oscillator resistor value any stray capacitance on the OSC RES pin or any changes in the supply voltage will result in a change in the oscillator frequency This will directly affect the device Differential Input Impedance and Low Pass filter response Additional circuitry takes the oscillator signal and generates two non-overlapping clock signals and a CLK OUT signal The clock signals operate at one half the oscillator frequency or typically 100 kHz This results in a Nyquist frequency of typically 50 kHz Clock Out Clock In For the input stage to work with common mode voltages below Ground potential a negative bias voltage (VBB) is needed The CLK OUT pin is used to provide the AC signal needed to drive the internal VBB bias generator through an external coupling capacitor A minimum coupling capacitor value of 100 pF to a maximum value of 0 1 mF is recommended The CLK IN pin is the input to the VBB bias generator circuitry Differential Input Circuit The input stage can be best described as a switched Sample and Difference circuit (see Figure 4 ) When the input capacitor CIN is switched to the non-inverting input the input voltage plus the common mode voltage is stored on CIN When CIN is switched to the inverting input CIN will be discharged by an amount equal to the common mode voltage The remaining charge across CIN will be equal to the differential input voltage and a proportional charge will be transferred through the virtual ground via the gain stage TL H 12372 – 14 FIGURE 4 Simplified Switched Capacitor Input Circuit TL H 12372–13 FIGURE 3 Simplified Circuit Oscillator The device contains an internal oscillator which is used to drive the internal two-phase clock generator The oscillator requires an external resistor value of 178 kX from the ‘‘OSC RES’’ pin to device VCC This resistor value determines the charge rate of the internal capacitor and thus sets the oscillator frequency The internal oscillator capacitor is matched to the switched capacitor networks so that the absolute capacitance values are not as important as is the absolute ratios of the capacitors The oscillator frequency is approximately 200 kHz 4 Differential Input Circuit (Continued) The differential input impedance is a function of the value of the input capacitor array and the sampling frequency The capacitor CBIAS is used to generate a bias voltage across the Differential Input impedance (ZDIFF) This bias voltage is similar to the Lambda Sensor output voltage at the stoichiometric air-fuel mixture (l e 1) The bias voltage is set by the ratio of CIN and CBIAS and the value of VCC The resulting bias voltage across the Differential Input is defined as VCC  CBIAS (CIN a CBIAS) With CBIAS e 0 7286 pF CIN e 7 421 pF FCLOCK e 100 kHz and VCC e 5V 5  7 286E-13 VBIAS e (7 4213E-12 a 7 286E-13) VBIAS e 447 mV In effect the result is the same as forcing a bias current through the Differential Input impedance The bias current is defined as VBIAS e IBIAS e VCC  CBIAS  FCLOCK IBIAS e 364 3 nA The Differential Input impedance is defined as 1 ZDIFF e (CIN a CBIAS)  FCLOCK ZDIFF e 1 227 MX This bias voltage will be developed across the Differential Input impedance (ZDIFF) if there is no other path available from the non-inverting input pin for IBIAS and the inverting input has a current path to ground See Figure 5 During normal operating conditions IBIAS will have a negligible effect on accuracy Differential Input Filtering Since each input is sampled independently an anti-aliasing filter is required at the amplifier inputs to ensure that the input signal does not exceed the Nyquist frequency This external low-pass filter is implemented by adding a capacitor (CDIFF) across the differential input See Figure 6 This forms an RC network across the differential inputs in conjunction with the required external 4 kX resistors and the differential input impedance (ZDIFF) The capacitor selected should be small enough to have minimal effect on gain accuracy in the application yet large enough to filter out unwanted noise Given that the FC of the LM9040 is typically 500 Hz the use of a 0 01 mF capacitor will generally provide adequate filtering with less than b0 4 dB of input attenuation at 500 Hz and approximately b28 dB at 50 kHz A larger value capacitor can be used if needed but a value larger than typically 0 02 mF will begin to dominate the cutoff frequency of the application This capacitor must be a low leakage and low ESR type so that circuit performance is not degraded TL H 12372 – 16 FIGURE 6 Differential and Common Mode Filtering Common Mode Filtering The differential input sampling of the LM9040 actually reduces the effects of common mode input noise at low frequencies The time interval between the sampling of the inverting input and the non-inverting input is one half of a clock period A change in the common mode voltage during this short time interval can cause an error in the charge stored on CIN This will result in an error seen on the output voltage For a sine-wave common mode voltage the minimum common mode rejection is CMRR e 2  q  FCMR  (0 5 FCLOCK)  4 53 Where FCMR is the frequency of the common mode signal and FCLOCK is the clock frequency TL H 12372 – 15 FIGURE 5 Equivalent Input Bias Circuit 5 Common Mode Filtering (Continued) For a common mode sine wave signal having a frequency 100 Hz and with a FCLOCK of 100 kHz the minimum common mode rejection would be CMRR e 2  3 14159  100  5E-6  4 53 CMRR e 0 014 e b37 dB If the common mode sine wave has a peak to peak value of 2V the maximum voltage error at the output would be VOUT(CM) e 2V  0 014 e 28 mV As this formula shows the value of VOUT(CM) is proportional to the frequency of the CMR signal If the frequency is doubled the value of VOUT(CM) is also doubled The addition of a small bypass capacitor (CCM) from the non-inverting input to ground will help counter this problem See Figure 6 However the use of this bypass capacitor creates a new problem in that the differential input is no longer balanced While the Lambda sensor is cold (i e RSENSOR l 10 MegX) there is little difference in CMR performance As the Lambda sensor heats to the operating temperature and the sensor resistance decreases the common mode signal is no longer applied to both inputs equally This imbalance causes VOUT(CM) to increase as RSENSOR decreases as the noninverting input will see the full common mode signal while the non-inverting input will see an attenuated common mode signal The selection of the value of the CMR bypass capacitor needs to be balanced with the need for reasonable reduction or elimination of common mode signals with both cold and hot sensors Since normal operation will need to include consideration of the entire impedance range of the sensor a trade off in overall application performance may be needed Generally the value of the CMR bypass capacitor should be kept as low as possible and should not be larger than the differential input filter capacitor Values in the range of 0 001 mF to 0 01 mF will usually provide reasonable CMR results but optimum results will need to be determined empirically as the source of common mode signals will be unique to each application TL H 12372 – 17 FIGURE 7 Simplified Gain and Filter Circuit The internal gain is set by the ratio of CIN and CFB CIN GAINDC e CFB 7 4213 pF e 4 53 V V GAINDC e 1 6383 pF The corner frequency (b3 dB) is set by the ratio of CFB and CINT and by FCLOCK FCLOCK  CFB FC e 2  q  CINT 1E5  1 6383E-12 e e 500 Hz FC 2  3 14159  52 1E-12 Gain and Filter Stage The signal gain and filter stage is designed to have a DC gain of 4 53 V V with a cut-off frequency of typically 500 Hz The external 4 kX resistors on each input pin are in series with the differential input impedance Together they form a voltage divider circuit across the input such that the net DC gain of the application circuit is 4 50 V V TL H 12372 – 18 FIGURE 8 Equivalent Gain and Filter Circuit 6 Cold Sensor Typically a Lambda sensor will have an impedance of less than 10 kX when operating at temperatures between 300 C and 500 C When a Lambda sensor is not at operating temperature its impedance can be more than 10 MegX Any voltage signal that may be developed is seriously attenuated During this high impedance condition the LM9040 will provide a default output voltage Open Input Pins Defaults In any remote sensor application it is desirable to be able to deal with the possibility of open connections between the sensor and the control module The LM9040 is capable of providing an output voltage scaled to VCC should either or both of the wires to the Lambda sensor open The two inputs handle the open circuit condition differently The LM9040 will provide a default VOUT that is typically 2 025V when VCC is at 5V For the case of an open connection of the non-inverting input the device would react the same as for the Cold Sensor condition The internal bias voltage across ZIN would cause the output voltage to be at a value defined by VCC and the LM9040 DC gain The inverting input would still be connected to the Lambda sensor ground so any common mode signals would still need to be allowed for in this condition See Figure 9 For the case of an open connection of the inverting input the device output stage switches from the amplifier output to a resistive voltage divider In this case the default VOUT is not dependent on the gain stage and any signal on the non-inverting input will have no effect on the output Each amplifier has a comparator to monitor the voltage on the inverting input pin When the voltage on an inverting pin goes above typically 2 5V the comparator will switch the output from the amplifier output to the voltage divider stage To fully implement this function requires external pull-up resistors for each of the inverting inputs To minimize signal errors due to DC currents through the 4 kX resistors the pull-up resistors need to be added in the application circuit between the 4 kX input resistor and the connection to the Lambda sensor ground point A typical pull-up value of 51 kX to VCC is recommended During this condition the effective resistance of the output stage will be 3 5 kX typically See Figure 10 TL H 12372 – 19 FIGURE 9 VOUT with Cold Lambda Sensor Each amplifier input has a bias charge applied across the Differential Input impedance (ZDIFF) by means of charge redistribution through the switched capacitor network This bias charge is a ratio of VCC and is typically 447 mV for a VCC value of 5 00V This will provide an output voltage of typically 2 025V While the Lambda sensor is high impedance the 447 mV across ZDIFF will be the dominant input signal As the Lambda sensor is heated and the sensor impedance begins to drop the voltage signal from the sensor will become the dominate signal Output Resistance With normal operation each output has typically 2 5 kX of resistance This resistance along with an external capacitor form a RC low pass filter to remove any clock noise from the output signal An external output filter capacitor value of 0 01 mF is recommended Additionally the output resistance will provide current limiting for the output stage should it become shorted to Ground or VCC Any DC loading of the output will cause an error in the measured output voltage This error will be equal to the I  R drop across the output resistance VERROR e ILOAD  2 5 kX TL H 12372 – 20 FIGURE 10 VOUT with Open Inverting Input 7 Open Input Pins Defaults (Continued) In the cases where both the inverting and non-inverting pins are open the non-inverting condition (i e voltage divider across the output) will be the dominant condition Any common mode signal seen by inverting input pin should not be allowed to exceed the Common Mode voltage range Exceeding the positive Common Mode voltage limit could cause the inverting input pin voltage comparator to act as if the inverting input pin is open Since the comparator circuit is not part of the switched capacitor network there is no frequency limitation on the signal to the comparator Any transient on the inverting input pin which goes above the comparator threshold will immediately cause the output to switch to the open sensor mode The output will return to normal operation when the voltage on the inverting input falls below the comparator threshold Supply Bypassing For best performance the LM9040 requires a VCC supply which is stable and noise free The same 5V VREF supply used for the A D converter is the recommended VCC supply During operation the device will generate current spikes coincident with the clock edges Inadequate bypassing will cause excessive clock noise on the outputs as well as noise on the VCC line The LM9040 VCC pin should be bypassed with a minimum 0 1 mF capacitor to the Signal Ground pin and should be located as close to the device as possible Some applications may require an additional 4 7 mF tantalum capacitor especially if there are several other switched capacitor devices running off the same 5V supply line The Signal and Digital Ground pins should be tied together as close to the device as possible TL H 12372 – 21 FIGURE 11 Typical Application 8 9 LM9040 Dual Lambda Sensor Interface Amplifier Physical Dimensions inches (millimeters) 14-Lead (0 300 Wide) Molded Small Outline Package JEDEC Order Number LM9040M NS Package Number M14B LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user National Semiconductor Corporation 1111 West Bardin Road Arlington TX 76017 Tel 1(800) 272-9959 Fax 1(800) 737-7018 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor Europe Fax (a49) 0-180-530 85 86 Email cnjwge tevm2 nsc com Deutsch Tel (a49) 0-180-530 85 85 English Tel (a49) 0-180-532 78 32 Fran ais Tel (a49) 0-180-532 93 58 Italiano Tel (a49) 0-180-534 16 80 National Semiconductor Hong Kong Ltd 13th Floor Straight Block Ocean Centre 5 Canton Rd Tsimshatsui Kowloon Hong Kong Tel (852) 2737-1600 Fax (852) 2736-9960 National Semiconductor Japan Ltd Tel 81-043-299-2309 Fax 81-043-299-2408 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications