LM9627

LM9627 Color CMOS Imag e S ensor VGA 30 F PS March 2001 LM9627 Color CMOS Image Sensor VGA 30 FPS General Description The LM9627 is a high performance, low power, third inch VGA CMOS Active Pixel Sensor capable of capturing color digital still or motion images and converting them to a digital data stream. In addition to the active pixel array, an on-chip 12 bit A/D convertor, fixed pattern noise elimination circuits and a video gain amplifier is provided. Furthermore, an integrated programmable smart timing and control circuit allows the user maximum flexibility in adjusting integration time, active window size, gain and frame rate. Various control, timing and power modes are also provided. Applications • • • • • • PC Camera Digital Still Camera Video Conferencing Security Cameras Toys Machine Vision Key Specifications • Array Format • Effective Image Area Total: 664H x 504V Active: 648H x 488V Total: 4.98mm x 3.78 mm Active: 4.86 mm x 3.66 mm 1/3“ 7.5µm x 7.5 µ m 8,10 & 12 Bit Digital 57dB 0.35% red green blue • Quantum Efficiency • Fill Factor • Color Mosaic • Package • Single Supply • Power Consumption • Operating Temp 14.5 kLSBs/lux.s 7.5 kLSBs/lux.s 5.1 kLSBs/lux.s 27% 47% (no micro lens) Bayer pattern 48 LCC 3.3 V 90 mW 0 to 50o C Features • • • • • • • • • • Supplied with micro lenses Video or snapshot operations Programmable pixel clock, inter-frame and inter-line delays. Programmable partial or full frame integration Programmable gain adjustment Horizontal & vertical sub-sampling (2:1 & 4:2) Windowing External snapshot trigger & event synchronisation signals Auto black level compensation Flexible digital video read-out supporting programmable: - polarity for synchronisation and pixel clock signals - leading edge adjustment for horizontal synchronization • Optical Format • Pixel Size • Video Outputs • Dynamic Range • FPN • Sensitivity • Programmable via 2 wire I2C compatible serial interface • Power on reset & power down mode System Block Diagram Storage lens LM9627 12bit digital image Digital Image Processor I2 C compatible event trigger snapshot ©2000 National Semiconductor Corporation Confidential www.national.com L M 962 7 Overall Chip Block Diagram Bad Pixel Detect & Correct Horizontal Shift Register Column CDS Black Lev el Compensation Digital Video Framer d[11:0] pclk hsync vsync Row Address Decoder APS Array POR Reset Gen Row Address Gen Vertical Timing AMP 12 Bit A/D Horizontal Timing Gain Control Register Bank I2C Compatible Serial I/F sda sclk sadr Clock Gen Controller (sequencer) Master Timer Power Control mclk extsync snapshot irq pdwn Figure 1. Chip Block Diagram Connection Diagram vdd_od1 vss_od1 vdd_od3 vss_od3 ex tsy nc vdd_pix vsrvdd sadr sda 6 sclk snapshot resetb pdwn vss_dig vdd_dig hsync vsync pclk mclk d0 NC 7 8 9 10 11 12 13 14 15 16 17 18 5 4 3 2 1 48 47 46 45 44 43 42 41 40 39 NC fine_i gnd fine_ctrl offset vdd_ana1 vss_ana1 vref_adc vss_ana2 vdd_ana2 vss_od2 vdd_od2 LM9627 48 PIN LCC 31 19 20 21 22 23 24 25 26 27 28 29 30 NC d1 d9 d2 d3 d4 d5 d6 d7 d8 d10 d11 Ordering Information Temperature (0°C ≤ TA ≤ + 50°C) LM9627 CCEA NS Package LCC Confidential 2 NC 38 37 36 35 34 33 32 irq vrl www.national.com L M 96 27 Typical Application Circuit System Control Camera Control Serial Control Bus 16 mclk 9 resetb 10 pdwn 4 irq 8 sna psh ot 48 extsync 7 sclk 6 sda 5 sadr 3.3V analog 3.3V analog 37 vdd_ana1 0.1 F µ vdd_ana2 33 vss_ana2 34 3.3V digital 0.1µ F 36 vss_ana1 3.3V digital 47 vdd_od1 0.1 F µ vdd_od2 31 vss_od2 32 46 vss_od1 0.1µF 3.3V digital 3.3Vdigital 44 vdd_od3 45 vss_od3 vdd_dig 12 0.1 F µ 0.1 F µ vss_dig 11 3.3V analog 3 vdd_pix 2 vrl LM9627 vsrvdd 1 1.0 F µ 0.1 F µ 3.3V analog vdd_ana vdd_ana 1.5k Ω 35 820Ω 0.1µF vref_adc fine_i 41 fine_ctrl 39 1N4148 22k Ω 1% 2N3904 10k Ω 1% 18 19 42 43 NC NC NC NC hsync vsync pclk d1 0 d11 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1.2k Ω 1% offset 38 4.7 µ F 470 Ω 1% gnd 40 13 14 15 30 29 28 27 26 25 24 23 22 21 20 17 Digital Video Bus Figure 2. Typical Application Diagram Scan Read Out Direction pin 1 (0,0) v e rtica l s c an (0,0) digital out (0,0) horizontal scan lens CMOS Image Sensor Figure 3. Scan directions and position of origin in imaging system Confidential 3 www.national.com L M 962 7 Pin Descriptions Pin 1 2 3 4 Name vsrvdd vrl vdd_pix irq I/O I0 I I O Typ P A P D Description Analog bidirectional, it should be connect to ground via a 1.0µ f capacitor. This pin is the internal charge pump voltage source. Anti blooming pin. This pin is normally tied to ground. 3.3 volt supply for the pixel array. Digital output, the interrupt request pin. This pin generates interrupts during snapshot mode. Digital input with pull down resistor. This pin is used to program different slave addresses for the sensor in an I2 C compatible system. I2 C compatible serial interface data bus. The output stage of this pin has an open drain driver. I2 C compatible serial interface clock. Digital input with pull down resistor used to activate (trigger) a snapshot sequence. Digital input with pull up resistor. When forced to a logic 0 the sensor is reset to its default power up state. The resetb signal is internally synchronized to mclk which must be running for a reset to occur. Digital input with pull down resistor. When forced to a logic 1 the sensor is put into power down mode. 0 volt power supply for the digital circuits. 3.3 volt power supply for the digital circuits. Digital Bidirectional. This is a dual mode pin. When the sensor’s digital video port is configured to be a master, (the default), this pin is an output and is the horizontal synchronization pulse. When the sensor’s digital video port is configured to be a slave, this pin is an input and is the row trigger. Digital Bidirectional. This is a dual mode pin. When the sensor’s digital video port is configured to be a master, (the default), this pin is an output and is the vertical synchronization pulse. When the sensor’s digital video port is configured to be a slave, this pin is an input and is the frame trigger. Digital output. The pixel clock. Digital input. The sensor’s master clock input. Digital output. Bit 0 of the digital video output bus. This output can be put into tri-state mode. Pin not used, do not connect. Pin not used, do not connect. O D Digital output. Bit 1 of the digital video output bus. This output can be put into tri-state mode. Digital output. Bit 2 of the digital video output bus. This output can be put into tri-state mode. Digital output. Bit 3 of the digital video output bus. This output can be put into tri-state mode. Digital output. Bit 4 of the digital video output bus. This output can be put into tri-state mode. Digital output. Bit 5 of the digital video output bus. This output can be put into tri-state mode. Digital output. Bit 6 of the digital video output bus. This output can be put into tri-state mode. 5 sadr I D 6 7 8 sda sclk snapshot IO I I D D D 9 resetb I D 10 11 12 pdwn vss_dig vdd_dig I I I D P P 13 hsync IO D 14 vsync IO D 15 16 17 18 19 20 pclk mclk d0 NC NC d1 O I O D D D 21 d2 O D 22 d3 O D 23 d4 O D 24 d5 O D 25 d6 O D Confidential 4 www.national.com L M 96 27 Pin Descriptions (Continued) Pin 26 Name d7 I/O O Typ D Description Digital output. Bit 7 of the digital video output bus. This output can be put into tri-state mode. Digital output. Bit 8 of the digital video output bus. This output can be put into tri-state mode. Digital output. Bit 9 of the digital video output bus. This output can be put into tri-state mode. Digital output. Bit 10 of the digital video output bus. This output can be put into tri-state mode. Digital output. Bit 11 of the digital video output bus. This output can be put into tri-state mode. 3.3 volt supply for the digital IO buffers. 0 volt supply for the digital IO buffers 3.3 volt supply for analog circuits. 0 volt supply for analog circuits. A/D reference resistor ladder voltage. See figure 4 for equivalent circuit. 0 volt supply for analog circuits. 3.3 volt supply for analog circuits. Analog input used to adjust the offset of the sensor. See figure 4 for equivalent circuit. Analog output used to drive the offset pin. This pin must be tied to ground. I A Bias current for the fine offset adjust. Pin not used, do not connect. Pin not used, do not connect. I I I I O P P P P D 3.3 volt supply for the sensor. 0 volt supply for the sensor. 0 volt supply for the digital IO buffers 3.3 volt supply for the digital IO buffers. Digital output. The external event synchronization signal is used to synchronize external events in snapshot mode. 27 d8 O D 28 d9 O D 29 d10 O D 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 d11 vdd_od2 vss_od2 vdd_ana2 vss_ana2 vref_adc vss_ana1 vdd_ana1 offset fine_ctrl gnd fine_i NC NC vdd_od3 vss_od3 vss_od1 vdd_od1 extsync O I I I I I I I I O D P P P P A P P A A Legend: (I=Input), (O=Output), (IO=Bi-directional), (P=Power), (D=Digital), (A=Analog ). adc_vref 800Ω offset 1K Ω 200Ω Figure 4. Equivalent Circuits For adc_ref and offset pins Confidential 5 www.national.com L M 962 7 Absolute Maximum Ratings (Notes 1 & 2) Any Positive Supply Voltage 6.5V Voltage On Any Input or Output Pin -0.5V to 6.5V Input Current at any pin (Note 3) ±25mA ESD Susceptibility (Note 5) Human Body Model 2000V Machine Model 200V Package Input Current (Note 3) ±50mA Package Power Dissipation @ TA (Note 4) 2.5W Soldering Temperature Infrared, 10 seconds (Note 6) 220°C Storage Temperature -40°C to 125°C Operating Ratings ( Notes 1 & 2) Operating Temperature Range All VDD Supply Voltages Voltage Range on vref_adc pin Voltage Range on offset pin 0°C ≤T≤+50°C +3.15V to +3.6V +0.6V to +1.0V +0.04V to +0.4V DC and logic level specifications The following specifications apply for all VDD pins= +3.3V. Boldface limits apply for TA = TMIN to TMAX : all other limits TA = 2 5o C (Note 7) Symbol Parameter Conditions Min note 9 Typical note 8 Max note 9 Units sclk, sda, sadr, Digital Input/Output Characteristics VIH VIL VOL Vhys Ileak Logical “1” Input Voltage Logical “0” Input Voltage Logical “0” Output Voltage Hysteresis (SCLK pin only) Input Leakage Current vdd_od = +3.15V, Iout=3.0mA vdd_od = +3.15V Vin=vss_od 0.05*vdd_o d -1 0.7* vdd_od -0.5 vdd_od+0.5 0.3* vdd_od 0.5 V V V V mA mclk, snapshot, pdwn, resetb, hsync, vsync Digital Input Characteristics VIH VIL IIH IIL Logical “1” Input Voltage Logical “0” Input Voltage Logical “1” Input Current Logical “0” Input Current vdd_dig = +3.6V vdd_dig = +3.15V VIH = vdd_dig VIL = vss_dig 0.1 -1 2.0 0.8 V V mA mA d0 - d11, pclk, hsync, vsync, extsync, irq, Digital Output Characteristics VOH VOL IOZ IOS Logical “1” Output Voltage Logical “0” Output Voltage TRI-STATE Output Current Output Short Circuit Current vdd_od=3.15V, Iout=-1.6mA vdd_od=3.15V, Iout =-1.6mA VOUT = vss_od VOUT = vdd_od -0.1 0.1 +/-17 2.2 0.5 V V mA mA mA Power Supply Characteristics IA ID Analog Supply Current Digital Supply Current Power down mode, no clock. Operational mode in dark Power down mode, no clock. Operational mode in dark 700 19 300 7 mA mA mA mA Power Dissipation Specifications The following specifications apply for All VDD pins = +3.3V. Boldface limits apply for TA = T MIN to TMAX : all other limits TA = 25 o C. Symbol Pdwn PWR Parameter Power Down Average Power Dissipation Conditions no clock running mclk = 48Mhz & sensors default settings in dark. Min note 9 Typical note 8 5 90 Max note 9 Units mW mW Confidential 6 www.national.com L M 96 27 Video Amplifier Specifications The following specifications apply for all VDD pins= +3.3V. Boldface limits apply for TA = TMIN to TMAX : all other limits TA = 25oC. Symbol Parameter Video Amplifier Nominal Gain Conditions 64 linear steps Min note 9 Typical note 8 0-15 Max note 9 Units dB AC Electrical Characteristics The following specifications apply for All VDD pins = +3.3V. Boldface limits apply for T A = TMIN to T MAX: all other limits TA = 25 o C. Symbol Fmclk Tch Tcl Parameter Input Clock Frequency Clock High Time Clock Low Time Clock Duty Cycle Trc , Tfc Fhclk Treset FRM rate Note 1: Clock Input Rise and Fall Time Internal System Clock Frequency Reset pulse width Frame Rate 1.0 1.0 1 30 @ CLKmax @ CLKmax @ CLKmax Conditions Min note 9 12 10 10 45/55 3 14.0 Typical note 8 Max note 9 48 45 45 55/45 Units MHz ns ns min/max ns MHz µs fps Note 2: Note 3: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. All voltages are measured with respect to VSS = vss_ana = vss_od = vss_dig = 0V, unless otherwise specified. When the voltage at any pin exceeds the power supplies (VIN < VSS or VIN > VDD), the current at that pin should be limited to 25mA. The 50mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25mA. The absolute maximum junction temperature (TJmax) for this device is 125 o C. The maximum allowable power dissipation is dictated by TJmax, the junction-to-ambient thermal resistance (ΘJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax - TA)/ ΘJA. In the 48-pin LCC, ΘJA is 38.5 o C/W, so PDMAX = 2.5W at 25o C and 1.94W at the maximum operating ambient temperature of 50oC. Note that the power dissipation of this device under normal operation will be well under the PDMAX of the package. Human body model is 100pF capacitor discharged through a 1.5kΩ resistor. Machine model is 220pF discharged through ZERO Ohms. See AN450, “Surface Mounting Methods and Their Effect on Product Reliability”, or the section entitled “Surface Mount” found in any post 1986 National Semiconductor Linear Data Book, for other methods of soldering surface mount devices. The analog inputs are protected as shown below. Input voltage magnitude up to 500mV beyond the supply rails will not damage this device. However, input errors will be generated If the input goes above AV+ and below AGND. VDD Note 4: Note 5: Note 6: Note 7: Pad IOP Internal Circuits VSS Note 8: Note 9: Typical figures are at TJ = 25o C, and represent most likely parametric norms. Test limits are guaranteed to National's AOQL (Average Outgoing Quality Level). Confidential 7 www.national.com L M 962 7 CMOS Active Pixel Array Specifications Parameter Number of pixels (column, row) Total Active Array size (x,y Dimensions) Total Active Pixel Pitch Fill Factor (without micro-lens) Value 664 x 504 648 x 488 4.98 x 3.78 4.86 x 3.66 7.5 47 Units pixels pixels mm mm µ % Image Sensor Specifications The following specifications apply for All VDD pins = +3.3V, TA = 2 5o C, Illumination Color Temperature = 2850 o K, IR cutoff filter at 700nm, mclk = 48MHz, frame rate = 30Hz, vref_adc = 0.6 volt, video gain 0dB. Parameter Optical Sensitivity @ A/D output red green blue Optical Sensitivity @ A/D input red green blue Dynamic Range Read Noise Offset Fixed Pattern Noise RMS value of pixel FPN in dark as a percentage of full scale. RMS variation of pixel sensitivities as a percentage of the average sensitivity. Conditions Min Typical note 1 14.5 7.5 5.1 2.12 1.1 0.75 57 5.3 0.35 Max Units kLSBs/(lux.s) volt/(lux.s) dB LSBs % Sensitivity Fixed Pattern Noise 1 % Note 1: Typical figures are at TJ = 25o C, and represent most likely parametric norms. Confidential 8 www.national.com L M 96 27 Sensor Response Curves 8.00E+02 red 7.00E+02 Spectral sensitivity [V/((W/m^2)*s)] 6.00E+02 green 5.00E+02 blue 4.00E+02 3.00E+02 2.00E+02 1.00E+02 0.00E+00 370 420 470 520 570 620 670 720 770 820 wavelength [nm] Figure 5. Spectral Response Curve A/D o utpu t c od e 5000 4000 ADC output code [LSBs] 3000 green 2000 red blue 1000 0 0 0.1 0.2 0.3 Exposure [lux.s] 0.4 0.5 0.6 Figure 6. Linearity Response Curve Confidential 9 www.national.com L M 962 7 Functional Description 1.0 OVERVIEW 0-15dB Video AMP 1.1 Light Capture and Conversion The LM9627 contains a CMOS active pixel array consisting of 648 rows by 488 columns. This active region is surrounded by 8 columns and 8 rows of optically shielded (black) pixels as shown in Figure7. 648 columns, 488 rows color (Bayer pattern) active pixels 8 columns, 8 rows black pixels 12 Bit A/D Analog pixel values Digital pixel data Figure 9: Analog Signals Conditioning & Conversion to Digital The digital pixel data is further processed to: • remove defects due to bad pixels, • compensate black level, before being framed and presented on the digital output port. (see Figure 10). do[11:0] pclk hsync vsync Black Level Compensation 8 columns, 8 rows black pixels Figure 10. Digital Pixel Processing. Figure 7: CMOS APS region of the LM9627 The color filters are Bayer pattern coded starting at row 8 and column 8. (rows 0 to 7 & columns 0 to 7 are black). The color coding is green, red, green, red until the end of row 8, then blue, green, blue, green until the end or row 9 and so on (see Figure 7). At the beginning of a given integration time the on-board timing and control circuit will reset every pixel in the array one row at a time as shown in Figure 8. Note that all pixels in the same row are simultaneously reset, but not all pixels in the array. abc 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 def gh i j k lmnopqr 1.2 Program and Control Interfaces The programming, control and status monitoring of the LM9627 is achieved through a two wire I2 C compatible serial bus. In addition, a slave address pin is provided (see Figure 11). Di gital Vi deo Fr amer irq extsyn snapshot Bad Pix el Cor r ection sda Register Bank I2C Compatible Serial I/F sclk sadr Line Address Figure 11. Control Interface to the LM9627. Additional control and status pins: snapshot and external event synchronization are provided allowing the latency of the serial control port to be bypassed during single frame capture. An interrupt request pin is also available allowing complex snapshot operations to be controlled via an external micro-processor (see Figure 12). CDS/Shift Register Timing Generator Analog Data Out Figure 8: CMOS APS Row and Column addressing scheme At the end of the integration time, the timing and control circuit will address each row and simultaneously transfer the integrated value of the pixel to a correlated double sampling circuit and then to a shift register as shown in Figure 8. Once the correlated double sampled data has been loaded into the shift register, the timing and control circuit will shift them out one pixel at a time starting with column “a”. The pixel data is then fed into an analog video amplifier, where a user programmed gain is applied (see Figure 9). After gain adjustment the analog value of each pixel is converted to a 12 bit digital data as shown in Figure 9. Confidential Figure 12. Snapshot & External Event Trigger Signals 10 www.national.com L M 96 27 Functional Description (continued) 2.0 WINDOWING Column/Horizontal a b c d e f g h i j k l mn o p q r 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 The integrated timing and control circuit allows any size window in any position within the active region of the array to be read out with a 1x1 pixel resolution. The window read out is called the “Display Window ”. A “ Scan Window” must be defined first, by programing the start and end row addresses as shown in Figure 13. Four coordinates (start row address, start column address, end row address & end column address) are programmed to define the size and location of the “ Display Window” to be read out (see Figure 13 ). display col display col scan row end address start address start address display row start address display row end address scan row end address Display Window Scan Window Active Pixel Array 3.2 Interlaced Readout Mode In interlaced readout mode, pixels are read out in two fields, an Odd Field followed by an Even Field. The Odd Field, consisting of all even row pairs contained within the display window, is read out first. Each pixel in the “ Odd Field ” is consecutively read out, one pixel at a time, starting with the left most pixel in the top most row pair. The Even Field, consisting of all odd row pairs contained within the display window, is then read out. Each pixel in the “Even Field ” is consecutively read out, one pixel at a time, starting with the left most pixel in the top most row pair. Column/Horizontal a b c d e f g h i j k l mn o p q r 0 1 4 5 8 9 12 13 16 17 Odd Field Column/Horizontal a b c d e f g h i j k l mn o p q r 2 3 6 7 10 11 14 15 18 19 Figure 13. Windowing Notes: • The “Display Window” must always be defined within the “Scan Window”. • A “Display Window” can only be read out in the progressive scan mode. • By default the “Display Window ” is the complete array. 2.1 Programming the scan window Two registers (SROWS & SROWE) are provided to program the size of the scan window. The start and end row address of the scan window is given by: scan row start address = (2* SwStartRow) + SwLsb scan row end address = (2* SwEndRow) + 1 + SwLsb Where: SwStartRow is the contents of the Scan Window start row register (SROWS) SwEndROW is the contents of the Scan Window end row register (SROWE) SwLsb is bit 6 of the Display Window LSB register (DWLSB) 2.2 Programming the display window Five register (DROWS, DROWE, DCOLS, DCOLE and DWLSB) are provided to program the display window as described in the register section of this datasheet. Ro w/Ve rtica l 11 R ow /Vertic al 3.0 READ OUT MODES 3.1 Progressive Scan Readout Mode In progressive scan readout mode, every pixel in every row in the display window is consecutively read out, one pixel at a time, starting with the left most pixel in the top most row. Hence, for the example shown in Figure 14, the read out order will be a0,b0,...,r0 then a1,b1,...,r1 and so on until pixel r 20 is read out. Even Field Figure 15: Interlace Read Out Mode Hence, for the example shown in Figure 15, the display window is broken up into two fields, as shown in Figure 15. Pixels a0,b0,...,r0 and a1,b1,...,r1 are readout first and so on until pixels a17,b17,...r17 in the even field are read out. The even field read out is followed by pixels in the odd field, a2,b2,...,r2 then a3,b3,...,r3 until pixels a19,b19,...,r19 Confidential R o w/Ver tic a l Figure 14: Progressive Scan Read Out Mode www.national.com L M 962 7 Functional Description (continued) 4.0 SUBSAMPLING MODES 4.2 4:2 Sub-Sampling The timing and control circuit can be programmed to sub-sample pixels in the display window vertically, horizontally or both, with an aspect ratio of 4:2 as illustrated in Figure17 Column/Horizontal a b c d e f g h i j k l mn o p q r 0 1 4.1 2:1 Sub-Sampling The timing and control circuit can be programmed to sub-sample pixels in the display window vertically, horizontally or both, with an aspect ratio of 2:1 as illustrated in Figure16. Column/Horizontal a b c d e f g h i j k l mn o p q r 0 1 2 3 4 5 6 7 8 9 a) Horizontal Sub-Sampling Column/Horizontal a b c d e f g h i j k l mn o p q r 0 1 2 3 4 5 6 7 8 9 b) Vertical Sub-Sampling Column/Horizontal ab cde f gh i j k l 0 1 2 3 4 5 6 7 8 9 c) Horizontal & Vertical Sub-Sampling Green Pixel Not Read Out Figure 16: Example of 2:1 Sub-sampling Red Pixel Blue Pixel R ow /Ver tic al Ro w/Ve rtica l 2 3 4 5 6 7 8 9 a) Horizontal Sub-sampling Column/Horizontal a b c d e f g h i j k l mn o p q r 0 1 2 3 4 5 6 7 8 9 b) Vertical Sub-sampling Column/Horizontal a b c d e f g h i j k l mn o p q r 0 1 2 3 4 5 6 7 8 9 c) Horizontal & Vertical Sub-sampling Green Pixel Not Read Out Figure 17: Example 4:2 Sub-sampling Red Pixel Blue Pixel R ow /Vertic al lnopqr Row/Vertical 12 Confidential R ow /Ver tic al Row/Vertical www.national.com L M 96 27 Functional Description (continued) 5.0 SNAPSHOT MODE The LM9627 is capable of capturing a single frame of an image under hardware or software control, with or without the aid of an external shutter. Two registers, SNAPSHOTMODE0 & SNAPSHOTMODE1, are provided to program, monitor and control all snapshot sequences. 5.1 Software Controlled Snapshots The snapshot mode events can be software controlled by writing to and reading from the snapshot mode registers over the I2C compatible interface. 5.2 Hardware Controlled Snapshots Two dedicated pins are provided on the LM9627, snapshot & extsync , allowing the snapshot mode events to be controlled by hardware. The snapshot pin must be enabled by writing to the SnapEnable bit of the MCFG0 register. 5.3 Auto Snapshot Mode In auto snapshot mode (see figure 20), upon the receipt of a snapshot o r FTriggerNow trigger signal, the integrated timing and control circuit will set the FTriggerEN bit and generate an internal TRIGGER signal (see figure 19), thus resetting the array one row at a time. At end of the reset cycle the timing and control circuit will signal the shutter to open via extsync pin or FtSync bit. At the end of the programmed integration time the shutter will be signalled to close, and the pixel read-out will commence as shown in figure 18a. At the end of the read-out sequence the FTriggerEN will be automatically reset and the sensor will return to video capture mode as shown in figure 20. If an external shutter is not available then at least two frames need to be taken so that the pixels can be integrated over one frame as shown in Figure 18b. To use auto snapshot mode the SsEngage bit of the SNAPSHOTMODE1 register must be set to zero. Capture Data image read-out Array reset, programmable 1 to 4 frames snapshot or FTriggerNow note 1 note 2 irq FTriggerEn extsync or FtSync FtBusy note 3 Start Snapshot Sequence Start of Array Reset Frames Open Shutter Close shutter & start read-out Read-out complete a) With External Shutter Array reset, Capture Data programmable 1 to 4 frames image read-out snapshot or FTriggerNow note 1 note 2 irq FTriggerEn extsync or FtSync FtBusy note 3 Start Snapshot sequence Start of Array Reset Frames Integration Start Start Read-out Read-out Complete b) Without External Shutter Note 1: Note 2: Note 3: This wave form shows the snapshot pin programmed to the default pulse mode. The irq pulse is taken low when the snapshot trigger interrupt flag (SsTrigFlag) in the snapshot mode1 ( SNAPMODE1) register is read. The irq pulse is taken low when the snapshot trigger interrupt flag (SsRdFlag ) in the snapshot mode1 (SNAPMODE1 ) register is read. Bold external pins italic register bits Figure 18. Snapshot Mode Confidential 13 www.national.com L M 962 7 Functional Description (continued) snapshot SnapShotPol SnapEnable c : Ss R dFla g && ( Sn ap sh otMod | | ( Sn ap sh otMod && TR IG GER )) FTriggerNow Figure 19. Snapshot Trigger Generation Logic TRIGGER VIDEO c:TRIGGER==1 VIDEO c: Snap sh otMod || ( Snap sh otMod && TR IGGER ) IRQ a: SsTrigFlag =1 c:TRIGGER==1 c:FTriggerEn==1 SNAP a:FTriggerEn=1 SNAP PREVIEW a:FTriggerEn=0 PREVIEW a: SsRdFlag = 1 a: FtTriggerEn = 0 Figure 20. Auto Snapshot Mode State Diagram 5.4 CPU Snapshot Mode In CPU snapshot mode, the FTriggerEN is not set automatically and an Interrupt generator can be enabled. Hence, upon the receipt of a snapshot o r FTriggerNow trigger signal, the integrated timing and control circuit will generate an internal TRIGGER signal as shown in figure 19 and then wait in the IRQ state for the FTriggerEN bit to be manually set as shown in figure 21. Once the FtriggerEn bit is set the integrated timing and control circuit will start resetting the array one row at a time. At end of the reset cycle the timing and control circuit will signal the shutter to open via extsync pin or FtSync bit. At the end of the programmed integration time the shutter will be signalled to close, and the pixel read-out will commence as shown in figure 18a. At the end of the read-out sequence the FTriggerEN will be automatically disabled and the sensor will return to video capture mode as shown in figure 20. If an external shutter is not available then at least two frames need to be taken so that the pixels can be integrated over one frame as shown in Figure 18b. To use CPU snapshot mode the SsEngage bit of the SNAPSHOTMODE1 register must be set to one. An interrupt generator can be enabled in CPU snapshot mode by setting the SnapIntEn bit of SNAPSHOTMODE1 register. An interrupt will be generated on the external interrupt pin, irq, when a snapshot sequence is triggered (TRIGGER=1) or when the array readout is complete at the end of the snapshot sequence as shown figure 21. Confidential Figure 21. CPU Snapshot Mode State Diagram When an interrupt is generated by a TRIGGER event, the SsTrigFlag bit in the SNAPSHOTMODE1 register is set. Similarly when an interrupt is generated at the completion of a readout the SsRdFlag in the SNAPSHOTMODE1 register is set. The polarity of the irq pin can be programmed. The interrupt can only be cleared by reading SsTrigFlag and the SsRdFlag as shown in figure 22. SsTrigFlag SsRdFlag SnapIntEn IrqPol Figure 22. Interrupt Request Generation Logic 5.5 Pulse & Level Trigger Mode The snapshot pin can be programmed to operate in pulse trigger mode where one snapshot sequence is executed per active pulse or in level trigger mode where by snapshot sequences are repeated as long as the level on the snapshot pin is held active. (see figures 20 and 21). Pulse and level trigger modes can be set by programming the SnapshotMod bit in the SNAPSHOTMODE0 register. irq 14 www.national.com L M 96 27 Functional Description (continued) 6.0 CLOCK GENERATION MODULE The number of rows in a scan window is given by: SWN rows = (RADend - RADstart) + 1 Where: RADend RADstart The LM9627 contains a clock generation module that will create two clocks as follows: Hclk, the horizontal clock. This is an internal system clock and can be programmed to be the input clock (mclk) or mclk divided by any number between 1 and 255. CLKpixel the pixel clock. This is the external pixel clock that appears at the digital video port. It can be Hclk or Hclk divided by 2. This clock cannot be programed. is the end row address of the defined scan window. (See section 2.1) is the start row address of the defined scan window. (Scan section 2.1). The number of H clk clocks required to process a full frame is given by: FN Hclk = [ (Mfactor * SWN rows ) + Fdelay ] * R NHclk Where: Mfactor 7.0 FRAME RATE PROGRAMING A frame is defined as the time it takes to reset every pixel in the array, integrate the incident light, convert it to digital data and present it on the digital video port. This is not a concurrent process and is characterized in a series of events each needing a certain amount of time as shown in Figure 23. Start is a Mode Factor which must be applied. It is dependent on the selected mode of operation as shown in the table below: Progressive Scan 1 0.5 Row address = 0 Sub-sampling or Interlace Row delay time SWN rows is the Number of Rows in Selected Scan Window. Fdelay a programmable value between 0 & 4097 representing the Inter Frame Delay in multiples of RN Hclk . This parameter allows the frame time to be extended. (See the Frame Delay High and Frame Delay Low registers). The frame rate is given by: Frame Rate = Hclk FN Hclk Transfer all pixels to CDS Ro w Time Reset all pixels in row Shift all pixels out of row Row address + 1 Yes 7.2 Partial Frame Integration In some cases it is desirable to reduce the time during which the pixels in the array are allowed to integrate incident light without changing the frame rate. No This is known as Partial Fame Integration and can be achieved by resetting pixels in a given row ahead of the row being selected for readout as shown in Figure 24. The number of Hclk clocks required to process a partial frame is given by: FPHclk = R N Hclk * Itime Where: RN Hclk Itime is the number of Hclk clock cycles required to process & shift out one row of pixels. is the number of rows ahead of the current row Last row? Figure 23. Frame Readout Flow Diagram 7.1 Full Frame Integration Full frame integration is when each pixel in the array integrates light incident on it for the duration of a frame (see Figure 24). The number of Hclk clock cycles required to process & shift out one row of pixels is given by: RN Hclk = R opcycle + R delay Where: R opcycle to be reset. (See the Integration Time High and Low registers). The Integration time is subject to the following limits: Mode Progressive Scan Interlace Sub-Sampled Limit Itime d[11:2] A/D [8:0] -> d[11:3] 1 OddEvenEn 0 TriState 3:0 Reserved Register Name Address Mnemonic Type Reset Value Bit 7:4 Digital Video Mode 2 08 Hex VMODE2 Read/Write 00 Hex Description Use to program the leading edge of h sync to the first valid pixel at the beginning of each row. This can be 0-hex to F-hex corresponding to 0 - 15 pixel clocks. Default 0. Reserved www.national.com Bit Symbol HsyncAdjust 3:0 Confidential 26 L M 96 27 Register Set (continued) Register Name Address Mnemonic Type Reset Value Bit 7.6 Snapshot Mode Configuration Register 0 09 Hex SNAPMODE0 Read/Write 00 Hex Description Program to set the number of frames required before readout during a snapshot with no external shutter, (see Figure 18). By default these two bits are set to 00 resulting in one frame before readout: 0 01 10 11 5 ShutterEn one frame two frames three frames four frames 5 SsRdFlag 7 Register Name Address Mnemonic Type Reset Value Bit Snapshot Mode Configuration Register 1 0A Hex SNAPMODE1 Read/Write 00 Hex. Description Assert to enable the snapshot interrupt generator. Clear (the default) to disable the interrupt generator. (Read Only Bit) Snapshot trigger interrupt flag. A logic 1 in this bit indicates that the generated interrupt on the irq pin is due to a snapshot trigger. This bit is cleared when read. (Read Only Bit) Snapshot read done interrupt flag. A logic 1 in this bit indicates that the generated interrupt on the i rq pin is due to the completion of a snapshot readout sequence. This bit is cleared when read. Assert to allow a CPU controlled snapshot sequence. In this mode the snapshot trigger will only generate an interrupt to the CPU and the CPU must manually start the snapshot sequence by asserting the FTriggerEn bit of this register. Clear (the default) engage an automatic snapshot sequence. In auto mode the snapshot sequence is started as soon as a snapshot trigger is asserted. (Read Only Bit) The internal synchronisation signal. A logic 1 on this bit indicates a synchronization event is required. This bit is functionally equivalent to the external extsync pin. (Read Only Bit) The Frame Trigger Busy bit. A logic 1 on this bit indicates that the sensor is busy reading out pixel data as shown in Figure 18. Assert to start a snapshot sequence. The frame trigger now is functionally equivalent to the external snapshot pin. The default is 0. Assert to enable a snapshot sequence (see the SsEngage bit of this register). The default is 0. Bit Symbol SsFrames Bit Symbol SnapIntEn 6 SsTrigFlag Assert to indicate that an external shutter will be used during snapshot mode. Clear (the default) to indicate that snapshot mode will be carried out without the aid of an external shutter. Assert to set the active level of the extsync signal to 0. Clear (the default) to set the active level of the extsync signal to 1. Reserved 4 SsEngage 4 ExtSynPol 3 2 SnapshotMod Assert to set the snapshot pin to level mode. In level mode the sensor will continually run snapshot sequences as long as the snapshot pin is held to the active level. Clear (the default) to set the snapshot signal to pulse mode. In pulse mode the sensor will only carry out one snapshot sequence per pulse applied to the snapshot pin. Assert to set the snapshot pin to be active on the positive edge. Clear (the default) to set the snapshot pin to be active on the negative edge. Assert to set the active level of the irq signal to 0, Clear (the default) to set the active level of the irq signal to 1. 3 FtSync 1 SnapShotPol 2 FtBusy 0 IrqPol 1 FTriggerNow 0 FTriggerEn Confidential 27 www.national.com L M 962 7 Register Set (continued) Register Name Address Mnemonic Type Reset Value Bit 7:0 Scan Window Row Start Register 0B Hex SROWS Read/Write 00 Hex Description Use to program the scan window’s start row address MSBs. If bit 6 of register DWLSB is set to 1 the start row address is incremented by 1 else the raw value is used. Register Name Address Mnemonic Type Reset Value Bit 7:0 Display Window Column Start Register 10 Hex DCOLS Read/Write 00 Hex Description Use to program the display window’s start column address MSBs. The two LSBs can be programmed using the DWLSB register. Bit Symbol SwStartRow Bit Symbol DwStartCol Register Name Address Mnemonic Type Reset Value Bit 7:0 Scan Window Row End Register 0C Hex SROWE Read/Write FB Hex Description Use to program the scan window’s end row address MSBs. If bit 6 of register DWLSB is set to 1 the end row address is incremented by 1. else the raw value is used. Register Name Address Mnemonic Type Reset Value Bit 7:0 Display Window Column End Register 11 Hex DCOLE Read/Write A5 Hex Description Use to program the scan window’s end column address MSBs. The two LSBs can be programmed using the DWLSB register. Bit Symbol SwEndRow Bit Symbol DwEndCol Register Name Address Mnemonic Type Reset Value Bit 7:0 Display Window Row Start Register 0E Hex DROWS Read/Write 00 Hex Description Use to program the display window’s start row address MSBs. The LSB can be programmed using the DWLSB register. Register Name Address Mnemonic Type Reset Value Bit 7 6 Display Window LSB register 12 Hex DWLSB Read/Write 32 Hex Description Reserved Bit Symbol Bit Symbol DwStartRow SwLsb Assert to increment the value of the scan window start and end row addresses by 1. Clear (the default) to use the raw values. Use to program bit 1 of the display window’s end column address. Default is 1. Use to program bit 0 of the display window’s end column address. Default is 1. Use to program bit 1 of the display window’s start column address. Default is 0. Use to program bit 0 of the display window’s start column address. Default is 0. Use to program bit 0 of the display window’s end row address. Default is 1. Use to program bit 0 of the display window’s start row address. Default is 0. Register Name Address Mnemonic Type Reset Value Bit 7:0 Display Row End Register 0F Hex DROWE Read/Write FB Hex Description Use to program the scan window’s end row address. The LSB can be programmed using the DWLSB register. 5 DwCel[1] 4 DwCel[0] Bit Symbol DwEndRow 3 DwCSL[1] 2 DwCSL [0] 1 DwERLsb 0 DwSRLsb Confidential 28 www.national.com L M 96 27 Register Set (continued) Register Name Address Mnemonic Type Reset Value Bit 7:4 3:0 Itime[11:8] Integration Time High Register 13 Hex ITIMEH Read/Write 00 Hex. Description Reserved Program to set the integration time of the array. The value programmed in the register is the number of rows ahead of the selected row to be reset. Register Name Address Mnemonic Type Reset Value Bit 7:0 Frame Delay Low Register 18 Hex FDELAYL Read/Write 00 Hex Description Use to program the LSBs of the frame delay. Bit Symbol Bit Symbol FDelay [7:0] Register Name Address Mnemonic Type Reset Value Bit 7:6 5:0 Video Gain Register 19 Hex VGAIN Read/Write 00 Hex Description Reserved Register Name Address Mnemonic Type Reset Value Bit 7:0 Integration Time Low Register 14 Hex ITIMEL Read/Write 00 Hex. Description Program to set the integration time of the array. The value programmed in the register is the number of rows ahead of the selected row to be reset. Bit Symbol VidGain Bit Symbol Itime[7:0] Use to program the overall video gain. 00hex corresponds to a gain of 0dB while 3Fhex corresponds to a gain of 15dB. Steps are in linear increments. Register Name Address Mnemonic Type Reset Value Bit 7:3 2:0 Row Delay High Register 15 Hex RDELAYH Read/Write 00 Hex. Description Reserved Register Name address Mnemonic Type Reset Value Bit 7:0 Offset Compensation Register 0 1FHex OCR0 Read/Write 00 Hex Description This register defines the voltage level appearing on the offset_ctrl pin. Bit Symbol OffsetVol Bit Symbol Rdelay[10:8] Use to program the MSBs of the row delay. Register Name Address Mnemonic Type Reset Value Bit 7:0 Row Delay Low Register 16 Hex RDELAYL Read/Write 00 Hex Description Use to program the LSBs of the row delay. Register Name address Mnemonic Type Reset Value Bit 7:0 Offset Compensation Register 1 22 Hex OCR1 Read/Write 00 Hex Description This register defines the voltage level appearing on the offset_ctrl pin. Bit Symbol OffsetVol Bit Symbol Rdelay[7:0] Register Name Address Mnemonic Type Reset Value Bit 7:4 3:0 Frame Delay High Register 17 FDELAYH Read/Write 00 Hex Description Reserved Register Name address Mnemonic Type Reset Value Bit 7:0 Offset Compensation Register 2 25 Hex OCR2 Read/Write 00 Hex Description This register defines the voltage level appearing on the offset_ctrl pin. Bit Symbol OffsetVol Bit Symbol FDelay[11:8] Use to program the MSBs of the frame delay. Confidential 29 www.national.com L M 962 7 Register Set (continued) Register Name Black Level Register Address 26 Hex Mnemonic BLCOEFF Type Read/Write Reset Value 00 Hex Bit 7:0 Bit Symbol Alpha[7:0] Compensation Coefficient Description Exponential averaging coefficient for black pixels Register Name Address Mnemonic Type Reset Value Bit 7:0 Threshold 0 High Register 27 Hex BPTH0H Read/Write 00 Hex. Description Use to program the MSBs of the bad pixel correction threshold 0. Bit Symbol BpT0 [11:4] Register Name Address Mnemonic Type Reset Value Bit 7:4 Threshold 0 Low Register 28 Hex BPTH0L Read/Write 00 Hex Description Use to program the LSBs of the bad pixel correction threshold 0. Reserved Threshold 1 High Register 29 Hex BPTH1H Read/Write 00 Hex Description Use to program the MSBs of the bad pixel correction threshold 1. Bit Symbol BpT0 [3.0] 3:0 Register Name Address Mnemonic Type Reset Value Bit 7:0 Bit Symbol THR1[11.4] Register Name Address Mnemonic Type Reset Value Bit 7:4 Threshold 1 Low Register 2A Hex BPTH1L Read/Write 00 Hex Description Use to program the LSBs of the bad pixel correction threshold 1. Reserved Bit Symbol THR1 [3.0] 3:0 Confidential 30 www.national.com L M 96 27 Timing Information 1.0 pclk hsync t1 t2 DIGITAL VIDEO PORT MASTER MODE TIMING d[11:0] t3 P0 P1 Pn Figure 49. Row Timing Diagram pclk vsync t5 t6 hsync R2 t2 t1 R3 Rn Figure 50. Frame Timing pclk vsync t5 t6 hsync Fdelayn-2 Fdelayn-1 F delayn R0 R1 t1 R2 t2 Frame (n) Rn Inter Frame Delay Figure 51. Frame Delay Timing (With Inter Frame Delay). Label t0 Descriptions pclk period Min 74.4ns Typ 83.3ns Max 1.0µs t1 hsync low level mode pulse mode level mode pulse mode (116- HsyncAdjust ) *pclk 16 * pclk (664 -HsyncAdjust) *pclk 764 * pclk HsyncAdjust * pclk 116 *pclk 16 * pclk (FN Hclk - 116) * pclk 16 * pclk (see note a & b) t2 t3 t5 hsync high (see note a & b) first valid pixel data after hsync active vsync low level mode pulse mode level mode pulse mode (see note a & b) (see note a & b) t6 vsync high (see note a & b) Note a: Note b: See Frame Rate Programming section for more details See Digital Video Port Registers for more details 31 www.national.com Confidential L M 962 7 Timing Information (continued) d[11:0] hsync vsync pclk t1 t2 Figure 52. d[11:0] , hsync & vsync to Active High p clk Timing d[11:0] hsync vsync pclk t3 t4 Figure 53. d[11:0], hsync & vsync to Active Low pclk T iming The following specifications apply for all supply pins = +3.3V and C L = 10pF unless otherwise noted. Boldface limits apply for TA = TMIN to T MAX: all other limits TA = 25o C (Note 7) Label t1 t2 t3 t4 Descriptions Rising p clk to Rising hsync, vsync or d[11:0] Rising p clk to Falling hsync, vsync or d[11:0] Falling pclk to rising hsync, vsync or d[11:0] Falling pclk to falling hsync, vsync or d[11:0] Min Typ 25ns 23ns 25ns 23ns Max Confidential 32 www.national.com L M 96 27 Timing Information (continued) 2.0 DIGITAL VIDEO PORT SLAVE MODE TIMING t3 t1 hsync trigger row n t2 trigger row n+1 d[11:0] P652 P653 P654 P640 P1 P652 P653 P654 P655 mclk Row n-1 Row n Figure 54. Slave Mode Row Trigger and Readout Timing hsync trigger last row in frame n t5 vsync trigger Frame n+1 mclk t4 Figure 55. Slave Mode d[11:0] , hsync & vsync to p clk Timing d[11:0] mclk t6 Figure 56. Rising Edge of mclk to Valid Pixel Data The following specifications apply for all supply pins = +3.0V & CL = 10pF unless otherwise noted. Boldface limits apply for TA = TMIN to T MAX: all other limits TA = 25o C (Note 7) Label t1 t2 t3 t4 t5 t6 Descriptions Pulse width of row trigger First pixel out after rising edge of row trigger Minimum time between row triggers. Max time to assert next frame trigger after last row trigger. Pulse width of Frame trigger Time to valid pixel data after rising edge of mclk Min 2 * mclk 124 * mclk 780 * mclk Typ Max 124 * mclk 96 * mclk 2 * mclk 44ns Confidential 33 www.national.com L M 962 7 Timing Information (continued) 3.0 DIGITAL VIDEO PORT SINGLE FRAME CAPTURE (SNAPSHOT MODE) TIMING t1 snapshot or FTriggerNow irq FTriggerEn extsync or FtSync FtBusy t2 t3 t4 Figure 57. Snapshot Mode Timing With External Shutter t1 snapshot or FTriggerNow irq FTriggerEn extsync or FtSync FtBusy t2 t3 t4 Figure 58. Snapshot Timing Without External Shutter Label t1 t2 t3 t4 Descriptions Minimum Snapshot Trigger Pulse Width Minimum time from Snapshot Pulse to extsync Array Integration Time Pixel Read Out Equation 2 * mclk FN Hclk FN Hclk FN Hclk (see notes a & b) (see notes a & b) (see notes a & b) (see notes a & b) Note a: Note b: See 7.0 Frame Rate Programming section for more details See Snapshot Mode for more details Confidential 34 www.national.com L M 96 27 Timing Information (continued) 4.0 SERIAL BUS TIMING Sr Sr P tfDA tfDA SDA tSU;STA tHD;DAT tHD;STA tSU;DAT t SU;STO SCLK trCL trCL = Rp resistor pull-up = MCS current source pull-up (1) Rising edge of the first SCLK pulse after an acknowledge bit. Figure 59. I 2 C Compatible Serial Bus Timing. The following specifications apply for all supply pins = +3.3V, CL = 10pF, and sclk = 400KHz unless otherwise noted. Boldface limits apply for TA = TMIN to T MAX: all other limits T A = 25o C (Note 7) trCL1 trCL1 tHIGH tLOW tLOW tHIGH (1) PARAMETER sclk clock frequency Set-up time (repeated) START condition Hold time (repeated) START condition LOW period of the sclk clock HIGH period of the sclk clock Data set-up time Data hold time Set-up time for STOP condition Capacitive load for sda and sclk lines SYMBOL fSCLH tSU;STA tHD;STA tL O W tHIGH tSU;DAT tHD;DAT tSU;STO Cb MIN 0 0.6 0.6 1.3 0.6 180 0 0.6 MAX 400 0.9 UNIT KHz µS µS µS µS nS µS µS 4 00 pF Confidential 35 www.national.com L M 962 7 Array Mechanical Information .440 +/-.005 TYP [11.18 +/- 0.12] .040 +/-.003 TYP [1.02 +/- 0.07] .060 +.010 TYP -.005 [1.52 + 0.25] [- 0.12] 7 43 .085 +/-.010 [2.16 +/- 0.25] 48 1 6 42 distance from pixel (die surface) to top surface of glass lid= 0.894 mm R.0075 +/-.0050 [0.191+/- 0.127] TYP .020 +/-.003 [0.51 +/- 0.07] TYP 0.328 [8.325] Note 3 31 18 30 .040 +/-.007 TYP [1.02 +/- 0.17] Optical Center of Sensor Array .102 MAX [2.58] 0.281 [7.131] Note 3 19 (4X R.0075) [0.19] .560 +.012 -.00 5 [14. 22 + 0.30] [ - 0.12] Notes: 1. Controlling dimensions are in inches, values in [] are in millimeters 2. All Exposed metallized areas shall be gold plated 60 micro-inches [1.52 micrometers] minimum thickness over nickel plate 3. Reference dimensions only. Tolerance will depend on die placement [+/-0.1 mm]. 4. Reference JEDEC registration MS-009, variation AF issue A, dated 9/29/1980. Confidential 36 www.national.com LM9627 Color CMOS Imag e S ensor VGA 30 F PS LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support @ nsc.com www.national.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: europe.support @ nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Francais Tel: +33 (0) 1 41 91 8790 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: ap.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 N ational does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.