LM98501

LM98501 10-Bit, 27 MSPS Camera Signal Processor February 2000 LM98501 10-Bit, 27 MSPS Camera Signal Processor General Description The LM98501 is a CCD signal processor for electronic cameras. The processor provides a common interface to a number of different image sensors including CCD, CMOS, and CIS. Correlated double sampling reduces kTC noise from the image signal. A fast, temperature stable, 8-bit digitally programmable gain amplifier enables pixel-rate white-balancing. An auxiliary input is provided, allowing for the selection of an external signal, useful for electronic titling and video overlay. The 10-bit A/D converter preserves the image quality with excellent noise performance. The LM98501 also includes the supporting functions of digital black level clamp and power down, ideally suited for portable video applications. This low-power processor is a natural choice for the most demanding imaging systems. Features n n n n n n n n n +3V single power supply Low power CMOS design 4-wire serial interface 2.5V data output voltage swing No missing codes AUX input with input clamp and programmable gain Four color gain and offset registers Digital black level clamp Small 48-lead LQFP package Key Specifications j Maximum Input Level j CDS Sampling Rate j PGA Gain Steps j PGA Gain Range j ADC Resolution j ADC Sampling Rate j *Signal-to-Noise Ratio j Power Dissipation AV+ = DV+ = DV+ I/O = 3.0V j Operating Temperature Applications n n n n n n n n Digital still camera Digital video camcorder Video conferencing Security camera Plain paper copier Flatbed or handheld color scanner Video processing for x-ray or infrared Barcode scanner 1.0V peak-peak 27 MSPS 256 Steps 0.0 dB-32.0 dB 10-Bit 27 MSPS 60 dB 0 dB Gain, 1.0V Input 195 mW (typical) 0˚C to 70˚C *20 log10 (VIN/RMS Output Noise) Typical Digital Camera Block Diagram DS101292-1 © 2000 National Semiconductor Corporation DS101292 www.national.com LM98501 Overall Chip Block Diagram DS101292-2 FIGURE 1. Chip Block Diagram LM98501 Chip Pin Out DS101292-3 FIGURE 2. Pin Out Diagram Ordering Information Commercial (0˚C ≤ TA ≤ +70˚C) LM98501CCVBH NS Package LQFP www.national.com 2 LM98501 Typical Application Circuit DS101292-4 FIGURE 3. Typical Application Circuit Diagram Pin Descriptions Pin 1 2 3 4 5 6 7 8 9 10 Name AUX IN AGND VIN AGND AV+ ACLP RESET AV+ DGND DGND I I I I/O I Typ A P A P P D D P P P Auxiliary analog input. Analog ground return. Analog input. AC-couple input signal through a 0.1 µF capacitor Analog ground return. +3V power supply for the analog circuits. Bypass each supply pin with 0.1 µF and 10 µF capacitors in parallel. Analog clamp switch. Float pin when function not being used. Active-high master reset. Float pin when function not being used. +3V power supply for the analog circuits. Bypass each supply pin with 0.1 µF and 10 µF capacitors in parallel. Digital ground return. Digital ground return. Description 3 www.national.com LM98501 Pin Descriptions Pin 11 12 13 Name DV+ CLK SHP I I I/O (Continued) Typ P D D Description +3V power supply for the digital circuits. Bypass each supply pin with 0.1 µF and 10 µF capacitors in parallel. 27 MHz clock input. Correlated double sampler reset voltage clamp override. Programmable active-high or active-low through serial interface. Connect to +3V digital supply when function not being used (register values in default condition). Correlated double sampler video signal voltage sample override. Programmable active-high or active-low through serial interface. Connect to +3V digital supply when function not being used (register values in default condition). Active-high beginning of line switch input. Hold high during entire line of effective pixels. Hold low during blanking period. Active-high black level clamp switch input. Pulse high during black pixels to eliminate black pixel offset from video signal. Top of DAC reference ladder. Normally bypassed with a 0.1 µF capacitor. An external DAC reference voltage may be applied to this pin. Bottom of DAC reference ladder. Normally bypassed with a 0.1 µF capacitor. An external DAC reference voltage may be applied to this pin. Bottom of ADC reference ladder. Normally bypassed with a 0.1 µF capacitor. An external ADC reference voltage may be applied to this pin. Active-low chip enable for the serial interface. Serial interface clock used to decode the serial input data. Serial interface input port. Serial interface output port. Digital output driver ground return. +3V power supply for the digital output driver circuits. Bypass each supply pin with 0.1 µF and 10 µF capacitors in parallel. Digital output. Bit 0 of 9 (LSB) of the digital video output bus. Digital output. Bit 1 of 9 of the digital video output bus. Digital output. Bit 2 of 9 of the digital video output bus. Digital output. Bit 3 of 9 of the digital video output bus. Digital output. Bit 4 of 9 of the digital video output bus. Digital output. Bit 5 of 9 of the digital video output bus. Digital output. Bit 6 of 9 of the digital video output bus. Digital output. Bit 7 of 9 of the digital video output bus. Digital output. Bit 8 of 9 of the digital video output bus. Digital output. Bit 9 of 9 (MSB) of the digital video output bus. +3V power supply for the digital output driver circuits. Bypass each supply pin with 0.1 µF and 10 µF capacitors in parallel. Digital output driver ground return. Digital ground return. +3V power supply for the digital circuits. Bypass each supply pin with 0.1 µF and 10 µF capacitors in parallel. +3V power supply for the analog circuits. Bypass each supply pin with 0.1 µF and 10 µF capacitors in parallel. Analog ground return. Top of ADC reference ladder. Normally bypassed with a 0.1 µF capacitor. An external ADC reference voltage may be applied to this pin. +3V power supply for the analog circuits. Bypass each supply pin with 0.1 µF and 10 µF capacitors in parallel. Analog ground return. Negative differential analog output from correlated double sampler or PGA (selectable through the serial interface). 4 14 SHD I D 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 BOL BLKCLP VREFP VREFN VREFB CE SCLK SI DATA SO DATA DGND I/O DV+ I/O D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DV+ I/O DGND I/O DGND DV+ AV+ AGND VREFT AV+ AGND AOUT− I I IO IO IO I I I O D D A A A D D D D P P O O O O O O O O O O D D D D D D D D D D P P P P P P IO A P P O A www.national.com LM98501 Pin Descriptions Pin 46 47 48 Name AOUT+ AV+ AGND I/O O (Continued) Typ A P P Description Positive differential analog output from correlated double sampler or PGA (selectable through the serial interface). +3V power supply for the analog circuits. Bypass each supply pin with 0.1 µF and 10 µF capacitors in parallel. Analog ground return. Legend: (I = Input), (O = Output), (IO = Bi-directional), (P = Power), (D = Digital), (A = Analog). 5 www.national.com LM98501 Absolute Maximum Ratings (Notes 1, 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Any Positive Supply Voltage Voltage on Any Input or Output Pin Input Current at Any Pin (Note 3) Package Input Current (Note 3) Package Dissipation at TA = 25˚C (Note 4) ESD Susceptibility (Note 5) Human Body Model Machine Model Soldering Temperature Infrared, 10 seconds (Note 6) 4.2V −0.3V to +4.2V ± 35 mA ± 50 mA Storage Temperature −65˚C to +150˚C Operating Ratings (Notes 1, 2) Operating Temperature Range All Supply Voltages VIN Voltage Range VREFT Voltage Range VREFB Voltage Range VREFP Voltage Range VREFN Voltage Range All Digital Inputs Voltage Range 0˚C ≤ TA ≤ +70˚C +2.7V to +3.3V 0.0V to AV+ 2.0V to 2.5V 0.4V to 0.9V 1.3V to 1.9V 1.3V to 1.9V −0.05V to +3.35V 2000V 200V 260˚C DC and Logic Level Specifications The following specifications apply for DV+ = AV+ = DV + I/O = +3.0V, CL = 10 pF, and fCLK = 27 MHz unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25˚C (Note 7). Symbol Parameter Conditions Min (Note 9) 2.0 1.0 VIH = DV+, Digital Inputs Except Reset VIH = DV+, Reset (internal pull-down resistor) IIL VOH VOL IOS IA ID ID I/O Logical “0” Input Current Logical “1” Output Voltage Logical “0” Output Voltage Output Short Circuit Current Analog Supply Current Digital Supply Current Digital Output Driver Supply Current PD = LOW PD = HIGH PD = LOW PD = HIGH PD = LOW PD = HIGH VIL = DGND DV+ = 3.3V, IOUT = −0.5 mA DV+ = 2.7V, IOUT = −0.5 mA DV+ = 3.3V, IOUT = 1.6 mA DV+ = 2.7V, IOUT = 1.6 mA 30 56.8 3.1 6.5 0.1 2.3 0.1 1.0 1.0 5.0 POWER SUPPLY CHARACTERISTICS mA mA mA mA mA mA 2.5 2.3 0.4 0.4 DIGITAL OUTPUT CHARACTERISTICS V V mA 100 400 −100 Typical (Note 8) Max (Note 9) Units DIGITAL INPUT CHARACTERISTICS VIH VIL IIH Logical “1” Input Voltage Logical “0” Input Voltage Logical “1” Input Current V V nA µA nA Power Dissipation Specifications The following specifications apply for DV+ = AV+ = DV + I/O = +3.0V, CL = 10 pF, and fCLK = 27 MHz unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25˚C (Note 7). Symbol PWR Parameter Average Power Dissipation Conditions AV+ = DV+ = DV+ I/O = 2.7V AV+ = DV+ = DV+ I/O = 3.0V AV+ = DV+ = DV+ I/O = 3.3V Min (Note 9) Typical (Note 8) 150 195 240 mW Max (Note 9) Units www.national.com 6 LM98501 Correlated Double Sampler Specifications The following specifications apply for DV+ = AV+ = DV + I/O = +3.0V, CL = 10 pF, and fCLK = 27 MHz unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25˚C (Note 7). Symbol VIN IIN CIN RIN tAD tSHP tSHD Parameter Input Voltage Level Input Leakage Current Input Capacitance Input Resistance Aperture Delay CLK Falling Edge to SHP Falling Edge CLK Rising Edge to SHD Falling Edge 0 5 10 2 10 14 Conditions Min (Note 9) Typical (Note 8) 1.0 10 Max (Note 9) Units Vp-p nA pF kΩ ns PGA Specifications The following specifications apply for DV+ = AV+ = DV + I/O = +3.0V, CL = 10 pF, and fCLK = 27 MHz unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25˚C (Note 7). Symbol Parameter Gain Resolution Step Size Maximum Gain Minimum Gain Gain Error @ 20 MHz Gain Error @ 27 MHz Deviation from Best-Fit Line after End-Point Correction Deviation from Best-Fit Line after End-Point Correction (Gain / Resolution) 0 Conditions Min (Note 9) Typical (Note 8) 8 0.125 32.0 0.0 Max (Note 9) Units Bits dB dB dB % % ±5 ±5 Offset DAC and Black Level Clamp Specifications The following specifications apply for DV+ = AV+ = DV + I/O = +3.0V, CL = 10 pF, and fCLK = 27 MHz unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25˚C (Note 7). Symbol RREF Parameter Reference Ladder Resistance Resolution Offset Adjustment Range Black Level Clamp Accuracy tBLKCLP Black Clamp Switch Pulse Width PGA Gain = 1.0 dB PGA Gain = 0.0 dB PGA Gain = 32.0 dB 20 Conditions Min (Note 9) Typical (Note 8) 50 Max (Note 9) Units kΩ Bits mV LSB LSB TCLK ±7 ± 93 ± 0.5 ± 0.5 Analog to Digital Converter Specifications The following specifications apply for DV+ = AV+ = DV + I/O = +3.0V, CL = 10 pF, and fCLK = 27 MHz unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25˚C (Note 7). Symbol RREF VREFT VREFB VREFT– VREFB Parameter Reference Ladder Resistance Top of Reference Ladder Bottom of Reference Ladder Differential Reference Voltage Overrange Output Code Underrange Output Code Guaranteed No Missing Codes 7 Conditions Min (Note 9) 850 Typical (Note 8) 1000 2.25 0.75 1.5 1023 0 Max (Note 9) 1150 2.4 Units kΩ V V V VREFT not driven externally VREFB not driven externally VREFT and VREFB not driven externally VIN > VREFT VIN < VREFB 10 0.6 Bits www.national.com LM98501 AC Electrical Characteristics The following specifications apply for DV+ = AV+ = DV + I/O = +3.0V, CL = 10 pF, and fCLK = 27 MHz unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25˚C (Note 7). Symbol fCLK TCLK tch tcl trc, tfc tVALID tOH tOD Parameter Input Clock Frequency Input Clock Period Clock High Time Clock Low Time Clock Duty Cycle Clock Input Rise and Fall Time Pipeline Delay (Latency) Data Valid Time Output Data Hold Time Output Delay Time 9 14 @ CLKmax @ CLKmax @ CLKmax Conditions Min (Note 9) 1 33 15 15 Typical (Note 8) 27 37 Max (Note 9) 30 1000 Units MHz ns ns ns 45/55 5 7 27 13 20 19 26 min/max ns TCLK ns ns ns Full Channel Performance Specifications The following specifications apply for DV+ = AV+ = DV + I/O = +3.0V, CL = 10 pF, and fCLK = 27 MHz unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25˚C (Note 7). Symbol DNL INL *SNR Parameter Differential Non-Linearity Integral Non-Linearity 0 dB Gain, 1.0V Input Effective Number of Bits Total Harmonic Distortion Conditions Min (Note 9) −1.0 Typical (Note 8) Max (Note 9) 1.5 Units LSB LSB dB dB Bits Bits dB dB ± 0.5 +3.0/−1.5 60 61 7.5 7.6 −51 −60 @ fCLK = 27 MHz @ fCLK = 20 MHz @ fCLK = 27 MHz @ fCLK = 20 MHz @ fCLK = 27 MHz @ fCLK = 20 MHz ENOB THD *20 log10 (VIN/RMS Output Noise) Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified. Note 3: When the voltage at any pin exceeds the power supplies (VIN < GND or VIN > AV+ or DV+), the current at that pin should be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with in input current of 25 mA to two. Note 4: The absolute maximum junction temperature (TJMAX) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJMAX, the junction-to-ambient thermal resistance (*JA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJMAX – TA)/*JA. In the 48-pin LQFP, *JA is 69˚C/W, so PDMAX = 1,811 mW at 25˚C and 1,159 mW at the maximum operating ambient temperature of 70˚C. Note that the power dissipation of this device under normal operation will typically be about 180 mW. The values for maximum power dissipation listed above will be reached only when the LM98501 is operated in a severe fault condition. Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through 0Ω. Note 6: See AN450, “Surface Mounting Methods and Their Effect on Product Reliability”, or the section entitled “Surface Mount” found in any post 1986 National Semiconductor Linear Data Book, for other methods of soldering surface mount devices. Note 7: The analog inputs are protected as shown below. Input voltage magnitude up to 500 mV beyond the supply rails will not damage this device. However, input errors will be generated if the input goes above AV+ and below AGND. DS101292-18 Note 8: Typical figures are at TJ = 25˚C, and represent most likely parametric norms. Note 9: Test limits are guaranteed to National’s AOQL (Averaging Outgoing Quality Level). www.national.com 8 LM98501 Typical Performance Characteristics DNL vs. Temperature DNL vs. Supply Voltage DS101292-19 DS101292-20 DNL vs. Clock Frequency DNL vs. Clock Duty Supply DS101292-21 DS101292-22 INL vs. Temperature INL vs. Supply Voltage DS101292-23 DS101292-24 9 www.national.com LM98501 Typical Performance Characteristics INL vs. Clock Frequency (Continued) INL vs. Clock Duty Cycle DS101292-25 DS101292-26 Power Dissipation vs. Temperature Power Dissipation vs. Clock Frequency DS101292-27 DS101292-28 Actual vs. Ideal PGA Gain and Clock Frequency PGA Gain vs. Supply Voltage and Clock Frequency DS101292-29 DS101292-30 www.national.com 10 LM98501 Typical Performance Characteristics Grounded Input Noise @ 20 MHz Clock Frequency (Continued) Grounded Input Noise @ 27 MHz Clock Frequency DS101292-31 DS101292-32 Spectral Response @ 20 MHz Clock Frequency Spectral Response @ 27 MHz Clock Frequency DS101292-33 DS101292-34 DNL vs. Power Setting @ 27 MHz Clock Frequency Power Dissipation vs. Power Setting DS101292-35 DS101292-36 11 www.national.com LM98501 CDS Sampling Timing DS101292-5 1 SHP overrides the CLAMP signal’s falling edge for sampling the reset voltage (SHP is active-low by default). 2 The CLAMP signal is an internal signal derived from the CLK input whose falling edge samples the CCD reset voltage by default. FIGURE 4. Pixel Rate Reset Voltage Sampling DS101292-6 1SHP overrides the CLAMP signal’s falling edge for sampling the reset voltage (SHD is active-low by default). 2The SAMPLE signal is an internal signal derived from the CLK input whose falling edge samples the CCD video signal by default. FIGURE 5. Pixel Rate Video Signal Sampling Horizontal Interval Timing DS101292-7 FIGURE 6. Typical Horizontal Interval Timing www.national.com 12 LM98501 Digital Output Timing DS101292-8 FIGURE 7. Digital Output Data Timing System Timing DS101292-9 FIGURE 8. System Timing System Overview INTRODUCTION The LM98501 is a 10-bit, complete analog-to-digital camera signal processor for use with CCD imager systems operating from a single +3V supply. The internal processing is carefully optimized to maintain the signal-to-noise ratio and excellent dynamic performance of most popular CCD imagers. The system block diagram of the LM98501, shown on the cover page of the datasheet, highlights the main features of the device: correlated double sampling (CDS), 0 dB–32 dB digitally programmable gain amplifier (PGA), digital black level correction feedback loop, 8-bit DAC, analog clamp, bandgap voltage reference, and a 10-bit, 27 MHz analog-to-digital converter. CORRELATED DOUBLE SAMPLING Correlated double sampling (CDS) is a key feature in CCD image processors. The sampling process consists of two samples being taken for each pixel. The first stores the reset voltage of the input pixel, and the second stores the video signal amplitude. The two samples are subtracted from one another, effectively removing the reset error offset of each pixel. This sampling system operates at 27 MHz, allowing the use of imagers that have resolution at high speeds. Operation at these higher clock rates generates electronic images similar to a high-speed camera, preventing blearing of the image caused by motion during the exposure. 13 www.national.com LM98501 System Overview (Continued) each case; therefore, appropriate gain and offset values should be written to PGA gain and DAC offset register 0 prior AUX IN usage. BLACK LEVEL CLAMP CCD signal processors require a reference level for the proper handling of input signals; this reference level is commonly referred to as the black level. The LM98501 is designed to determine a signal’s black level during the CCD imager’s optical black pixels. The LM98501 provides both an analog clamp and a digital black level correction loop. Pulsing the ACLP pin during optical black pixels causes the analog clamp circuitry to remove the offset associated with the input signal. During dummy black pixels at the end of a horizontal line, setting the BLKCLP pin for a minimum of 20 CLK cycles enables the digital black level correction loop. Actual black level correction may be performed through one of two available methods — automatic or manual. In automatic mode, the black level is sampled from the ADC output during black pixels by setting the BLKCLP input of the LM98501. The ADC black level output value is then averaged over eight pixels and subtracted from the desired black level stored in the black level configuration register. The result of the subtraction may then be integrated by a preset scaling factor, effectively smoothing any sharp transitions present in the black level signal, before the resulting error is finally applied to the input of the PGA as an analog offset generated by the DAC. The offset integration scaling factor is stored in two bits of the software control register 0, and the values available range from the full offset to offset divided-by-16. In addition, an offset output enable bit is provided in the software control register 0, which when set, routes the offset value to the digital output bus rather than the DAC. Use of the automatic mode involves enabling the black level offset auto-calibration bit in the software control register 0 through the serial interface. The manual method is intended for use with processing systems where the desired black level correction loop is external to the LM98501. In this mode, up to four available configuration registers may be used to store predetermined offset values that will be applied on a pixel-rate basis. During the vertical interval, new values may be stored in these registers for each horizontal line. DS101292-10 FIGURE 9. Correlated Double Sampling PROGRAMMABLE GAIN AMPLIFIER In a CCD imager, there may be millions of photo diodes that normally have some gain variation from pixel to pixel. Other gain errors are generated by the amount of light transmission and the quality of the color filters on the front of each pixel of the imager. These filters make it possible for camera to recognize color; therefore, each filter has to have correct gain in order to generate the electronic voltages that would be equal to white. Luminosity of a scene may have a colorcast, and the gain of a pixel must be changed in order to compensate for the colorcast. These three sources of gain error associated with each pixel are compensated for with a wide bandwidth programmable gain amplifier that operates at a pixel rate. The amplifier has a gain ranging from 0 dB–32 dB, and is “linear in dB” as shown in Figure 16. A linear in dB amplifier contains more gain steps in the lower portion of the gain range so that color balance may be maintained during low light levels. AUXILIARY INPUT The LM98501 includes a high-level video switch that allows a recorder playback video signal to be selected instead of the camera image. This feature is especially useful when adding electronic titles to images in the digital domain. In addition, the PGA gain and DAC offset are set to register 0 in DS101292-11 FIGURE 10. Digital Black Level Correction Loop www.national.com 14 LM98501 System Overview ANALOG CLAMP (Continued) SERIAL INTERFACE AND CONFIGURATION REGISTERS There are many options available to the user that may be programmed via the LM98501’s serial interface. Configuration values are stored in registers for use by several functions such as programmable gain, offset, black level, and color filter array. The LM98501’s serial interface is used to store values into 16 8-bit configuration registers. Upon power-up or external reset, the configuration registers will contain their respective default values. Default values place the LM98501 in ‘single channel’ mode, where only one PGA gain and offset are applied to the input signal. The master CLK input is required to be running during serial interface commands. Each command issued through the serial interface must have a minimum of 13 data bits (see Figures 13, 14). PGA GAIN The four PGA gain registers store four possible gain values for the programmable gain amplifier (PGA). For example, these four gain values may correspond to four possible colors in a color filter array. ANALOG OFFSET The analog offset registers store four possible values that correspond to the four gain values. For example, the value stored in the PGA gain register 0 (address 0h) is used in conjunction with the offset value stored in the analog offset register 0 (address 4h). This allows for four possible combinations of PGA gain and analog offset, one for each color filter. These registers are read-only when offset auto-calibration is enabled in the software control register 0. It should be noted that each offset DAC step (1 LSB) corresponds to a 0.4 LSB step at the ADC output. Therefore, if an offset of 20 digital codes is desired at the ADC output, a digital code value of 50 should be stored in the analog offset register(s). As a result, the maximum offset seen at the ADC output as a result of digital code values stored in the analog offset register(s) is ± 54 codes. It is possible to increase the digital output range of the analog offset DAC, resulting in a increased maximum ADC output code corresponding to a given DAC input. for more information on increasing the DAC range, please see ANALOG OFFSET DAC RANGE ADJUSTMENT. OUTPUT BLACK LEVEL The output black level register is occupied by an 8-bit word stored by the user that specifies the output level corresponding to optical black. For example, a user that wants an output level of 16 for black pixels must write this value into the register during the horizontal interval. Once this has been accomplished, driving the BLKCLP high for 20 cycles of CLK activates the digital black clamp loop and the black level is forced to the value stored in the output black level register, in the example case the code value of 16. As a result of the relationship between the DAC input and the ADC output (see ’Analog Offset’), the largest output black level code the LM98501 is capable of clamping to is 54 codes. During optical black pixels, an offset often appears on the CCD generated input signal. This offset may be seen by the CDS circuitry as a valid video signal rather than the actual black level signal; therefore, the LM98501 provides an analog clamp designed to eliminate this offset during black pixels. Pulsing the analog input pin, ACLP, causes the output of the CDS to be sampled by the analog clamp circuitry. Subsequently, an adjustment is made to the CDS reference voltages by the analog clamp to effectively eliminate any offset present in the signal during black pixels. 10-BIT ANALOG-TO-DIGITAL CONVERTER The selected imager’s analog signal is sampled by the CDS and amplified to match the input requirements of the 10-bit analog-to-digital converter by the PGA. The final step performed by the system is to convert the selected analog image to digital values with a 10 bits of resolution. The ADC has differential inputs and outputs (internally) which aids in the coping with headroom constraints common to +3V systems. Data is acquired at the falling edge of the clock and is available at the digital output pins 7.0 clock cycles plus tOD later. INTERNAL VOLTAGE REFERENCE An on-board, temperature stable voltage reference is employed based on a differential, continuous-time bandgap circuit. The employment of this on-chip reference eliminates the need for external reference drive circuitry and components, minimizing cost and board space in a design. The use of external bypass capacitors from the reference pins to ground is recommended for reducing reference drive requirements, resulting in reduced power dissipation. A second on-chip reference is used exclusively for the offset DAC and follows the same procedures for bypassing with external capacitors. INTERNAL TIMING GENERATION All if the necessary clocks for the CDS and ADC operation are generated internally from the LM98501’s master clock input. The CDS sampling clocks may be overridden by the user via the SHP and SHD clock inputs. As depicted in Figure 4 and Figure 5, there are two signals generated internally for CDS sampling referred to as CLAMP and SAMPLE. These signals provide the rising edge reference for the sampling of the CCD input signal. The timing of CLAMP and SAMPLE is derived from the clock; therefore, shifting the clock phasing with respect to the CCD input signal would also shift the rising (and falling) edges of CLAMP and SAMPLE. The actual sampling of the CCD’s reset voltage and video signal is performed on the falling edges of the CLAMP and SAMPLE signals respectively. The user may modify the position of the falling edges where the sampling of the CCD input occurs by driving the SHP and SHD inputs of the LM98501. The falling edges of SHP and SHD will supersede the falling edges of CLAMP and SAMPLE respectively and cause the duration of the sample pulse to shorten accordingly. As evidenced in Figure 4 and Figure 5, the falling edges of SHP and SHD should not occur earlier than tSHP or tSHD after the respective falling [SHP] (or rising [SHD]) edge of CLK. 15 www.national.com LM98501 System Overview (Continued) cates that the color magenta uses the gain and offset values stored in PGA gain register 1 (address 1h) and analog offset register 1 (address 5h). Also, the first line indicates that the color cyan uses the gain and offset values in PGA gain register 2 (address 2h) and analog offset register 2 (address 6h). The second line indicates gain and offset values for the color blue and the color green in the same fashion as the first line. Example A 7 CFA Line 0 CFA Line 1 CFA Definition XX 11 00 XX 00 00 01 00 11 0 10 11 01 DS101292-37 FIGURE 11. ADC Output vs. Black Level Register Value COLOR FILTER ARRAY (CFA) CONFIGURATION In order to utilize the LM98501’s programmable pixel-rate gain, a color filter array (CFA) pattern must be defined. Some commonly used CFA patterns are as follows: Bayer Pattern Line 0 Line 1 Green Blue Red Green CMYG Pattern Line 0 Line 1 Cyan Cyan Magenta Green Yellow Yellow Green Magenta Green Blue Red Green Therefore, two 8-bit words must be written to the CFA line registers to specify the CFA pattern being used. Also, two 2-bit numbers must be written to the CFA definition register indicating the number of pixels per pattern in each line of the defined CFA pattern. The information contained in the CFA line registers indicates the registers where the respective PGA gain and offset values are stored. For example, a system using the Bayer pattern defined above would first write four PGA gains and their respective offsets into the four PGA gain and four analog offset registers. Next, two 8-bit words (one word/CFA line) would be written to the CFA configuration registers. The 8-bit CFA configuration words each consist of four 2-bit numbers, each of which is the address for the gain and offset values of the color that appears in that location in the CFA line. Finally, two 2-bit numbers specifying the number of elements in each CFA line must be written into the CFA definition register. A CFA configuration will then contain four 2-bit numbers indicating the registers where the gain and offset values are located for a maximum of four colors on each CFA line. In addition, the CFA definition register will contain two 2-bit numbers that designate the number of elements used in each CFA line for the particular CFA pattern being applied to the system. Example A contains a CFA pattern that repeats the colors cyan and magenta on the first line, and repeats the pattern blue, green, green, blue on the second line. Each 2-bit number in the CFA line registers refers to a common set of PGA gain and offset registers for each color. The first line indi- In addition to specifying the gain and offset for each line, it is also necessary to specify the number of elements contained in each CFA line’s pixel pattern. The CFA definition register is used to store this value (number of elements per line). In example A, the user has stored the 2-bit binary number 01 into the CFA definition register’s two LSB’s indicating that the pattern in line 0 contains two repeating colors or elements. Also, the 2-bit binary number 11 has been written into bit 2 and bit 3 of the CFA definition register indicating that the respective CFA pattern contains four repeating colors or elements, as the colors blue and green alternate position in the example pattern. Once both lines for the pattern have been stored, it is applied when the beginning of line (BOL) signal is asserted by the user. One line of the CFA pattern is applied repeatedly until the BOL signal is reset (at the end of the current line). Once the BOL signal is set again, the CFA line information is changed from that defined by the CFA line 0 register to that defined by the CFA line 1 register and the process starts again. For more details of the timing of the BOL signal, please refer to Figure 6. SOFTWARE CONTROL There are two software control registers accessible via the serial interface. The software control registers are divided into customer (register 0) and advanced (register 1) functions. Please refer to the register data descriptions for more information on the software control registers. POWER LEVEL CONTROL The LM98501 is equipped with two power trim registers that may be used to adjust power levels of various circuits internal to the device. In its default condition, the LM98501 is set for optimum power and performance, and modifying the values stored in the power level control registers will affect performance as a result of the change in power level(s). In applications where maximum performance is desired, the default values should be used. Otherwise, power levels may be decreased at the slight expense of performance. Please refer to the register data descriptions for more information regarding the power level control registers. The ADC coarse and fine bank power adjustment bits are located in the power level control 2 register, bits 7:4. Altering these bits may significantly affect performance and power dissipation. Please see “DNL vs. Power Control Setting @ 27 MHz Clock Frequency” and “Power Dissipation vs. Power Control Setting” on page 11. www.national.com 16 LM98501 Register Memory Map Title PGA Gain 0 PGA Gain 1 PGA Gain 2 PGA Gain 3 Analog Offset 0 Analog Offset 1 Analog Offset 2 Analog Offset 3 CFA Configuration 0 CFA Configuration 1 CFA Definition Output Black Level Software Control 0 Software Control 1 Power Level Control 0 Power Level Control 1 Address 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Default Value 0000 0000 (0d) 0000 0000 (0d) 0000 0000 (0d) 0000 0000 (0d) 0000 0000 (0d) 0000 0000 (0d) 0000 0000 (0d) 0000 0000 (0d) 0000 0000 (0d) 0000 0000 (0d) XXXX 0000 (0d) 0001 0000 (32d) 0100 1110 (78d) XX00 0X00 (0d) 1010 1010 (170d) 0101 1010 (90d) FIGURE 12. Register Memory Map Register Data The following section describes all available registers in the LM98501 register bank and their functions. PGA GAIN REGISTERS Register Name PGA Gain 0 Address 0 Hex Type Read/Write Reset Value 0000 0000 Binary Bit [7:0] Bit Symbol PGA Gain Description 0.0 dB–32.0 dB in 0.125 dB steps. Reset Value Bit [7:0] 0000 0000 Binary Description 0.0 dB–32.0 dB in 0.125 dB steps. Bit Symbol PGA Gain ANALOG OFFSET REGISTERS Register Name Analog Offset 0 Address 4 Hex Type Read/Write Reset Value 0000 0000 Binary Bit [7:0] Bit Symbol Signed Analog Offset Description Digital representation of the analog offset to be applied to the input of the PGA. See “Analog Offset” on page 15. Register Name Address Type Reset Value Bit [7:0] PGA Gain 1 1 Hex Read/Write 0000 0000 Binary Description 0.0 dB–32.0 dB in 0.125 dB steps. Bit Symbol PGA Gain Register Name Address Type Reset Value Bit [7:0] Analog Offset 1 5 Hex Read/Write 0000 0000 Binary Description Digital representation of the analog offset to be applied to the input of the PGA. See “Analog Offset” on page 15. Bit Symbol Signed Analog Offset Register Name Address Type Reset Value Bit [7:0] PGA Gain 2 2 Hex Read/Write 0000 0000 Binary Description 0.0 dB–32.0 dB in 0.125 dB steps. Bit Symbol PGA Gain Register Name Address Type Reset Value Analog Offset 2 6 Hex Read/Write 0000 0000 Binary Register Name PGA Gain 3 Address 3 Hex Type Read/Write 17 www.national.com LM98501 Register Data Bit [7:0] Bit Symbol Signed Analog Offset (Continued) Description Digital representation of the analog offset to be applied to the input of the PGA. See “Analog Offset” on page 15. Bit [3:2] Bit Symbol Line1:Pixel1 Gain/Offset Description 2 LSB’s of register addresses where the gain and offset for pixel 1 of the CFA pattern are stored. 2 LSB’s of register addresses where the gain and offset for pixel 0 of the CFA pattern are stored. [1:0] Line1:Pixel0 Gain/Offset Register Name Address Type Reset Value Bit [7:0] Analog Offset 3 7 Hex Read/Write 0000 0000 Binary Description Digital representation of the analog offset to be applied to the input of the PGA. See “Analog Offset” on page 15. Bit Symbol Signed Analog Offset Register Name Address Type Reset Value Bit [3:2] Color Filter Array Definition A Hex Read/Write XXXX 0000 Binary Description Number of pixels in CFA pattern defined in CFA line 1. Number of pixels in CFA pattern defined in CFA line 0. Bit Symbol Line 1 Pixels COLOR FILTER ARRAY REGISTERS Register Name Color Filter Array Configuration 0 Address 8 Hex Type Read/Write Reset Value 0000 0000 Binary Bit [7:6] Bit Symbol Line0:Pixel3 Gain/Offset Description 2 LSB’s of register addresses where the gain and offset for pixel 3 of the CFA pattern are stored. 2 LSB’s of register addresses where the gain and offset for pixel 2 of the CFA pattern are stored. 2 LSB’s of register addresses where the gain and offset for pixel 1 of the CFA pattern are stored. 2 LSB’s of register addresses where the gain and offset for pixel 0 of the CFA pattern are stored. [2:1] Line 0 Pixels OUTPUT BLACK LEVEL REGISTER Register Name Output Black Level Address B Hex Type Read/Write Reset Value 0001 0000 Binary Bit [7:0] Bit Symbol Black Level Description 0–256 output black level digital code value. (see “Output Black Level” on page 15) [5:4] Line0:Pixel2 Gain/Offset [3:2] Line0:Pixel1 Gain/Offset [1:0] Line0:Pixel0 Gain/Offset SOFTWARE CONTROL REGISTERS Register Name Software Control 0 (Customer) Address C Hex Type Read/Write Reset Value 0100 1110 Binary Bit [7] Bit Symbol Offset Output Enable Description Directs the offset error calculated by the digital black level correction loop to the 10 digital output data pins. Enables the serial interface output for reading register values. Offset integration factor selection: 00 No Scaling 01 Divide-by-4 10 Divide-by-8 11 Divide-by-16 Register Name Address Type Reset Value Bit [7:6] Color Filter Array Configuration 1 9 Hex Read/Write 0000 0000 Binary Description 2 LSB’s of register addresses where the gain and offset for pixel 3 of the CFA pattern are stored. 2 LSB’s of register addresses where the gain and offset for pixel 2 of the CFA pattern are stored. Bit Symbol Line1:Pixel3 Gain/Offset [6] Serial Output Enable Offset Integration [5:4] [5:4] Line1:Pixel2 Gain/Offset www.national.com 18 LM98501 Register Data Bit [3] Bit Symbol (Continued) Description Enables the digital black level correction loop. Analog offset registers are read-only when offset auto-calibration is enabled. Inverts the SHP and SHD inputs causing the CDS to sample on the rising edges of SHP and SHD. Sampling is performed on the falling edges of SHP and SHD when the signals are Active-low. Instructs the CDS to sample the CCD input. Otherwise, the AUX In input is sampled in sample-and-hold mode. Cuts power to the on-chip analog circuitry including the CDS, PGA, ADC, and bandgap references. Register Name Power Level Control 0 Address Type Reset Value Bit [7:6] E Hex Read/Write 1010 1010 Binary Description Adjusts the power level of the PGA stage 1 amplifier. The power level is relative to the value of the binary number stored. Adjusts the power level of the PGA common-mode input. The power level is relative to the value of the binary number stored. Adjusts the power level of the CDS amplifier. The power level is relative to the value of the binary number stored. Adjusts the power level of the CDS common-mode input. The power level is relative to the value of the binary number stored. Offset Auto-Calibration Enable Bit Symbol PGA Stage 1 Amplifier Bias [2] SHP/SHD Active-HIGH Enable [5:4] PGA Common-Mode Input Bias [1] CDS Enable (AUX-In Disable) Analog Power Down [3:2] CDS Amplifier Bias [0] [1:0] CDS Common-Mode Input Bias Register Name Address Type Reset Value Bit [5:4] Software Control 1 (Customer) D Hex Read/Write XX00 0X00 Binary Description Routes the selected internal analog signal to the differential analog output pins AOUT+ and AOUT−. 00 CDS 01 PGA Stage 1 10 PGA Stage 2 11 PGA Stage 3 Enables the differential analog output pins AOUT+ and AOUT−. If the analog outputs are disabled, the pins should not be loaded. Reference biasing selection for the analog-to-digital converter. 0 Passive Biasing (Resistors) 1 Active Biasing (Bandgap) Reference biasing selection for the digital-to-analog converter. 0 Active Biasing (Bandgap) 1 Passive Biasing (Resistors) Bit Symbol Analog Output Select Register Name Address Type Reset Value Bit [7:6] Power Level Control 1 F Hex Read/Write 0101 1010 Binary Description Adjusts the power level of the ADC coarse bank. The power level is relative to the value of the binary number stored. Adjusts the power level of the ADC fine bank. The power level is relative to the value of the binary number stored. Adjusts the power level of the PGA stage 3 amplifier. The power level is relative to the value of the binary number stored. Adjusts the power level of the PGA stage 2 amplifier. The power level is relative to the value of the binary number stored. Bit Symbol ADC Coarse Bank Bias [5:4] [3] Analog Output Enable ADC Fine Bank Bias [3:2] [1] ADC Reference Select PGA Stage 3 Amplifier Bias [1:0] PGA Stage 2 Amplifier Bias [0] DAC Reference Select 19 www.national.com LM98501 Serial Interface Timing Specifications The following specifications apply AV+ = DV+ = DV + I/O = +3.0V, CL = 10 pF, and fCLK = 27 MHz unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25˚C (Note 7). Symbol tMIN Parameter SCLK Period SCLK Duty Cycle SCLK Rise/Fall Time tIH tIS tCESC tSCCE tCEW tDCE tOD Input Hold Time Input Setup Time SCLK Start Time after CE Low CE Low after Last SCLK Rising Edge CE Pulse Width Input Data to CE Rising Edge Output Delay Time MCLK must be active during serial interface commands. 5 6 10 5 2 15 15 Conditions Min (Note 9) 36 40/60 50/50 60/40 4 Typical (Note 8) Max (Note 9) Units ns % ns ns ns ns ns TCLK tMIN ns Serial Interface Timing DS101292-12 1 Serial output enable must be set in software control 0 for SO DATA output. Please see Register Data section for more information. FIGURE 13. Serial Interface Read Command Timing DS101292-13 1 Serial output enable must be set in software control 0 for SO DATA output. Please see Register Data section for more information. FIGURE 14. Serial Interface Write Command Timing www.national.com 20 LM98501 PGA Gain Plots DS101292-14 FIGURE 15. PGA Gain (Linear Scale) vs. PGA Gain Code DS101292-15 FIGURE 16. PGA Gain (Logarithmic Scale) vs. PGA Gain Code Applications Information ANALOG-TO-DIGITAL CONVERTER REFERENCE BYPASSING Figure 17 shows a simple reference bypassing scheme with minimal components. The VREFT and VREFB pins should each be bypassed to analog ground with 10 µF tantalum as well as 0.1 µF ceramic capacitors. In a case where the internally generated reference voltages are not sufficient, the user may supply external voltages to the reference pins. However, the reference pin VREFT should be within the range of 2.0V to 2.5V. Similarly, VREFB should be driven in the range of 0.4V to 0.9V. Any device used to drive the reference pins should be able to source adequate current into the VREFT and sink adequate current from the VREFB pin when the reference resistor ladder is at its minimum resistivity of 850Ω. The reference voltage at the top of the resistor ladder (VREFT) may be as low as 1.2V above the voltage at the bottom of the resistor ladder (VREFB) and may be as high as 1.8V above. VREFB may be as low as 0.4V and as high as 0.9V above ground. However, noise effects will be minimized and accurate conversions insured when the total reference voltage is approximately 2.25V and offset from ground by 0.75V. DS101292-16 FIGURE 17. Reference Bypassing ANALOG OFFSET DAC REFERENCE BYPASSING The analog offset DAC reference pins, VREFP and VREFN, should be capacitively bypassed in the same fashion as the ADC reference pins VREFT and VREFB (see ’Analog-to-Digital Converter Reference Bypassing’). 21 www.national.com LM98501 Applications Information (Continued) ANALOG OFFSET DAC RANGE ADJUSTMENT The analog offset DAC has an input range of ± 127 LSB (see Register Data). This analog offset corresponds to approximately 0.4 LSB at the ADC output per DAC input code LSB step. Therefore, the offset DAC is limited to providing offset values less than or equal to ± 54 LSB at the ADC output. In some applications, this range of output may not be sufficient. It is possible to increase the range of the DAC by adjusting the DAC reference range. The DAC reference range may be adjusted by lowering the voltage at the DAC lower reference pin, VREFN via use of a pull-down resistor from VREFN to AGND. A resistor value of x.xx kΩ will increase the DAC range by a factor of 1.25x, allowing offsets of ± 64 LSB to be applied at the ADC output rather than the default maximum and minimum offsets of ± 54 LSB, resulting in a 2 LSB DAC step to 1 LSB ADC output step relationship. Likewise, a resistor value of 750Ω will increase the DAC range by a factor of 2.5x, allowing offsets of ± 127 LSB to be applied at the ADC output, in this configuration, 1 LSB step of the DAC corresponds to 1 LSB step at the ADC output. POWER SUPPLY CONSIDERATIONS The LM98501 may draw a sufficient amount of current to corrupt improperly bypassed power supplies. A 10 µF to 50 µF capacitor should be placed within 1 cm of the analog power (AV+) pins of the device in parallel with a 0.1 µF ceramic chip capacitor placed as close to the device as layout permits. Leadless chip capacitors are preferred because they have a low lead inductance. As is the case with virtually all high-speed semiconductors, the LM98501 should be assumed to have little power supply rejection; therefore, a noise-free analog power source is required. The analog and digital power supplies of the LM98501 should be sourced from the same supply voltage, but the supply pins should be well isolated from one another. Isolating the supplies prevents digital noise from coupling back into the analog supply pins. A choke (ferrite bead) is recommended to be placed between the analog and digital power supply pins as well as a ceramic chip capacitor placed as close as possible to the analog supply pin(s) of the device. Additionally, it is not recommended that the LM98501’s digital supply be used for any other digital circuitry on the circuit board. All other digital devices should be powered from a separate digital supply well isolated from both the analog and digital supplies of the LM98501. THE LM98501 CLOCK Although the LM98501 is tested and its performance guaranteed with a 27 MHz clock, it typically will function with clock frequencies ranging from 1 MHz to 30 MHz. Performance is best if the clock rise and fall times are less than 5 ns and the clock trace is terminated near the clock input pin with a series RC network consisting of a 100Ω resistor and a 47 pF capacitor. LAYOUT AND GROUNDING TECHNIQUES The proper routing of all signals and pertinent grounding techniques are essential to insure the best signal-to-noise ratio and dynamic performance possible. Separate analog and digital ground planes ease meeting the datasheet limits. The analog ground plane should be low impedance and free from noise of other components of the system. All bypass capacitors should be located as close to the pin as possible and connected to the appropriate ground plane with short traces ( < 1 cm). The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input. Figure 18 provides an example of a suitable layout, including power supply routing, ground plane separation, and bypass capacitor placement. All input amplifiers, filters, and reference components should be placed on or over the analog ground plane. All digital circuitry and I/O lines should be placed over and grounded via the digital ground plane. Digital and analog signal lines should never run parallel to each other in close proximity with each other. These signals should only cross when absolutely necessary and then only at 90˚ angles. DYNAMIC PERFORMANCE The LM98501 is AC tested and its dynamic performance is guaranteed. The clock source driving the CLK input must be free of jitter. For best AC performance, the clock source should be isolated from other system digital circuitry with a clock tree buffer(s). Meeting noise specifications depends largely upon keeping digital noise out of the analog input of the LM98501. COMMON APPLICATION PITFALLS Driving the inputs (analog or digital) beyond the power supply potential. For proper operation, all input potentials should not be greater than 300 mV above that of the power supply. It is not uncommon for high speed digital circuits (e.g. 74F and 74AC devices) to exhibit undershoot that falls to a potential greater than 1.0V below the ground potential and overshoot that rises to a potential greater than 1.0V above the power supply potential. A resistor of 50Ω to 100Ω in series with the offending digital input will, in most cases, eliminate this problem. Attempting to drive a high capacitance digital data bus. The more capacitance the output drivers have to charge for each conversion output, the more instantaneous digital current is required from the DV+ I/O and DGND I/O supply pins. These large charging current spikes can couple into the analog section and subsequently may degrade dynamic performance of the system. Adequate bypassing and maintaining separate analog and digital ground planes will reduce this problem on the application system board. Buffering the digital data outputs may be necessary if the data bus being driven by the LM98501 is heavily loaded. Dynamic performance may also be improved by adding series resistors of 47Ω at each digital output. Driving the reference pins with devices that cannot source or sink the current required by the reference resistor ladder. As mentioned previously, any devices driving the reference resistor ladder must source sufficient current into the top of the ladder. Additionally, the device connected to the bottom of the ladder must be able to sink the necessary amount of current to keep the reference voltage(s) stable. If the reference resistor ladder voltages are not stable the converter output will not generate predictable output codes. www.national.com 22 LM98501 Applications Information (Continued) DS101292-17 FIGURE 18. Recommended Layout Pattern 23 www.national.com LM98501 10-Bit, 27 MSPS Camera Signal Processor Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead LQFP Package Order Number LM98501CCVBH NS Package Number VBH48A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com www.national.com National Semiconductor Europe Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: ap.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.