LM98503

LM98503 10-Bit, 18 MSPS Camera Signal Processor October 2000 LM98503 10-Bit, 18 MSPS Camera Signal Processor General Description The LM98503 is a CCD signal processor for digital cameras. The processor provides a common interface to a number of different image sensors including CCD, CMOS, and CIS. Correlated double sampling reduces kTC noise from the image signal. A fast, temperature stable, 8-bit digitally programmable gain amplifier enables pixel-rate white-balancing. An auxiliary input is provided, allowing for the selection of an external signal, useful for sampling analog video signals. The 10-bit A/D converter preserves the image quality with excellent noise performance. The LM98503 also includes the supporting functions of digital black level clamp and power down, ideally suited for portable video applications. This low-power processor is a natural choice for the most demanding imaging systems. N Features ! ! ! ! ! ! ! ! ! +3 Volt single power supply Low power CMOS design 4-Wire serial interface 2.5V data output voltage swing AUX input with analog clamp and programmable gain Four color gain and offset registers Digital black level clamp Small 48-lead LQFP package Supports interlace and progressive scan CCDs. Key Specifications !Maximum Input Level !CDS Sampling Rate !PGA Gain Steps !PGA Gain Range !ADC Resolution !ADC Sampling Rate !*Signal-to-Noise Ratio !Power Dissipation AV+ = DV+ = 2.7V !Operating Temp * Note: 20 log10 (VIN / RMS Output Noise) 1.0 Volt peak-peak 18 MSPS 256 Steps 0.0 - 32.0 dB 10-Bit 18 MSPS 68dB @ 0dB Gain, 1.0V Input 86 mW (typical) 0oC to 70oC Applications ! ! ! ! ! ! ! ! Digital still cameras Digital video camcorders Video conferencing Security cameras Plain paper copiers Flatbed or handheld color scanners Video processing for X-ray or infrared Barcode scanners Typical Digital Camera Block Diagram Auxiliary Video Input CCD/CIS Sensor LM98503 10 Image Processor Microcontroller Sensor Driver Timing Generator Motor Controllers © 2000 National Semiconductor Corporation www.national.com LM98503 Block Diagram /CE SCLK SI DATA SO DATA VREFP VREFN BOL SHP SHD CLK Serial Port Interface Configuration Registers 8 Timing Control Pixel-Rate Offset DAC 8 V IN Correlated Double Sampler Sample/Hold Black Level Clamp 8 BLKCLP 2 AUX IN ACLP Analog Clamp Bandgap Voltage Reference Pixel-Rate PGA 2 10-Bit Analogto-Digital Converter 10-Bit Data Output AOUT+ AOUT- VREFT VREFB Figure 1: Chip Block Diagram Pin Out DGND I/O VREFT AOUT+ AOUTAGND DGND AGND AGND AV+ AUX IN AGND V IN AGND AV+ ACLP RESET AV+ DGND DGND DV+ CLK 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 AV+ DV+ AV+ DV+ I/O D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DV+ I/O LM98503 48 Pin LQFP 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 SHP SHD BOL DGND I/O VREFN VREFP BLKCLP VREFB /CE SCLK SO DATA SI DATA Figure 2: Pin Out Diagram www.national.com 2 LM98503 Ordering Information Commercial (0°C ≤ TA ≤ 70°C) 70 LM98503CCVV NS Package LQFP Typical Application Circuit System Control Camera Control Serial Control Bus 12 CLK 7 RESET 13 SHP 14 SHD 15 BOL 6 ACLP 16 BLKCLP 21 SCLK 22 23 20 SO DATA SI DATA /CE 10µF 0.1µF 42 VREFT VREFP 17 0.1µF 0.1µF 19 VREFB VREFN 18 0.1µF 1.5K 3V AV+ AV+ 5 47 8 40 43 44 4,48 2,41 0.1µF 10µF LM98503 AV+ AV+ AV+ AGND 3V AGND 11,39 DV+ 25,36 DV+ I/O 24,37 DGND I/O 9,10,38 AGND 10µF 0.1µF DGND AUX IN V IN AOUT+ 46 AOUT- 45 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 3 1 35 34 33 32 31 30 29 28 27 26 Digital Video Bus Figure 3: Typical Application Circuit Diagram www.national.com 3 LM98503 Pin Descriptions Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 Name AUX IN AGND V IN AGND AV+ ACLP RESET AV+ DGND DGND DV+ CLK SHP I I I I I I/O I Typ A P A P P D D P P P P D D Description Auxiliary analog input. Analog ground return. Analog input. AC-couple input signal through a 0.1µF capacitor. Analog ground return. +3 Volt power supply for the analog circuits. Bypass each supply pin with 0.1µF and 10µF capacitors in parallel. Analog clamp switch. Active-high master reset. Float pin when function not being used. +3 Volt power supply for the analog circuits. Bypass each supply pin with 0.1µF and 10µF capacitors in parallel. Digital ground return. Digital ground return. +3 Volt power supply for the digital circuits. Bypass each supply pin with 0.1µF and 10µF capacitors in parallel. 18 MHz clock input. Correlated double sampler reset voltage clamp override. Programmable active-high or active-low through serial interface. Connect to +3 Volt digital supply when function not being used (register values in default condition). Correlated double sampler video signal voltage sample override. Programmable activehigh or active-low through serial interface. Connect to +3 Volt digital supply when function not being used (register values in default condition). Active-high beginning of line switch input. Hold high during entire line of effective pixels. Hold low during blanking period. Active-high black level clamp switch input. Pulse high during black pixels to set black pixel level to the value stored in Output Black Level register. (See page 15.) Top of DAC reference ladder. Normally bypassed with a 0.1µF capacitor. An external DAC reference voltage may be applied to this pin. Bottom of DAC reference ladder. Normally bypassed with a 0.1µF capacitor. An external DAC reference voltage may be applied to this pin. Alternately, an external pull-down resistor may be used to extend the DAC range. (See section 3.0). Bottom of ADC reference ladder. Normally bypassed with a 0.1µF capacitor and 10µF capacitors in parallel. An external ADC reference voltage may be applied to this pin. Active-low chip enable for the serial interface. Serial interface clock used to decode the serial input data. Serial interface input port. Serial interface output port. Digital output driver ground return. +3 Volt power supply for the digital output driver circuits. Bypass each supply pin with 0.1µF and 10µF capacitors in parallel. Digital output. Bit 0 of 9 (LSB) of the digital video output bus. Digital output. Bit 1 of 9 of the digital video output bus. Digital output. Bit 2 of 9 of the digital video output bus. Digital output. Bit 3 of 9 of the digital video output bus. Digital output. Bit 4 of 9 of the digital video output bus. Digital output. Bit 5 of 9 of the digital video output bus. Digital output. Bit 6 of 9 of the digital video output bus. 14 SHD I D 15 16 17 BOL BLKCLP VREFP I I IO D D A 18 VREFN IO A 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VREFB /CE SCLK SI DATA SO DATA DGND I/O DV+ I/O D0 D1 D2 D3 D4 D5 D6 IO I I I O A D D D D P P O O O O O O O D D D D D D D www.national.com 4 LM98503 Pin Descriptions (continued) Pin 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Name D4 D5 D6 D7 D8 D9 DV+ I/O DGND I/O DGND DV+ AV+ AGND VREFT AV+ AGND AOUTAOUT+ AV+ AGND O O IO I/O O O O O O O Typ D D D D D D P P P P P P A P P A A P P Description Digital output. Bit 4 of 9 of the digital video output bus. Digital output. Bit 5 of 9 of the digital video output bus. Digital output. Bit 6 of 9 of the digital video output bus. Digital output. Bit 7 of 9 of the digital video output bus. Digital output. Bit 8 of 9 of the digital video output bus. Digital output. Bit 9 of 9 (MSB) of the digital video output bus. +3 Volt power supply for the digital output driver circuits. Bypass each supply pin with 0.1µF and 10µF capacitors in parallel. Digital output driver ground return. Digital ground return. +3 Volt power supply for the digital circuits. Bypass each supply pin with 0.1µF and 10µF capacitors in parallel. +3 Volt power supply for the analog circuits. Bypass each supply pin with 0.1µF and 10µF capacitors in parallel. Analog ground return. Top of ADC reference ladder. Normally bypassed with a 0.1µF capacitor and 10µF capacitors in parallel. An external ADC reference voltage may be applied to this pin. +3 Volt power supply for the analog circuits. Bypass each supply pin with 0.1µF and 10µF capacitors in parallel. Analog ground return. Negative differential analog output from correlated double sampler or PGA (selectable through the serial interface). Positive differential analog output from correlated double sampler or PGA (selectable through the serial interface). +3 Volt power supply for the analog circuits. Bypass each supply pin with 0.1µF and 10µF capacitors in parallel. Analog ground return. Legend: (I=Input), (O=Output), (IO=Bi-directional), (P=Power), (D=Digital), (A=Analog) www.national.com 5 LM98503 Absolute Maximum Ratings (Notes 1 & 2) Any Positive Supply Voltage 4.2V Voltage On Any Input or Output Pin -0.3V to 4.2V Input Current at any pin (Note 3) ±35mA Package Input Current (Note 3) ±50mA Package Dissipation at TA = 25°C (Note 4) ESD Susceptibility (Note 5) Human Body Model 2500V Machine Model 250V Soldering Temperature Infrared, 10 seconds (Note 6) 260°C Storage Temperature -65°C to 150°C Operating Ratings (Notes 1 & 2) Operating Temperature Range All Supply Voltages V IN Voltage Range VREFT Voltage Range VREFB Voltage Range VREFP Voltage Range VREFN Voltage Range All Digital Inputs Voltage Range -0°C≤TA≤+70°C +2.85V to +3.15V 0.0V to AV+ 2.0V to 2.5V 0.4V to 0.9V 1.3V to 1.9V 1.3V to 1.9V -0.05V to 3.35V DC and Logic Level Specifications The following specifications apply for DV+ = AV+ = DV+ I/O = +3.0V, CL = 10pF, and fCLK = 18MHz unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25oC (Note 7). Symbol Parameter Conditions Min (note 9) Typical (note 8) Max (note 9) Units Digital Input Characteristics VIH VIL Logical “1” Input Voltage Logical “0” Input Voltage VIH = DV+, Digital inputs except Reset IIH Logical “1” Input Current VIH = DV+, Reset (internal pull-down resistor) IIL Logical “0” Input Current VIL = DGND 400 -100 µA nA 100 2.0 1.0 V V nA Digital Output Characteristics VOH VOL IOS Logical “1” Output Voltage Logical “0” Output Voltage Output Short Circuit Current DV+ = 3.15V, Iout = -0.5mA DV+ = 2.85V, Iout = -0.5mA DV+ = 3.15V, Iout = 1.6mA DV+ = 2.85V, Iout = 1.6mA 30 2.5 2.3 0.4 0.4 V V mA Power Supply Characteristics Power Dissipation Specifications The following specifications apply for DV+ = AV+ = DV+ I/O = +3.0V, CL = 10pF, and fCLK = 18MHz unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25oC (Note 7) Symbol Parameter Conditions AV+ = DV+ = DV+ I/O = 2.7V AV+ = DV+ = DV+ I/O = 3.0V AV+ = DV+ = DV+ I/O = 3.3 Min (note 9) Typical (note 8) 86 100 116 Max (note 9) Units PWR Average Power Dissipation mW www.national.com 6 LM98503 Correlated Double Sampler Specifications The following specifications apply for DV+ = AV+ = DV+ I/O = +3.0V, CL = 10pF, and fCLK = 18MHz unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25oC (Note 7) Symbol VIN IIN CIN RIN tAD tSHP tSHD Parameter Input Voltage Level Input Leakage Current Input Capacitance Input Resistance Aperture Delay CLK falling edge to SHP falling edge CLK rising edge to SHD falling edge Conditions Min (note 9) Typical (note 8) 1.0 5 5 10 2 10 14 Max (note 9) Units Vp-p nA pF kΩ ns PGA Specifications The following specifications apply for DV+ = AV+ = DV+ I/O = +3.0V, CL = 10pF, and fCLK = 18MHz unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25oC (Note 7) Symbol Parameter Gain Resolution Step Size Maximum Gain Minimum Gain Gain Error @ 20MHz Deviation from best-fit line after endpoint correction (Gain / Resolution) Conditions Min (note 9) Typical (note 8) 8 0.125 32.0 0.0 ±5 Max (note 9) Units Bits dB dB dB % Offset DAC and Black Level Clamp Specifications The following specifications apply for DV+ = AV+ = DV+ I/O = +3.0V, CL = 10pF, and fCLK = 18MHz unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25oC (Note 7) Symbol RREF Parameter Reference Ladder Resistance Resolution Offset Adjustment Range Black Level Clamp Accuracy tBLKCLP Black Clamp Switch Pulse Width PGA Gain = 1.0 PGA Gain = 0.0dB PGA Gain = 32.0dB 20 Conditions Min (note 9) Typical (note 8) 50 ±7 ±54 ±.5 ±.5 Max (note 9) Units kΩ Bits mV LSB LSB TCLK www.national.com 7 LM98503 Analog to Digital Converter Specifications The following specifications apply for DV+ = AV+ = DV+ I/O = +3.0V, CL = 10pF, and fCLK = 18 MHz unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25oC (Note 7) Symbol RREF VREFT VREFB VREFT VREFB Parameter Reference Ladder Resistance Top of Reference Ladder Bottom of Reference Ladder Differential Reference Voltage Overrange Output Code Underrange Output Code VREFT not driven externally. VREFB not driven externally. VREFT and VREFB not driven externally. V IN > VREFT V IN < VREFB Conditions Min (note 9) Typical (note 8) 1000 2.25 0.75 1.5 1023 0 Max (note 9) Units kΩ V V V AC Electrical Characteristics The following specifications apply for DV+ = AV+ = DV+ I/O = +3.0V, CL = 10pF, and fCLK = 18 MHz unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25oC (Note 7) Symbol Symbol fCLK TCLK tch tcl Parameter Parameter Input Clock Frequency Input Clock Period Clock High Time Clock Low Time Clock Duty Cycle trc, tfc Clock Input Rise and Fall Time Pipeline Delay (Latency) tVALID tOH tOD Data valid time Output Data Hold Time Output Delay Time @ CLKmax @ CLKmax @ CLKmax Conditions Conditions Min (note 9) Min (note 9) 1 50 27.5 22.5 45/55 5 7 40 27 20 33 Typical (note 8) Typical (note 8) 18 55 Max (note 9) Max (note 9) 20 1000 Units Units MHz ns ns ns min/max ns TCLK ns ns ns Full Channel Performance Specifications The following specifications apply for AV+ = DV+ = DV+ I/O = 3.0V, CL = 10pF, and fCLK = 18MHz unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25oC (Note 7) Symbol DNL INL * Note: Note 1: Parameter Differential Non-Linearity Integral Non-Linearity Conditions Min (note 9) Typical (note 8) ±0.5 +3.0/-1.5 Max (note 9) Units LSB LSB Note 2: Note 3: 20 log10 (VIN / RMS Output Noise) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified. When the voltage at any pin exceeds the power supplies (VIN < GND or VIN > AV+ or DV+), the current at that pin should be limited to 35mA. The 50mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25mA to two. www.national.com 8 LM98503 Full Channel Performance Specifications (continued) Note 4: The absolute maximum junction temperature (TJmax) for this device is 150oC. The maximum allowable power dissipation is dictated by TJmax, the junction-to-ambient thermal resistance (*JA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax - TA)/*JA. In the 48-pin LQFP, *JA is 69oC/W, so PDMAX = 1,811mW at 25oC and 1,159 mW at the maximum operating ambient temperature of 70oC. Note that the power dissipation of this device under normal operation will typically be about TBDmW. The values for maximum power dissipation listed above will be reached only when the LM98503 is operated in a severe fault condition. Human body model is 100pF capacitor discharged through a 1.5kΩ resistor. Machine model is 220pF discharged through ZERO Ohms. See AN450, “Surface Mounting Methods and Their Effect on Product Reliability”, or the section entitled “Surface Mount” found in any post 1986 National Semiconductor Linear Data Book, for other methods of soldering surface mount devices. The analog inputs are protected as shown below. Input voltage magnitude up to 500mV beyond the supply rails will not damage this device. However, input errors will be generated If the input goes above AV+ and below AGND. VDD Note 5: Note 6: Note 7: Pad IOP Internal Circuits VSS Note 8: Note 9: Typical figures are at TJ = 25oC, and represent most likely parametric norms Test limits are guaranteed to National's AOQL (Average Outgoing Quality Level). www.national.com 9 LM98503 Typical Performance Characteristics (Default conditions are fS = 27MHz, TA = 3.0V, and AV+ = DV+ = DV+ I/O = 3.0V, unless otherwise noted.) Gain variation part to part 40 39 38 fC LK =18 M H z 37 36 fC LK =18M H z 35 34 33 32 31 30 2. 7 3 3. 3 Power Dissipation vs. Clock Frequency S up p l V o l y tag e (V o l ts) Grounded Input Noise @ 14MHz Clock Frequency 160000 M in im u m P G A G a in σ = 0 .8 Grounded Input Noise @ 18MHz Clock Frequency 160000 M in im u m P G A G a in 140000 σ = 0 .8 140000 120000 120000 Number of Hits 80000 Number of Hits 100000 100000 80000 60000 60000 40000 40000 20000 20000 0 30 31 32 33 34 35 36 0 30 31 32 33 34 35 36 D ig ita l O u t p u t C o d e ( D e c im a l) D ig ita l O u t p u t C o d e ( D e c im a l) Spectral Response @ 20MHz Clock, Fin= 4.4MHz www.national.com 10 LM98503 CDS Sampling Timing CCD SHP1 CLAMP2 CLK tAD 1SHP 2 tSHP overrides the CLAMP signal’s falling edge for sampling the reset voltage (SHP is active-low by default). The CLAMP signal is an internal signal derived from the CLK input whose falling edge samples the CCD reset voltage by default. Figure 4: Pixel Rate Reset Voltage Sampling CCD SHD1 SAMPLE2 CLK tAD 1SHD 2 tSHD overrides the SAMPLE signal’s falling edge for sampling the video signal (SHD is active-low by default). The SAMPLE signal is an internal signal derived from the CLK input whose falling edge samples the CCD video signal by default. Figure 5: Pixel Rate Video Signal Sampling www.national.com 11 LM98503 Horizontal Interval Timing Effective Pixels Black Pixels Blanking Interval Dummy Black Pixels Effective Pixels CCD BOL ACLP BLKCLP Figure 6: Typical Horizontal Interval Timing Digital Output Timing tAD n n+1 n+2 n+7 tRC 90% n+8 n+9 CCD CLK 10% 10% tFC OUTPUT DATA tOD n-7 tOH n-6 n-5 n-4 tVALID n-3 n-2 n-1 n Figure 7: Digital Output Data Timing www.national.com 12 LM98503 System Timing CCD CLAMP n n+1 n+2 n+3 SHP SAMPLE SHD CLK OUTPUT DATA n-8 n-7 n-2 n-1 n Figure 8: System Timing www.national.com 13 LM98503 System Overview 1.0 Introduction The LM98503 is a 10-bit, complete analog-to-digital camera signal processor for use with CCD imager systems operating from a single +3 Volt supply. The internal processing is carefully optimized to maintain the signal-to-noise ratio and excellent dynamic performance of most popular CCD imagers. The system block diagram of the LM98503, shown on the cover page of the datasheet, highlights the main features of the device: correlated double sampling (CDS), 0-32dB digitally programmable gain amplifier (PGA), digital black level correction feedback loop, 8-bit DAC, analog clamp, bandgap voltage reference, and a 10-bit, 18MHz analog-to-digital converter. 1.1 Correlated Double Sampling signal, before the resulting error is finally applied to the input of the PGA as an analog offset generated by the DAC. The offset integration scaling factor is stored in two bits of the software control register 0, and the values available range from full offset to offset divided-by-16. In addition, an offset output enable bit is provided in the software control register 0, which when set, routes the offset value to the digital output bus rather than the DAC. Use of the automatic mode involves enabling the black level offset auto-calibration bit in the software control register 0 through the serial interface. Refer to Figure 10. Analog Offset Register Black Level Register Automatic Offset Calibration DAC 8 Black Pixels Offset Integration Pixel Averaging BLKCLP Output Data Correlated double sampling (CDS) is a key feature in CCD image processors. The sampling process consists of two samples being taken for each pixel. The first stores the reset voltage of the input pixel, and the second sample stores the video signal amplitude. The two samples are subtracted from one another, effectively removing the reset error offset of each pixel. This sampling system operates from 1 to 18MHz. . Reset Voltage CDS + PGA ADC 10 n CCD n+1 n+2 Figure 10: Digital Black Level Correction Loop The manual method is intended for use with processing systems where the desired black level correction loop is external to the LM98503. In this mode, up to four available configuration registers may be used to store predetermined offset values that will be applied on a pixel-rate basis. During the vertical interval, new values may be stored in these registers for each horizontal line. 1.4 Auxiliary Input Video Signal Figure 9: Correlated Double Sampling 1.2 Programmable Gain Amplifier The LM98503 includes a high-level video switch that allows a an auxiliary video signal to be selected instead of the camera image. When the auxiliary input is selected, the PGA gain and DAC offset are fixed to the value in register 0, so the appropriate gain and offset values should be written to PGA gain and DAC offset register 0 prior to AUX IN usage. 1.5 Analog Clamp The amplifier has a gain ranging from 0-32dB, and is “linear in dB” as shown in Figure 15. The PGA is addressed via an 8 bit word downloaded through the serial interface. 1.3 Black Level Clamp CCD signal processors require a reference level for the proper handling of input signals; this reference level is commonly referred to as the black level. The LM98503 is designed to determine a signal’s black level during the CCD imager’s optical black pixels. The LM98503 provides both an analog clamp and a digital black level correction loop. Pulsing the ACLP pin during optical black pixels causes the analog clamp circuitry to remove the offset associated with the input signal. Pulsing the BLKCLP pin during dummy black pixels at the begining of a horizontal line enables the digital black level correction loop. Black level correction may be performed through one of two available methods- automatic or manual. In automatic mode, the black level is sampled from the ADC output during black pixels by setting the BLKCLP input of the LM98503. The ADC black level output value is then averaged over eight pixels and subtracted from the desired black level code stored in the black level configuration register. The result of the subtraction may then be integrated by a preset scaling factor, effectively smoothing any sharp transitions present in the black level During optical black pixels, a signal appears at the CCD output. This signal is generally refered to as the “black signal level”. This signal may be seen by the CDS circuitry as a valid video signal rather than the actual black level signal; therefore, the LM98503 provides an analog clamp designed to eliminate this black signal level. Pulsing the analog input pin, ACLP, causes the output of the CDS to be sampled by the analog clamp circuitry. Subsequently, an adjustment is made to the CDS reference voltages by the analog clamp to effectively eliminate any signal level present during black pixels. 10-Bit Analog-to-Digital Converter The selected imager’s analog signal is sampled by the CDS and amplified to match the input requirements of the 10-bit analog to digital converter by the PGA. The final step performed by the system is to convert the selected analog image to digital values with a 10 bits of resolution. The ADC has differential inputs which aids in the coping with headroom constraints common to +3 Volt systems. Data is acquired at the falling edge of the clock and is available at the digital output pins 7.0 clock cycles plus tOD later.Internal Timing Generation All if the necessary clocks for the CDS and ADC operation are generated internally from the LM98503’s master clock input. The CDS sampling clocks may be overridden by the user via the SHP and SHD clock inputs. As depicted in Figure 4 and Figure 5, there are two signals generated internally for CDS sampling www.national.com 14 LM98503 System Overview (continued) referred to as CLAMP and SAMPLE.These signals provide the rising edge reference for the sampling of the CCD input signal. The timing of CLAMP and SAMPLE is derived from the clock; therefore, shifting the clock phasing with respect to the CCD input signal would also shift the rising (and falling) edges of CLAMP and SAMPLE. The actual sampling of the CCD’s reset voltage and video signal is performed on the falling edges of the CLAMP and SAMPLE signals respectively. The user may modify the position of the falling edges where the sampling of the CCD input occurs by driving the SHP and SHD inputs of the LM98503. The falling edges of SHP and SHD will supersede the falling edges of CLAMP and SAMPLE respectively and cause the duration of the sample pulse to shorten accordingly. As evidenced in Figure 4 and Figure 5, the falling edges of SHP and SHD should not occur earlier than tSHP or tSHD after the respective falling [SHP] (or rising [SHD]) edge of CLK. 1.6 Serial Interface and Configuration Registers to optical black. For example, a user that wants an output level of 16 for black pixels must write this value into the register during the horizontal interval. Note that it is not recommended that a value of 0 be stored as the output black level. Once this has been accomplished, driving the BLKCLP high for 20 cycles of CLK activates the digital black clamp loop and the black level is forced to the value stored in the output black level register, in the example case the code value of 16. As a result of the relationship between the DAC input and the ADC output, under default conditions the largest black level code the LM98503 is capable of clamping to is 36 codes. As a result, the offset DAC may be ‘pinned’ at full range when the default setting of 32 is used. When this occurs, the result may be that the DAC is unable to correct line to line variations in the black level. consequently, horizontal lines or ‘banding’ may be observed. See Analog Offset DAC Range Adjustment, Section 3.0 of the applications information for instructions on how to increase this range. 60 LM98501, LM98502 50 ADC Output Code There are many options available to the user that may be programmed via the LM98503’s serial interface. Configuration values are stored in registers for use by several functions such as programmable gain, offset, black level, and color filter array. The LM98503’s serial interface is used to store values into 16 8bit configuration registers. Upon power-up or external reset, the configuration registers will contain their respective default values. Default values place the LM98503 in ‘single channel’ mode, where only one PGA gain and offset are applied to the input signal. The master CLK input is required to be running during serial interface commands. Each command issued through the serial interface must have a minimum of 13 data bits (see Figure 12 and Figure 13). 1.7 PGA Gain Registers 40 LM98503 Default Black Level 30 20 10 0 0 15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240 255 Output Black Level Register Value Figure 11: ADC Output vs. Black Level Register Value 1.10 Color Filter Array (CFA) Configuration Four PGA gain registers store four possible gain values for the programmable gain amplifier (PGA). For example, these four gain values may correspond to four possible colors in a color filter array. 1.8 Analog Offset In order to utilize the LM98503’s programmable pixel-rate gain, a color filter array (CFA) pattern must be defined. Some commonly used CFA patterns are as follows: Bayer Pattern Line 0 Line 1 Green Blue Red Green Green Blue Red Green Four analog offset registers store four possible offset values that correspond to the four PGA gain values. For example, the value stored in the PGA gain register 0 (address 0h) is used in conjunction with the offset value stored in the analog offset register 0 (address 4h). This allows for four possible combinations of PGA gain and analog offset, one for each color filter. These registers are read-only when offset auto-calibration is enabled in the software control register 0. It should be noted that each offset DAC step (1 LSB) corresponds to a 0.4 LSB step at the ADC output. Therefore, if an offset of 20 digital codes is desired at the ADC output, a digital code value of 50 should be stored in the analog offset register(s). As a result, the maximum offset seen at the ADC output as a result of digital code values stored in the analog offset register(s) is ±54 codes. It is possible to increase the digital output range of the analog offset DAC, resulting in an increased maximum ADC output code corresponding to a given DAC input, but at the expense of DAC step resolution. For more information on increasing the DAC range, please see “Analog Offset DAC Range Adjustment” on page 23. 1.9 Output Black Level CMYG Pattern Line 0 Line 1 Cyan Cyan Magenta Green Yellow Yellow Green Magenta Therefore, two 8-bit words must be written to the CFA line registers to specify the CFA pattern being used. Also, two 2-bit numbers must be written to the CFA definition register indicating the number of pixels per pattern in each line of the defined CFA pattern. The information contained in the CFA line registers indicates the registers where the respective PGA gain and offset values are stored. For example, a system using the Bayer pattern defined above would first write four PGA gains and their respective offsets into the four PGA gain and four analog offset registers. Next, two 8-bit words (one word/CFA line) would be written to the CFA configuration registers. The 8-bit CFA configuration words each consist of four 2-bit numbers, each of which is the address for the gain and offset values of the of the color that appears in that location in the CFA line. Finally, two 2bit numbers specifying the number of elements in each CFA line must be written into the CFA definition register. A CFA configuration will then contain four 2-bit numbers indicating the registers where the gain and offset values are located for a The output black level register is occupied by an 8-bit word stored by the user that specifies the output level corresponding www.national.com 15 LM98503 System Overview (continued) configuration will then contain four 2-bit numbers indicating the registers where the gain and offset values are located for a maximum of four colors on each CFA line. In addition, the CFA definition register will contain two 2-bit numbers that designate the number of elements used in each CFA line for the particular CFA pattern being applied to the system. Example A contains a CFA pattern that repeats the colors cyan and magenta on the first line, and repeats the pattern blue, green, green, blue on the second line. Each 2-bit number in the CFA line registers refers to a common set of PGA gain and offset registers for each color. The first line indicates that the color magenta uses the gain and offset values stored in PGA gain register 1 (address 1h) and analog offset register 1 (address 5h). Also, the first line indicates that the color cyan uses the gain and offset values in PGA gain register 2 (address 2h) and analog offset register 2 (address 6h). The second line indicates gain and offset values for the color blue and the color green in the same fashion as the first line. Example A 7 CFA Line 0 CFA Line 1 CFA Definition XX 11 00 XX 00 00 01 00 11 0 10 11 01 descriptions for more information regarding the power level control registers. The ADC coarse and fine bank power adjustment bits are located in the power level control 2 register, bits 7:4. Altering these bits may significantly affect performance and power dissipation. Please see ’DNL vs. Power Control Setting @ 18MHz Clock Frequency’ and ’Power Dissipation vs. Power Control Setting’ on page ’13. In addition to specifying the gain and offset for each line, it is also necessary to specify the number of elements contained in each CFA line’s pixel pattern. The CFA definition register is used to store this value (number of elements per line). In example A, the user has stored the 2-bit binary number 01 into the CFA definition register’s two LSB’s indicating that the pattern in line 0 contains two repeating colors or elements. Also, the 2-bit binary number 11 has been written into bit 2 and bit 3 of the CFA definition register indicating that the respective CFA pattern contains four repeating colors or elements, as the colors blue and green alternate position in the example pattern. Once both lines for the pattern have been stored, it is applied when the beginning of line (BOL) signal is asserted by the user. One line of the CFA pattern is applied repeatedly until the BOL signal is reset (at the end of the current line). Once the BOL signal is set again, the CFA line information is changed from that defined by the CFA line 0 register to that defined by the CFA line 1 register and the process starts again. For more details of the timing of the BOL signal, please refer to Figure 6. 1.11 Software Control There are two software control registers accessible via the serial interface. The software control registers are divided into customer (register 0) and advanced (register 1) functions. Please refer to the register data descriptions for more information on the software control registers. 1.12 Power Level Control The LM98503 is equipped with two power trim registers that may be used to adjust power levels of various circuits internal to the device. In its default condition, the LM98503 is set for optimum power and performance, and modifying the values stored in the power level control registers will affect performance as a result of the change in power level(s). In applications where maximum performance is desired, the default values should be used. Otherwise, power levels may be decreased at the slight expense of performance. Please refer to the register data www.national.com 16 LM98503 Register Memory Map Title PGA Gain 0 PGA Gain 1 PGA Gain 2 PGA Gain 3 Analog Offset 0 Analog Offset 1 Analog Offset 2 Analog Offset 3 CFA Configuration 0 CFA Configuration 1 CFA Definition Output Black Level Software Control 0 Software Control 1 Power Level Control 0 Power Level Control 1 Address 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Default Value 0000 0000 (0d) 0000 0000 (0d) 0000 0000 (0d) 0000 0000 (0d) 0000 0000 (0d) 0000 0000 (0d) 0000 0000 (0d) 0000 0000 (0d) 0000 0000 (0d) 0000 0000 (0d) XXXX 0000 (0d) 0001 0000 (32d) 0100 1110 (78d) XX00 0X00 (0d) 1010 1010 (170d) 0101 1010 (90d) Register Data The following section describes all available registers in the LM98503 register bank and their functions. 2.0 PGA Gain Registers Register Name Address Type Reset Value Bit [7:0] PGA Gain 3 3 Hex Read/Write 0000 0000 Binary Description 0.0dB - 32.0dB in 0.125dB steps. Register Name Address Type Reset Value Bit [7:0] PGA Gain 0 0 Hex Read/Write 0000 0000 Binary Description 0.0dB - 32.0dB in 0.125dB steps. Bit Symbol PGA Gain Bit Symbol PGA Gain 3.0 Analog Offset Registers Register Name Address Type Reset Value Bit [7:0] PGA Gain 1 1 Hex Read/Write 0000 0000 Binary.Register NamePGA Gain Description 0.0dB - 32.0dB in 0.125dB steps. Register Name Address Type: Reset Value Bit [7:0] Analog Offset 0 4 Hex Read/Write 0000 0000 Binary Description Digital representation of the analog offset to be applied to the input of the PGA. See “Analog Offset” on page 15. Bit Symbol Signed Analog Offset Bit Symbol PGA Gain Address Type Reset Value Bit [7:0] 2 2 Hex Read/Write 0000 0000 Binary Bit Symbol PGA Gain Description 0.0dB - 32.0dB in 0.125dB steps. www.national.com 17 LM98503 Register Data (continued) Register Name Address Type Reset Value Bit [7:0] Analog Offset 1 5 Hex Read/Write 0000 0000 Binary Description Digital representation of the analog offset to be applied to the input of the PGA. See “Analog Offset” on page 15. Register Name Address Type Reset Value Bit [7:6] Color Filter Array Configuration 1 9 Hex Read/Write 0000 0000 Binary) Description 2 LSB’s of register addresses where the gain and offset for pixel 3 of the CFA pattern are stored. 2 LSB’s of register addresses where the gain and offset for pixel 2 of the CFA pattern are stored. 2 LSB’s of register addresses where the gain and offset for pixel 1 of the CFA pattern are stored. 2 LSB’s of register addresses where the gain and offset for pixel 0 of the CFA pattern are stored. Bit Symbol Line1:Pixel3 Gain/Offset Bit Symbol Signed Analog Offset [5:4] Line1:Pixel2 Gain/Offset Register Name Address Type Reset Value Bit [7:0] Analog Offset 2 6 Hex Read/Write 0000 0000 Binary Description Digital representation of the analog offset to be applied to the input of the PGA. See “Analog Offset” on page 15. [3:2] Line1:Pixel 1 Gain/Offset Bit Symbol Signed Analog Offset [1:0] Line1:Pixel0 Gain/Offset Register Name Address Type Reset Value Bit [7:0] Analog Offset 3 7 Hex Read/Write 0000 0000 Binary Description Digital representation of the analog offset to be applied to the input of the PGA. See “Analog Offset” on page 15. Register Name Address Type Reset Value Bit [3:2] Color Filter Array Definition A Hex Read/Write XXXX 0000 Binary Description Number of pixels in CFA pattern defined in CFA line 1. Number of pixels in CFA pattern defined in CFA line 0. Bit Symbol Line 1 Pixels Bit Symbol Signed Analog Offset [2:1] Line 0 Pixels 5.0 Output Black Level Register 4.0 Color Filter Array Registers Register Name Address Type Reset Value Bit [7:6] Color Filter Array Configuration 0 8 Hex Read/Write 0000 0000 Binary Description 2 LSB’s of register addresses where the gain and offset for pixel 3 of the CFA pattern are stored. 2 LSB’s of register addresses where the gain and offset for pixel 2 of the CFA pattern are stored. 2 LSB’s of register addresses where the gain and offset for pixel 1 of the CFA pattern are stored. 2 LSB’s of register addresses where the gain and offset for pixel 0 of the CFA pattern are stored. Register Name Address Type Reset Value Bit [7:0] Output Black Level B Hex Read/Write 0001 0000 Binary Description 0 - 256 output black level digital code value. (see “Output Black Level” on page 15) Bit Symbol Black Level Bit Symbol Line0:Pixel3 Gain/Offset 6.0 Software Control Registers [5:4] Line0:Pixel2 Gain/Offset [3:2] Line0:Pixel 1 Gain/Offset Register Name Address Type Reset Value Bit [7] Software Control 0 (Customer) C Hex Read/Write 0100 1110 Binary Description Directs the offset error calculated by the digital black level correction loop to the 10 digital output data pins. Enables the serial interface output for reading register values. Bit Symbol Offset Output Enable [1:0] Line0:Pixel0 Gain/Offset [6] Serial Output Enable www.national.com 18 LM98503 Register Data (continued) Register Name Address Type Reset Value Bit [5:4] Software Control 1 D Hex Read/Write XX00 0X00 Binary Description Bit [5:4] Bit Symbol PGA CommonMode Input Bias CDS Amplifier Bias Description Adjusts the power level of the PGA common-mode input. The power level is relative to the value of the binary number stored. Adjusts the power level of the CDS amplifier. The power level is relative to the value of the binary number stored. Adjusts the power level of the CDS common-mode input. The power level is relative to the value of the binary number stored. Bit Symbol Analog Output Select [3:2] Routes the selected internal analog signal to the differential analog output pins AOUT+ and AOUT-. 00 CDS 01 PGA Stage 1 10 PGA Stage 2 11 PGA Stage 3 Enables the differential analog output pins AOUT+ and AOUT-. If the analog outputs are disabled, the pins should not be loaded. Reference biasing selection for the analog-to-digital converter. 0 Passive biasing (resistors) 1 Active biasing (bandgap) Reference biasing selection for the digital-to-analog converter. 0 Active biasing (bandgap) 1 Passive biasing (resistors) Offset integration factor selection: 00 No Scaling 01 Divide-by-4 10 Divide-by-8 11 Divide-by-16 Enables the digital black level correction loop. Analog offset registers are read-only when offset auto-calibration is enabled. Inverts the SHP and SHD inputs causing the CDS to sample on the rising edges of SHP and SHD. Sampling is performed on the falling edges of SHP and SHD when the signals are active-low. Instructs the CDS to sample the CCD input. Otherwise, the AUX In input is sampled in sample-andhold mode. Cuts power to the on-chip analog circuitry including the CDS, PGA, ADC, and bandgap references. [1:0] CDS CommonMode Input Bias [3] Analog Output Enable Register Name Address Type Reset Value Bit [7:6] Power Level Control 1 F Hex Read/Write 0101 1010 Binary Description Adjusts the power level of the ADC coarse bank. The power level is relative to the value of the binary number stored. Adjusts the power level of the ADC fine bank. The power level is relative to the value of the binary number stored. Adjusts the power level of the PGA stage 3 amplifier. The power level is relative to the value of the binary number stored. Adjusts the power level of the PGA stage 2 amplifier. The power level is relative to the value of the binary number stored. [1] ADC Reference Select Bit Symbol ADC Coarse Bank Bias [0] DAC Reference Select [5:4] ADC Fine Bank Bias [5:4] Offset Integration [3:2] PGA Stage 3 Amplifier Bias [3] Offset AutoCalibration Enable [1:0] PGA Stage 2 Amplifier Bias [2] SHP/SHD Active-HIGH Enable [1] CDS Enable (AUX-In disable) [0] Analog Power Down Register Name Address Type Reset Value Bit [7:6] Power Level Control 0 E Hex Read/Write 1010 1010 Binary Description Adjusts the power level of the PGA stage 1 amplifier. The power level is relative to the value of the binary number stored. Bit Symbol PGA Stage 1 Amplifier Bias www.national.com 19 LM98503 Serial Interface Timing Specifications The following specifications apply for all supply pins = +3.0V, CL = 10pF, and fCLK = 18MHz unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25oC (Note 7) Symbol tMIN Parameter SCLK Period SCLK Duty Cycle SCLK Rise / Fall Time tCESC tDCE SCLK Start Time After CE Low Input Data to CE Rising Edge 10 13 Conditions Min note 9 55 50/50 60/40 4 Typical note 8 Max note 9 Units ns % ns ns tMIN Serial Interface Timing tCEW tIH tSCCE tIS SCLK /CE SI DATA XX 1 A3 A2 A1 A0 XX 1 A3 A2 A1 A0 SO DATA1 tDCE 1 Serial D7 D6 D5 D4 D3 D2 D1 D0 tOD output enable must be set in software control 0 for SO DATA output. Please see register data section for more information. Figure 12: Serial Interface Read Command Timing tCEW tIH tCESC tIS tMIN SCLK /CE SI DATA XX 0 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 XX 0 A3 A2 A1 A0 SO DATA1 tDCE 1 D7 D6 D5 D4 D3 D2 D1 D0 Serial output enable must be set in software control 0 for SO DATA output. Please see register data section for more information. Figure 13: Serial Interface Write Command Timing www.national.com 20 LM98503 Serial Interface Read/Write Description 1.0 Writing to the Serial Registers To write to the serial registers, the timing diagram shown in Figure 13 must be met. First CE is toggled low. SI DATA may then be clocked in, and the data present on the rising edge of the serial clock is loaded in. The data continues to be clocked in, until CE toggles high. The data present in the register is the last 13 bits of data sent before CE toggled high. Therefore, for example, if 20 bits were sent when CE was toggled low, the first 7 bits were discarded, and the data loaded are the remaining 13 bits. As seen in Figure 13, these 13 bits are composed of 8 data bits, 4 address bits, and 1 read/write bit. When writing to the registers, the read/write bit must be low. When CE toggles high, the register is written to, and the LM98503 now functions with this new data. 2.0 Reading the Serial Registers To read the serial registers, the timing diagram shown in Figure 12 must be met. When CE is toggled low, and data is loaded as described above in the writing sequence. When CE toggles high, the new 13 bit word is considered, except this time the read/write bit should be a 1 indicating a read. The 8 data bits are not considered, but act only as place holders. When CE toggles low again, the data that resides at the address considered in the previous read or write routine, begins clocking out SO DATA. The data streams out MSB-LSB as shown in Figure 12. Whether a read or a write was invoked in the previous sequence, the SO DATA will clock out the contents of the address considered in the previous sequence. www.national.com 21 LM98503 PGA Gain Plots 40 Max. Gain = 39.0 35 30 25 PGA Gain (V/V) 20 15 10 5 0 0 15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240 255 Figure 14: PGA Gain (Linear Scale) vs. PGA Gain Code 35 Max. Gain = 32.0 dB 30 25 PGA Gain (dB) 20 15 10 5 0 0 15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240 255 PGA Gain Code Figure 15: PGA Gain (Logarithmic Scale) vs. PGA Gain Code www.national.com 22 LM98503 Applications Information 3.0 Analog-to-Digital Converter Reference Bypassing Figure 16 shows a simple reference bypassing scheme with minimal components. The VREFT and VREFB pins should each be bypassed to analog ground with 10µF tantalum as well as 0.1µF ceramic capacitors. In a case where the internally generated reference voltages are not sufficient, the user may supply external voltages to the reference pins. However, the reference pin VREFT should be within the range of 2.0 to 2.5 Volts. Similarly, VREFB should be driven in the range of 0.4 to 0.9 Volts. Any device used to drive the reference pins should be able to source adequate current into the VREFT and sink adequate current from the VREFB pin when the reference resistor ladder is at its minimum resistivity of 850Ω. The reference voltage at the top of the resistor ladder (VREFT) may be as low as 1.2 Volts above the voltage at the bottom of the resistor ladder (VREFB) and may be as high as 1.8 Volts above. VREFB may be as low as 0.4 Volts and as high as 0.9 Volts above ground. However, noise effects will be minimized and accurate conversions insured when the total reference voltage is approximately 2.25 Volts and offset from ground by 0.75 Volts. AV+ 960Ω VREFT 0.1µF 10µF of ±128 LSB to be applied at the ADC output rather than the default maximum and minimum offsets of ±64 LSB, resulting in a 0.8 LSB DAC step to 1 LSB ADC output step relationship. Power Supply Considerations The LM98503 may draw a sufficient amount of current to corrupt improperly bypassed power supplies. A 10µF to 50µF capacitor should be placed within 1cm of the analog power (AV+) pins of the device in parallel with a 0.1µF ceramic chip capacitor placed as close to the device as layout permits. Leadless chip capacitors are preferred because they have a low lead inductance. As is the case with virtually all high-speed semiconductors, the LM98503 should be assumed to have little power supply rejection; therefore, a noise-free analog power source is required. The analog and digital power supplies of the LM98503 should be sourced from the same supply voltage, but the supply pins should be well isolated from one another. Isolating the supplies prevents digital noise from coupling back into the analog supply pins. A choke (ferrite bead) is recommended to be placed between the analog and digital power supply pins as well as a ceramic chip capacitor placed as close as possible to the analog supply pin(s) of the device. Additionally, it is not recommended that the LM98503’s digital supply be used for any other digital circuitry on the circuit board. All other digital devices should be powered from a separate digital supply well isolated from both the analog and digital supplies of the LM98503. 6.0 The LM98503 Clock AGND 1kΩ Although the LM98503 is tested and its performance guaranteed with a 18MHz clock, it typically will function with clock frequencies ranging from 1MHz to 20MHz (see the LM98501 for conversion speeds greater than 20MHz). Performance is best if the clock rise and fall times are less than 5ns and the clock trace is terminated near the clock input pin with a series RC network consisting of a 100Ω resistor and a 47pF capacitor. 7.0 Layout and Grounding Techniques 0.1µF VREFB 610Ω AGND AGND LM98503 Figure 16: Reference Bypassing 4.0 Analog Offset DAC Reference Bypassing The proper routing of all signals and pertinent grounding techniques are essential to insure the best signal-to-noise ratio and dynamic performance possible. Separate analog and digital ground planes ease meeting the datasheet limits. The analog ground plane should be low impedance and free from noise of other components of the system. All bypass capacitors should be located as close to the pin as possible and connected to the appropriate ground plane with short traces (