LMC6574AIN

LMC6572 Dual/LMC6574 Quad Low Voltage (2.7V and 3V) Operational Amplifier December 1996 LMC6572 Dual/LMC6574 Quad Low Voltage (2.7V and 3V) Operational Amplifier General Description Low voltage operation and low power dissipation make the LMC6574/2 ideal for battery-powered systems. 3V amplifier performance is backed by 2.7V guarantees to ensure operation throughout battery lifetime. These guarantees also enable analog circuits to operate from the same 3.3V supply used for digital logic. Battery life is maximized because each amplifier dissipates only micro-watts of power. The LMC6574/2 does not sacrifice functionality for low voltage operation. The LMC6574/2 generates 120 dB of open-loop gain just like a conventional amplifier, but the LMC6574/2 can do this from a 2.7V supply. These amplifiers are designed with features that optimize low voltage operation. The output voltage swings rail-to-rail to maximize signal-to-noise ratio and dynamic signal range. The common-mode input voltage range extends from 800 mV below the positive supply to 100 mV below ground. This device is built with National’s advanced Double-Poly Silicon-Gate CMOS process. LMC6572 is also available in MSOP package which is almost half the size of a SO-8 device. Features (Typical unless otherwise noted) n Guaranteed 2.7V and 3V Performance n Rail-to-Rail Output Swing (within 5 mV of supply rail, 100 kΩ load) n Ultra-Low Supply Current: 40 µA/Amplifier n Low Cost n Ultra-Low Input Current: 20 fA n High Voltage Gain @ VS = 2.7V, RL = 100 kΩ: 120 dB n Specified for 100 kΩ and 5 kΩ loads n Available in MSOP Package Applications n n n n n n Transducer Amplifier Portable or Remote Equipment Battery-Operated Instruments Data Acquisition Systems Medical Instrumentation Improved Replacement for TLV2322 and TLV2324 Connection Diagrams 8-Pin DIP/SO/MSOP 14-Pin DIP/SO DS011934-1 Order Number LMC6572AIN, LMC6572BIN, LMC6572AIM, LMC6572BIM or LMC6572BIMM See NS Package Number N08E, M08A or MUA08A DS011934-2 Order Number LMC6574AIN, LMC6574BIN, LMC6574AIM or LMC6574BIM See NS Package Number N14A or M14A © 1999 National Semiconductor Corporation DS011934 www.national.com Ordering Information Package 8-Pin Molded DIP 8-Pin Small Outline 8-Pin Mini SO 14-Pin Molded DIP 14-Pin Small Outline Temperature Range Industrial, −40˚C to +85˚C LMC6572AIN, LMC6572BIN LMC6572AIM, LMC6572BIM LMC6572AIMX, LMC6572BIMX LMC6572BIMM LMC6572BIMMX LMC6574AIN, LMC6574BIN LMC6574AIM, LMC6574BIM LMC6574AIMX, LMC6574BIMX N14A M14A MUA08A N08E M08A NSC Drawing Transport Media Rail Rail Tape and Reel Rail Tape and Reel Rail Rail Tape and Reel www.national.com 2 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. ESD Tolerance (Note 2) Differential Input Voltage Voltage at Input/Output Pin Supply Voltage (V+ − V−) Current at Input Pin Current at Output Pin (Note 3) Current at Power Supply Pin Lead Temperature (Soldering, 10 Seconds) Storage Temperature Range 2000V ± Supply Voltage (V+) +0.3V, (V−) −0.3V 12V ± 5 mA ± 10 mA 35 mA 260˚C −65˚C to +150˚C Junction Temperature (Note 4) 150˚C Operating Ratings (Note 1) Supply Voltage Junction Temperature Range LMC6572AI, LMC6572BI LMC6574AI, LMC6574BI Thermal Resistance (θJA) N Package, 8-Pin Molded DIP M Package, 8-Pin Surface Mount MSOP Package, 8-Pin Mini SO N Package, 14-Pin Molded DIP M Package, 14-Pin Surface Mount 2.7V ≤ V+ ≤ 11V −40˚C ≤ TJ ≤ +85˚C −40˚C ≤ TJ ≤ +85˚C 115˚C/W 193˚C/W 217˚C/W 81˚C/W 126˚C/W 2.7V DC Electrical Characteristics Unless otherwise specified, all limits guaranteed for TJ = 25˚C. V+ = 2.7V, V− = 0V, VCM = VO = V+/2 and RL > 1MΩ. Boldface limits apply at the temperature extremes. Symbol Parameter Conditions Typ (Note 5) LMC6574AI LMC6572AI Limit (Note 6) VOS TCVOS IB IOS RIN CIN CMRR +PSRR −PSRR VCM Input Offset Voltage Input Offset Voltage Average Drift Input Current Input Offset Current Input Resistance Common-Mode Input Capacitance Common Mode Rejection Ratio Positive Power Supply Rejection Ratio Negative Power Supply Rejection Ratio Input Common-Mode Voltage Range 0V ≤ VCM ≤ 3.5V V+ = 5V 2.7V ≤ V+ ≤ 5V, V− = 0V −2.7V ≤ V− ≤ −5V, V+ = 0V V+ = 2.7V and 3V for CMRR ≥ 50 dB V+ − 0.8 AV Large Signal Voltage Gain RL = 100 kΩ (Note 7) Sinking 500 V/mV Sourcing 1000 + LMC6574BI LMC6572BI Limit (Note 6) 7 7.5 Units V+ = 2.7V and 3V 0.5 1.5 0.02 3 3.5 mV Max µV/˚C pA 10 0.01 6 10 6 Max pA Max Tera Ω pF >1 3 75 75 83 −0.1 63 60 67 65 75 73 −0.05 0 V+ − 1.0 V − 1.3 60 57 60 58 67 65 −0.05 0 V+ − 1.0 V+ − 1.3 dB Min dB Min dB Min V Max V Min V/mV 3 www.national.com 2.7V DC Electrical Characteristics Symbol Parameter (Continued) Unless otherwise specified, all limits guaranteed for TJ = 25˚C. V+ = 2.7V, V− = 0V, VCM = VO = V+/2 and RL > 1MΩ. Boldface limits apply at the temperature extremes. Conditions Typ (Note 5) LMC6574AI LMC6572AI Limit (Note 6) VO Output Swing V+ = 2.7V RL = 100 kΩ to V+/2 2.695 0.005 V+ = 2.7V RL = 5 kΩ to V+/2 2.66 0.04 V+ = 3V RL = 100 kΩ to V+/2 2.995 0.005 V+ = 3V RL = 5 kΩ to V+/2 2.96 0.04 ISC Output Short Circuit Current Sinking, VO = 2.7V IS Supply Current Quad Package V+ = +2.7V, VO = V+/2 Quad Package V+ = +3V, VO = V+/2 Dual Package V+ = +2.7V, VO = V+/2 Dual Package V+ = +3V, VO = V+/2 4.0 160 160 80 80 Sourcing, VO = 0V 6.0 2.68 2.66 0.03 0.05 2.55 2.45 0.15 0.25 2.98 2.96 0.03 0.05 2.85 2.75 0.15 0.25 4.0 3.0 3.0 2.0 240 280 240 280 120 140 120 140 LMC6574BI LMC6572BI Limit (Note 6) 2.65 2.62 0.06 0.09 2.45 2.35 0.25 0.35 2.95 2.93 0.06 0.09 2.75 2.65 0.25 0.35 3.0 2.0 2.5 1.5 240 280 240 280 120 140 120 140 V Min V Max V Min V Max V Min V Max V Min V Max mA Min mA Min µA Max µA Max µA Max µA Max Units 2.7V AC Electrical Characteristics Unless otherwise specified, all limits guaranteed for TJ = 25˚C, V+ = 2.7V, V− = 0V, VCM = VO = V+/2 and RL > 1 MΩ. Boldface limits apply at the temperature extremes. Symbol Parameter Conditions Typ (Note 5) LMC6574AI LMC6572AI Limit (Note 6) SR GBW φm Gm en in Slew Rate Gain-Bandwidth Product Phase Margin Gain Margin Amp-to-Amp Isolation Input-Referred Voltage Noise Input-Referred (Note 9) F = 1 kHz VCM = 1V F = 1 kHz 4 LMC6574BI LMC6572BI Limit (Note 6) 30 10 Units V+ = 2.7V and 3V (Note 8) V+ = 3V 90 0.22 60 12 120 45 0.002 30 10 V/ms Min MHz Deg dB dB nV/√Hz pA/√Hz www.national.com 2.7V AC Electrical Characteristics Symbol Parameter (Continued) Unless otherwise specified, all limits guaranteed for TJ = 25˚C, V+ = 2.7V, V− = 0V, VCM = VO = V+/2 and RL > 1 MΩ. Boldface limits apply at the temperature extremes. Conditions Typ (Note 5) LMC6574AI LMC6572AI Limit (Note 6) Current Noise T.H.D. Total Harmonic Distortion F = 10 kHz, AV = −2 RL = 10 kΩ, VO = 1.0 VPP 0.05 % LMC6574BI LMC6572BI Limit (Note 6) Units Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and test conditions, see the Electrical Characteristics. Note 2: Human body model, 1.5 kΩ in series with 100 pF. Note 3: Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150˚C. Note 4: The maximum power dissipation is a function of TJ(Max), θJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(Max) − TA)/θJA. All numbers apply for packages soldered directly into a PC board. Note 5: Typical values represent the most likely parametric norm. Note 6: All limits are guaranteed by testing or statistical analysis. Note 7: V+ = 3V, VCM = 1.5V and RL connected to 1.5V. For Sourcing tests, 1.5V ≤ VO ≤ 2.5V. For Sinking tests, 0.5V ≤ VO ≤ 1.5V. Note 8: Connected as Voltage Follower with 1.0V step input. Number specified is the slower of the positive and negative slew rates. Note 9: Input referred, V+ = 3V and RL = 100 kΩ connected to 1.5V. Each amp excited in turn with 1 KHz to produce VO = 2 VPP. Typical Performance Characteristics Supply Current vs Supply Voltage (Dual Package) Input Current vs Temperature VS = +3V, TA = 25˚C, Unless otherwise specified Sourcing Current vs Output Voltage DS011934-18 DS011934-19 DS011934-20 Sinking Current vs Output Voltage Output Voltage Swing vs Supply Voltage Input Voltage Noise vs Frequency DS011934-21 DS011934-22 DS011934-23 5 www.national.com Typical Performance Characteristics Crosstalk Rejection vs Frequency VS = +3V, TA = 25˚C, Unless otherwise specified (Continued) Negative PSRR vs Frequency Positive PSRR vs Frequency DS011934-24 DS011934-25 DS011934-26 CMRR vs Frequency Input Voltage vs Output Voltage (VS = ± 1.5) Open Loop Frequency Response DS011934-27 DS011934-28 DS011934-29 Open Loop Frequency Response vs Temperature Maximum Output Swing vs Frequency ZOUT vs Frequency DS011934-32 DS011934-30 DS011934-31 www.national.com 6 Typical Performance Characteristics Slew Rate vs Supply Voltage VS = +3V, TA = 25˚C, Unless otherwise specified (Continued) Non-Inverting Small Signal Pulse Response Non-Inverting Large Signal Pulse Response DS011934-33 DS011934-34 DS011934-35 Inverting Large Signal Pulse Response Inverting Small Signal Pulse Response Stability vs Capacitive Load DS011934-36 DS011934-37 DS011934-38 Stability vs Capacitive Load Stability vs Capacitive Load Stability vs Capacitive Load DS011934-39 DS011934-40 DS011934-41 7 www.national.com Typical Performance Characteristics Bandwidth vs Capacitive Load VS = +3V, TA = 25˚C, Unless otherwise specified (Continued) Capacitive Load vs Gain Margin Capacitive Load vs Phase Margin DS011934-44 DS011934-45 DS011934-46 Applications Hints 1.0 LOW VOLTAGE AMPLIFIER TOPOLOGY The LMC6574/2 incorporates a novel op-amp design topology that enables it to maintain rail-to-rail output swing even when driving a large load. Instead of relying on a push-pull unity gain output buffer stage, the output stage is taken directly from the internal integrator, which provides both low output impedance and large gain. Special feed-forward compensation design techniques are incorporated to maintain stability over a wider range of operating conditions than traditional micropower op-amps. These features make the LMC6574/2 both easier to design with, and provide higher speed than products typically found in this ultra-low power class. 2.0 COMPENSATING FOR INPUT CAPACITANCE It is quite common to use large values of feedback resistance for amplifiers with ultra-low input current, like the LMC6574/2. Although the LMC6574/2 is highly stable over a wide range of operating conditions, a large feedback resistor will react even with small values of capacitance at the input of the op-amp to reduce phase margin. The capacitance at the input of the op-amp comes from transducers, photodiodes and circuit board parasitics. The effect of input capacitance can be compensated for by adding a capacitor, Cf, around the feedback resistors (as in Figure 1) such that: DS011934-6 FIGURE 1. Cancelling the Effect of Input Capacitance 3.0 CAPACITIVE LOAD TOLERANCE Direct capacitive loading will reduce the phase margin of many op-amps. A pole in the feedback loop is created by the combination of the op-amp’s output impedance and the capacitive load. This pole induces phase lag at the unity-gain crossover frequency of the amplifier resulting in either an oscillatory or underdamped pulse response. With a few external components, op amps can easily indirectly drive capacitive loads, as shown in Figure 2. or R1 CIN ≤ R2 Cf Since it is often difficult to know the exact value of CIN, Cf can be experimentally adjusted so that the desired pulse response is achieved. Refer to the LMC660 and LMC662 for a more detailed discussion on compensating for input capacitance. When high input impedances are demanded, guarding of the LMC6574/2 is suggested. Guarding input lines will not only reduce leakage, but lowers stray input capacitance as well. (See Printed-Circuit-Board Layout for High Impedance Work). DS011934-7 FIGURE 2. LMC6574/2 Noninverting Gain of 10 Amplifier, Compensated to Handle Capacitive Loads In the circuit of Figure 2, R1 and C1 serve to counteract the loss of phase margin by feeding the high frequency compo- www.national.com 8 Applications Hints (Continued) nent of the output signal back to the amplifier’s inverting input, thereby preserving phase margin in the overall feedback loop. 4.0 PRINTED-CIRCUIT-BOARD LAYOUT FOR HIGH-IMPEDANCE WORK It is generally recognized that any circuit which must operate with less than 1000 pA of leakage current requires special layout of the PC board. When one wishes to take advantage of the ultra-low bias current of the LMC6574/2, typically less than 20 fA, it is essential to have an excellent layout. Fortunately, the techniques of obtaining low leakages are quite simple. First, the user must not ignore the surface leakage of the PC board, even though it may sometimes appear acceptably low, because under conditions of high humidity or dust or contamination, the surface leakage will be appreciable. To minimize the effect of any surface leakage, lay out a ring of foil completely surrounding the LMC6574/2’s inputs and the terminals of capacitors, diodes, conductors, resistors, relay terminals, etc. connected to the op-amp’s inputs, as in Figure 3. To have a significant effect, guard rings should be placed on both the top and bottom of the PC board. This PC foil must then be connected to a voltage which is at the same voltage as the amplifier inputs, since no leakage current can flow between two points at the same potential. For example, a PC board trace-to-pad resistance of 1012Ω, which is normally considered a very large resistance, could leak 5 pA if the trace were a 5V bus adjacent to the pad of the input. This would cause a 250 times degradation from the LMC6574/2’s actual performance. However, if a guard ring is held within 5 mV of the inputs, then even a resistance of 1011Ω would cause only 0.05 pA of leakage current. See Figure 4 for typical connections of guard rings for standard op-amp configurations. DS011934-9 Inverting Amplifier DS011934-10 Non-Inverting Amplifier DS011934-11 Follower FIGURE 4. Typical Connections of Guard Rings The designer should be aware that when it is inappropriate to lay out a PC board for the sake of just a few circuits, there is another technique which is even better than a guard ring on a PC board: Don’t insert the amplifier’s input pin into the board at all, but bend it up in the air and use only air as an insulator. Air is an excellent insulator. In this case you may have to forego some of the advantages of PC board construction, but the advantages are sometimes well worth the effort of using point-to-point up-in-the-air wiring. See Figure 5. DS011934-8 FIGURE 3. Example of Guard Ring in P.C. Board Layout DS011934-12 (Input pins are lifted out of PC board and soldered directly to components. All other pins connected to PC board). FIGURE 5. Air Wiring 9 www.national.com Applications Hints 5.0 SPICE MACROMODEL (Continued) A spice macromodel is available for the LMC6574/2. This model includes accurate simulation of: • input common-mode voltage range • frequency and transient response • GBW dependence on loading conditions • quiescent and dynamic supply current • output swing dependence on loading conditions and many more characteristics as listed on the macromodel disk. Contact your local National Semiconductor sales office to obtain an operational amplifier spice model library disk. Typical Single-Supply Applications DS011934-15 FIGURE 8. 1 Hz Square Wave Oscillator DS011934-13 FIGURE 6. Low-Power Two-Op-Amp Instrumentation Amplifier DS011934-16 FIGURE 9. Adder/Subtractor Circuit DS011934-14 FIGURE 7. Sample and Hold DS011934-17 FIGURE 10. Low Pass Filter www.national.com 10 Physical Dimensions inches (millimeters) unless otherwise noted 8-Pin Small Outline Package Order Package Number LMC6572AIM or LMC6572BIM NS Package Number M08A 14-Pin Small Outline Package Order Package Number LMC6574AIM or LMC6574BIM NS Package Number M14A 11 www.national.com Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 8-Lead Mini-Small Outline Molded Package, JEDEC Order Number LMC6572BIMM or LMC6572BIMMX NS Package Number MUA08A 8-Pin Molded Dual-In-Line Package Order Number LMC6572AIN or LMC6572BIN NS Package Number N08E www.national.com 12 LMC6572 Dual/LMC6574 Quad Low Voltage (2.7V and 3V) Operational Amplifier Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Pin Molded Dual-In-Line Package Order Number LMC6574AIN or LMC6574BIN NS Package Number N14A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com www.national.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: sea.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.