LMF60CIN-100

LMF60 High Performance 6th-Order Switched Capacitor Butterworth Lowpass Filter May 1996 LMF60 High Performance 6th-Order Switched Capacitor Butterworth Lowpass Filter General Description The LMF60 is a high performance precision 6th-order Butterworth lowpass active filter It is fabricated using National’s LMCMOS process an improved silicon-gate CMOS process specifically designed for analog products Switchedcapacitor techniques eliminate external component requirements and allow a clock-tunable cutoff frequency The ratio of the clock frequency to the low-pass cutoff frequency is internally set to 50 1 (LMF60-50) or 100 1 (LMF60-100) A Schmitt trigger clock input stage allows two clocking options either self-clocking (via an external resistor and capacitor) for stand-alone applications or for tighter cutoff frequency control a TTL or CMOS logic compatible clock can be directly applied The maximally flat passband frequency response together with a DC gain of 1V V allows cascading LMF60 sections for higher-order filtering In addition to the filter two independent CMOS op amps are included on the die and are useful for any general signal conditioning applications The LMF60 is pin- and functionally-compatible with the MF6 but provides improved performance Features Y Y Y Y Y Y Y Y Y Y Y Cutoff frequency range of 0 1 Hz to 30 kHz Cutoff frequency accuracy of g 1 0% maximum Low offset voltage g 100 mV maximum g 5V supply Low clock feedthrough of 10 mVp– p typical Dynamic range of 88 dB typical Two uncommitted op amps available No external components required 14-pin DIP or 14-pin wide-body S O package Single Dual Supply Operation a 4V to a 14V ( g 2V to g 7V) Cutoff frequency set by external or internal clock Pin-compatible with the MF6 Applications Y Y Y Y Y Y Communication systems Audio filtering Anti-alias filtering Data acquisition noise filtering Instrumentation High-order tracking filters Block and Connection Diagrams All Packages TL H 9294 – 2 Top View Order Number LMF60CMJ-50 (5962-9096 701MCA or LMF60CMJ50 883) LMF60CMJ-100 or (5962-9096 702MCA or LMF60CMJ100 883) See NS Package Number J14A TL H 9294 – 1 Order Number LMF60CIWM-50 or LMF60CIWM-100 See NS Package Number M14B Order Number LMF60CIN-50 or LMF60CIN-100 See NS Package Number N14A TRI-STATE is a registered trademark of National Semiconductor Corporation C1996 National Semiconductor Corporation TL H 9294 RRD-B30M56 Printed in U S A Absolute Maximum Ratings (Note 1) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage (V a Soldering Information b V ) (Note 2) a b 15V V a 0 2V b V b 0 2V 5 mA 20 mA 500 mW b 65 C to a 150 C 2000V 1700V  N Package 10 sec  J Package 10 sec  SO Package Vapor Phase (60 sec ) Infrared (15 sec ) (Note 6) Voltage at Any Pin Input Current at Any Pin (Note 3) Package Input Current (Note 3) Power Dissipation (Note 4) Storage Temperature ESD Susceptibility (Note 5) CLK IN Pin 260 300 215 220 C C C C Operating Ratings (Note 1) Temperature Range TMin s TA s TMax LMF60CIN-50 LMF60CIN-100 LMF60CIJ-50 LMF60CIJ-100 LMF60CIWM-50 b 40 C s TA s a 85 C LMF60CIWM-100 LMF60CMJ-50 LMF60CMJ-100 LMF60CMJ50 883 b 55 C s TA s a 125 C LMF60CMJ100 883 a 4V to 14V Supply Voltage (V b Vb) Filter Electrical Characteristics The following specifications apply for fCLK e 500 kHz (Note 7) unless otherwise specified Boldface limits apply for TA e TJ e TMIN to TMAX all other limits TA e TJ e 25 C Symbol V a Parameter Conditions Typical (Note 8) Limits (Note 9) Units (Limits) e a 5V V b e b 5V fCLK IS Clock Frequency Range (Note 16) Total Supply Current Clock Feedthrough VIN e 0V Filter Opamp 5 15 70 10 5 0 10 b 0 26 Hz (Min) MHz (Max) 12 0 mA (Max) mVp-p mVp-p 0 10 b 0 30 Ho fCLK fC DC Gain Clock to Cutoff Frequency Ratio (Note 10) LMF60-50 LMF60-100 RSource s 2 kX dB (Max) dB (Min) (Max) (Max) 49 00 g 0 8% 98 10 g 0 8% 49 00 g 1 0% 98 10 g 1 0% Temperature Coefficient of fCLK fC AMIN VOS VOUT ISC Stopband Attenuation DC Offset Voltage Output Voltage Swing (Note 2) Output Short Circuit Current (Note 11) Dynamic Range (Note 12) Additional Magnitude Response Test Points (Note 13) LMF60-50 fIN e 12 kHz fIN e 9 kHz LMF60-100 fIN e 6 kHz fIN e 4 5 kHz Source Sink LMF60-50 LMF60-100 At 2 c fC 4 36 g 100 g 150 ppm C dB (Min) mV (Max) mV (Max) a3 7 b4 0 a3 9 b4 2 V (Min) V (Max) mA mA dB 90 22 88 b 9 45 g 0 46 b 0 87 g 0 16 b 9 30 g 0 46 b 0 87 g 0 16 b 9 45 g 0 50 b 0 87 g 0 20 b 9 30 g 0 50 b 0 87 g 0 20 dB dB dB dB http www national com 2 Filter Electrical Characteristics (Continued) The following specifications apply for fCLK e 250 kHz (Note 7) unless otherwise specified Boldface limits apply for TA e TJ e TMIN to TMAX all other limits TA e TJ e 25 C Symbol Parameter Conditions Typical (Note 8) Limits (Note 9) Units (Limits) V a e a 2 5V Vb e b2 5V fCLK IS Clock Frequency Range (Note 16) Total Supply Current Clock Feedthrough (Peak to Peak) Ho DC Gain (with RSource s 2 kX) VIN e 0V Filter Opamp 6 3 0 10 b 0 26 b 0 08 5 750 50 65 Hz (Min) kHz (Max) mA (Max) mV mV 0 10 b 0 30 fCLK e 250 kHz fCLK e 500 kHz dB (Max) dB (Min) dB fCLK fC Clock to Cutoff Frequency Ratio (Note 10) LMF60-50 fCLK e 250 kHz fCLK e 500 kHz 49 00 g 0 6% 49 00 g 0 8% 49 00 g 1 0% (Max) LMF60-100 fCLK e 250 kHz fCLK e 500 kHz 98 10 g 0 6% 4 At 2 c fC 98 10 g 0 8% 98 10 g 1 0% (Max) Temperature Coefficient of fCLK fC AMIN VOS VOUT ISC Stopband Attenuation DC Offset Voltage Output Voltage Swing (Note 2) Output Short Circuit Current (Note 11) Dynamic Range (Note 12) Additional Magnitude Response Test Points (Note 13) LMF60-50 fIN e 6 kHz fIN e 4 5 kHz LMF60-100 fIN e 3 kHz fIN e 2 25 kHz LMF60-50 LMF60-100 RL e 5 kX Source Sink ppm C 36 g 60 g 90 dB (Min) mV (Max) mV (Max) a1 2 b1 8 a1 4 b2 0 V (Min) V (Max) mA mA dB 42 09 81 b 9 45 g 0 46 b 0 87 g 0 16 b 9 30 g 0 46 b 0 87 g 0 16 b 9 45 g 0 50 b 0 87 g 0 20 b 9 30 g 0 50 b 0 87 g 0 20 dB dB dB dB 3 http www national com Op Amp Electrical Characteristics Boldface limits apply for TA e TJ e TMIN to TMAX all other limits TA e TJ e 25 C Symbol V a Parameter Conditions Typical (Note 8) Limits (Note 9) Units (Limits) e a 5V V b e b 5V VOS IB CMRR VO ISC SR AVOL GBW V a Input Offset Voltage Input Bias Current Common Mode Rejection Ratio (Op Amp 2 Only) Output Voltage Swing Output Short Circuit Current (Note 13) Slew Rate DC Open Loop Gain Gain Bandwidth Product Test Input Range e b 2 2V to a 1 8V RL e 5 kX Source Sink 90 21 4 80 20 38 b4 2 g 20 mV (Max) pA 10 55 36 b4 0 dB V (Min) V (Max) mA mA V ms dB (Min) MHz e a 2 5V V b e b 2 5V VOS IB CMRR VO ISC SR AVOL GBW Input Offset Voltage Input Bias Current Common Mode Rejection Ratio (Op Amp 2 Only) Output Voltage Swing Output Short Circuit Current (Note 13) Slew Rate DC Open Loop Gain Gain Bandwidth Product Test Input Range e b 0 9V to a 0 5V RL e 5 kX Source Sink 42 09 3 74 20 13 b1 8 g 20 mV (Max) pA 10 55 11 b1 6 dB V (Min) V (Max) mA mA V ms dB (Min) MHz Logic Input-Output Characteristics The following specifications apply for Vb e 0V (Note 15) L Sh e 0V unless otherwise specified Boldface limits apply for TA e TJ e TMIN to TMAX all other limits TA e TJ e 25 C Symbol Parameter Conditions Typical (Note 8) Limits (Note 9) Units (Limits) TTL CLOCK INPUT CLK R PIN (NOTE 14) VIH VIL VIH VIL TTL Input Voltage CLK R Input Voltage Logical ‘‘1’’ Logical ‘‘0’’ Logical ‘‘1’’ Logical ‘‘0’’ V V a e a 5V V b e b 5V e a 2 5V V b e b 2 5V 20 08 20 06 20 04 V (Min) V (Max) V (Min) V (Max) mA a Maximum Leakage Current at CLK R http www national com 4 Logic Input-Output Characteristics (Continued) The following specifications apply for V b e 0V (Note 15) L Sh e 0V unless otherwise specified Boldface limits apply for TA e TJ e TMIN to TMAX all other limits TA e TJ e 25 C Symbol SCHMITT TRIGGER VT a Positive Going Input Threshold Voltage V V VTb Negative Going Input Threshold Voltage V V VT a bVTb Hysteresis V V VOH VOL ISOURCE Logical ‘‘1’’ Voltage IO e b10 mA Pin 11 Logical ‘‘0’’ Voltage IO e b10 mA Pin 11 Output Source Current Pin 11 Output Sink Current Pin 11 a Parameter Conditions Typical (Note 8) Limits (Note 9) Units (Limits) e 10V e 5V e 10V e 5V e 10V e 5V 61 88 30 43 14 38 07 19 23 74 11 36 91 46 09 04 49 16 49 16 60 89 29 44 13 39 06 20 21 76 09 38 90 45 10 05 37 12 37 12 V (Min) V (Max) V (Min) V (Max) V (Min) V (Max) V (Min) V (Max) V (Min) V (Max) V (Min) V (Max) V (Min) V (Min) V (Max) V (Max) mA (Min) mA (Min) mA (Min) mA (Min) a a a a a a V e a 10V a V e a 5V a V e a 10V a V e a 5V CLK R to V a V e a 10V a V e a 5V CLK R to V a V e a 10V a V e a 5V a b ISINK Note 1 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur Operating Ratings indicate conditions for which the device is functional Specified Electrical Characteristics do not apply when operating the device outside its specified conditions Note 2 All voltages are measured with respect to AGND unless otherwise specified Note 3 When the input voltage (VIN) at any pin exceeds the power supply rails (VIN k Vb or VIN l V a ) the absolute value of current at that pin should be limited to 5 mA or less The 20 mA package input current limits the number of pins that can exceed the power supply boundaries with 5 mA to four Note 4 The Maximum power dissipation must be derated at elevated temperatures and is dictated by TJ Max iJA and the ambient temperature TA The maximum allowable power dissipation is PD e (TJ Max b TA) iJA or the number given in the absolute ratings whichever is lower For this device TJ Max e 125 C and the typical junction-to-ambient thermal resistance of the LMF60CCN when board mounted is 67 C W For the LMF60CIJ this number decreases to 62 C W For the LMF60CIWM iJA e 78 C W Note 5 Human body model 100 pF discharged through a 1 5 kX resistor Note 6 See AN450 ‘‘Surface Mounting Methods and Their Effect on Product Reliability’’ or the section titled ‘‘Surface Mount’’ found in any current Linear Databook for other methods of soldering surface mount devices Note 7 The specifications given are for a clock frequency (fCLK) of 500 kHz at a 5V and 250 kHz at g 2 5V Above this frequency the cutoff frequency begins to deviate from the specified error band over the temperature range but the filter still maintains its amplitude characteristics See application hints Note 8 Typicals are at 25 C and represent the most likely parametric norm Note 9 Guaranteed to National’s Average Outgoing Quality Level (AOQL) Note 10 The cutoff frequency of the filter is defined as the frequency where the magnitude response is 3 01 dB less than the DC gain of the filter Note 11 The short circuit source current is measured by forcing the output to its maximum positive swing and then shorting that output to the negative supply The short circuit sink current is measured by forcing the output being tested to its maximum negative voltage and then shorting that output to the positive supply These are worst case conditions Note 12 For g 5V supplies the dynamic range is referenced to 2 62 Vrms (3 7V peak) where the wideband noise over a 20 kHz bandwidth is typically 100 mV For g 2 5V supplies the dynamic range is referenced to 0 849 Vrms (1 2V peak) where the wideband noise over a 20 kHz bandwidth is typically 75 mVrms Note 13 The filter’s magnitude response is tested at the cutoff frequency fC at fIN e 2 fC and at these two additional frequencies Note 14 The LMF60 is operated with symmetrical supplies and L Sh is tied to GND Note 15 For simplicity all the logic levels (except for the TTL input logic levels) have been referenced to Vb e 0V The logic levels will scale accordingly for g 5V and g 2 5V supplies Note 16 The nominal ratio of the clock frequency to the low-pass cutoff frequency is internally set to 50-to-1 (LMF60-50) or 100-to-1 (LMF60-100) 5 http www national com Typical Performance Characteristics fCLK fC Deviation vs Power Supply Voltage fCLK fC Deviation vs Temperature fCLK fC Deviation vs Clock Frequency fCLK fC Deviation vs Power Supply Voltage fCLK fC Deviation vs Temperature fCLK fC Deviation vs Clock Frequency DC Gain Deviation vs Power Supply Voltage DC Gain Deviation vs Temperature DC Gain Deviation vs Clock Frequency TL H 9294 – 3 http www national com 6 Typical Performance Characteristics DC Gain Deviation vs Power Supply Voltage (Continued) DC Gain Deviation vs Temperature DC Gain Deviation vs Clock Frequency DC Offset Voltage Deviation vs Power Supply Voltage Power Supply Current vs Power Supply Voltage Power Supply Current vs Temperature Positive Voltage Swing vs Power Supply Voltage Negative Voltage Swing vs Power Supply Voltage Positive Voltage Swing vs Temperature TL H 9294 – 4 7 http www national com Typical Performance Characteristics Negative Voltage Swing vs Temperature (Continued) CLK R Trigger Threshold vs Power Supply Voltage Schmitt Trigger Threshold vs Power Supply Voltage Crosstalk from Filter to Op Amps Crosstalk from Either Op Amp to Filter Equivalent Input Noise Voltage of Op Amps TL H 9294 – 5 http www national com 8 Crosstalk Test Circuits From Filter to Op-Amps TL H 9294 – 6 From Either Op-Amp to Filter Output TL H 9294 – 7 Pin Description (Pin Numbers) Pin FILTER OUT (3) Description The output of the lowpass filter will typically swing to within 1V of each supply rail The input to the lowpass filter To minimize gain errors the source impedance that drives this input should be less than 2k (See Section 1 4) For single supply operation the input signal must be biased to mid-supply or AC coupled This pin is used to adjust the DC offset of the filter output if not used it must be tied to the AGND potential (See Section 1 3) The analog ground pin This pin sets the DC bias level for the filter section and the noninverting input of Op-Amp 1 and must be tied to the system ground for split supply operation or to mid-supply for single supply operation (See Section 1 2) When tied to mid-supply this pin should be well bypassed VO1 is the output and INV1 is the inverting input of Op-Amp 1 The non-inverting input of this Op-Amp is internally connected to the AGND pin VO2 is the output INV2 is the inverting input and NINV2 is the non-inverting input of Op-Amp 2 The positive and negative supply pins The total power supply range is 4V to 14V Decoupling these pins with 0 1 mF capacitors is highly recommended 9 Pin CLK IN (9) Description A CMOS Schmitt-trigger input to be used with an external CMOS logic level clock Also used for self-clocking Schmitt-trigger oscillator (See Section 1 1) A TTL logic level clock input when in split supply operation ( g 2V to g 7V) and L Sh tied to system ground This pin becomes a low impedance output when L Sh is tied to Vb Also used in conjunction with the CLK IN pin for self clocking Schmitt-trigger oscillator (See Section 1 1) Level shift pin selects the logic threshold levels for the desired clock When tied to Vb it enables an internal TRISTATE buffer stage between the Schmitt trigger and the internal clock level shift stage thus enabling the CLK IN Schmitt-trigger input and making the CLK R pin a low impedance output When the voltage level at this input exb ceeds 25% (V a b Vb) a V the internal TRI-STATE buffer is disabled allowing the CLK R pin to become the clock input for the internal clock level shift stage The CLK R threshold level is now 2V above the voltage applied to the L Sh pin Driving the CLK R pin with TTL logic levels can be accomplished through the use of split supplies and by tying the L Sh pin to system ground FILTER IN (8) CLK R (11) VOSADJ (7) AGND (5) L Sh (12) VO1(4) INV1 (13) VO2(2) INV2 (14) NINV2 (1) V a (6) Vb (10) http www national com 1 0 LMF60 Application Hints The LMF60 is comprised of a non-inverting unity gain lowpass sixth-order Butterworth switched capacitor filter section and two undedicated CMOS Op-Amps The switchedcapacitor topology makes the cutoff frequency (where the gain drops 3 01 dB below the DC gain) a direct ratio (100 1 or 50 1) of the clock frequency supplied to the lowpass filter Internal integrator time constants set the filter’s cutoff frequency The resistive element of these integrators is actually a capacitor which is ‘‘switched’’ at the clock frequency (for a detailed discussion see Input Impedance section) Varying the clock frequency changes the value of this resistive element and thus the time constant of the integrators The clock to cutoff frequency ratio (fCLK fC) is set by the ratio of the input and feedback capacitors in the integrators The higher the clock to cutoff frequency ratio (or the sampling rate) the closer the approximation is to the theoretical Butterworth response The LMF60 is available in fCLK fC ratios of 50 1 (LMF60-50) or 100 1 (LMF60-100) 1 1 CLOCK INPUTS The LMF60 has a Schmitt-trigger inverting buffer which can be used to construct a simple R C oscillator The oscillator frequency is dependent on the buffer’s threshold levels as well as on the resistor capacitor tolerance (See Figure 1 ) Schmitt-trigger threshold voltage levels can vary significantly causing the R C oscillator’s frequency to vary greatly from part to part Where accuracy in fC is required an external clock can be used to drive the CLK R input of the LMF60 This input is TTL logic level compatible and also presents a very light load to the external clock source ( E 2 mA) with split supplies and L Sh tied to system ground The logic level is programmed by the voltage applied to level shift (L Sh) pin (See the Pin Description for L Sh pin) 1 2 POWER SUPPLY BIASING The LMF60 can be biased from a single supply or dual split supplies The split supply mode shown in Figures 2 and 3 is the most flexible and easiest to implement As discussed earlier split supplies g 2V to g 7V will enable the use of TTL or CMOS clock logic levels Figure 4 shows two schemes for single supply biasing In this mode only CMOS clock logic levels can be used fCLK e RC In Typically for fCLK e VCC e V a b  1 VCC b VTb b VT a VCC Vb e JV ( VT a Tb 10V 1 1 37 RC TL H 9294 – 8 FIGURE 1 Schmitt Trigger R C Oscillator http www national com 10 1 0 LMF60 Application Hints (Continued) If the LMF60-50 or the LMF60-100 were set up for a cutoff frequency of 10 kHz the input impedance would be RIN e 1 c 1010 e 1 MX 10 kHz cies these leakage currents can cause millivolts of error for example fCLK e 100 Hz ILEAKAGE e 1 pA C e 1 pF 1 pA e 10 mV Ve 1 pF (100 Hz) The propagation delay in the logic and the settling time required to acquire a new voltage level on the capacitors increases as the LMF60 power supply voltage decreases This causes a shift in the fCLK fC ratio which will become noticeable when the clock frequency exceeds 500 kHz The amplitude characteristic will stay within tolerance until fCLK exceeds 750 kHz and will peak at about 0 4 dB at the cutoff frequency with a 2 MHz clock The response of the LMF60 is still a reasonable approximation of the ideal Butterworth lowpass characteristic as can be seen in Figure 7 In this example with a source impedance of 10k the overall gain if the LMF60 had an ideal gain of 1 (0 dB) would be 1 MX e 0 99009 ( b 86 4 mdB) AV e 10 kX a 1 MX Since the maximum overall gain error for the LMF60 is a 0 1 dB b0 3 dB with a RS s 2 kX the actual gain error for this case would be a 0 21 dB to b0 39 dB 1 5 CUTOFF FREQUENCY RANGE The filter’s cutoff frequency (fC) has a lower limit caused by leakage currents through the internal switches discharging the stored charge on the capacitors At lower clock frequen- TL H 9294 – 17 TL H 9294 – 18 FIGURE 7a LMF60-100 g 5V Supplies Amplitude Response FIGURE 7b LMF60-50 g 5V Supplies Amplitude Response TL H 9294 – 19 TL H 9294 – 20 FIGURE 7c LMF60-100 g 2 5V Supplies Amplitude Response FIGURE 7d LMF60-50 g 2 5V Supplies Amplitude Response 11 http www national com 1 0 LMF60 Application Hints (Continued) TL H 9294–9 TL H 9294 – 10 FIGURE 2 Dual Supply Operation LMF60 Driven with CMOS Logic Level Clock (VIH t V a b 0 3 VS and VIL s Vb a 0 3 VS where VS e V a b Vb) FIGURE 3 Dual Supply Operation LMF60 Driven with TTL Logic Level Clock TL H 9294 – 11 a) Resistor Biasing of AGND TL H 9294 – 12 b) Using Op-Amp 2 to Buffer AGND FIGURE 4 Single Supply Operation http www national com 12 1 0 LMF60 Application Hints (Continued) TL H 9294 – 13 TL H 9294 – 14 FIGURE 5 VOS Adjust Schemes 1 3 OFFSET ADJUST The VOSADJ pin is used in adjusting the output offset level of the filter section If this pin is not used it must be tied to the analog ground (AGND) level either mid-supply for single ended supply operation or ground for split supply operation This pin sets the zero reference for the output of the filter The implementation of this pin can be seen in Figure 5 In 5(a) DC offset is adjusted using a potentiometer in 5(b) the Op-Amp integrator circuit keeps the average DC output level at AGND The circuit in 5(b) is therefore appropriate only for AC-coupled signals and signals biased at AGND 1 4 INPUT IMPEDANCE The LMF60 lowpass filter input (FILTER IN pin) is not a high impedance buffer input This input is a switched capacitor resistor equivalent and its effective impedance is inversely proportional to the clock frequency The equivalent circuit of the input to the filter can be seen in Figure 6 The input capacitor charges to the input voltage (VIN) during one half of the clock period during the second half the charge is transferred to the feedback capacitor The total transfer of charge in one clock cycle is therefore Q e CINVIN and since current is defined as the flow of charge per unit time the average input current becomes IIN e Q T (where T equals one clock period) or CINVIN e CINVINfCLK IIN e T The equivalent input resistor (RIN) then can be defined as 1 RIN e VIN IIN e CINfCLK The input capacitor is 2 pF for the LMF60-50 and 1 pF for the LMF60-100 so for the LMF60-100 RIN e and 5 c 1011 5 c 1011 1 c 1010 e e fCLK fC c 50 fC for the LMF60-50 As shown in the above equations for a given cutoff frequency (fC) the input impedance remains the same for the LMF60-50 and the LMF60-100 The higher the clock to cutoff frequency ratio the greater equivalent input resistance for a given clock frequency As the cutoff frequency increases the equivalent input impedance decreases This input resistance will form a voltage divider with the source impedance (RSOURCE) Since RIN is inversely proportional to the cutoff frequency operation at higher cutoff frequencies will be more likely to load the input signal which would appear as an overall decrease in gain at the output of the filter Since the filter’s ideal gain is unity its overall gain is given by RIN e AV e RIN RIN a RSOURCE 1 c 1012 1 c 1012 1 c 1010 e e fCLK fC c 100 fC TL H 9294 – 15 a) Equivalent Circuit for LMF60 Filter Input TL H 9294 – 16 b) Actual Circuit for LMF60 Filter Input FIGURE 6 LMF60 Filter Input 13 http www national com 2 0 Designing with the LMF60 Given any lowpass filter specification two equations will come in handy in trying to determine whether the LMF60 will do the job The first equation determines the order of the lowpass filter required log (100 1AMin b 1) b log(100 1AMax b 1) (1) 2 log (fs fb) where n is the order of the filter AMin is the minimum stopband attenuation (in dB) desired at frequency fs and AMax is the passband ripple or attenuation (in dB) at frequency fb If the result of this equation is greater than 6 then more than a single LMF60 is required The attenuation at any frequency can be found by the following equation Attn(f) e 10 log 1 a (100 1AMax b 1) (f fb)2n dB (2) ne where n e 6 (the order of the filter) 2 1 A LOWPASS DESIGN EXAMPLE Suppose the amplitude response specification in Figure 8 is given Can the LMF60 be used The order of the Butterworth approximation will have to be determined using eq 1 AMin e 30 dB AMax e 1 0 dB fs e 2 kHz and fb e 1 kHz log(103 b 1) b log(100 1 b 1) e 5 96 2 log(2) Since n can only take on integer values n e 6 Therefore the LMF60 can be used In general if n is 6 or less a single LMF60 stage can be utilized Likewise the attenuation at fs can be found using equation 2 with the above values and n e 6 giving Atten (2 kHz) e 10 log 1 a (100 1 b 1) (2 1)12 e 30 26 dB This result also meets the design specification given in Figure 8 again verifying that a single LMF60 section will be adequate ne To implement this example for the LMF60-50 the clock frequency will have to be set to fCLK e 50(1 119 kHz) e 55 95 kHz or for the LMF60-100 fCLK e 100(1 119 kHz) e 111 9 kHz 2 2 CASCADING LMF60s In the case where a steeper stopband attenuation rate is required two LMF60’s can be cascaded (Figure 9) yielding a 12th order slope of 72 dB per octave Because the LMF60 is a Butterworth filter and therefore has no ripple in its passband when LMF60’s are cascaded the resulting filter also has no ripple in its passband Likewise the DC and passband gains will remain at 1V V The resulting response is shown in Figure 10 In determining whether the cascaded LMF60’s will yield a filter that will meet a particular amplitude response specification as above equations 3 and 4 can be used shown below ne log (100 05 Amin b 1) b log(100 05 AMax b 1) 2 log (fs fb) (3) (4) Attn(f) e 10 log 1 a (100 05 AMax b 1) (f fb)2n dB where n e 6 (the order of each filter) Equation 3 will determine whether the order of the filter is adequate (n s 6) while equation 4 can determine if the required stopband attenuation is met and what actual cutoff frequency (fC) is required to obtain the particular frequency response desired The design procedure would be identical to the one shown in Section 2 1 2 3 IMPLEMENTING A ‘‘NOTCH’’ FILTER WITH THE LMF60 A ‘‘notch’’ filter with 60 dB of attenuation can be obtained by using one of the Op-Amps available in the LMF60 and three external resistors The circuit and amplitude response are shown in Figure 11 The frequency where the ‘‘notch’’ will occur is equal to the frequency at which the output signal of the LMF60 will have the same magnitude but be 180 degrees out of phase with its input signal For a sixth order Butterworth filter 180 phase shift occurs where f e fn e 0 742 fC The attenuation at this frequency is 0 12 dB which must be compensated for by making R1 e 1 014 c R2 Since R1 does not equal R2 there will be a gain inequality above and below the notch frequency At frequencies below the notch frequency (f m fn) the signal through the filter has a gain of one and is non-inverting Summing this with the input signal through the Op-Amp yields an overall gain of two or a 6 dB For f n fn the signal at the output of the filter is greatly attenuated thus only the input signal will appear at the output of the Op-Amp With R3 e R1 e 1 014 R2 the overall gain is 0 986 or b0 12 dB at frequencies above the notch TL H 9294–21 FIGURE 8 Design Example Magnitude Response Specification Where the Response of the Filter Design Must Fall Within the Shaded Area of the Specification Since the LMF60’s cutoff freqency fC which corresponds to a gain attenuation of b3 01 dB was not specified in this example it needs to be calculated Solving equation 2 where f e fC as follows 100 1(3 01 dB) b 1) 1 (2n) fc e fb (100 1AMax b 1) 100 301 b 1 1 12 e1 100 1 b 1 e 1 119 kHz where fC e fCLK 50 or fCLK 100  J ( http www national com 14 2 0 Designing with the LMF60 (Continued) TL H 9294 – 22 FIGURE 9 Cascading Two LMF60s TL H 9294 – 24 TL H 9294 – 23 FIGURE 10a One LMF60-50 vs Two LMF60-50s Cascaded FIGURE 10b Phase Response of Two Cascaded LMF60-50s 15 http www national com 2 0 Designing with the LMF60 (Continued) TL H 9294 – 25 FIGURE 11a ‘‘Notch’’ Filter TL H 9294 – 26 FIGURE 11b LMF60-50 ‘‘Notch’’ Filter Amplitude Response http www national com 16 2 0 Designing with the LMF60 (Continued) 2 4 CHANGING CLOCK FREQUENCY INSTANTANEOUSLY The LMF60 will respond well to a sudden change in clock frequency Distortion in the output signal occurs at the transition of the clock frequency and lasts approximately three cutoff frequency (fC) cycles As shown in Figure 12 if the control signal is low the LMF60-50 has a 100 kHz clock making fC e 2 kHz when this signal goes high the clock frequency changes to 50 kHz yielding 1 kHz fC The transient response of the LMF60 seen in Figure 13 is also dependent on the fc and thus the fCLK applied to the filter The LMF60 responds as a classical sixth order Butterworth lowpass filter component will be ‘‘reflected’’ about fCLK 2 into the frequency range below fCLK 2 as in Figure 14b If this component is within the passband of the filter and of large enough amplitude it can cause problems Therefore if frequency components in the input signal exceed fCLK 2 they must be attenuated before being applied to the LMF60 input The necessary amount of attenuation will vary depending on system requirements In critical applications the signal components above fCLK 2 will have to be attenuated at least to the filter’s residual noise level An example circuit is shown in Figure 15 using one of the uncommitted Op-Amps available in the LMF60 TL H 9294 – 27 TL H 9294 – 28 fIN e 1 5 kHz (Scope Time Base e 2 ms Div) FIGURE 12 LMF60-50 Abrupt Clock Frequency Change 2 5 ALIASING CONSIDERATIONS Aliasing effects have to be taken into consideration when input signal frequencies exceed half the sampling rate For the LMF60 this equals half the clock frequency (fCLK) When the input signal contains a component at a frequency higher than half the clock frequency as in Figure 14a that FIGURE 13 LMF60-50 Step Input Response Vertical e 2V Div Horizontal e 1 ms Div fCLK e 100 kHz TL H 9294 – 29 TL H 9294 – 30 (a) Input Signal Spectrum (b) Output Signal Spectrum Note that the input signal at fs 2 a f causes an output signal to appear at fs 2 b f FIGURE 14 The phenomenon of aliasing in sampled-data systems An input signal whose frequency is greater than one-half the sampling frequency will cause an output to appear at a frequency lower than one-half the sampling frequency In the LMF60 fs e fCLK 17 http www national com 2 0 Designing with the LMF60 (Continued) TL H 9294 – 31 f0 e 1 2 q 0R 1 R 2C 1C 2 H0 e R4 R3 (H0 e 1 when R3 and R4 are omitted and VO2 is directly tied to INV2) Design Procedure pick C1 R2 e 1 2QC100 0 113 C 1f 0 for a 2nd Order Butterworth Q e 0 707 R2 e make R1 e R2 and C2 e 1 (2qf0R1)2C1 2 Note The parallel combination of R4 (if used) R1 and R2 should be t 10 kX in order not to load Op-Amp FIGURE 15 Second Order Butterworth Anti-Aliasing Filter Using Uncommitted Op-Amp 2 http www national com 18 Physical Dimensions inches (millimeters) unless otherwise noted Cavity Dual-In-Line Package (J) Order Number LMF60CMJ-50 LMF60CMJ50 883 LMF60CMJ-100 or LMF60CMJ100 883 NS Package Number J14A Small Outline Wide Body (M) Order Number LMF60CIWM-50 or LMF60CIWM-100 NS Package Number M14B 19 http www national com LMF60 High Performance 6th-Order Switched Capacitor Butterworth Lowpass Filter Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Lit 108461 Molded Dual-In-Line Package (N) Order Number LMF60CIN-50 or LMF60CIN-100 NS Package Number N14A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user National Semiconductor Corporation 1111 West Bardin Road Arlington TX 76017 Tel 1(800) 272-9959 Fax 1(800) 737-7018 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness http www national com National Semiconductor Europe Fax a49 (0) 180-530 85 86 Email europe support nsc com Deutsch Tel a49 (0) 180-530 85 85 English Tel a49 (0) 180-532 78 32 Fran ais Tel a49 (0) 180-532 93 58 Italiano Tel a49 (0) 180-534 16 80 National Semiconductor Hong Kong Ltd 13th Floor Straight Block Ocean Centre 5 Canton Rd Tsimshatsui Kowloon Hong Kong Tel (852) 2737-1600 Fax (852) 2736-9960 National Semiconductor Japan Ltd Tel 81-043-299-2308 Fax 81-043-299-2408 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications