LMH0070SQE

LMH0340, LMH0040, LMH0070, LMH0050 3Gbps, HD, SD, DVB-ASI SDI Serializer and Cable Driver with LVDS Interface October 20, 2008 LMH0340, LMH0040, LMH0070, LMH0050 3 Gbps, HD, SD, DVB-ASI SDI Serializer and Cable Driver with LVDS Interface General Description The LMH0340/0040/0070/0050 SDI Serializers are part of National’s family of FPGA-Attach SER/DES products supporting 5-bit LVDS interfaces with FPGAs. An FPGA Host will format data with supplied IP such that the output of the LMH0340 is compliant with the requirements of DVB-ASI, SMPTE 259M-C, SMPTE 292M and SMPTE 424M standards. See Table 1 for details on which Standards are supported per device. The interface between the SER (Serializer) and the FPGA consists of a 5 bit wide LVDS data bus, an LVDS clock and an SMBus interface. The LMH0340/0040/0070 SER devices include an integrated cable driver which is fully compliant with all of the SMPTE specifications listed above. The LMH0050 has a CML output driver that can drive a differential transmission line or interface to a cable driver. The FPGA-Attach SER/DES family is supported by a suite of IP which allows the design engineer to quickly develop video applications using the SER/DES products. The SER is packaged in a physically small 48 pin LLP package. Key Specifications ■ Output compliant with SMPTE 424M, SMPTE 292M, SMPTE 259M-C and DVB-ASI (See Table 1) ■ Typical power dissipation: 440 mW ■ 30 ps typical output jitter (HD, 3G) Features ■ ■ ■ ■ ■ ■ LVDS Interface to Host FPGA No external VCO or clock ref required Integrated Variable Output Cable Driver 3.3V SMBus configuration interface Integrated TXCLK PLL cleans clock noise Small 48pin LLP package Applications ■ SDI interfaces for: — — — — Video Cameras DVRs Video Switchers Video Editing Systems General Block Diagram 30017001 TRI-STATE® is a registered trademark of National Semiconductor Corporation. © 2008 National Semiconductor Corporation 300170 www.national.com LMH0340, LMH0040, LMH0070, LMH0050 Pin Descriptions Pin Name LVDS Input Interface TX[4:0]+ TX[4:0]TXCLK+ TXCLKTXOUT+ TXOUTSMBus Interface SDA SCK SMB_CS I/O, LVCMOS Input, LVCMOS Input, LVCMOS SMBus Data I/O Pin SMBus Clock Input Pin SMBus Chip Select Input Pin Device is selected when High. Reset Input Pin H = normal mode L = device in RESET PLL LOCK Status Output H = unlock condition L = Device is Locked DVB_ASI Select Input H = DVB_ASI Mode enabled L = Normal Mode enabled General Purpose Input / Output Software configurable I/O pins. Configuration Input – Must tie High Pull High via 5 kΩ resistor to VDD3V3 Serial Output Amplitude Control Resistor connected from this pin to ground to set the signal amplitude. Nominally 8.06kΩ for 800mV output (SMPTE). Loop Filter Connection Loop Filter Reference Do Not Connect – Leave Open Power Power Power Ground 3.3V Power Supply connection 3.3V PLL Power Supply connection 2.5V Power Supply connection Ground connection – The DAP (large center pad) is the primary GND connection for the device and must be connected to Ground along with the GND pins. TABLE 1. Feature Table Device LMH0340 LMH0040 LMH0070 LMH0050 X SMPTE 424M Support (3G) X SMPTE 292M Support (HD) X X SMPTE 259M Support (SD) X X X X DVB-ASI Support X X X X SMPTE compliant Cable Driver X X X Input, LVDS Input, LVDS LVDS Data Input Pins Five channel wide DDR interface. Internal 100Ω termination. LVDS Clock Input Pins DDR Interface. Internal 100Ω termination. Serial Digital Interface Output Pin Non-Inverting Output Serial Digital Interface Output Pin Inverting Output Type Description Serial Output Interface Output, CML Output, CML Control and Configuration Pins RESET Input, LVCMOS LOCK Output, LVCMOS DVB_ASI Input, LVCMOS GPIO[2:0] RSVD_H Analog Inputs RSET I/O, LVCMOS Input, LVCMOS Input, analog LF_CP LF_REF DNC Input, analog Input, analog Power Supply and Ground VDD3V3 VDDPLL VDD2V5 GND www.national.com 2 LMH0340, LMH0040, LMH0070, LMH0050 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VDD3V3) Supply Voltage (VDD2V5) LVCMOS input voltage LVCMOS output voltage −0.3V to +4.0V −0.3V to +3.0V −0.3V to (VDD3V3+0.3V) −0.3V to (VDD3V3+0.3V) SMBus I/O voltage LVDS Input Voltage Junction Temperature Storage Temperature Thermal Resistance—  Junction to Ambient—θJA ESD Rating—Human Body Model,   1.5 KΩ, 100 pF -0.3V to +3.6V -0.3V to +3.6V +150°C −65° to 150°C 25°C/W ≥±8kV Recommended Operating Conditions Parameter Supply Voltage (VDD3V3-GND) Supply Voltage (VDD2V5-GND) Supply noise amplitude (10 Hz to 50 MHz) Ambient Temperature Case Temperature TXCLK input frequency – LMH0340 TXCLK input frequency – LMH0040 TXCLK input frequency – LMH0070 TXCLK input frequency – LMH0050 LVDS PCB board trace length (mismatch