LMH0356

LMH0356 3 Gbps HD/SD SDI Reclocker with 4:1 Input Mux and FR4 EQs August 19, 2008 LMH0356 3 Gbps HD/SD SDI Reclocker with 4:1 Input Mux and FR4 EQs General Description The LMH0356 3 Gbps HD/SD SDI Reclocker with 4:1 Input Mux and FR4 EQs retimes serial digital video data conforming to the SMPTE 424M, SMPTE 292M, and SMPTE 259M (C) standards. The LMH0356 operates at serial data rates of 270 Mbps, 1.483 Gbps, 1.485 Gbps, 2.967 Gbps, and 2.97 Gbps. The LMH0356 supports DVB-ASI operation at 270 Mbps. The LMH0356 includes an integrated 4:1 input multiplexer for selecting one of four input data streams for retiming. In addition, the four inputs of the LMH0356 each have an FR4 equalizer capable of equalizing 0-30” of FR4 trace length. The LMH0356 automatically detects the incoming data rate and adjusts itself to retime the incoming data to suppress accumulated jitter. The LMH0356 recovers the serial data-rate clock and optionally provides it as an output. The LMH0356 has two differential serial data outputs; the second output may be selected as a low-jitter, data-rate clock output. Controls and indicators are: serial clock or second serial data output select, manual rate select input, SD/HD rate indicator output, lock detect output, auto/manual data bypass, output mute, and device enable. The serial data inputs, outputs, and serial clock outputs are differential LVPECL compatible. The CML serial data and serial clock outputs are suitable for driving 100Ω differentially terminated networks. The control logic inputs and outputs are LVCMOS compatible. The LMH0356 is powered from a single 3.3V supply. Power dissipation is typically 430 mW. The device is housed in a 48pin LLP (also known as QFN) package. Features ■ Supports SMPTE 424M, SMPTE 292M, and SMPTE 259M (C) serial digital video standards ■ Supports 270 Mbps, 1.483 Gbps, 1.485 Gbps, 2.967 ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Gbps, and 2.97 Gbps serial data rate operation Supports DVB-ASI at 270 Mbps Single 3.3V supply operation 430 mW typical power consumption Integrated 4:1 multiplexed input 0-30” FR4 equalizer on each multiplexed input Two differential, reclocked outputs Choice of second reclocked output or recovered clock output Single 27 MHz external crystal or reference clock input Manual rate select input SD/HD operating rate indicator output Lock Detect indicator output Output mute function for data and clock Auto/Manual reclocker bypass Power saver mode with device power down control (10 mW typical power consumption in disabled state) Differential LVPECL compatible serial data inputs and outputs LVCMOS control inputs and indicator outputs 48-Pin LLP package Industrial temperature range: -40°C to +85°C Footprint compatible with the LMH0056 and LMH0036 Applications ■ SDTV/HDTV and 3 Gbps serial digital video interfaces for: — — — — Digital video routers and switchers Digital video processing and editing equipment DVB-ASI equipment Video standards and format converters 2.97 Gbps Signal Before FR4 Equalization (0.6 UI Jitter) 2.97 Gbps Signal After FR4 Equalization (0.23 UI Jitter) 2.97 Gbps Signal After Reclocking (0.06 UI Jitter) 30016710 30016711 30016712 © 2008 National Semiconductor Corporation 300167 www.national.com LMH0356 Typical Application 30016701 Block Diagram 30016703 www.national.com 2 LMH0356 Pin Descriptions Pin 1 2 4 5 7 8 9 10 11 15 16 18 22 24 28 29 32 33 36 37 43 44 45 46 47 48 SDI0 SDI0 SDI1 SDI1 SDI2 SDI2 ENABLE SDI3 SDI3 BYPASS/AUTO BYPASS OUTPUT MUTE XTAL IN/EXT CLK XTAL OUT LOCK DETECT SCO/SDO2 SCO/SDO2 SDO SDO SD/HD SCO_EN LF1 LF2 RATE0 RATE1 SEL0 SEL1 Name Data Input 0 True. Data Input 0 Complement. Data Input 1 True. Data Input 1 Complement. Data Input 2 True. Data Input 2 Complement. Device Enable. Powers down device when low. This pin has an internal pullup. Data Input 3 True. Data Input 3 Complement. Bypass/Auto Bypass mode select. Bypasses reclocking when high. This pin has an internal pulldown. Data and Clock Output Mute input. Mutes the output when low. This pin has an internal pullup. Crystal or External Oscillator input. Crystal Oscillator output. PLL Lock Detect output (active high). Serial Clock or Serial Data Output 2 Complement. Serial Clock or Serial Data Output 2 True. Data Output Complement. Data Output True. Data Rate Range output. Output is high for SD and low for HD or 3G. Serial Clock or Serial Data 2 Output select. Sets second output to output the clock when high and the data when low. This pin has an internal pulldown. Loop Filter. Loop Filter. Data Rate select input. This pin has an internal pulldown. Data Rate select input. This pin has an internal pulldown. Data Input select input. This pin has an internal pulldown. Data Input select input. This pin has an internal pulldown. Positive power supply input. Negative power supply input. Description 3, 6, 12, 14, 30, VCC 31, 34, 35, DAP, 13, 17, VEE 19, 20, 21, 23, 25, 26, 27, 38, 39, 40, 41, 42 3 www.national.com LMH0356 Connection Diagram 30016702 The exposed die attach pad is the primary negative electrical terminal for this device. It must be connected to the negative power supply voltage. 48-Pin LLP Order Number LMH0356SQ See NS Package Number SQA48A www.national.com 4 LMH0356 Absolute Maximum Ratings (Note 1) It is anticipated that this device will not be offered in a military qualified version. If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (VCC–VEE) Logic Supply Voltage (Vi) Logic Input Current (single input): Vi = VEE−0.15V Vi = VCC+0.15V Logic Output Voltage (Vo) Logic Output Source/Sink Current Serial Data Input Voltage (VSDI) Serial Data Output Sink Current (ISDO) Package Thermal Resistance  θJA 48-pin LLP  θJC 48-pin LLP 4.0V VEE−0.15V to VCC +0.15V −5 mA +5 mA VEE−0.15V to VCC +0.15V ±8 mA VCC to VCC−2.0V 24 mA 24°C/W 1.5°C/W Storage Temp. Range Junction Temperature Lead Temperature (Soldering 4 Sec) ESD Rating (HBM) ESD Rating (MM) ESD Rating (CDM) −65°C to +150°C +125°C +260°C (Pb-free) 8 kV 400V 1250V Recommended Operating Conditions Supply Voltage (VCC–VEE) Logic Input Voltage Differential Serial Input Voltage Serial Data or Clock Output Sink Current (ISO) Operating Free Air Temperature (TA) 3.3V ±5% VEE to VCC 800 mV ±10% 16 mA max. −40°C to +85°C DC Electrical Characteristics Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. (Notes 2, 3) Symbol VIH VIL IIH IIL VOH VOL VSDID VCMI VSDOD VSCOD VCMO ICC Parameter Input Voltage High Level Input Voltage Low Level Input Current High Level Input Current Low Level VIH = VCC VIL = VEE Logic outputs SDI 2 VEE + 0.6 200 VEE+1.2 SDO SCO SDO, SCO 620 400 750 525 VCC− VSDOD 130 3 150 1600 VCC−0.2 880 650 Conditions Reference Logic inputs Min 2 VEE 47 −18 Typ Max VCC 0.8 65 −25 Units V V µA µA V V mVP-P V mVP-P mVP-P V mA mA Output Voltage High Level IOH = −2 mA Output Voltage Low Level IOL = +2 mA Serial Input Voltage, Differential Input Common Mode Voltage Serial Data Output Voltage, Differential Serial Clock Output Voltage, Differential Output Common Mode Voltage Power Supply Current, 3.3V supply, Total (Note 8) VSDID = 200 mV, (Note 8) 100Ω differential load 100Ω differential load, 2970 Mbps, (Note 8) 100Ω differential load 2970 Mbps, device enabled Device disabled (ENABLE = 0) 5 www.national.com LMH0356 AC Electrical Characteristics Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. (Note 3) Symbol BRSD BRSD BRSD TOLJIT TOLJIT TOLJIT TOLJIT TOLJIT TOLJIT tJIT tJIT tJIT BWLOOP Parameter Serial Data Rate Serial Data Rate Serial Data Rate Serial Input Jitter Tolerance Serial Input Jitter Tolerance Serial Input Jitter Tolerance Serial Input Jitter Tolerance Serial Input Jitter Tolerance Serial Input Jitter Tolerance Serial Data Output Jitter Serial Data Output Jitter Serial Data Output Jitter Loop Bandwidth Conditions SMPTE 259M, C SMPTE 292M SMPTE 424M 270 Mbps, (Notes 7, 8, 9) 270 Mbps, (Notes 7, 8, 10) 1483 or 1485 Mbps, (Notes 7, 8, 9) 1483 or 1485 Mbps, (Notes 7, 8, 10) 2967 or 2970 Mbps, (Notes 7, 8, 9) 2967 or 2970 Mbps, (Notes 7, 8, 10) 270 Mbps, (Notes 8, 11) 1483 or 1485 Mbps, (Notes 8, 12) 2967 or 2970 Mbps, (Notes 8, 13) 270 Mbps, 6 >0.6 >6 >0.6 0.01 0.04 0.08 275 1.5 2.75 270 1483 1485 2967 2970 2 3 0.03 0.05 0.09 Max Units Mbps Mbps Mbps UIP-P UIP-P UIP-P UIP-P UIP-P UIP-P UIP-P UIP-P UIP-P kHz MHz MHz MHz MHz MHz MHz MHz psRMS 45 55 15 % ms ns www.national.com 6 LMH0356 Symbol tr, tf tr, tf tr, tf tr, tf tr, tf FREF FTOL Parameter Input rise/fall time Input rise/fall time Input rise/fall time Output rise/fall time Output rise/fall time Reference Clock Frequency Reference Clock Frequency Tolerance Conditions 20%–80%, 270 Mbps, (Note 4) 20%–80%, 1483 or 1485 Mbps, (Note 4) 20%–80%, 2967 or 2970 Mbps, (Note 4) 10%–90% 20%–80%, (Notes 5, 8) Reference SDI Min Typ Max 1500 270 135 Units ps ps ps ns Logic outputs SDO, SCO 1.5 90 27 ±50 130 ps MHz ppm Note 1: “Absolute Maximum Ratings” are those parameter values beyond which the life and operation of the device cannot be guaranteed. The stating herein of these maximums shall not be construed to imply that the device can or should be operated at or beyond these values. The table of “Electrical Characteristics” specifies acceptable device operating conditions. Note 2: Current flow into device pins is defined as positive. Current flow out of device pins is defined as negative. All voltages are referenced to VEE (equal to zero volts). Note 3: Typical values are stated for: VCC = +3.3V, TA = +25°C. Note 4: This specification is guaranteed by design. Note 5: RL = 100Ω differential. Note 6: Measured from first SDI transition until Lock Detect (LD) output goes high (true). Note 7: Peak-to-peak amplitude with sinusoidal modulation per SMPTE RP 184-1996 paragraph 4.1. The test data signal shall be color bars. Note 8: This parameter is guaranteed by characterization over voltage and temperature limits. Note 9: Refer to “A1” in Figure 1 of SMPTE RP 184-1996. Note 10: Refer to “A2” in Figure 1 of SMPTE RP 184-1996. Note 11: PRBS 210– 1, input jitter = 31 psP-P. Note 12: PRBS 210– 1, input jitter = 24 psP-P. Note 13: PRBS 210– 1, input jitter = 22 psP-P. 7 www.national.com LMH0356 Device Description The LMH0356 3 Gbps HD/SD SDI Reclocker with 4:1 Input Mux and FR4 EQs is used in many types of digital video signal processing equipment. Supported serial digital video standards are SMPTE 259M (C), SMPTE 292M, and SMPTE 424M. Corresponding serial data rates are 270 Mbps, 1.483 Gbps, 1.485 Gbps, 2.967 Gbps, and 2.97 Gbps. DVB-ASI data at 270 Mbps may also be retimed. The LMH0356 retimes the serial data stream to suppress accumulated jitter. It provides two low-jitter, differential, serial data outputs. The second output may be selected to output either serial data or a low-jitter serial data-rate clock. Controls and indicators are: serial clock or second serial data output select, manual rate select input, SD/HD rate output, lock detect output, auto/manual data bypass and output mute. Serial data inputs are CML and LVPECL compatible. Serial data and clock outputs are differential CML and produce LVPECL compatible levels. The output buffer design can drive AC or DC-coupled, terminated 100Ω differential loads. The differential output level is 750 mVP-P into 100Ω AC or DCcoupled differential loads. Logic inputs and outputs are LVCMOS compatible. The device package is a 48–pin LLP with an exposed die attach pad. The exposed die attach pad is electrically connected to device ground (VEE) and is the primary electrical terminal for the device. This terminal must be connected to the negative power supply or circuit ground. Serial Data Inputs, Serial Data and Clock Outputs SERIAL DATA INPUT AND OUTPUTS The differential serial data inputs, SDI0-SDI3, accept serial digital video data at the rates specified in Table 1. Figure 1 shows the equivalent input circuit for SDI[3:0] and SDI[3:0]. The serial data inputs are differential LVPECL compatible. These inputs have 50Ω internal terminations (100Ω differential) with an internal bias as shown in Figure 1. These inputs are intended to be DC coupled to devices such as the LMH0344 adaptive cable equalizer. DC-coupled inputs must be kept within the specified common mode range. The inputs may be AC coupled if the input signal is outside the LMH0356's input common mode range (such as when interfacing to 5V PECL), and in that case the bias is supplied internally so no additional input biasing is required. See Application Information for more information on input interfacing. The LMH0356 provides four independent, equalized and multiplexed data inputs. The active input channel is selected via the SEL0 and SEL1 pins, as shown in Table 2. The equalizer on each of the four inputs is capable of equalizing up to 30” of FR4 trace without the need for programming for different trace lengths or data rates. The LMH0356 has two, retimed, differential, serial data outputs, SDO and SCO/SDO2. These outputs provide low jitter, differential, retimed data to devices such as the LMH0302 cable driver or the LMH0031 deserializer. Output SCO/SDO2 is multiplexed and can provide either a second serial data output or a serial clock output. Figure 2 shows the equivalent output circuit for SDO, SDO, SCO/SDO2, and SCO/SDO2. The SCO_EN input controls the operating mode for the SCO/ SDO2 output. When the SCO_EN input is high the SCO/ SDO2 output provides a serial clock. When SCO_EN is low, the SCO/SDO2 output provides retimed serial data. Both differential serial data outputs, SDO and SCO/SDO2, are muted when the OUTPUT MUTE input is a logic low level. SCO/SDO2 also mutes when the Bypass mode is activated when this output is operating as the serial clock output. When muted, SDO and SDO (or SDO2 and SDO2) will assume opposite differential output levels. The CML serial data outputs are differential LVPECL compatible. These outputs have internal 50Ω pull-ups and are suitable for driving AC or DCcoupled, 100Ω center-tapped, AC grounded or 100Ω uncenter-tapped, differentially terminated networks. 30016708 FIGURE 1. Equivalent SDI Input Circuit (SDI[3:0], SDI[3:0]) www.national.com 8 LMH0356 30016709 FIGURE 2. Equivalent SDO Output Circuit (SDO, SDO, SCO/SDO2, SCO/SDO2) OPERATING SERIAL DATA RATES This device operates at serial data rates of 270 Mbps, 1483 Mbps, 1485 Mbps, 2967 Mbps, and 2970 Mbps. The device does not lock to harmonics of these rates. The device does not lock and automatically enters the reclocker bypass mode for the following data rates: 143 Mbps, 177 Mbps, 360 Mbps, and 540 Mbps. SERIAL DATA CLOCK/SERIAL DATA 2 OUTPUT The Serial Data Clock/Serial Data 2 Output is controlled by the SCO_EN input and provides either a second retimed serial data output or a low jitter differential clock output appropriate to the serial data rate being processed. When operating as a serial clock output, the rising edge of the clock will be positioned within the corresponding serial data bit interval within 10% of the center of the data interval. Differential output SCO/SDO2 functions as the second serial data output when the SCO_EN input is a logic-low level. This output functions as the serial clock output when the SCO_EN input is a logic-high level. The SCO_EN input has an internal pull-down device and the default state of SCO_EN is low (serial data output 2 enabled). SCO/SDO2 is muted when the OUTPUT MUTE input is a logic low level. When the Bypass mode is activated and this output is functioning as a serial clock output, the output will also be muted. If an unsupported data rate is used while in Auto Bypass mode with this output functioning as a serial clock output, the output is invalid. downs which maintain a logic-low input condition unless externally driven to a logic-high condition. This input also serves to place the device in a test mode. The codes shown in Table 1 select the desired operating serial data rate. The LMH0356 then enters either the Auto-Rate Detect mode or a single operating rate. Selecting the 270 Mbps rate mode may also be used when reclocking DVB-ASI data. DVB-ASI data is MPEG2 coded data that is transmitted in 8B10B coding. The device will reclock this data without harmonic locking. TABLE 1. Data Rate Select Input Codes RATE [1:0] Code 00 Data Rate or Mode Auto-Rate Detect mode 270 Mbps 1483/1485 Mbps, 2967/2970 Mbps May be used to support DVBASI operation Comments 01 10 Control Inputs and Indicator Outputs SERIAL DATA RATE SELECTOR The Serial Data Rate Selector (RATE [1:0]) permits the user to fix the operating serial data rate. The pins have internal pull- 9 www.national.com LMH0356 SERIAL DATA INPUT SELECTOR The Serial Data Input Selector (SEL [1:0]) allows the user to select the active input channel. Table 2 shows the input selected for a given state of SEL [1:0]. The SEL pins have internal pull-downs. TABLE 2. Data Input Select Codes SEL [1:0] Code 00 01 10 11 Selected Input SDI0 SDI1 SDI2 SDI3 OUTPUT MUTE The OUTPUT MUTE input, when low, mutes the serial data and clock outputs. It may be connected to Lock Detect or externally driven to mute or un-mute the outputs. If OUTPUT MUTE is connected to LD, then the data and clock outputs are muted when the PLL is not locked. This function overrides the Bypass function: see Table 3. OUTPUT MUTE has an internal pull-up device to enable the output by default. BYPASS/AUTO BYPASS The Bypass/Auto Bypass input, when high, forces the device to output the data without reclocking it. When this input is low, the device automatically bypasses the reclocking function when the device is in an unlocked condition or the detected data rate is a rate which the device does not support. Note than when the Bypass/Auto Bypass input is set high, Lock Detect will remain low. See Table 3. BYPASS/AUTO BYPASS has an internal pull-down device. LOCK DETECT The Lock Detect (LD) output, when high, indicates that data is being received and the PLL is locked. LD may be connected to the OUTPUT MUTE input to mute the data and clock outputs when no data signal is being received. Note than when the Bypass/Auto Bypass input is set high, Lock Detect will remain low. See Table 3. TABLE 3. Control Functionality LOCK DETECT 0 1 X 0 1 OUTPUT MUTE 1 1 0 LOCK DETECT LOCK DETECT BYPASS/AUTO BYPASS X 0 X X 0 DEVICE STATUS PLL unlocked, reclocker bypassed PLL locked to supported data rate, reclocker not bypassed Outputs muted Outputs muted PLL locked to supported data rate, reclocker not bypassed www.national.com 10 LMH0356 SD/HD The SD/HD output indicates whether the LMH0356 is processing SD or HD / 3 Gbps data rates. It may be used to control another device such as the LMH0302 cable driver. When this output is high it indicates that the data rate is 270 Mbps. When low, the indicated data rate is 1483, 1485, 2967, or 2970 Mbps. The SD/HD output is a registered function and is only valid when the PLL is locked and the Lock Detect output is high. When the PLL is not locked (the Lock Detect output is low), the SD/HD output defaults to HD (low). The SD/ HD output is undefined for a short time after lock detect assertion or de-assertion due to a data rate change on SDI. See Figure 3 for a timing diagram showing the relationship between SDI, Lock Detect, and SD/HD. 30016705 FIGURE 3. SDI, Lock Detect, and SD/HD Timing 11 www.national.com LMH0356 SCO_EN Input SCO_EN enables the SCO/SDO2 differential output to function either as a serial clock or second serial data output. SCO/SDO2 functions as a serial clock when SCO_EN is high. This pin has an internal pull-down device. The default state (low) enables the SCO/SDO2 output as a second serial data output. ENABLE The ENABLE pin is used to enable or disable the LMH0356. When the device is disabled, the output drivers and most of the internal circuitry are powered down. The crystal oscillator / external clock reference circuitry (XTAL IN and XTAL OUT) remain active regardless of the state of ENABLE, allowing the 27 MHz reference clock signal to be generated and passed on to additional reclockers. The ENABLE pin is active high and has an internal pull-up device to enable the LMH0356 by default. CRYSTAL OR EXTERNAL CLOCK REFERENCE The LMH0356 uses a 27 MHz crystal or external clock signal as a timing reference input. A 27 MHz parallel resonant crystal and load network may be connected to the XTAL IN/EXT CLK and XTAL OUT pins. Alternatively, a 27 MHz LVCMOS compatible clock signal may be input to XTAL IN/EXT CLK. Parameters for a suitable crystal are given in Table 4. TABLE 4. Crystal Parameters Parameter Frequency Frequency Stability Operating Mode Load Capacitance Shunt Capacitance Series Resistance Recommended Drive Level Maximum Drive Level Operating Temperature Range 27 MHz ±50 ppm @ recommended drive level Fundamental mode, Parallel Resonant 20 pF 7 pF 40Ω max. 100 µW 500 µW −10°C to +60°C Value www.national.com 12 LMH0356 Application Information Figure 4 shows a typical application circuit for the LMH0356. 30016704 FIGURE 4. Application Circuit ENABLE has an internal pullup to enable the device by default. This pin may be pulled low to put the LMH0356 into a powered down mode. BYPASS/AUTO BYPASS has an internal pulldown to enable Auto Bypass mode by default. This pin may be pulled high to force the LMH0356 to bypass all data. OUTPUT MUTE has an internal pullup to enable the outputs by default. This pin may be pulled low to mute the outputs. The XTAL IN/EXT CLK and XTAL OUT pins are shown with a 27 MHz crystal and the proper loading. The crystal should match the parameters described in Table 4. Alternately, a 27MHz LVCMOS compatible clock signal may be input to XTAL IN/EXT CLK. The active high LOCK DETECT output provides an indication that proper data is being received and the PLL is locked. The SD/HD output may be used to drive the SD/HD pin of an SDI cable driver (such as the LMH0302) in order to properly set the cable driver’s edge rate for SMPTE compliance. It defaults to HD/3G (low) when the LMH0356 is not locked. SCO_EN has an internal pulldown to set the second output (SCO/SDO2) to output data. This pin may be pulled high to set the second output as a serial clock. The external loop filter capacitor (between LF1 and LF2) should be 56 nF. This is the only supported value; the loop filter capacitor should not be changed. RATE0 and RATE1 have internal pulldowns to select AutoRate Detect mode by default. These pins may also be used to set the device to SD mode or HD/3G mode. SEL0 and SEL1 have internal pulldowns to select the SDI0 input by default. The inputs are LVPECL compatible. The LMH0356 has a wide input common mode range and in most cases the input should be DC coupled. For DC coupling, the inputs must be kept within the common mode range specified in DC Electrical Characteristics. Figure 5 shows an example of a DC coupled interface between the LMH0344 cable equalizer and the LMH0356. The LMH0344 output common mode voltage and voltage swing are within the range of the input common mode voltage and 13 www.national.com LMH0356 voltage swing of the LMH0356. In this figure, the LMH0344 cable equalizer restores the signal after the coaxial cable. The LMH0356 FR4 equalizer restores the signal after the loss due to the FR4 trace. The LMH0356 inputs have 50Ω internal terminations (100Ω differential) to terminate the transmission line, so no additional components are required. The outputs are LVPECL compatible. SDO is the primary data output and SCO/SDO2 is a second output that may be set as the serial clock or a second data output. Both outputs are always active. The LMH0356 output should be DC coupled to the input of the receiving device as long as the common mode ranges of both devices are compatible. Figure 6 shows an example of a DC coupled interface between the LMH0356 and LMH0302 cable driver. All that is required is a 100Ω differential termination as shown. The resistor should be placed as close to the LMH0302 input as possible. If desired, this network may be terminated with two 50Ω resisters and a center tap capacitor to ground in place of the single 100Ω resistor. The LMH0356 has multiple ground connections, however; the primary ground connection is through the large exposed DAP. The DAP must be connected to ground for proper operation of the LMH0356. 30016706 FIGURE 5. DC Input Interface 30016707 FIGURE 6. DC Output Interface www.national.com 14 LMH0356 Physical Dimensions inches (millimeters) unless otherwise noted 48-Pin LLP Order Number LMH0356SQ NS Package Number SQA48A 15 www.national.com LMH0356 3 Gbps HD/SD SDI Reclocker with 4:1 Input Mux and FR4 EQs Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Amplifiers Audio Clock Conditioners Data Converters Displays Ethernet Interface LVDS Power Management Switching Regulators LDOs LED Lighting PowerWise Serial Digital Interface (SDI) Temperature Sensors Wireless (PLL/VCO) www.national.com/amplifiers www.national.com/audio www.national.com/timing www.national.com/adc www.national.com/displays www.national.com/ethernet www.national.com/interface www.national.com/lvds www.national.com/power www.national.com/switchers www.national.com/ldo www.national.com/led www.national.com/powerwise www.national.com/sdi www.national.com/tempsensors www.national.com/wireless WEBENCH Analog University App Notes Distributors Green Compliance Packaging Design Support www.national.com/webench www.national.com/AU www.national.com/appnotes www.national.com/contacts www.national.com/quality/green www.national.com/packaging www.national.com/quality www.national.com/refdesigns www.national.com/feedback Quality and Reliability Reference Designs Feedback THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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