LMH2180YD

LMH2180 75 MHz Dual Clock Buffer January 24, 2008 LMH2180 75 MHz Dual Clock Buffer General Description The LMH2180 is a high speed dual clock buffer designed for portable communications and applications requiring multiple accurate multi-clock systems. The LMH2180 integrates two 75 MHz low noise buffers with independent shutdown pins into a small package. The LMH2180 ensures superb system operation between the baseband and the oscillator signal path by eliminating crosstalk between the multiple clock signals. Unique technology and design provides the LMH2180 with the ability to accurately drive both large capacitive and resistive loads. Low supply current combined with shutdown pins for each channel means the LMH2180 is ideal for battery powered applications. The LMH2180's rapid recovery after disable optimizes performance and current consumption. This part does not use an internal ground reference, thus providing additional system flexibility. The LMH2180 operates both with single and split supplies. The flexible buffers provide system designers the capacity to manage complex clock signals in the latest wireless applications. Each buffer delivers 106 V/μs internal slew rate with independent shutdown and duty cycle precision. The patented analog circuit of each buffer drives capacitive loads greater than 20 pF. Each input is internally biased to 1V, removing the need for external resistors. Both channels have rail-to-rail inputs and outputs, a gain of one, and are AC coupled with the use of one capacitor. Replacing a discrete buffer solution with the LMH2180 provides many benefits: simplified board layout, minimized parasitic components, simplified BOM, design durability across multiple applications, simplification of clock paths, and the ability to reduce the number of clock signal generators in the system. The LMH2180 is produced in the tiny 8-pin LLP solder bump and no pullback packages minimizing the required PCB space. National’s advanced packaging offers direct PCB-IC evaluation via pin access. Features (Typical values are: VSUPPLY = 2.7V and CL = 10 pF, unless otherwise specified.) 78 MHz ■ Small signal bandwidth 2.4V to 5V ■ Supply voltage range -123dBc/Hz ■ Phase noise (VIN = 1 VPP, fC = 38.4 MHz, Δf = 1kHz) 106 V/μs ■ Slew rate 2.3 mA ■ Total supply current 30 µA ■ Shutdown current ■ Rail-to-rail input and output ■ Individual buffer enable pins ■ Rapid Ton technology ■ Crosstalk rejection circuitry ■ 8-pin LLP, pin access packaging −40°C to 85°C ■ Temperature range Applications ■ ■ ■ ■ ■ 3G mobile applications WLAN–WiMAX modules TD_SCDMA multi-mode MP3 and camera GSM modules Oscillator modules Typical Application 30024602 © 2008 National Semiconductor Corporation 300246 www.national.com LMH2180 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltages (V+– V−) ESD Tolerance Human Body (Note 4) Machine Model (Note 5) Charged Device Model Storage Temperature Range 5.5V 2000V 200V 1000V −65°C to +150°C Junction Temperature (Note 3) Soldering Information Infrared or Convection (35 sec.) +150°C 235°C Operating Ratings (V+ V−) (Note 1) Supply Voltage – 2.4V to 5.0V Temperature Range (Notes 2, 3) −40°C to +85°C Package Thermal Resistance (Notes 2, 3) LLP-8 (θJA) 217°C/W 2.7V Electrical Characteristics Unless otherwise specified, all limits are guaranteed for TJ = 25°C, VDD = 2.7V, VSS = 0V, VCM = 1V, Enable1,2 = VDD, CL = 10 pF, RL = 30 kΩ, Load is connected to VSS, CCOUPLING = 10 nF. Boldface limits apply at temperature range extremes of operating condition. See (Note 2) Symbol Parameter Conditions Min (Note 7) Typ (Note 6) 78 60 4.9 −123 −132 13 84 41 6 5 1 VPP Step 0.1 VPP Step VIN = 2 VPP Enable1,2 = VDD ; No Load Enable1 = VDD , Enable2 = VSS , No Load Enable1,2 = VSS ; No Load PSRR ACL VOS TC VOS ROUT Power Supply Rejection Ratio Small Signal Voltage Gain Output Offset Voltage Temperature Coefficient Output Offset Voltage (Note 9) Output Resistance f = 100 kHz f = 38.4 MHz DC (3.0V to 5.0V) VIN = 0.2 VPP 65 64 0.95 120 37 106 2.7 2.9 1.5 1.6 41 46 Max (Note 7) Units Frequency Domain Response SSBW LSBW GFN φn en ISOLATION CT tr tf ts OS SR IS Small Signal Bandwidth Large Signal Bandwidth Gain Flatness < 0.1 dB Phase Noise VIN = 100 mVPP; −3 dB VIN = 1.0 VPP; −3 dB f > 100 kHz VIN = 1 VPP, fC = 38.4 MHz, Δf = 1 kHz VIN = 1 VPP, fC = 38.4 MHz, Δf = 10 kHz Input-Referred Voltage Noise Output to Input Crosstalk Rejection Rise Time Fall Time Settling Time to 0.1% Overshoot Slew Rate (Note 8) Supply Current f = 1 MHz, RSOURCE = 50Ω f = 1 MHz, RSOURCE = 50Ω f = 38.4 MHz, VIN = 1 VPP 0.1 VPP Step (10-90%) MHz MHz MHz dBc/Hz dBc/Hz nV/ dB dB ns ns ns % V/µs Distortion and Noise Performance Time Domain Response Static DC Performance 2.3 1.3 30 68 1.0 -0.5 2.8 0.6 166 1.05 17 18 mA mA μA dB V/V mV µV/°C Ω www.national.com 2 LMH2180 Symbol Parameter Conditions Min (Note 7) Typ (Note 6) 137 137 1.3 1.3 4.5 4.2 Max (Note 7) Units Miscellaneous Performance RIN CIN ZIN VO Input Resistance per Buffer Input Capacitance per Buffer Input Impedance Output Swing Positive Output Swing Negative ISC Output Short-Circuit Current (Notes 10, 11) Enable = VDD Enable = VSS Enable = VDD Enable = VSS f = 38.4 MHz, Enable = VDD f = 38.4 MHz, Enable = VSS VIN = VDD VIN = VSS Sourcing, VIN = VDD, VOUT = VSS Sinking, VIN = VSS, VOUT = VDD Ven_hmin Ven_lmax Enable High Active Minimum Voltage Enable Low Inactive Maximum Voltage −21 −18 23 15 2.66 2.65 kΩ pF kΩ V 35 37 mV 2.69 19 −25 mA 25 1.2 0.6 V 5V Electrical Characteristics Unless otherwise specified, all limits are guaranteed for TJ = 25°C, VDD = 5V, VSS = 0V, VCM = 1V, Enable1,2 = VDD, CL = 10 pF, RL = 30 kΩ, Load is connected to VSS, CCOUPLING = 10 nF. Boldface limits apply at temperature range extremes of operating condition. See (Note 2) Symbol Parameter Conditions Min (Note 7) Typ (Note 6) 87 68 25 −123 −132 12 84 59 6 6 1 VPP Step 0.1VPP Step VIN = 2 VPP Enable1,2 = VDD ; No Load Enable1 = VDD, Enable2 = VSS ; No Load Enable1,2 = VSS ; No Load 70 13 124 4.0 4.1 2.2 2.3 43 49 Max (Note 7) Units Frequency Domain Response SSBW LSBW GFN φn en ISOLATION CT tr tf ts OS SR IS Small Signal Bandwidth Large Signal Bandwidth Gain Flatness < 0.1 dB Phase Noise VIN = 100 mVPP; −3 dB VIN = 1.0 VPP; −3 dB f > 100 kHz VIN = 1 VPP, fC = 38.4 MHz, Δf = 1 kHz VIN = 1 VPP, fC = 38.4 MHz, Δf = 10 kHz Input-Referred Voltage Noise Output to Input Crosstalk Rejection Rise Time Fall Time Settling Time to 0.1% Overshoot Slew Rate (Note 8) Supply Current f = 1 MHz, RSOURCE = 50Ω f = 1 MHz, RSOURCE = 50Ω f = 38.4 MHz, PIN = 0 dBm 0.1 VPP Step (10-90%) MHz MHz MHz dBc/Hz dBc/Hz nV/ dB dB ns ns ns % V/µs Distortion and Noise Performance Time Domain Response Static DC Performance 3.4 1.8 32 mA mA μA 3 www.national.com LMH2180 Symbol PSRR ACL VOS TC VOS ROUT Parameter Power Supply Rejection Ratio Small Signal Voltage Gain Output Offset Voltage Temperature Coefficient Output Offset Voltage (Note 9) Output Resistance f = 100 kHz f = 38.4 MHz Conditions DC (3.0V to 5.0V) VIN = 0.2 VPP Min (Note 7) 65 64 0.95 Typ (Note 6) 68 1.0 −1.4 2.4 0.5 126 138 138 1.3 1.3 4.3 4.2 Max (Note 7) Units dB 1.05 21 22 V/V mV µV/°C Ω Miscellaneous Performance RIN CIN ZIN VO Input Resistance per Buffer Input Capacitance per Buffer Input Impedance Output Swing Positive Output Swing Negative ISC Output Short-Circuit Current (Notes 10, 11) Enable = VDD Enable = VSS Enable = VDD Enable = VSS f = 38.4 MHz, Enable = VDD f = 38.4 MHz, Enable = VSS VIN = VDD VIN = VSS Sourcing, VIN = VDD, VOUT = VSS Sinking, VIN = VSS, VOUT = VDD Ven_hmin Ven_lmax Enable High Active Minimum Voltage Enable Low Inactive Maximum Voltage −80 −62 60 43 4.96 4.95 kΩ pF kΩ V 35 50 mV 4.99 10 −90 mA 65 1.2 0.6 V Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of the device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All voltages are measured with respect to the ground pin, unless otherwise specified. Note 2: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed. Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJ(MAX), θJA , and the ambient temperature TA. The maximum allowable power dissipation is PDMAX = (TJMAX − TA) / θJA or the number given in the Absolute Maximum Ratings, whichever is lower. Note 4: Human body model, applicable std. JESD22–A114C. Note 5: Machine model, applicable std. JESD22–A115–A. Note 6: Typical values represent the most likely parametric norms at TA = +25°C, and at the Recommended Operation Conditions at the time of product characterization and are not guaranteed. Note 7: Datasheet min/max specification limits are guaranteed by test or statistical analysis. Note 8: Slew rate is the average of the rising and falling slew rates. Note 9: Average Temperature Coefficient is determined by dividing the changing in a parameter at temperature extremes by the total temperature change. Note 10: Short−Circuit test is a momentary test. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150°C. Note 11: Positive current corresponds to current flowing into the device. www.national.com 4 LMH2180 Block Diagram 30024601 Pin Descriptions Pin No. 1 2 3 4 5 6 7 8 Pin Name VDD IN 1 IN 2 ENABLE 2 VSS OUT 2 OUT 1 ENABLE 1 Voltage supply connection Input 1 Input 2 Enable buffer 2 Ground connection Output 2 Output 1 Enable buffer 1 Description Connection Diagram 8-Pin LLP 30024631 Top View Ordering Information Package 8-Pin LLP Solder Bump 8-Pin LLP No Pullback Part Number LMH2180YD LMH2180YDX LMH2180SD LMH2180SDX Package Marking LMH2180YD LMH2180SD Transport Media 1k Units Tape and Reel 4.5k Units Tape and Reel 1k Units Tape and Reel 4.5 Units Tape and Reel NSC Drawing YDA08A SDA08A 5 www.national.com LMH2180 Typical Performance Characteristics Frequency Response RL = 30kΩ and CCOUPLING = 10nF, unless otherwise specified. TJ = 25°C, VDD = 2.7V, VSS = 0V, Enable1,2 = VDD, CL = 10 pF, Phase Response 30024603 30024604 Frequency Response Over Temperature Frequency Response Over Temperature 30024605 30024606 Phase Response Over Temperature Phase Response Over Temperature 30024607 30024608 www.national.com 6 LMH2180 Large Signal Bandwidth Gain Flatness < 0.1 dB (GFN) 30024609 30024610 Voltage Noise Phase Noise 30024611 30024612 Isolation Output to Input vs. Frequency Crosstalk Rejection vs. Frequency 30024613 30024614 7 www.national.com LMH2180 Transient Response Positive Transient Response Negative 30024615 30024616 Small Signal Pulse Response Small Signal Pulse Response 30024617 30024618 Large Signal Response Large Signal Response 30024619 30024620 www.national.com 8 LMH2180 ISUPPLY vs. VSUPPLY ISUPPLY vs. VSUPPLY 30024621 30024622 ISUPPLY vs. VSUPPLY PSRR vs. Frequency 30024623 30024624 VOS vs. VSUPPLY ROUT vs. Frequency 30024625 30024626 9 www.national.com LMH2180 Input Impedance vs. Frequency VOUT vs. IOUT (Sourcing) 30024627 30024628 VOUT vs. IOUT (Sourcing) VOUT vs. IOUT (Sinking) 30024629 30024630 VOUT vs. IOUT (Sinking) ISC Sourcing vs. VSUPPLY Over Temperature 30024632 30024633 www.national.com 10 LMH2180 ISC Sinking vs. VSUPPLY Over Temperature ISUPPLY vs. VENABLE 30024634 30024635 ISUPPLY vs. VENABLE 30024636 11 www.national.com LMH2180 Application Information GENERAL The LMH2180 is designed to minimize the effects of spurious signals from the base chip to the oscillator. Also the influence of varying load resistance and capacitance to the oscillator is minimized, while the drive capability is increased. The inputs of the LMH2180 are internally biased at 1V, making AC coupling possible without external bias resistors. To optimize current consumption, a buffer that is not in use can be disabled by connecting it's enable pin to VSS. The LMH2180 has no internal ground reference; therefore, either single or split supply configurations can be used. The LMH2180 is an easy replacement for discrete circuitry. It simplifies board layout and minimizes the effect of layout related parasitic components. INPUT CONFIGURATION The internal 1V input biasing allows AC coupling of the input signal. This biasing avoids the use of external resistors, as depicted in Figure 1. The biasing prevents a large DC load at the oscillators output that creates a load impedance and may affect it's oscillating frequency. As a result of this biasing, the maximum amplitude of the AC signal is 2VPP. The coupling capacitance C1 should be large enough to let the AC signal pass. This is a unity gain buffer with rail-to-rail inputs and outputs. teristic graphic entitled Isolation Output to Input vs. Frequency. A block diagram of the isolation is shown in Figure 2. Crosstalk rejection between buffers prevents signals from affecting each other. Figure 2 shows a Baseband IC and a Bluetooth module as an example. See the characteristic graphic labeled Crosstalk Rejection vs. Frequency for more information. 30024645 FIGURE 2. Isolation Block Diagram DRIVING CAPACITIVE LOADS Each buffer can drive a capacitive load. Be aware that every capacitor directly connected to the output becomes part of the loop of the buffer. In most applications the load consists of the capacitance of copper tracks and the input capacitance of the application blocks. Capacitance reduces the gain/phase margin and decreases the stability. This leads to peaking in the frequency response and in extreme situations oscillations can occur. To drive a large capacitive load it is recommended to include a series resistor between the buffer and the load capacitor. The best value for this isolation resistance can be found by experimentation. The LMH2180 datasheet reflects measurements with capacitive loads of 10 pF at the output of the buffers. Most common applications will probably use a lower capacitive load, which will result in lower peaking and significantly greater bandwidth, see Figure 3. 30024644 FIGURE 1. Input Configuration FREQUENCY PULLING Frequency pulling is the frequency variation of an oscillator caused by a varying load. In the typical application, the load of the oscillator is a fixed capacitor (C1) in series with the input impedance of the buffer. To keep the input impedance as constant as possible, the input is biased at 1V, even when the part is disabled. A simplified schematic of the input configuration is shown in Figure 1. ISOLATION AND CROSSTALK Output to input isolation prevents the clock signal of the oscillator from being affected by spurious signals generated by the digital blocks behind the output buffer. See the charac30024646 FIGURE 3. Bandwidth and Peaking www.national.com 12 LMH2180 PHASE NOISE A clock buffer adds noise to the clock signal. This noise causes uncertainty in the phase of the clock signal. This uncertainty is described by jitter (time domain) or phase noise (frequency domain). Communication systems, such as Wireless LAN, require a low jitter / phase noise clock signal to obtain a low Bit Error Rate. Figure 4 shows the frequency domain representation of a clock signal with frequency fC. Without Phase Noise the entire signal power would only be located at the frequency fC. Phase Noise spreads some of the power to adjacent frequencies. Phase Noise is usually specified in dBc/Hz at a given frequency offset Δf from the carrier, where dBc is the power level in dB relative to the carrier. The noise power is measured within a 1Hz bandwidth. Figure 5 shows the setup used to measure the LMH2180 phase noise. The clock driving the LMH2180 is a state of the art 38.4MHz TCXO. Both the TCXO phase noise and the phase noise at the LMH2180 output were measured. At offset frequencies of 1kHz and higher from the carrier, the TCXO phase noise is sufficiently low to accurately calculate the LMH2180 contribution to the phase noise at the output. The LMH6559, whose phase noise contribution can be neglected, is used to drive the 50Ω input impedance of the Signal Source Analyzer. LAYOUT DESIGN RECOMMENDATION Careful consideration during circuit design and PCB layout will eliminate problems and will optimize the performance of the LMH2180. It is best to have the same ground plane on the PCB for all decoupling and other ground connections. To ensure a clean supply voltage it is best to place decoupling capacitors close to the LMH2180, between VDD and VSS. Another important issue is the value of the components, because this also determines the sensitivity to disturbances. Resistor values have to be low enough to avoid a significant noise contribution and large enough to avoid a significant increase in power consumption while loading inputs or outputs to heavily. 30024648 FIGURE 4. Phase Noise 30024647 FIGURE 5. Measurement Setup 13 www.national.com LMH2180 Physical Dimensions inches (millimeters) unless otherwise noted 8-Pin LLP NS Package Number YDA08A 8–Pin LLP NS Package Number SDA08A www.national.com 14 LMH2180 Notes 15 www.national.com LMH2180 75 MHz Dual Clock Buffer Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Amplifiers Audio Clock Conditioners Data Converters Displays Ethernet Interface LVDS Power Management Switching Regulators LDOs LED Lighting PowerWise Serial Digital Interface (SDI) Temperature Sensors Wireless (PLL/VCO) www.national.com/amplifiers www.national.com/audio www.national.com/timing www.national.com/adc www.national.com/displays www.national.com/ethernet www.national.com/interface www.national.com/lvds www.national.com/power www.national.com/switchers www.national.com/ldo www.national.com/led www.national.com/powerwise www.national.com/sdi www.national.com/tempsensors www.national.com/wireless WEBENCH Analog University App Notes Distributors Green Compliance Packaging Design Support www.national.com/webench www.national.com/AU www.national.com/appnotes www.national.com/contacts www.national.com/quality/green www.national.com/packaging www.national.com/quality www.national.com/refdesigns www.national.com/feedback Quality and Reliability Reference Designs Feedback THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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