LMH2190

LMH2190 Quad Channel 27 MHz Clock Tree Driver with I2C Interface October 7, 2009 LMH2190 Quad Channel 27 MHz Clock Tree Driver with I2C Interface General Description The LMH2190 is a quad channel configurable clock tree driver which supplies a digital system clock to peripherals in mobile handsets or other applications. It provides a solution to clocking issues such as limited drive capability for fanout or longer traces, protection of the master clock from varying loads and frequency pulling effects, isolation buffering from noisy modules, and crosstalk isolation. It has very low phase noise which enables it to drive sensitive modules such as Wireless LAN and Bluetooth. The LMH2190 can be clocked up to 27 MHz, and has an independent clock request pin for each clock output which allows the peripheral to control the clock. It features an integrated LDO which provides an ultra low noise voltage supply with 10 mA external load current which can be used to supply the TCXO or other clock source. The I2C serial interface can be used to override the default configuration of the device to optimize the LMH2190 for the application. Some of these programmable features include setting the polarity of both the clock and the clock request inputs. In addition, the clock outputs have programmable output drive current to optimize for the connected load. EMI switching noise can be controlled by configuring output drive and skew settings. The LMH2190 quad clock distributor is offered in a tiny 1.615mm x 1.615mm 16 bump microSMD package. Its small size and low supply current make it ideal for portable applications. Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 1 input clock, 4 output clocks Supports both square or sine wave input 1.8V square wave clock outputs Skewed clock outputs Independent clock request High isolation of supply noise to clock input High output to output Isolation Output Drive up to 50 pF EMI controlled output edges and EMI filtering Integrated 1.8V Low-Dropout Regulator — Low Output Noise Voltage — 10 mA load current ■ I2C Configurable up to 400 kHz (Fast Mode) ■ Ultra low standby current ■ VBAT range = 2.5V to 5.5V Applications ■ Mobile handsets ■ PDAs ■ Portable Equipment Typical Application 30083802 © 2009 National Semiconductor Corporation 300838 www.national.com LMH2190 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage VBAT - VSS LVCMOS port IO voltage Current on CLKx pins ESD Tolerance (Note 2) Human Body Model Machine Model Storage Temperature Range Junction Temperature (Note 3) Maximum Lead Temperature (Soldering,10 sec) -0.3V to 6V -0.3V to (VOUT + 0.3V) +/- 65 mA 2000V 200V −65°C to 150°C 150°C 230°C Operating Ratings Supply Voltage (VBAT - VSS) VENABLE Input Clock, SCLK_IN DC Mode AC Mode Duty Cycle Temperature Range Package Thermal Resistance θJA (Note 3) (Note 1) 2.5V to 5.5V 0 to 2V 32 kHz to 27 MHz 13 MHz to 27 MHz 45% to 55% -20°C to +85°C 113.6°C/W (Note 4, Note 11) Unless otherwise specified, all limits are guaranteed at TA = 25°C, VBAT = 3.5V, fSCLK_IN = 26 MHz, COUT = 2.2 µF, VDD_IO = 1.8V (See Block Diagram and (Note 9)), IOUT = 1 mA, Registers are in default setting. Boldface limits apply at the temperature extremes. Symbol Parameter Condition Min (Note 6) Typ (Note 5) Max (Note 6) Units 3.5 V DC and AC Electrical Characteristics Supply Current (Note 8) IDD Active Supply Current Clock outputs toggling at 26 MHz without external capacitors on CLK1/2/3/4, LDO is ON, IOUT = 0 mA In Shutdown. No clocks toggling. LDO is OFF In Shutdown. Input CLK toggling, no Clock outputs toggling. LDO is OFF IDDQ Quiescent Supply Current No Clock outputs toggling. LDO is ON, IOUT = 0 mA No Clock outputs toggling, LDO is ON, IOUT = 10 mA IDDEN CPD Current to Enable pin Power Dissipation Capacitance per CLK output, (Note 7) Propagation Delay SCLK_IN to CLK1 - Low to High, Figure 1 (Note 7) Propagation Delay SCLK_IN to CLK1 - High to Low, Figure 1 (Note 7) Skew Between Outputs (Either Edge), Figure 1, (Note 7) Rise Time, Figure 3, (Note 7, Note 13) I2C port is operational I2C port is idle Defined with respect to VOUT = 1.8V 15.7 3 mA Shutdown Supply Current 0.1 0.1 36 50 1 μA 1 60 μA 80 300 0.1 17.5 μA pF Clock Outputs (CLK1/2/3/4) tpLH 50% to 50% 6.5 50% to 50% 7.5 CLK1 to CLK2, 50% to 50% CLK2 to CLK3 and CLK3 to CLK4, 50% to 50% CL = 10 pF to 50 pF, 20% to 80% 3 1 6 3.5 3 2.5 42 50 11 8.5 7.3 6 ns 5 58 % ns ns 10 ns tpHL tSKEW tRISE tFALL CLK_DC Fall Time, Figure 3, (Note 7, Note CL = 10 pF to 50 pF, 80% to 20% 13) Output Clock Duty Cycle, Figure 3, (Note 7) CL = 10 pF to 50 pF www.national.com 2 LMH2190 Symbol JitterRMS Parameter Additive RMS period Jitter Condition BW = 100 Hz to 1 MHz CLK1 CLK2 CLK3 CLK4 Min (Note 6) Typ (Note 5) 100 240 330 400 -130 -144 -152 -158 -165 -128 -139 -146 -151 -153 -127 -138 -144 -148 -150 -125 -135 -142 -147 -148 Max (Note 6) Units fs Phase Noise CLK1 Additive Phase Noise with f = 100 Hz all Outputs toggling f = 1 kHz f = 10 kHz f = 100 kHz f = 1 MHz CLK2 Additive Phase Noise with f = 100 Hz all Outputs toggling f = 1 kHz f = 10 kHz f = 100 kHz f = 1 MHz CLK3 Additive Phase Noise with f = 100 Hz all Outputs toggling f = 1 kHz f = 10 kHz f = 100 kHz f = 1 MHz CLK4 Additive Phase Noise with f = 100 Hz all Outputs toggling f = 1 kHz f = 10 kHz f = 100 kHz f = 1 MHz dBc/Hz VOH VOL CLK1/2/3/4 Output Voltage High CLK1/2/3/4 = -2 mA Level CLK1/2/3/4 Output Voltage Low Level SCLK_IN Input Voltage High Level SCLK_IN Input Voltage Low Level SCLK_IN Input Current High Level SCLK_IN Input Current Low Level Input Capacitance (Note 7) DC Bias Voltage Input Resistance AC Mode AC Mode, Clock path enabled. CLK1/2/3/4 = 2 mA 1.6 V 0.2 System Clock Input (SCLK_IN) VIH DC Mode AC Mode VIL DC Mode AC Mode IIH IIL CIN VBIAS RIN SCLK_IN = 1.8V, Clock path disabled SCLK_IN = VSS, Clock path disabled 0.65 x VOUT 1.2 0 0 0 -0.1 0 7.5 0.805 21 30 10 2.0 1.8 0.35 x VOUT 0.6 0.1 µA µA pF V kΩ V V 3 www.national.com LMH2190 Symbol Parameter Condition Min (Note 6) Typ (Note 5) Max (Note 6) Units Clock Request Output (SCLK_REQ) tpLH Propagation Delay, Push-Pull and Open Source, Figure 2, (Note 7) Propagation Delay, Push-Pull and Open Drain, Figure 2, (Note 7) 50% to 50% 21 50% to 50% 15 21 32 ns tpHL VOH SCLK_REQ Output Voltage High SCLK_REQ = -500 µA, Push-Pull Level Output SCLK_REQ = -500 µA, Open Source Output 1.52 V 1.52 0.2 0.2 V VOL SCLK_REQ Output Voltage Low SCLK_REQ = 500 µA, Push-Pull Output Level SCLK_REQ = 500 µA, Open Drain Output Setup Time from CLK_REQx to SCLK_IN, to enable CLKx, Figure 4, (Note 7) CLK_REQ1/2/3/4 Input Voltage High Level CLK_REQ1/2/3/4 Input Voltage Low Level CLK_REQ1/2/3/4 Input Current High Level 200 kΩ internal pull down resistor. CLK_REQ1/2/3/4 = 1.8V Without internal / external pull down resistor. CLK_REQ1/2/3/4 = 1.8V 8.3 0 -0.1 0 Clock Request Inputs (CLK_REQ1/2/3/4) tSET 16 0.8 x VDD_IO 0.2 x VDD_IO 12.7 µA 0.1 µA ns VIH VIL IIH V V IIL CLK_REQ1/2/3/4 Input Current Low Level SCL and SDA Input Voltage High Level SCL and SDA Input Voltage Low Level VIL = VSS SCL and SDA Inputs, VENABLE = 1.8V (Note 10) VIH VIL IIH IIL VOL VIH VIL IIH IIL LDO VOUT ILOAD VDO ISC Output Voltage Load Current (Note 12) Dropout Voltage (Note 14) Short Circuit Current Limit IOUT = 1 mA VOUT > 1.74V VOUT = 1.7V, IOUT = 10 mA 1.78 0 100 300 1.805 1.82 10 150 V mA mV mA 0.8 x VENABLE 0.2 x VENABLE 0 -28 -18 0.2 0.1 V V µA µA V SCL and SDA Input Current High SCL/SDA = VENABLE Level SCL and SDA Input Current Low 100 kΩ internal Pull-up resistor, SCL/ Level SDA = VSS SDA Output Voltage Low Level ENABLE Input Voltage High Level ENABLE Input Voltage Low Level ENABLE Input Current High Level ENABLE = VOUT -0.1 SDA = 3 mA ENABLE Input 1.65 2 0.5 0.1 V V µA µA ENABLE Input Current Low Level ENABLE = VSS www.national.com 4 LMH2190 Symbol PSRR Parameter Power Supply Rejection Ratio Condition VBAT ripple = 200 mVPP, f = 100 Hz IOUT = 10 mA f = 217.5 Hz f = 1 kHz f = 10 kHz f = 50 kHz f = 100 kHz f = 1 MHz f = 3.25 MHz Min (Note 6) Typ (Note 5) 93 90 78 62 54 50 42 35 10 160 20 Max (Note 6) Units dB EN TSHTDWN ΔVOUT Output Noise Voltage Thermal Shutdown Line Transient (Note 7) BW = 10Hz to 100 kHz, VBAT = 4.2V, COUT = 2.2 µF, All Outputs are Off Temperature Hysteresis VBAT = (VOUT (NOM) + 1.0V) to (VOUT (NOM) + 1.6V) in 30 µs VBAT = (VOUT (NOM) + 1.6V) to (VOUT (NOM) + 1.0V) in 30 µs -1 µVRMS °C mV 1 -70 30 100 5 mV mV Ω 270 µs Load Transient (Note 7) Overshoot on Startup (Note 7) ROUT TON DC Output Resistance Turn on Time (Note 7) IOUT = 0 mA to 10 mA in 10 µs IOUT = 10 mA to 0 mA in 10 µs to 95% of VOUT (NOM) 185 Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see the Electrical Characteristics Tables. Note 2: Human body model, applicable std. MIL-STD-883, Method 3015.7. Machine model, applicable std. JESD22–A115–A (ESD MM std of JEDEC). FieldInduced Charge-Device Model, applicable std. JESD22–C101–C. (ESD FICDM std. of JEDEC) Note 3: The maximum power dissipation is a function of TJ(MAX) , θJA and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA)/θJA. All numbers apply for packages soldered directly onto a PC board. Note 4: Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. Note 5: Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not guaranteed on shipped production material. Note 6: Limits are 100% production tested at 25°C. Limits over temperature range are guaranteed through correlations using statistical quality control (SQC) method. Note 7: This parameter is guaranteed by design and/or characterization and is not tested in production. Note 8: IDD current depends on switching frequency and load. Note 9: VDD_IO is equal to VOUT when the LDO is enabled and it is equal to VENABLE when it is disabled. Note 10: I2C interface uses IO cells guaranteed for 1.8V typical supply (1.6V Min - 2.0V Max). Note 11: CBAT, COUT: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics. Note 12: The device maintains stable, regulated output voltage without a load. Note 13: Appropriate output load register must be set. Note 14: Dropout voltage is the voltage difference between the supply voltage and the output voltage at which the output voltage drops to 100 mV below its nominal value. 5 www.national.com LMH2190 Timing Waveforms 30083805 FIGURE 1. Clock Output Timing Waveforms 30083806 FIGURE 2. Clock Request Timing Waveforms 30083807 FIGURE 3. Rise / Fall Time and Duty Cycle Waveform for Clock Outputs 30083808 FIGURE 4. Setup Time from SCLK_IN to CLK_REQ www.national.com 6 LMH2190 Connection Diagrams 16-Bump micro SMD 16–Bump micro SMD Marking 300838a8 Top View XY = Date Code TT = Die Tracebility AA = LMH2190TM-38 30083803 Top View Pin Descriptions Pin C1 C2 A3 B3 A4 B4 D4 C4 D3 C3 A2 D2 D1 A1 B1 B2 Pin Name SCLK_IN SCLK_REQ CLK1 CLK_REQ1 CLK2 CLK_REQ2 CLK3 CLK_REQ3 CLK4 CLK_REQ4 ENABLE SCL SDA VBAT VOUT VSS Port / Direction Host Host Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral Host Host Host / Bidirectional Battery / Input LDO / Output Ground Type I O O I O I O I O I I I I/O Power Power Ground Description Source Clock Input Source Clock Request Clock Output 1 Clock Request Input 1 Clock Output 2 Clock Request Input 2 Clock Output 3 Clock Request Input 3 Clock Output 4 Clock Request Input 4 Enable Device, Active High I2C Clock Input, 100 kΩ Pull-up to ENABLE I2C Data I/O, 100 kΩ Pull-up to ENABLE Power Supply Power Supply to Clock Source and Clock Outputs Ground Pin I = Input, O = Output, I/O = Input / Output 7 www.national.com LMH2190 Ordering Information Package 16-Bump Thin microSMD Part Number LMH2190TM-38 LMH2190TMX-38 I2C Address 38 Package Marking AA Transport Media 250 Units Tape and Reel 3000 Units Tape and Reel NSC Drawing TMD16AAA Note: For other I2C addresses please contact your local sales office. Block Diagram 30083804 LMH2190 www.national.com 8 LMH2190 Typical Performance Characteristics Unless otherwise specified, TA = 25°C, VBAT = 3.5V, fSCLK_IN = 26 MHz, COUT = 2.2 µF, VDD_IO = 1.8V (See Block Diagram), Registers are in default configuration. Supply Current vs. Supply Voltage Supply Current vs. Input Clock Frequency 30083839 30083831 Supply Current vs. Capacitive Load LDO Output Voltage vs. Supply Voltage 30083832 30083840 LDO Output Voltage vs. LDO Output Current LDO Output Voltage vs. Time 30083841 30083833 9 www.national.com LMH2190 Additive Phase Noise vs. Frequency Offset CLK1 Response, CL = 10 pF 30083830 30083834 CLK1 Response, CL = 22pF CLK1 Response, CL = 33 pF 30083835 30083836 CLK1 Response, CL = 50 pF Power Supply Rejection Ratio vs. Frequency 30083837 30083838 www.national.com 10 LMH2190 Application Information The LMH2190 is a quad channel configurable clock distribution device which supplies a digital system clock to peripherals in mobile handsets or other applications. Examples of peripherals are Bluetooth, Wireless LAN, and/or Digital Video Broadcast-H (DVB-H). The LMH2190 provides a solution to clocking issues such as limited drive capability, frequency pulling and crosstalk. The drive capability of a TCXO can be insufficient when traces are long and/ or multiple peripherals are connected to one TCXO. The LMH2190’s clock outputs can be configured independently to drive capacitive loads up to 50 pF per channel. The buffer function of the LMH2190 prevents frequency pulling of the TCXO. Frequency pulling can occur when the TCXO observes varying loads. A peripheral device that shuts down can cause this load variation for instance. Crosstalk between peripheral devices is minimal since each peripheral has its own LMH2190 digital clock output. Also isolation from peripheral to TCXO is ensured by use of the LMH2190. Adding a component in the clock path inherently means adding noise. The LMH2190 though has excellent phase noise specifications in order to minimize degradation of the clock quality. A typical LMH2190 application is depicted in Figure 5. The LMH2190 clock tree driver can be divided into 4 blocks: • Clock tree driver The clock tree driver provides a clean clock to a maximum of 4 separately connected peripheral devices. • Clock request logic Independent clock request inputs allow the peripheral to control when the particular clock should be enabled. Further, the clock request inputs control the source clock request (SCLK_REQ) and enabling of the LDO. • Low Dropout regulator (LDO) The LDO provides a low noise, high PSRR supply voltage that enables low phase noise on the clock outputs, and low quiescent current for portable applications. It can also be used to provide a low noise supply to the TCXO eliminating the need for a separate LDO. • I2C Control logic An I2C control port enables re-configuration of settings of many features of the device in order to optimize the device performance based on the application. For these settings see Tables 2, 3, 4, 5, 6 in section I2C Registers. All the blocks can be switched into a low power-consumption mode to save energy. This functionality is controlled via the ENABLE pin. The following sections provide an explanation on phase noise and a detailed description of each block. 30083802 FIGURE 5. Typical LMH2190 Setup 11 www.national.com LMH2190 PHASE NOISE An important specification for oscillators and clock buffers is phase noise. It determines the timing and thus accuracy of various peripheral devices in a cell phone such as Bluetooth, WLAN and DVB-H. Phase noise is expressed in the frequency domain and is usually specified at a number of offset frequencies from the carrier frequency. The phase noise of the oscillator and the LMH2190 together determine the phase noise of the clock that is distributed to the peripheral devices. Therefore an additive phase noise is specified for the LMH2190 rather than its total output phase noise since that depends on the TCXO connected to the LMH2190. Knowing the TCXO phase noise and the additive phase noise of the LMH2190, the total phase noise to the peripheral can be calculated: In shutdown mode, the input stage is completely switched off to prevent unnecessary power consumption when the source clock is still present. In the DC coupled mode, the clock input may range from 32 kHz to 27 MHz. DC coupling mode requires that the input is a square wave. In AC mode an external capacitor needs to be connected in series with the clock source and the SCLK_IN pin to block external DC. Internally, a DC bias network centers it at about VOUT/2. This enables the use of a sine wave clock source with a amplitude between 0.8 VPP and 1.8 VPP. The bias voltage is enabled only when the clock request output is activated in order to eliminate the DC power. In the AC coupled mode, the clock input may range from 13 MHz up to 27 MHz. It is assumed to be a sine wave. Signals with sharp edges, such as square wave signals, should be prevented as the DC control loop will not be able to maintain its internal DC level. Clock Tree Driver Outputs The LMH2190's clock tree driver outputs have many modes of operation to reduce power consumption and minimize EMI. The output drive strength of the LMH2190 can be selected in 4 steps based on the load capacitance it needs to drive. The configuration can be done via the I2C interface. There are two dedicated methods for reducing EMI that can be selected through the I2C interface. As shown in Figure 7 the first method (default) skews all of the clock edges individually, so that the EMI generated by the switching is spread out over time. The second method inverts two of the outputs and also skews one pair from the other. 30083842 Where, PN is the total phase noise at the output of the LMH2190, PN_TCXO is the TCXO’s phase noise and add.PN_LMH2190 is the additive phase noise of the LMH2190, all in dBc/Hz. CLOCK TREE DRIVER The clock tree driver consists of one input that drives 4 outputs (Figure 6). It is supplied by the highly accurate 1.8V LDO. In default configuration the outputs are switched on when the clock request inputs are high. The input as well as the output can be configured in several ways though I2C programming. Clock Tree Driver Input The source clock input (SCLK_IN) is the input for the clock tree driver. It can be configured to DC or AC coupled mode. 30083811 FIGURE 6. Clock Tree Driver www.national.com 12 LMH2190 30083815 30083816 (a) Outputs with Skew only (b) Outputs with Skew and Inversion FIGURE 7. Clock Outputs Timing CLOCK REQUEST LOGIC The clock request logic enables an independent control of the clock tree driver outputs (CLK1 to CLK4) as well as an overall source clock request (SCLK_REQ) and LDO enabling. Since the clock request logic always needs to be active, it is supplied by either the output of the LDO (VOUT) or by the external ENABLE. Further details about the selection between VOUT and ENABLE can be found in the LOW DROPOUT REGULATOR section later in the datasheet. Clock Request Inputs A clock request input is provided for each clock output (Figure 8). This allows the peripheral device to control the LMH2190 when it wants to receive a clock. In case the peripheral device does not have clock request functionality, the CLKx_REQ can be wired to a logic high level to enable the clock output (in default register setting). Alternatively, it can be controlled through I2C. The CLKx_REQ input can be configured to be active high or active low. When the LDO is off, the clock request logic still need to be powered such that it can turn on the LDO. This is why the ENABLE input is used to power the Clock Request Logic in case the LDO is off. Although the CLK_REQ logic is supplied with 1.8V LDO voltage (or ENABLE), the CLKx_REQ input can tolerate voltages up to VBAT. To prevent glitches on CLK outputs, enabling of the outputs is done synchronously. A latch is used to ensure that the CLK outputs will be enabled on the falling edge of the source clock input (SCLK_IN). 30083819 FIGURE 8. Clock Request Input System Clock Request Output In the typical mode of operation, the clock request output will be enabled if one of the 4 CLK_REQ inputs is high (Figure 9). However, this can be overridden via the I2C interface which has a register bit that forces the output to be enabled, independent of the CLK_REQ input. The polarity of the output can 13 be controlled via I2C (CLK_REQ Output Polarity) along with whether the output is configured as push/pull, open drain or open source. For the open drain case, there needs to be an external resistor that pulls the SCLK_REQ to a high level. This high level may www.national.com LMH2190 be greater than the LDO voltage of 1.8V, but not more than the supply voltage (VBAT) of the LMH2190. 30083814 FIGURE 9. System Clock Request Output The System Clock Request Output pin can be used to enable or disable an external TCXO to save power consumption. A typical application diagram is shown in Figure 10. The LDO powers the TCXO, while the SCLK_REQ enables or disables the TCXO. If the TXCO doesn't have an enable pin, power savings can be realized by switching off the LMH2190's LDO and therewith the TCXO. this configuration the CLK1/2/3/4 outputs may transmit the clock to a peripheral upon startup when it is not requested by the peripheral and before the device is initialized through the I2C port. This may happen for instance when the default settings of the device for SCLK_REQ and CLK_REQ1/2/3/4 polarities do not correspond to what is expected by the TCXO and the peripheral. Care must be taken to prevent any unwanted behavior in the peripheral device until the I2C port correctly configures the device. The setting of the registers is maintained as long as the VBAT voltage is present. LOW DROPOUT REGULATOR The linear and low dropout regulator (LDO) is used to regulate the input voltage, VBAT, to generate an accurate 1.8V supply voltage. This allows the LMH2190 to suppress VBAT voltage ripples. A voltage ripple would distort clock edges causing phase noise on the distributed clock signal. In default mode the LDO is powered-up when one or more Clock Request inputs are high. Therefore the Clock Request Logic needs to be powered continuously such that it can wake-up the LMH2190 and its LDO. The VDD_IO voltage that takes care of supplying the Clock Request Logic can therefore be driven by either the LDO output voltage or the ENABLE signal. Normally the VDD_IO signal is connected to the LDO output, unless the LDO is in a low power shutdown mode. In that case the ENABLE signal will drive VDD_IO (Figure 11). As soon as there is a clock request, the built in LDO will power up and takes over the sourcing of VDD_IO from the ENABLE signal. 30083812 FIGURE 10. TCXO Powered from LMH2190's LDO Note that the LMH2190 initializes to its default settings when VBAT is powered-up. As a consequence, the LMH2190 is in it's default state until it is configured through I2C. Because of www.national.com 14 LMH2190 30083826 FIGURE 11. Linear Regulator Block Diagram The LDO contains thermal overheating detection. If it does overheat, the LMH2190 (except the register logic) will shutdown and sets a status bit in the I2C status register. The LDO can be configured to be always ON for the case when it needs to supply power to the TCXO even when the LMH2190 is not requesting any clocks to be distributed. It is possible to use an external 1.8V supply connected to VOUT and shut off the internal LDO, although it is highly recommended to use the internally generated 1.8V. If an external supply is used, care should be taken during startup as the default configuration is for the internal LDO to be enabled. In this case, there could be contention between the two supplies which could cause excessive current flow. I2C CONTROL LOGIC The LMH2190 can be controlled by a I2C host device. The I2C address of the LMH2190 is 38h. It can configure the registers inside the LMH2190 to change the default configuration. The I2C communication is based on a READ/WRITE structure, following the I2C transmission protocol. According to the I2C specification one set of pull-up resistors needs to be present on the I2C bus. Some of the features are for instance setting the polarity of the clock request inputs and outputs and setting the drive strength of the clock outputs. It also allows direct control of the clock request signals and the LDO via the I2C. The I2C interface is powered by the ENABLE, while the control logic and registers are powered by the VBAT. I2C Data Validity The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, the state of the data line should only change when SCL is LOW (Figure 12). 30083822 30083821 FIGURE 12. I2C Signals: Data Validity I2C Start and Stop Condition START and STOP bits classify the beginning and the end of the I2C session. START condition is defined as SDA signal transitioning from HIGH to LOW while SCL line is HIGH (Figure 13). STOP condition is defined as the SDA transitioning from LOW to HIGH while SCL is HIGH. The I2C master always generates START and STOP bits. The I2C bus is considered to be busy after START condition and free after STOP condition. During data transmission, I2C master can generate repeated START conditions. First START and repeated START conditions are equivalent, function-wise. FIGURE 13. I2C Start and Stop Conditions Transferring Data Every frame on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first. Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated by the master. The transmitter releases the SDA line (HIGH) during the acknowl15 www.national.com LMH2190 edge clock pulse. The receiver must pull down the SDA line during the 9th clock pulse, signifying an acknowledge. A receiver which has been addressed must generate an acknowledge after each byte has been received. After the START condition, the I2C master sends a chip address (Figure 14). This address is seven bits long followed by an eight bit which is a data direction bit (R/W). For the eighth bit, a “0” indicates a WRITE and a “1” indicates a READ. The second byte selects the register to which the data will be written. The third byte contains data to write to the selected register. Register changes take effect at the SCL rising edge during the last ACK from slave. An example of a WRITE cycle is given in Figure 15. When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in the Read Cycle waveform (Figure 16). 30083820 FIGURE 14. I2C Chip Address 30083823 FIGURE 15. Example I2C Write Cycle 30083824 FIGURE 16. Example I2C Read Cycle www.national.com 16 LMH2190 I2C Timing The timing of the SDA and SCL signals is depicted in Figure 17 and the parameters are given in Table 1. 30083825 FIGURE 17. I2C Timing Diagram TABLE 1. I2C Timing Symbol fSCL 1 2 3 4 5 5 6 7 8 9 10 Cb Clock Frequency Hold Time (repeated) START Condition Clock Low Time Clock High Time Setup Time for a Repeated START Condition Data Hold Time (Output direction, delay generated by LMH2190) Data Hold Time (Input direction, delay generated by the Master) Data Setup Time Rise Time of SDA and SCL Fall Time of SDA and SCL Set-up Time for STOP condition Bus Free Time between a STOP and a START Condition Capacitive Load for Each Bus Line 0.6 1.3 600 600 300 0 100 20+0.1 Cb 10+0.1 Cb 600 1.3 10 200 300 300 900 900 Parameter Min Limit Max 400 kHz µs ns ns ns µs ns ns ns ns ns µs pF Units 17 www.national.com LMH2190 I2C Registers TABLE 2. Configuration Register Address = 00H, type = R/W, reset value = 44H, 0100_0100, Bold face settings are the default configuration. Field Output Mode Bits [0] Description Sets the timing relationship of the clock outputs (Figure 7). 0 - All 4 outputs are skewed from each other 1 - Two pair of outputs where one output of the pair is the inversion of the other and the second pair is skewed from the first pair. Sets whether the output is push-pull or open drain. 0 - Push-Pull Output 1 - Open Drain/Source Output (Open drain with Active low output, Open source with Active high output). Sets whether the clock request output is active low or active high. 0 - Active low output 1 - Active high output Sets how the clock request output operates. 0 - Use clock request inputs 1 - Force the clock request output to be asserted. Sets whether the input is AC or DC coupled. 0 - AC coupled 1 - DC coupled Sets the regulator mode of operation. 00 - OFF 01 - Reserved 10 - Track Clock Requests 11 - Force ON Clock Request Output Type [1] Clock Request Output Polarity [2] Clock Request Output Mode [3] Clock Input Type [4] LDO Mode [6-5] Reserved [7] TABLE 3. CLK1 Output Register Address = 01H, type = R/W, reset value = 06H, 0000_0110, Bold face settings are the default configuration. Field CLK1 Load Bits [1-0] Description Sets the drive strength of the clock output based on the capacitive load. 00 - 10pF to 15pF 01 - 15pF to 22.5pF 10 - 22.5pF to 33.5pF 11 - 33.5pF to 50pF Sets whether a logic low or high enables the clock output. 0 - Logic low enables the clock output. 1 - Logic high enables the clock output. Selects whether to use a clock request or I2C logic to enable the output. 0 - Use the clock request pin to control the output. 1 - Force the clock output to be enabled (Force ON). Selects whether to use a clock request or I2C logic to disable the output. 0 - Use the clock request pin to control the output. 1 - Force the clock output to be disabled (Force OFF). ”Force OFF" overrides ”Force ON". Selects whether an internal 200 kΩ pull down resistor on the clock request input to GND is present. 0 - No internal pull down resistor is present. 1 - Internal 200 kΩ pull-down resistor is present. CLK_REQ1 Input Polarity [2] CLK_REQ1 Force ON Control [3] CLK_REQ1 Force OFF Control [4] CLK_REQ1 Pull down Resistor [5] Reserved Reserved [6] [7] www.national.com 18 LMH2190 TABLE 4. CLK2 Output Register Address = 02H, type = R/W, reset value = 06H, 0000_0110, Bold face settings are the default configuration. Field CLK2 Load Bits [1-0] Description Sets the drive strength of the clock output based on the capacitive load. 00 - 10pF to 15pF 01 - 15pF to 22.5pF 10 - 22.5pF to 33.5pF 11 - 33.5pF to 50pF Sets whether a logic low or high enables the clock output. 0 - Logic low enables the clock output. 1 - Logic high enables the clock output. Selects whether to use a clock request or I2C logic to enable the output. 0 - Use the clock request pin to control the output. 1 - Force the clock output to be enabled (Force ON). Selects whether to use a clock request or I2C logic to disable the output. 0 - Use the clock request pin to control the output. 1 - Force the clock output to be disabled (Force OFF). ”Force OFF" overrides ”Force ON". Selects whether an internal 200 kΩ pull down resistor on the clock request input to GND is present. 0 - No internal pull down resistor is present. 1 - Internal 200 kΩ pull-down resistor is present. CLK_REQ2 Input Polarity [2] CLK_REQ2 Force ON Control [3] CLK_REQ2 Force OFF Control [4] CLK_REQ2 Pull down Resistor [5] Reserved Reserved [6] [7] TABLE 5. CLK3 Output Register Address = 03H, type = R/W, reset value = 06H, 0000_0110, Bold face settings are the default configuration. Field CLK3 Load Bits [1-0] Description Sets the drive strength of the clock output based on the capacitive load. 00 - 10pF to 15pF 01 - 15pF to 22.5pF 10 - 22.5pF to 33.5pF 11 - 33.5pF to 50pF Sets whether a logic low or high enables the clock output. 0 - Logic low enables the clock output. 1 - Logic high enables the clock output. Selects whether to use a clock request or I2C logic to enable the output. 0 - Use the clock request pin to control the output. 1 - Force the clock output to be enabled (Force ON). Selects whether to use a clock request or I2C logic to disable the output. 0 - Use the clock request pin to control the output. 1 - Force the clock output to be disabled (Force OFF). ”Force OFF" overrides ”Force ON". Selects whether an internal 200 kΩ pull down resistor on the clock request input to GND is present. 0 - No internal pull down resistor is present. 1 - Internal 200 kΩ pull-down resistor is present. CLK_REQ3 Input Polarity [2] CLK_REQ3 Force ON Control [3] CLK_REQ3 Force OFF Control [4] CLK_REQ3 Pull down Resistor [5] Reserved Reserved [6] [7] 19 www.national.com LMH2190 TABLE 6. CLK4 Output Register Address = 04H, type = R/W, reset value = 06H, 0000_0110, Bold face settings are the default configuration. Field CLK4 Load Bits [1-0] Description Sets the drive strength of the clock output based on the capacitive load. 00 - 10pF to 15pF 01 - 15pF to 22.5pF 10 - 22.5pF to 33.5pF 11 - 33.5pF to 50pF Sets whether a logic low or high enables the clock output. 0 - Logic low enables the clock output. 1 - Logic high enables the clock output. Selects whether to use a clock request or I2C logic to enable the output. 0 - Use the clock request pin to control the output. 1 - Force the clock output to be enabled (Force ON). Selects whether to use a clock request or I2C logic to disable the output. 0 - Use the clock request pin to control the output. 1 - Force the clock output to be disabled (Force OFF). ”Force OFF" overrides ”Force ON". Selects whether an internal 200 kΩ pull down resistor on the clock request input to GND is present. 0 - No internal pull down resistor is present. 1 - Internal 200 kΩ pull-down resistor is present. CLK_REQ4 Input Polarity [2] CLK_REQ4 Force ON Control [3] CLK_REQ4 Force OFF Control [4] CLK_REQ4 Pull down Resistor [5] Reserved Reserved [6] [7] TABLE 7. Status Register Address = 05H, type = R Field Thermal Shutdown (TSD) Bits [0] Description Indicates if a thermal shutdown event has occurred. 0 - Thermal shutdown has not occurred. 1 - Thermal shutdown has occurred Captures the state of the generated clock request input value. 0 - Generated clock request is low. 1 - Generated clock request is high. Captures the state of the generated clock request input value. 0 - Generated clock request is low. 1 - Generated clock request is high. Captures the state of the generated clock request input value. 0 - Generated clock request is low. 1 - Generated clock request is high. Captures the state of the generated clock request input value. 0 - Generated clock request is low. 1 - Generated clock request is high. Captures the state of the system clock request output value. 0 - System clock request is low. 1 - System clock request is high. CLK_REQ1 Input Value [1] CLK_REQ2 Input Value [2] CLK_REQ3 Input Value [3] CLK_REQ4 Input Value [4] SCLK_REQ Output Value [5] Reserved Reserved [6] [7] www.national.com 20 LMH2190 LAYOUT RECOMMENDATIONS As with any other device, careful attention must be paid to the board layout. If the board isn't properly designed, the performance of the device can be less than might be expected. Especially the input clock trace (SCLK_IN) and output traces (CLK1/2/3/4) should be as short as possible to reduce the capacitive load observed by the clock outputs. Also proper decoupling close to the device is necessary. Beside a capac- itor in the µF range (See Table 8), a capacitor of 100 nF on VBAT and VOUT is recommended close to device. The equivalent series resistance (ESR) of the capacitors should be sufficiently low. A standard capacitor is usually adequate. Advised values are given in Table 8. An evaluation board is available to ease evaluation and demonstrate a proper board layout. TABLE 8. Recommended Component Values Symbol CBAT COUT ESR CSCLK_IN Parameter Capacitor on VBAT Capacitor on VOUT Equivalent Series Resistance Input AC Coupling Capacitor Min 0.47 1 5 330 470 Typ 1 2.2 500 10000 Max Units µF mΩ pF CBAT, COUT: Low-ESR Surface-Mount Ceramic Capacitors (MLCC's) used in setting electrical characteristics. 21 www.national.com LMH2190 Physical Dimensions inches (millimeters) unless otherwise noted 16-Bump micro SMD NS Package Number TMD16AAA X1 = 1.615 ± 0.030 mm, X2 = 1.615 ± 0.030 mm, X3 = 0.600 ± 0.075 mm www.national.com 22 LMH2190 Notes 23 www.national.com LMH2190 Quad Channel 27 MHz Clock Tree Driver with I2C Interface Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Amplifiers Audio Clock and Timing Data Converters Interface LVDS Power Management Switching Regulators LDOs LED Lighting Voltage Reference PowerWise® Solutions Temperature Sensors Wireless (PLL/VCO) www.national.com/amplifiers www.national.com/audio www.national.com/timing www.national.com/adc www.national.com/interface www.national.com/lvds www.national.com/power www.national.com/switchers www.national.com/ldo www.national.com/led www.national.com/vref www.national.com/powerwise WEBENCH® Tools App Notes Reference Designs Samples Eval Boards Packaging Green Compliance Distributors Quality and Reliability Feedback/Support Design Made Easy Solutions Mil/Aero PowerWise® Design University Design Support www.national.com/webench www.national.com/appnotes www.national.com/refdesigns www.national.com/samples www.national.com/evalboards www.national.com/packaging www.national.com/quality/green www.national.com/contacts www.national.com/quality www.national.com/feedback www.national.com/easy www.national.com/solutions www.national.com/milaero www.national.com/solarmagic www.national.com/training Serial Digital Interface (SDI) www.national.com/sdi www.national.com/wireless www.national.com/tempsensors SolarMagic™ THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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